2GHz LOW NOISE AMPLIFIER WITH THE BFG425W

H
Philips Semiconductors B.V.
Gerstweg 2, 6534 AE Nijmegen, The Netherlands
Report nr.
Author
Date
Department
: RNR-T45-96-B-773
: T. Buss
: 14-Nov-1996
: P.G. Transistors & Diodes, Development
2GHz LOW NOISE AMPLIFIER
WITH THE BFG425W
Abstract:
This application note contains an example of a Low Noise Amplifier with the new BFG425W Double Poly
RF-transistor. The LNA is designed for a frequency f=2GHz. At 2GHz: [email protected],
[email protected],
[email protected]
Appendix I: Schematic of the circuit
Appendix II: Used components & materials
Appendix III: Simulation LNA-PCB
Appendix IV: Measurements LNA-PCB
1
H
Philips Semiconductors B.V.
Introduction:
With the new Philips silicon bipolar double poly BFG400W series, it is possible to design low noise
amplifiers for high frequency applications with a low current and a low supply voltage. These amplifiers are
well suited for the new generation low voltage high frequency wireless applications. In this note a first study
of such an amplifier will be given. This amplifier is designed for a working frequency of 2GHz.
Designing the circuit:
The circuit is designed to show the following performance:
transistor: BFG425W
Vce=2V, Ic =2...10mA, VSUP<5V
freq=2GHz
[email protected]
[email protected]
[email protected]
VSWRi<1:2
VSWRo<1:2
In the simulations the effect of extra RF-noise caused by the SMA-connectors was omitted, so in the practical
situation the NF is ~0.1dB higher. This LNA is not optimised for the highest IP3 and Noise Figure. The IP3
can be optimised by:
I. an extra series RC-decoupling of the base to the ground
II. increasing IC
With the solution I. two extra components are necessary, and with solution II, the Noise Figure of the LNA
increases and the optimum source impedance also.
The in- and outputmatching is realised with a LC-combination. Also extra emitter-inductance on both emitterleads (µ-strips) are used to improve the matching and the Noise Figure.
Designing the layout:
A lay-out has been designed with HP-MDS. Appendix II contains the printlayout.
Simulations:
Appendix III contains HP-MDS simulations of the LNA.
Measurements:
Appendix IV contains measurement-results of the LNA.
2
H
Philips Semiconductors B.V.
Appendix I: Schematic of the circuit
C6
C3
R5
C4
R1
+VSUP
C2
R3
R4
µS3
µS1
R2
OUT
50Ω
µS2
IN
50Ω
C5
BFG425W
W1
C1
µS4:
µS4
L1
L2
µS4
D1
L3
W2
Figure 1: LNA circuit
2 GHz LNA Component list:
Component:
Value:
Comment:
R1
R2
R3
R4
R5
C1
C2
C3
C4
C5
C6
µs1
µs2
µs3
µs4
Bias.
Omitted.
RF-block.
Cancelling HFE-spread.
To improve IP3-performance
Input match.
2GHz short.
2GHz short.
RF-short
Output match.
To improve IP3-performance
µ-stripline Z0~95Ω (PCB: εr ~4.6, H=0.5mm)
µ-stripline Z0~95Ω (PCB: εr ~4.6, H=0.5mm)
µ-stripline Z0~95Ω (PCB: εr ~4.6, H=0.5mm)
Emitter induction: µ-stripline + via
15
0
22
82
100
4.7
5.6
5.6
1
2.7
100
8.9 x
3.9 x
6.6 x
(next
KΩ
Ω
Ω
Ω
Ω
pF
pF
pF
nF
pF
nH
0.25mm
0.25mm
0.25mm
table)
3
H
Philips Semiconductors B.V.
µS4 Emitter induction (µ-stripline + via):
Name Dimension Description
L1
1.0mm
length µ-stripline; Z0 ~48Ω (PCB: εr ~4.6, H=0.5mm)
L2
1.0mm
length interconnect stripline and via-hole area
L3
1.0mm
length via-hole area
W1
0.5mm
width µ-stripline
W2
1.0mm
width via-hole area
D1
0.4mm
diameter of via-hole
4
H
Philips Semiconductors B.V.
Appendix II: Used components & materials
C1
BFG425W
RFin
R2
C6
RFout
R1
R5
C2
C5
C3
R3
Vsup
R4
C4
Figure 2: Printlayout
2GHz LNA Component list:
Component:
Value:
size:
R1
R2
R3
R4
R5
C1
C2
C3
C4
C5
C6
15 KΩ
0
Ω
22
Ω
82
Ω
100 Ω
4.7 pF
5.6 pF
5.6 pF
1
nF
2.7 pF
100 nF
0603 Philips
0603 Philips
0603 Philips
0603 Philips
0805 Philips
0603 Philips
0603 Philips
0603 Philips
0603 Philips
0603 Philips
0805 Philips
PCB
εr ~4.6, H=0.5mm
FR4
5
H
Philips Semiconductors B.V.
Appendix III: Simulation LNA-PCB
Ccmc=Contkop
model cap.
LOW NOISE AMP. WITH [email protected]/2mA
[email protected]/2mA
Ccmc=Contkop
R=22 OH
Subsp=s10m
R=3.3 KOH
Subsp=s10m
R=100 OH
Subsp=s10m
AGROUND
[email protected]/20mA
R=0.1 OH
Subsp=s10m
1
Ccmc=Cin
2
AGROUND
Ccmc=Cout
AGROUND
Figure 3: HP-MDS simulation circuit (Spice model and S_par 2-port model)
Results Simulations: f=2GHz
SPICE
SPICE
MODEL
MODEL
2
IC [mA]
|S 21|
IP3_B
[dB]
[dBm]
input,
∆f=
100KHz
2
3
5
6
8
10
14.3
15.0
15.6
15.8
16.1
16.3
-1.3
+0.6
+3.8
+6.1
+7.1
+8.5
SPICE
MODEL
NF
[dB]
note 1.
S_PAR
MODEL
S_PAR
MODEL
NF
[dB]
note 1.
1.7
1.7
1.9
2.0
2.2
2.4
14.3
1.5
16.3
2.0
note 1: There is a difference in Noise Figure between the Spice model and de S_par 2-port model. The latter
uses measured S- and Noise-parameters.The difference in Noise Figure between both models can be
explained by the fact that the Spice model is not extracted for Noise.
6
H
Philips Semiconductors B.V.
Appendix IV: Measurements LNA-PCB
Results Measurements: f=2GHz
2
IC [mA]
|S 21|
IP3_A
[dB]
[dBm]
VCE ~
input,
2.5V
∆f=
100KHz
note 1.
2
14.4
-10.9
3
15.9
-3.4
5
16.3
-0.9
6
16.6
1.0
8
16.9
3.9
10
17.1
6.5
IP3_B
[dBm]
input,
∆f=
100KHz
note 1.
-2.3
-0.4
1.8
2.6
5.6
6.7
NF
[dB]
1.5
1.7
1.8
1.9
2.1
2.3
note 1: IP3_A: IP3 without LF-decoupling at base
IP3_B: IP3 with LF-decoupling (R5 and C6) at base
At low currents, the IP3 can be improved by using a low frequency decouple network at the base of the
bipolar transistor (figure 1: R5 and C6). The improvement with the IP3 optimising circuit is 8dBm at low
current (IC =3mA). As the current is increased, the effect of IP3 improvement decreases.
7
Similar pages