MB9D560 Series, Datasheet

MB9D560 Series
32-bit Microcontroller
TraveoTM Family
MB9D560 series has Cypress 32-bit microcontrollers for automobile motor control. They use the ARM® Cortex-R5 MPCoreTM CPU
that is compatible with the ARM family.
Notes:
• ARM, Cortex, Thumb are the registered trademarks of ARM Limited in the EU and other countries.
• MPCore, CoreSight are the trademarks of ARM Limited in the EU and other countries.
Features
Technology
Debugging
 CMOS 90nm technology
 ARM CoreSightTM Technology
 Each
CPU embedded Embedded Trace Macro (ETM),
trace support of CPU operation
CPU
 Debugging interface
 ARM Cortex®-R5F
 JTAG
 32-bit ARM architecture
(5 pin )
clock : maximum 20 MHz
 Support
 2-instruction issuance super scalar
 Debugging security support
 8-stage pipeline
 128-bit
security key (Device security key)
 ARMv7 / Thumb®-2 instruction set
 Wakeup function on JTAG
 Floating-Point Unit (FPU)
Operation mode
 Double
precision
 User mode
 Memory protection Unit (MPU)
 16
 Normal
area
 Serial writer mode
 ECC support for the TCM port
 1-bit
error correction, 2-bit error detection ECC (SEC-DED)
 TCM port
2
 Fast-CR
 ATCM port
 Slow-CR
 BTCM 2 ports (B0TCM, B1TCM)
oscillation (8 MHz)
oscillation (100 kHz)
 External oscillation input
 Main
 VIC port
clock input
 Embedded PLL
latency interrupt
 Main
 AXI master interface
 64-bit AXI
interface (instruction / data access)
 32-bit AXI interface (I/O access)
 AXI slave interface
 64-bit AXI
Clock control
 Internal clock source
TCM ports
 Low
mode (internal memory activation)
interface (accessible to TCM port)
PLL (Multiplying clock of main oscillation )
 Oscillator stabilized timer
 Support
oscillator stabilized timer for all clock source
independently
 After a lapse of oscillator stabilized time, it is able to use
source clock timer (Except PLL for FlexRay/RDC)
 CPU configuration
2
CPUs (AMP operation)
 Operating frequency
 Maximum
200 MHz
 Trace with ETM-R5
Cypress Semiconductor Corporation
Document Number: 002-05679 Rev.*A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 22, 2016
MB9D560 Series
Reset control
Watchdog timer (WDT)
 Reset level
 Watchdog timer embedded
 Hardware
reset (system initialization)
 Software reset (programing initialization)
 Reset factor (Hardware reset )
 Power-on
reset (PONR), external reset input (RSTX,
NMIX+RSTX), clock stop waiting with time-out reset,
low-voltage detection reset (internal low-voltage detection
reset, 5V external low-voltage detection reset ), watchdog
reset (hardware watchdog reset, software watchdog reset ),
clock supervisor reset (main clock monitor, PLL clock
monitor), software trigger hardware reset , profile error
reset
 Reset factor (software reset )
 Software
reset
Low power consumption control
 Device state
 RUN
(Run State, CPU is operation status)
 PSS (Power Saving State, CPU wait event from WFI)
 Setting parameter of each devise state
 Clock
(clock source enable, clock source selection, clock
divider, clock domain enable)
 Clock monitor
 Low-voltage detection
Memory protection unit (MPU)
 Memory protection as master except processor
 Target master
 DMA controller
 Hardware
 Software
watchdog timer
watchdog timer
 Hardware watchdog timer
1
unit per system
watchdog timer with window function
 Clock source: fast-CR or slow-CR
 Set by boot program (BootROM maker)
 Not set by user program
 32-bit
 Software watchdog timer
1
unit per CPU
watchdog timer with window function
 Clock source: fast-CR, slow-CR, main clock
 One time set on user program (not set again)
 32-bit
Low-voltage detection (LVD)
 Select voltage monitor
 External
low-voltage detection (5V power line monitor):
3.9V, 4.1V, 4.3V
 Internal low-voltage detection (1.2V power line monitor):
0.9V
 Internal low-voltage detection: always valid
 External low-voltage detection: valid/invalid set
 External low-voltage detection: set threshold voltage
independently on RUN / PSS
 Output when low-voltage detection
 External
 Internal
low-voltage detection: reset or NMI
low-voltage detection: reset
 8 area
 NMI generation when violation detection
Timing protection unit (TPU)
Main Flash memory (TCFLASH)
 Cortex-R5F ATCM connection
1
Main Flash memory as CPU 1 unit
 TPU 1 unit as CPU 1 unit
 HPM connection with 64-bit AXI
 24-bit timer x 8 channels per unit
 Flash memory configuration
 Support execution time protection, locking time protection,
inter-arrival time protection, deadline protection
 Support normal mode and over flow mode
 Prescaler of each channels
 Timer
clock divider (1/1 to 1/64)
 Independent prescaler of each channels
 Timer
clock divider (1/1, 1/2, 1/4, 1/16)
 Interleave
with 64-bit Flash 2 units
 2 address areas
 TCM
 AXI
(read only)
(read / write)
 ECC support (SEC-DED)
 Parallel programming support
 Flash security
Clock supervisor (CSV)
Work Flash memory (WorkFLASH)
 Monitor target clock
 2 Work Flash memories
 Main
oscillation input , main PLL output
 Monitor method
 Monitor
of frequency range
 Operation after error detection
 Reset
or NMI
Document Number: 002-05679 Rev.*A
1
Work Flash memory as CPU 1 unit
 ECC support (SEC-DED)
 Parallel programming support
 Flash security
Page 2 of 91
MB9D560 Series
Main SRAM (TCRAM)
Exclusion access memory (EAM)
 BTCM connection of Cortex-R5F
 Small size memory to support exclusion control on exclusion
1
main SRAM as CPU 1 unit
 Interleave with 2 ports of B0TCM and B1TCM
access instruction
 Use for semaphore
 ECC support (SEC-DED)
 Size: 48 byte
BootROM
Bit-band unit (BBU)
 Size: 16K byte
 The bit operation of specified register bit on Bit band area, it
 Boot operation support
 Serial writer program support
is mapping 1 bit of bit band area to support bit band alias
area for 1 byte. The target of bit band access is specified
register bit on I/O area
DMA controller (DMAC)
CRC
 16 channels
 Output to register of CRC code according real time writing to
 Transfer mode
 Block
transfer, Burst transfer
 Addressing mode
 Fixed,
increment
 Priority between channels
 Fixed,
Dynamic, Round robin
input register
Base timer
 16-bit timer
 Any
of four PWM/PPG/reload/PWC timer functions can be
selected and used.
 A 32-bit timer can be used in 2 channels of cascade mode
as reload/PWC timer.
Interrupt control (IRC)
 Support normal interrupt (IRQ) and non-maskable interrupt
(NMI)
 Normal interrupt (IRQ)
 Use
Interrupt Request (IRQ) of Cortex-R5F
channels
 32 level for priority
 512
 Support low latency interrupt response from VIC port of
Cortex-R5F
 Non-maskable interrupt (NMI)
 Use
fast interrupt request (FIQ) of Cortex-R5F
 32 channels
 16 level for priority
 Support software interrupt generation
16-bit free-run timer (FRT)
 16 bit up/down counter (2 channels for motor control only)
32-bit free-run timer
 32 bit up/down counter
16-bit input capture (ICU)
 Input capture
 16-bit
capture register that detects rise edge, Fall edge,
both edge
 Generate interrupt request after latch of counter number of
16 bit
 Free-run timer with edge detection of pin input
32-bit input capture
External interrupt (EXT-IRQ)
 Input
 Normal
interrupt (IRQ): 8 input
 Non-maskable interrupt (NMI): 1 input
 Detection method
H
level , L level , rise edge, fall edge, both edge
Inter-processor communications unit (IPCU)
 Mailbox function
 Data
communication for CPU core communication by 8
Mailbox
 Support of interrupt between CPU core
 Input capture
 32-bit
capture register that detects rise edge, fall edge,
both edge
 Generate interrupt request after latch of counter number of
32 bit
 Free-run timer with edge detection of pin input
 LIN sync break/sync field relation is following.
capture ch.0  Multi-function serial interface ch.0
capture ch.1  Multi-function serial interface ch.1
 Input capture ch.2  Multi-function serial interface ch.2
 Input capture ch.3  Multi-function serial interface ch.3
 Input capture ch.4  Multi-function serial interface ch.4
 Input
 Input
16-bit output compare (OCU)
 Output interrupt signal when compare with 16-bit free-run
timer
Document Number: 002-05679 Rev.*A
Page 3 of 91
MB9D560 Series
Waveform generator (WFG)
CAN interface
 Generate variable output
 The CAN is based on the CAN protocol ver. 2.0A/B
 Real
time output
 16-bit PPG waveform output
 PPG uses 16-bit PPG timer of base timer
 The relation is following
 WFG(ch.0 to ch.5)
• Base timer ch.0  PPG0
• Base timer ch.2  PPG2
• Base timer ch.4  PPG4
 WFG(ch.6 to ch.11)
• Base timer ch.6  PPG6
• Base timer ch.8  PPG8
• Base timer ch.10  PPG10
 Non overlap three-phase waveform output (inverter
control)
 DC chopper waveform output
 Dead time timer function
 GATE function
 DTTI function
 64 message buffers x 3 channels
 An identification mask is applied to each message object
 Up to 1Mbps support
 Clock support CAN prescaler
 CAN wakeup functions
FlexRay controller
 Supports FlexRay protocol specification v2.1
 Maximum 128 message buffers
 8K Byte message RAM
 Variable length of message buffers
 Each message buffer can be allocated as a part of reception
buffer, transmission buffer or reception FIFO
 Host access to the message buffer via input and output
buffers
A/D converter (ADC)
 Filtering for slot counter, cycle counter and channels
 12-bit resolution A/D converter: 1 unit (32 channels)
 Maskable interrupts are supported
 Sampling analog value from input port of 32 channels
R/D converter (RDC)
 Conversion time: 1 s
 Connect to resolver interface
 External trigger activation (ADTG)
 Activation from internal timer (base timer)
D/A converter (DAC)
 10-bit resolution
4ch sample-hold A/D converter
 12 bit resolution A/D converter: 2 units (8 channels )
Multi-function serial interface (MFS)
 UART / CSIO / LIN interface (v2.1) communication available
by selecting the function
 Transmission FIFO: 64 Byte, reception FIFO: 64 Byte
 Reception interrupt factor (3 types)
 Reception
error detection (parity, over run, frame error)
 Reception to FIFO for data of setting value
 Reception data under setting value in FIFO, idle term
detection of over 8 clocks with baud rate clock
 Transmission interrupt factor (2 types)
 No
transmission operation
FIFO empty (contain transmission operation)
 Transmission
 SPI (serial peripheral interface) support
 LIN protocol revision 2.1 support
Up/Down counter (UDC)
Motor vector operation accelerator (MVA)
 Assist for three-phase current normalizing, three-phase to
two-phase DC conversion / two-phase to three- phase AC
conversion, angler calculation, PID control calculation.
 Error detection in processing (overflow/under flow/non
normalizing error of FLOP)
 Amplitude diagnosis /angle diagnosis function of R/D
converter
 Error current diagnosis function
Key code
 Key code supports
 A part
of General-purpose I/O (GPIO) register
pin configuration (PPC) register
 Analog input control register (ADER)
 4ch ADC analog input control register (ADER4CH_1,
ADER4CH_0)
 Analog output control register (DAC00_DAER,
DAC01_DAER)
 Port
 8/16-bit up/down counter (2 channels uses for R/D converter)
Document Number: 002-05679 Rev.*A
Page 4 of 91
MB9D560 Series
Contents
1. Product Lineup .................................................................................................................................................................. 6
2. Pin Assignment ................................................................................................................................................................. 7
3. Pin Description ................................................................................................................................................................ 11
4. I/O Circuit Type ............................................................................................................................................................... 25
5. Handling Precautions ..................................................................................................................................................... 28
5.1
Precautions for Product Design ................................................................................................................................... 28
5.2
Precautions for Package Mounting .............................................................................................................................. 29
5.3
Precautions for Use Environment ................................................................................................................................ 30
6. Handling Devices ............................................................................................................................................................ 31
7. Block Diagram ................................................................................................................................................................. 33
8. Memory Map .................................................................................................................................................................... 35
9. I/O Map ............................................................................................................................................................................. 38
10. Pin Statuses in CPU Status ............................................................................................................................................ 42
11. Electrical Characteristics ............................................................................................................................................... 44
11.1 Absolute Maximum Ratings ......................................................................................................................................... 44
11.2 Recommended Operating Conditions ......................................................................................................................... 46
11.3 DC Characteristics ...................................................................................................................................................... 47
11.4 AC Characteristics ....................................................................................................................................................... 54
11.4.1 Source Clock Timing .................................................................................................................................................... 54
11.4.2 Internal Clock Timing ................................................................................................................................................... 55
11.4.3 Reset Input ................................................................................................................................................................... 58
11.4.4 Power-on Conditions .................................................................................................................................................... 59
11.4.5 Multi-Function Serial Interface ..................................................................................................................................... 60
11.4.6 Timer Input Timing ....................................................................................................................................................... 77
11.4.7 Trigger Input Timing ..................................................................................................................................................... 78
11.4.8 NMI Input Timing .......................................................................................................................................................... 79
11.4.9 External Low-Voltage Detection ................................................................................................................................... 80
11.4.10 Internal Low-Voltage Detection................................................................................................................................. 80
11.5 A/D Converter .............................................................................................................................................................. 81
11.5.1 Electrical Characteristics .............................................................................................................................................. 81
11.5.2 Notes on Using A/D Converter ..................................................................................................................................... 81
11.6 4 Channels Same Time Sampling A/D Converter ....................................................................................................... 82
11.6.1 Electrical Characteristics .............................................................................................................................................. 82
11.6.2 Notes on Using A/D converter ...................................................................................................................................... 82
11.6.3 Definition of Terms ....................................................................................................................................................... 83
11.7 Flash Memory .............................................................................................................................................................. 84
11.8 R/D Converter ............................................................................................................................................................. 85
12. Ordering Information ...................................................................................................................................................... 86
13. Part Number Option ........................................................................................................................................................ 86
14. Package Dimensions ...................................................................................................................................................... 87
15. Major Changes ................................................................................................................................................................ 89
Document History ................................................................................................................................................................. 90
Document Number: 002-05679 Rev.*A
Page 5 of 91
MB9D560 Series
1. Product Lineup
Memory Size
Parameter
FLASH size (program)
FLASH size (Work)
RAM size
MB9DF564
(512KB+128KB)2
64KB2
64KB2
MB9DF565
(768KB+128KB)2
64KB2
96KB2
MB9DF566
(1024KB+128KB)2
64KB2
128KB2
Functions
Pin number
System clock
CR oscillator (fast/slow)
DMAC
Base timer
32-bit free-run timer
32-bit input capture
16-bit free-run timer
16-bit input capture
16-bit output compare
Waveform generator
External interrupt
A/D converter
4ch sample-hold A/D converter
R/D converter
D/A converter
Up/Down counter
Motor vector operation accelerator
Multi-function serial interface
CAN
FlexRay
Inter-processor communications unit
Exclusive access memory
Software watchdog timer
Hardware watchdog timer
CRC
Internal power supply low-voltage detection
External power supply low-voltage detection
Key code
Package
Debugging interface
208 pin
176 pin
On-chip PLL clock multiplication system
Minimum instruction execution time :5 ns (200 MHz)
Yes
16 channels
12 channels (0 to 11)
6 channels (0 to 3, 6, 7)
5 channels
3 units (6 channels)
*1
20 channels
8 units (0 to 7)
7 units (0 to 6)
(15 channels (0 to 14))
(13 channels (0 to 12))
12 units (0 to 11)
9 units (0 to 5, 9 to 11)
(24 channels (0 to 23))
(18 channels (0 to 11, 18 to 23))
4 units (0 to 3)
3 units (0, 1, 3)
(24 channels (0 to 23))
(18 channels (0 to 11, 18 to 23))
8 channels (0 to 7)
6 channels (0 to 4, 7)
1 unit (32 channels)
2 units (8 channels)
*2
2 units
*2
2 channels
4 channels
2 units
5 channels (0 to 4)
3 channels (0, 1, 4)
3 channels
*2
128 msb x 1 unit (ch.A / ch.B)
Yes
Yes
Yes
Yes
2 channels
Yes
Yes
2
Yes*
LER208
LEP176
JTAG interface
*1: 2 channels for motor control
*2: The function is different according to the part number. See “13. Part Number Option”.
Document Number: 002-05679 Rev.*A
Page 6 of 91
MB9D560 Series
2. Pin Assignment
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
MONCLK
TIOB9
TIOA9
TIOB8
TIOA8
AN15
AN14
AN13
AN12
AN11
AN10
AN9
AN8
MM
TIOB7
TIOA7
TIOB6
TIOA6
AN23
AN22
AN21
AN20
AN19
AN18
AN17
AN16
SCS43
SCS42
SCS41
SCS40
SCK4
SOT4
SIN4
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
VCC5
P304
P303
P302
P301
P300
P231
P230
P229
P228
P227
P226
P225
P224
VSS
VCC12
P223
P222
P221
P220
P219
P218
P217
P216
AVRH2
AVRL2
AVSS2
AVCC2
P215
P214
P213
P212
P211
P210
P209
P208
VCC12
VSS
P207
P206
P205
P204
P203
P202
P201
P200
P429
P428
P427
P426
P425
VCC5
TIOB11
TIOA11
TIOB10
TIOA10
ADTG0
AN31
AN30
AN29
AN28
AN27
AN26
AN25
AN24
FRCK7
FRCK6
FRCK5
FRCK4
IN5
IN4
IN3
IN2
IN1
IN0
INT7
208 Pin Part Number with RDC
4ADTG0
FRCK0
FRCK1
DTTI0
RTO0
RTO1
RTO2
RTO3
RTO4
RTO5
4AN0
4AN1
4AN2
4AN3
ZIN0
BIN0
AIN0
ZIN1
BIN1
AIN1
RDC_W0
RDC_V0
RDC_U0
RDC_Z0
RDC_B0
RDC_A0
P026
ERDS0
DTTI2
RTO12
RTO13
RTO14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
TOP VIEW
LER208
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VSS
VCC12
P423
P422
P421
P100
P101
P102
P103
P104
P105
P106
VCC5
VSS
P107
P108
P109
P110
AVRH1
AVRL1
AVR1
AVSS1
AVCC1
P111
P112
P113
P114
P115
P116
AREF21
SIN_IN1
COS_IN1
SIN_OUT1
SIN_MINUS1
SIN_PLUS1
COS_PLUS1
COS_MINUS1
COS_OUT1
ＲＶＲＨ1
RVRL1
RVR1
RVSS1
RVCC1
RDC_ACT1
MAG_MINUS1
MAG_PLUS1
MAG_OUT1
P431
P131
P420
P419
VCC5
SCK3
SOT3
SIN3
DTTI1
RTO6
RTO7
RTO8
RTO9
RTO10
RTO11
FRCK10 IN14
FRCK9
IN13
INT6
FRCK8
4ADTG1
4AN4
4AN5
4AN6
4AN7
RDC_W1
RDC_V1
RDC_U1
RDC_Z1
RDC_B1
RDC_A1
ZIN2
BIN2
AIN2
ZIN3
BIN3
AIN3
P126
ERDS1
SCK2
SOT2
SIN2
INT5
Document Number: 002-05679 Rev.*A
IN16
IN17
IN18
IN19
IN20
IN21
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
TIOA3
TIOB3
FRCK16
FRCK17
RTO15
RTO16
RTO17
DTTI3
RTO18
RTO19
RTO20
RTO21
RTO22
RTO23
INT3 SIN0
SOT0
SCK0
VSS
VCC12
P311
P312
P313
P314
P315
P316
P317
P318
P319
P320
P321
P322
P323
VCC12
VSS
IN6
STOPWT P324
IN7
RXDA
P325
IN8
TXDA
P326
IN9
TXE NA P327
IN10 RXDB
P328
IN11 TXDB
P329
IN12 TXE NB P330
NMIX
RSTX
MD1
MD0
X0
X1
VSS
TRSTX
TCK
TDO
TDI
TMS
nSRST
INT4 SIN1
P406
SOT1
P407
SCK1
P408
INT0 RX0
P409
TX0
P410
INT1 RX1
P411
TX1
P412
INT2 RX2
P413
TX2
P414
TIOA4
P415
TIOB4
P416
TIOA5
P417
TIOB5
P418
VCC12
VSS
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
FRCK12
FRCK13
FRCK14
FRCK15
VSS
VCC12
P305
P306
P000
P001
P002
P003
P004
P005
P006
VCC5
VSS
P007
P008
P009
P010
AVRH0
AVRL0
AVR0
AVSS0
AVCC0
P011
P012
P013
P014
P015
P016
AREF20
SIN_IN0
COS_IN0
SIN_OUT0
SIN_MINUS0
SIN_PLUS0
COS_PLUS0
COS_MINUS0
COS_OUT0
RVRH0
RVRL0
RVR0
RVSS0
RVCC0
RDC_ACT0
MAG_MINUS0
MAG_PLUS0
MAG_OUT0
P430
P030
P031
P309
P310
VCC5
Page 7 of 91
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
4AN0
4AN1
4AN2
4AN3
ZIN0
BIN0
AIN0
ZIN1
BIN1
AIN1
FRCK12
FRCK13
FRCK14
FRCK15
DAOUT0
ERDS0
DTTI2
RTO12
RTO13
RTO14
VSS
VCC12
P305
P306
P000
P001
P002
P003
P004
P005
P006
VCC5
VSS
P007
P008
P009
P010
AVRH0
AVRL0
AVR0
AVSS0
AVCC0
P011
P012
P013
P014
P015
P016
P017
P018
P019
P020
P021
P022
P023
P024
P025
RVRH0
RVRL0
RVR0
RVSS0
RVCC0
P026
P027
P028
P029
P430
P030
P031
P309
P310
VCC5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Document Number: 002-05679 Rev.*A
IN16
IN17
IN18
IN19
IN20
IN21
VSS
VCC12
P311
P312
P313
P314
P315
P316
P317
P318
P319
P320
P321
P322
P323
VCC12
VSS
IN6 STOPWT P324
IN7 RXDA
P325
IN8 TXDA
P326
IN9 TXE NA P327
IN10 RXDB
P328
IN11 TXDB
P329
IN12 TXE NB P330
NMIX
RSTX
MD1
MD0
X0
X1
VSS
TRSTX
TCK
TDO
TDI
TMS
nSRST
INT4 SIN1
P406
SOT1
P407
SCK1
P408
INT0 RX0
P409
TX0
P410
INT1 RX1
P411
TX1
P412
INT2 RX2
P413
TX2
P414
TIOA4
P415
TIOB4
P416
TIOA5
P417
TIOB5
P418
VCC12
VSS
RTO15
RTO16
RTO17
DTTI3
RTO18
RTO19
RTO20
RTO21
RTO22
RTO23
INT3 SIN0
SOT0
SCK0
4ADTG0
FRCK0
FRCK1
DTTI0
RTO0
RTO1
RTO2
RTO3
RTO4
RTO5
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
TIOA3
TIOB3
FRCK16
FRCK17
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
VCC5
P304
P303
P302
P301
P300
P231
P230
P229
P228
P227
P226
P225
P224
VSS
VCC12
P223
P222
P221
P220
P219
P218
P217
P216
AVRH2
AVRL2
AVSS2
AVCC2
P215
P214
P213
P212
P211
P210
P209
P208
VCC12
VSS
P207
P206
P205
P204
P203
P202
P201
P200
P429
P428
P427
P426
P425
VCC5
TIOB7
TIOA7
TIOB6
TIOA6
SCS43
SCS42
SCS41
SCS40
SCK4
SOT4
SIN4
FRCK7
FRCK6
FRCK5
FRCK4
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
MONCLK MM
TIOB9
TIOA9
TIOB8
TIOA8
AN15
AN14
AN13
AN12
AN11
AN10
AN9
AN8
AN23
AN22
AN21
AN20
AN19
AN18
AN17
AN16
TIOB11
TIOA11
TIOB10
TIOA10
ADTG0
AN31
AN30
AN29
AN28
AN27
AN26
AN25
AN24
IN5
IN4
IN3
IN2
IN1
IN0
INT7
MB9D560 Series
208 Pin Part Number without RDC
TOP VIEW
LER208
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VSS
VCC12
P423
P422
P421
P100
P101
P102
P103
P104
P105
P106
VCC5
VSS
P107
P108
P109
P110
AVRH1
AVRL1
AVR1
AVSS1
AVCC1
P111
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
RVRH1
RVRL1
RVR1
RVSS1
RVCC1
P126
P127
P128
P129
P431
P131
P420
P419
VCC5
SCK3
SOT3
SIN3
DTTI1
RTO6
RTO7
RTO8
RTO9
RTO10
RTO11
INT6
4ADTG1
FRCK10
FRCK9
FRCK8
IN14
IN13
4AN4
4AN5
4AN6
4AN7
ZIN2
BIN2
AIN2
ZIN3
BIN3
AIN3
DAOUT1
ERDS1
SCK2
SOT2
SIN2
INT5
Page 8 of 91
MB9D560 Series
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
MONCLK
AN15
AN14
AN13
AN12
AN11
AN10
AN9
AN8
MM
TIOB7
TIOA7
TIOB6
TIOA6
AN23
AN22
AN21
AN20
AN19
AN18
AN17
AN16
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VCC5
P300
P231
P230
P229
P228
P227
P226
P225
P224
VSS
VCC12
P223
P222
P221
P220
P219
P218
P217
P216
AVRH2
AVRL2
AVSS2
AVCC2
P215
P214
P213
P212
P211
P210
P209
P208
VCC12
VSS
P207
P206
P205
P204
P203
P202
P201
P200
P429
VCC5
ADTG0
AN31
AN30
AN29
AN28
AN27
AN26
AN25
AN24
SCS43
SCS42
SCS41
SCS40
SCK4
SOT4
SIN4
IN5
IN4
IN3
IN2
IN1
IN0
INT7
176 Pin Part Number with RDC
4ADTG0
DTTI0
RTO0
RTO1
RTO2
RTO3
RTO4
RTO5
4AN0
4AN1
4AN2
4AN3
ZIN0
BIN0
AIN0
ZIN1
BIN1
AIN1
RDC_W0
RDC_V0
RDC_U0
RDC_Z0
RDC_B0
RDC_A0
P026
ERDS0
VSS
VCC12
P000
P001
P002
P003
P004
P005
P006
P007
P008
P009
P010
AVRH0
AVRL0
AVR0
AVSS0
AVCC0
P011
P012
P013
P014
P015
P016
AREF20
SIN_IN0
COS_IN0
SIN_OUT0
SIN_MINUS0
SIN_PLUS0
COS_PLUS0
COS_MINUS0
COS_OUT0
RVRH0
RVRL0
RVR0
RVSS0
RVCC0
RDC_ACT0
MAG_MINUS0
MAG_PLUS0
MAG_OUT0
P430
VCC5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
TOP VIEW
LEP176
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VSS
VCC12
P100
P101
P102
P103
P104
P105
P106
P107
P108
P109
P110
AVRH1
AVRL1
AVR1
AVSS1
AVCC1
P111
P112
P113
P114
P115
P116
AREF21
SIN_IN1
COS_IN1
SIN_OUT1
SIN_MINUS1
SIN_PLUS1
COS_PLUS1
COS_MINUS1
COS_OUT1
RVRH1
RVRL1
RVR1
RVSS1
RVCC1
RDC_ACT1
MAG_MINUS1
MAG_PLUS1
MAG_OUT1
P431
VCC5
DTTI1
RTO6
RTO7
RTO8
RTO9
RTO10
RTO11
4AN4
4AN5
4AN6
4AN7
4ADTG1
RDC_W1
RDC_V1
RDC_U1
RDC_Z1
RDC_B1
RDC_A1
ZIN2
BIN2
AIN2
ZIN3
BIN3
AIN3
P126
ERDS1
Document Number: 002-05679 Rev.*A
IN16
IN17
IN18
IN19
IN20
IN21
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
TIOA3
TIOB3
DTTI3
RTO18
RTO19
RTO20
RTO21
RTO22
RTO23
INT3 SIN0
SOT0
SCK0
VSS
P314
P315
P316
P317
P318
P319
P320
P321
P322
P323
VCC12
VSS
IN6
STOPWT P324
IN7
RXDA
P325
IN8
TXDA
P326
IN9
TXE NA P327
IN10 RXDB
P328
IN11 TXDB
P329
IN12 TXE NB P330
NMIX
RSTX
MD1
MD0
X0
X1
VSS
TRSTX
TCK
TDO
TDI
TMS
nSRST
INT4 SIN1
P406
SOT1
P407
SCK1
P408
INT0 RX0
P409
TX0
P410
INT1 RX1
P411
TX1
P412
INT2 RX2
P413
TX2
P414
VCC12
VSS
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
Page 9 of 91
DAOUT0
ERDS0
Document Number: 002-05679 Rev.*A
INT2
INT1
ZIN0
BIN0
AIN0
ZIN1
BIN1
AIN1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
INT0
VSS
VCC12
P000
P001
P002
P003
P004
P005
P006
P007
P008
P009
P010
AVRH0
AVRL0
AVR0
AVSS0
AVCC0
P011
P012
P013
P014
P015
P016
P017
P018
P019
P020
P021
P022
P023
P024
P025
RVRH0
RVRL0
RVR0
RVSS0
RVCC0
P026
P027
P028
P029
P430
VCC5
INT4
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
DTTI0
RTO0
RTO1
RTO2
RTO3
RTO4
RTO5
4AN0
4AN1
4AN2
4AN3
IN6
IN7
IN8
IN9
IN10
IN11
IN12
VSS
P314
P315
P316
P317
P318
P319
P320
P321
P322
P323
VCC12
VSS
STOPWT P324
RXDA
P325
TXDA
P326
TXE NA
P327
RXDB
P328
TXDB
P329
TXE NB
P330
NMIX
RSTX
MD1
MD0
X0
X1
VSS
TRSTX
TCK
TDO
TDI
TMS
nSRST
SIN1
P406
SOT1
P407
SCK1
P408
RX0
P409
TX0
P410
RX1
P411
TX1
P412
RX2
P413
TX2
P414
VCC12
VSS
DTTI3
RTO18
RTO19
RTO20
RTO21
RTO22
RTO23
SIN0
SOT0
SCK0
4ADTG0
IN16
IN17
IN18
IN19
IN20
IN21
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
TIOA3
TIOB3 INT3
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VCC5
P300
P231
P230
P229
P228
P227
P226
P225
P224
VSS
VCC12
P223
P222
P221
P220
P219
P218
P217
P216
AVRH2
AVRL2
AVSS2
AVCC2
P215
P214
P213
P212
P211
P210
P209
P208
VCC12
VSS
P207
P206
P205
P204
P203
P202
P201
P200
P429
VCC5
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
MONCLK
AN15
AN14
AN13
AN12
AN11
AN10
AN9
AN8
AN23
AN22
AN21
AN20
AN19
AN18
AN17
AN16
ADTG0
AN31
AN30
AN29
AN28
AN27
AN26
AN25
AN24
MM
TIOB7
TIOA7
TIOB6
TIOA6
SCS43
SCS42
SCS41
SCS40
SCK4
SOT4
SIN4
IN5
IN4
IN3
IN2
IN1
IN0
INT7
MB9D560 Series
176 Pin Part Number without RDC
TOP VIEW
LEP176
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VSS
VCC12
P100
P101
P102
P103
P104
P105
P106
P107
P108
P109
P110
AVRH1
AVRL1
AVR1
AVSS1
AVCC1
P111
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
RVRH1
RVRL1
RVR1
RVSS1
RVCC1
P126
P127
P128
P129
P431
VCC5
DTTI1
RTO6
RTO7
RTO8
RTO9
RTO10
RTO11
4AN4
4AN5
4AN6
4AN7
4ADTG1
ZIN2
BIN2
AIN2
ZIN3
BIN3
AIN3
DAOUT1
ERDS1
Page 10 of 91
MB9D560 Series
3. Pin Description
Part Number with RDC
Pin Number
208 pin 176 pin
3
-
4
-
5
3
6
4
7
5
8
6
9
7
10
8
11
9
14
10
15
11
16
12
17
13
23
19
24
20
25
21
26
22
27
23
28
24
29
30
31
32
33
34
35
36
37
25
26
27
28
29
30
31
32
33
43
39
44
40
Pin Name
P305
FRCK0
P306
FRCK1
P000
DTTI0
4ADTG0
P001
RTO0
P002
RTO1
P003
RTO2
P004
RTO3
P005
RTO4
P006
RTO5
P007
4AN0
P008
4AN1
P009
4AN2
P010
4AN3
P011
RDC_W0
ZIN0
P012
RDC_V0
BIN0
P013
RDC_U0
AIN0
P014
RDC_Z0
ZIN1
P015
RDC_B0
BIN1
P016
RDC_A0
AIN1
AREF20
SIN_IN0
COS_IN0
SIN_OUT0
SIN_MINUS0
SIN_PLUS0
COS_PLUS0
COS_MINUS0
COS_OUT0
RDC_ACT0
P026
MAG_MINUS0
Document Number: 002-05679 Rev.*A
I/O Circuit
Type
E
E
E
E
E
E
E
E
E
F
F
F
F
E
E
E
E
E
E
L
K
K
L
K
K
K
K
L
E
K
Functions
General-purpose I/O port
16-bit free-run timer ch.0 external clock input pin
General-purpose I/O port
16-bit free-run timer ch.1 external clock input pin
General-purpose I/O port
Waveform generator output stop signal input pin 0
4ch sample-hold A/D converter unit0 external trigger input pin
General-purpose I/O port
Waveform generator ch.0 output pin
General-purpose I/O port
Waveform generator ch.1 output pin
General-purpose I/O port
Waveform generator ch.2 output pin
General-purpose I/O port
Waveform generator ch.3 output pin
General-purpose I/O port
Waveform generator ch.4 output pin
General-purpose I/O port
Waveform generator ch.5 output pin
General-purpose I/O port
4ch sample-hold A/D converter unit0 analog 0 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit0 analog 1 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit0 analog 2 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit0 analog 3 input pin
General-purpose I/O port
R/D converter unit0 W-phase output pin
Up/Down counter ch.0 ZIN input pin
General-purpose I/O port
R/D converter unit0 V-phase output pin
Up/Down counter ch.0 BIN input pin
General-purpose I/O port
R/D converter unit0 U-phase output pin
Up/Down counter ch.0 AIN input pin
General-purpose I/O port
R/D converter unit0 Z-phase output pin
Up/Down counter ch.1 ZIN input pin
General-purpose I/O port
R/D converter unit0 B-phase output pin
Up/Down counter ch.1 BIN input pin
General-purpose I/O port
R/D converter unit0 A-phase output pin
Up/Down counter ch.1 AIN input pin
R/D converter unit0 Aref output pin(RVCC0/2)
R/D converter unit0 SIN coil earth leakage detection input pin
R/D converter unit0 COS coil earth leakage detection input pin
R/D converter unit0 SIN output pin
R/D converter unit0 SIN input pinR/D converter unit0 SIN input pin+
R/D converter unit0 COS input pin+
R/D converter unit0 COS input pinR/D converter unit0 COS output pin
R/D converter unit0 operation status output pin
General-purpose I/O port
R/D converter unit0 excitation external input pinPage 11 of 91
MB9D560 Series
Pin Number
208 pin 176 pin
45
46
41
42
47
43
48
-
49
-
50
-
51
-
55
-
56
-
57
-
58
46
59
47
60
48
61
49
62
50
63
51
64
52
65
53
66
54
67
55
70
58
71
59
Pin Name
MAG_PLUS0
MAG_OUT0
P430
ERDS0
P030
DTTI2
FRCK12
P031
RTO12
FRCK13
P309
RTO13
FRCK14
P310
RTO14
FRCK15
P311
RTO15
FRCK16
P312
RTO16
FRCK17
P313
RTO17
P314
DTTI3
TIOA0
P315
RTO18
TIOB0
P316
RTO19
TIOA1
P317
RTO20
TIOB1
P318
RTO21
TIOA2
P319
RTO22
TIOB2
P320
RTO23
TIOA3
P321
SIN0
INT3
TIOB3
P322
SOT0
P323
SCK0
P324
STOPWT
IN6
IN16
P325
RXDA
IN7
IN17
Document Number: 002-05679 Rev.*A
I/O Circuit
Type
K
L
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
H
Functions
R/D converter unit0 excitation external input pin+
R/D converter unit0 excitation signal output pin
General-purpose I/O port
Error detection output pin ch.0
General-purpose I/O port
Waveform generator output stop signal input pin 2
16-bit free-run timer ch.12 external clock input pin
General-purpose I/O port
Waveform generator ch.12 output pin
16-bit free-run timer ch.13 external clock input pin
General-purpose I/O port
Waveform generator ch.13 output pin
16-bit free-run timer ch.14 external clock input pin
General-purpose I/O port
Waveform generator ch.14 output pin
16-bit free-run timer ch.15 external clock input pin
General-purpose I/O port
Waveform generator ch.15 output pin
16-bit free-run timer ch.16 external clock input pin
General-purpose I/O port
Waveform generator ch.16 output pin
16-bit free-run timer ch.17 external clock input pin
General-purpose I/O port
Waveform generator ch.17 output pin
General-purpose I/O port
Waveform generator output stop signal input pin 3
Base timer ch.0 TIOA output pin
General-purpose I/O port
Waveform generator ch.18 output pin
Base timer ch.0 TIOB input pin
General-purpose I/O port
Waveform generator ch.19 output pin
Base timer ch.1 TIOA I/O pin
General-purpose I/O port
Waveform generator ch.20 output pin
Base timer ch.1 TIOB input pin
General-purpose I/O port
Waveform generator ch.21 output pin
Base timer ch.2 TIOA output pin
General-purpose I/O port
Waveform generator ch.22 output pin
Base timer ch.2 TIOB input pin
General-purpose I/O port
Waveform generator ch.23 output pin
Base timer ch.3 TIOA I/O pin
General-purpose I/O port
Multi-function serial interface ch.0 serial data input pin
INT3 external interrupt input pin
Base timer ch.3 TIOB input pin
General-purpose I/O port
Multi-function serial interface ch.0 serial data output pin
General-purpose I/O port
Multi-function serial interface ch.0 clock I/O pin
General-purpose I/O port
FlexRay stop watch input pin
16-bit input capture ch.6 external pulse input pin
32-bit input capture ch.0 external pulse input pin
General-purpose I/O port
FlexRay ch.A data input pin
16-bit input capture ch.7 external pulse input pin
32-bit input capture ch.1 external pulse input pin
Page 12 of 91
MB9D560 Series
Pin Number
208 pin 176 pin
72
60
73
61
74
62
75
63
76
64
77
78
79
80
81
82
84
85
86
87
88
89
65
66
67
68
69
70
72
73
74
75
76
77
90
78
91
79
92
80
93
81
94
82
95
83
96
84
97
85
98
86
99
-
100
-
101
-
Pin Name
P326
TXDA
IN8
IN18
P327
TXENA
IN9
IN19
P328
RXDB
IN10
IN20
P329
TXDB
IN11
IN21
P330
TXENB
IN12
NMIX
RSTX
MD1
MD0
X0
X1
TRSTX
TCK
TDO
TDI
TMS
nSRST
P406
SIN1
INT4
P407
SOT1
P408
SCK1
P409
RX0
INT0
P410
TX0
P411
RX1
INT1
P412
TX1
P413
RX2
INT2
P414
TX2
P415
TIOA4
P416
TIOB4
P417
TIOA5
Document Number: 002-05679 Rev.*A
I/O Circuit
Type
H
H
H
H
H
B
B
C
C
A
J
J
I
J
J
J
E
E
E
E
E
E
E
E
E
E
E
E
Functions
General-purpose I/O port
FlexRay ch.A data output pin
16-bit input capture ch.8 external pulse input pin
32-bit input capture ch.2 external pulse input pin
General-purpose I/O port
FlexRay ch.A operation enable output pin
16-bit input capture ch.9 external pulse input pin
32-bit input capture ch.3 external pulse input pin
General-purpose I/O port
FlexRay ch.B data input pin
16-bit input capture ch.10 external pulse input pin
32-bit input capture ch.4 external pulse input pin
General-purpose I/O port
FlexRay ch.B data output pin
16-bit input capture ch.11 external pulse input pin
32-bit input capture ch.5 external pulse input pin
General-purpose I/O port
FlexRay ch.B operation enable output pin
16-bit input capture ch.12 external pulse input pin
Non-maskable interrupt input pin
External reset input pin
Mode pin 1 (with high-voltage control)
Mode pin 0 (with high-voltage control)
Main clock oscillation input pin
Main clock oscillation output pin
JTAG test reset input
JTAG test clock input
JTAG test data output
JTAG test data input
JTAG test mode status input
System reset input for debugger
General-purpose I/O port
Multi-function serial interface ch.1 serial data input pin
INT4 external interrupt input pin
General-purpose I/O port
Multi-function serial interface ch.1 serial data output pin
General-purpose I/O port
Multi-function serial interface ch.1 clock I/O pin
General-purpose I/O port
CAN ch.0 reception data input pin
INT0 external interrupt input pin
General-purpose I/O port
CAN ch.0 transmission data output pin
General-purpose I/O port
CAN ch.1 reception data input pin
INT1 external interrupt input pin
General-purpose I/O port
CAN ch.1 transmission data output pin
General-purpose I/O port
CAN ch.2 reception data input pin
INT2 external interrupt input pin
General-purpose I/O port
CAN ch.2 transmission data output pin
General-purpose I/O port
Base timer ch.4 TIOA output pin
General-purpose I/O port
Base timer ch.4 TIOB input pin
General-purpose I/O port
Base timer ch.5 TIOA I/O pin
Page 13 of 91
MB9D560 Series
Pin Number
208 pin 176 pin
102
-
106
-
107
-
108
-
109
90
110
111
112
91
92
93
113
94
119
120
121
122
123
124
125
126
127
100
101
102
103
104
105
106
107
108
128
109
129
110
130
111
131
112
132
113
133
114
139
120
140
121
141
122
142
123
145
124
146
125
147
126
148
127
Pin Name
P418
TIOB5
P419
SIN2
INT5
P420
SOT2
P131
SCK2
P431
ERDS1
MAG_OUT1
MAG_PLUS1
MAG_MINUS1
RDC_ACT1
P126
COS_OUT1
COS_MINUS1
COS_PLUS1
SIN_PLUS1
SIN_MINUS1
SIN_OUT1
COS_IN1
SIN_IN1
AREF21
P116
RDC_A1
AIN3
P115
RDC_B1
BIN3
P114
RDC_Z1
ZIN3
P113
RDC_U1
AIN2
P112
RDC_V1
BIN2
P111
RDC_W1
ZIN2
P110
4AN7
P109
4AN6
P108
4AN5
P107
4AN4
P106
RTO11
P105
RTO10
P104
RTO9
P103
RTO8
Document Number: 002-05679 Rev.*A
I/O Circuit
Type
E
E
E
E
E
L
K
K
E
L
K
K
K
K
L
K
K
L
E
E
E
E
E
E
F
F
F
F
E
E
E
E
Functions
General-purpose I/O port
Base timer ch.5 TIOB input pin
General-purpose I/O port
Multi-function serial interface ch.2 serial data input pin
INT5 external interrupt input pin
General-purpose I/O port
Multi-function serial interface ch.2 serial data output pin
General-purpose I/O port
Multi-function serial interface ch.2 clock I/O pin
General-purpose I/O port
Error detection output pin ch.1
R/D converter unit1excitation signal output pin
R/D converter unit1excitation external input pin+
R/D converter unit1excitation external input pinR/D converter unit1 operation status output pin
General-purpose I/O port
R/D converter unit1 COS output pin
R/D converter unit1 COS input pinR/D converter unit1 COS input pin+
R/D converter unit1 SIN input pin+
R/D converter unit1 SIN input pinR/D converter unit1 SIN output pin
R/D converter unit1 COS coil earth leakage detection input pin
R/D converter unit1 SIN coil earth leakage detection input pin
R/D converter unit1 Aref output pin(RVCC1/2)
General-purpose I/O port
R/D converter unit1 A phase output pin
Up/Down counter ch.3 AIN input pin
General-purpose I/O port
R/D converter unit1 B phase output pin
Up/Down counter ch.3 BIN input pin
General-purpose I/O port
R/D converter unit1 Z phase output pin
Up/Down counter ch.3 ZIN input pin
General-purpose I/O port
R/D converter unit1 U phase output pin
Up/Down counter ch.2 AIN input pin
General-purpose I/O port
R/D converter unit1 V phase output pin
Up/Down counter ch.2 BIN input pin
General-purpose I/O port
R/D converter unit1 W phase output pin
Up/Down counter ch.2 ZIN input pin
General-purpose I/O port
4ch sample-hold A/D converter unit1 analog 7 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit1 analog 6 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit1 analog 5 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit1 analog 4 input pin
General-purpose I/O port
Waveform generator ch.11 output pin
General-purpose I/O port
Waveform generator ch.10 output pin
General-purpose I/O port
Waveform generator ch.9 output pin
General-purpose I/O port
Waveform generator ch.8 output pin
Page 14 of 91
MB9D560 Series
Pin Number
208 pin 176 pin
149
128
150
129
151
130
152
-
153
-
154
-
158
-
159
-
160
-
161
-
162
134
163
135
164
136
165
137
166
138
167
139
168
140
169
141
170
142
173
145
174
146
175
147
176
148
177
149
178
150
179
151
Pin Name
P102
RTO7
P101
RTO6
P100
DTTI1
4ADTG1
P421
SIN3
INT6
FRCK8
P422
SOT3
FRCK9
IN13
P423
SCK3
FRCK10
IN14
P425
TIOA8
P426
TIOB8
P427
TIOA9
P428
TIOB9
P429
MONCLK
MM
P200
AN0
P201
AN1
P202
AN2
P203
AN3
P204
AN4
P205
AN5
P206
AN6
P207
AN7
P208
AN8
P209
AN9
P210
AN10
P211
AN11
P212
AN12
P213
AN13
P214
AN14
Document Number: 002-05679 Rev.*A
I/O Circuit
Type
E
E
E
E
E
E
E
E
E
E
E
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
Functions
General-purpose I/O port
Waveform generator ch.7 output pin
General-purpose I/O port
Waveform generator ch.6 output pin
General-purpose I/O port
Waveform generator output stop signal input pin1
4ch sample-hold A/D converter unit1 external trigger input pin
General-purpose I/O port
Multi-function serial interface ch.3 serial data input pin
INT6 external interrupt input pin
16-bit free-run timer ch.8 external clock input pin
General-purpose I/O port
Multi -function serial interface ch.3 serial data output pin
16-bit free-run timer ch.9 external clock input pin
16-bit input capture ch.13 external pulse input pin
General-purpose I/O port
Multi-function serial interface ch.3 clock I/O pin
16-bit free-run timer ch.10 external clock input pin
16-bit input capture ch.14 external pulse input pin
General-purpose I/O port
Base timer ch.8 TIOA output pin
General-purpose I/O port
Base timer ch.8 TIOB input pin
General-purpose I/O port
Base timer ch.9 TIOA I/O pin
General-purpose I/O port
Base timer ch.9 TIOB input pin
General-purpose I/O port
Clock monitor output pin
Clock supervisor main clock error detection output pin
General-purpose I/O port
A/D converter analog 0 input pin
General-purpose I/O port
A/D converter analog 1 input pin
General-purpose I/O port
A/D converter analog 2 input pin
General-purpose I/O port
A/D converter analog 3 input pin
General-purpose I/O port
A/D converter analog 4 input pin
General-purpose I/O port
A/D converter analog 5 input pin
General-purpose I/O port
A/D converter analog 6 input pin
General-purpose I/O port
A/D converter analog 7 input pin
General-purpose I/O port
A/D converter analog 8 input pin
General-purpose I/O port
A/D converter analog 9 input pin
General-purpose I/O port
A/D converter analog 10 input pin
General-purpose I/O port
A/D converter analog 11 input pin
General-purpose I/O port
A/D converter analog 12 input pin
General-purpose I/O port
A/D converter analog 13 input pin
General-purpose I/O port
A/D converter analog 14 input pin
Page 15 of 91
MB9D560 Series
Pin Number
208 pin 176 pin
180
152
185
157
186
158
187
159
188
160
189
161
190
162
191
163
192
164
195
167
196
168
197
169
198
170
199
171
200
172
201
173
202
174
203
175
204
-
205
-
Pin Name
P215
AN15
P216
AN16
P217
AN17
P218
AN18
P219
AN19
P220
AN20
TIOA6
P221
AN21
TIOB6
P222
AN22
TIOA7
P223
AN23
TIOB7
P224
AN24
P225
AN25
SIN4
INT7
P226
AN26
SOT4
IN0
P227
AN27
SCK4
IN1
P228
AN28
SCS40
IN2
P229
AN29
SCS41
IN3
P230
AN30
SCS42
IN4
P231
AN31
SCS43
IN5
P300
ADTG0
P301
TIOA10
FRCK4
P302
TIOB10
FRCK5
Document Number: 002-05679 Rev.*A
I/O Circuit
Type
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
E
E
E
Functions
General-purpose I/O port
A/D converter analog 15 input pin
General-purpose I/O port
A/D converter analog 16 input pin
General-purpose I/O port
A/D converter analog 17 input pin
General-purpose I/O port
A/D converter analog 18 input pin
General-purpose I/O port
A/D converter analog 19 input pin
General-purpose I/O port
A/D converter analog 20 input pin
Base timer ch.6 TIOA output pin
General-purpose I/O port
A/D converter analog 21 input pin
Base timer ch.6 TIOB input pin
General-purpose I/O port
A/D converter analog 22 input pin
Base timer ch.7 TIOA I/O pin
General-purpose I/O port
A/D converter analog 23 input pin
Base timer ch.7 TIOB input pin
General-purpose I/O port
A/D converter Analog 24 input pin
General-purpose I/O port
A/D converter analog 25 input pin
Multi-function serial interface ch.4 serial data input pin
INT7 external interrupt input pin
General-purpose I/O port
A/D converter analog 26 input pin
Multi-function serial interface ch.4 serial data output pin
16-bit input capture ch.0 external pulse input pin
General-purpose I/O port
A/D converter analog 27 input pin
Multi-function serial interface ch.4 clock I/O pin
16-bit input capture ch.1 external pulse input pin
General-purpose I/O port
A/D converter analog 28 input pin
Multi-function serial interface ch.4 serial chip select 0 I/O pin
16-bit input capture ch.2 external pulse input pin
General-purpose I/O port
A/D converter analog 29 input pin
Multi-function serial interface ch.4 serial chip select 1 I/O pin
16-bit input capture ch.3 external pulse input pin
General-purpose I/O port
A/D converter analog 30 input pin
Multi-function serial interface ch.4 serial chip select 2 I/O pin
16-bit input capture ch.4 external pulse input pin
General-purpose I/O port
A/D converter analog 31 input pin
Multi-function serial interface ch.4 serial chip select 3 I/O pin
16-bit input capture ch.5 external pulse input pin
General-purpose I/O port
A/D converter external trigger input pin
General-purpose I/O port
Base timer ch.10 TIOA output pin
16-bit free-run timer ch.4 external clock input pin
General-purpose I/O port
Base timer ch.10 TIOB input pin
16-bit free-run timer ch.5 external clock input pin
Page 16 of 91
MB9D560 Series
Pin Number
208 pin 176 pin
206
-
207
-
18
19
20
21
22
134
135
136
137
138
38
39
40
41
42
114
115
116
117
118
181
182
183
184
2
54
68
103
155
172
193
12
52
105
144
157
208
1
13
53
69
83
104
143
156
171
194
14
15
16
17
18
115
116
117
118
119
34
35
36
37
38
95
96
97
98
99
153
154
155
156
Pin Name
P303
TIOA11
FRCK6
P304
TIOB11
FRCK7
AVRH0
AVRL0
AVR0
AVSS0
AVCC0
AVCC1
AVSS1
AVR1
AVRL1
AVRH1
RVRH0
RVRL0
RVR0
RVSS0
RVCC0
RVCC1
RVSS1
RVR1
RVRL1
RVRH1
AVCC2
AVSS2
AVRL2
AVRH2
I/O Circuit
Type
Functions
-
General-purpose I/O port
Base timer ch.11 TIOA I/O pin
16-bit free-run timer ch.6 external clock input pin
General-purpose I/O port
Base timer ch.11 TIOB input pin
16-bit free-run timer ch.7 external clock input pin
4ch sample-hold A/D converter unit0 upper limit reference voltage
4ch sample-hold A/D converter unit0 lower limit reference voltage
4ch sample-hold A/D converter unit0 reference voltage
4ch sample-hold A/D converter unit0 analog GND
4ch sample-hold A/D converter unit0 analog power supply
4ch sample-hold A/D converter unit1 analog power supply
4ch sample-hold A/D converter unit1 analog GND
4ch sample-hold A/D converter unit1 reference voltage
4ch sample-hold A/D converter unit1 lower limit reference voltage
4ch sample-hold A/D converter unit1 upper limit reference voltage
R/D converter unit0 upper limit reference voltage
R/D converter unit0 lower limit reference voltage
R/D converter unit0 reference voltage
R/D converter unit0 analog GND
R/D converter unit0 analog power supply
R/D converter unit1 analog power supply
R/D converter unit1 analog GND
R/D converter unit1 reference voltage
R/D converter unit1 lower limit reference voltage
R/D converter unit1 upper limit reference voltage
A/D converter analog power supply
A/D converter analog GND
A/D converter lower limit reference voltage
A/D converter upper limit reference voltage
E
E
2
56
87
131
144
165
VCC12
-
1.2V power supply
44
89
133
176
VCC5
-
5.0V power supply
1
45
57
71
88
132
143
166
VSS
-
GND
Document Number: 002-05679 Rev.*A
Page 17 of 91
MB9D560 Series
Part Number without RDC
Pin Number
208pin
176pin
3
-
4
-
5
3
6
4
7
5
8
6
9
7
10
8
11
9
14
10
15
11
16
12
17
13
23
19
24
20
25
21
26
22
27
23
28
24
29
30
31
32
33
34
35
36
37
43
44
45
25
26
27
28
29
30
31
32
33
39
40
41
46
42
47
43
48
-
Pin Name
P305
FRCK0
P306
FRCK1
P000
DTTI0
4ADTG0
P001
RTO0
P002
RTO1
P003
RTO2
P004
RTO3
P005
RTO4
P006
RTO5
P007
4AN0
P008
4AN1
P009
4AN2
P010
4AN3
P011
ZIN0
P012
BIN0
P013
AIN0
P014
ZIN1
P015
BIN1
P016
AIN1
P017
P018
P019
P020
P021
P022
P023
P024
P025
P026
P027
P028
P029
DAOUT0
P430
ERDS0
P030
DTTI2
FRCK12
Document Number: 002-05679 Rev.*A
I/O Circuit
Type
E
E
E
E
E
E
E
E
E
F
F
F
F
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
G
E
E
Functions
General-purpose I/O port
16-bit free-run timer ch.0 external clock input pin
General-purpose I/O port
16-bit free-run timer ch.1 external clock input pin
General-purpose I/O port
Waveform generator output stop signal input pin 0
4ch sample-hold A/D converter unit0 external trigger input pin
General-purpose I/O port
Waveform generator ch.0 output pin
General-purpose I/O port
Waveform generator ch.1 output pin
General-purpose I/O port
Waveform generator ch.2 output pin
General-purpose I/O port
Waveform generator ch.3 output pin
General-purpose I/O port
Waveform generator ch.4 output pin
General-purpose I/O port
Waveform generator ch.5 output pin
General-purpose I/O port
4ch sample-hold A/D converter unit0 analog 0 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit0 analog 1 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit0 analog 2 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit0 analog 3 input pin
General-purpose I/O port
Up/Down counter ch.0 ZIN input pin
General-purpose I/O port
Up/Down counter ch.0 BIN input pin
General-purpose I/O port
Up/Down counter ch.0 AIN input pin
General-purpose I/O port
Up/Down counter ch.1 ZIN input pin
General-purpose I/O port
Up/Down counter ch.1 BIN input pin
General-purpose I/O port
Up/Down counter ch.1 AIN input pin
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
D/A converter ch.0 analog output pin
General-purpose I/O port
Error detection output pin ch.0
General-purpose I/O port
Waveform generator output stop signal input pin 2
16-bit free-run timer ch.12 external clock input pin
Page 18 of 91
MB9D560 Series
Pin Number
208pin
176pin
49
-
50
-
51
-
55
-
56
-
57
-
58
46
59
47
60
48
61
49
62
50
63
51
64
52
65
53
66
54
67
55
70
58
71
59
72
60
Pin Name
P031
RTO12
FRCK13
P309
RTO13
FRCK14
P310
RTO14
FRCK15
P311
RTO15
FRCK16
P312
RTO16
FRCK17
P313
RTO17
P314
DTTI3
TIOA0
P315
RTO18
TIOB0
P316
RTO19
TIOA1
P317
RTO20
TIOB1
P318
RTO21
TIOA2
P319
RTO22
TIOB2
P320
RTO23
TIOA3
P321
SIN0
INT3
TIOB3
P322
SOT0
P323
SCK0
P324
STOPWT
IN6
IN16
P325
RXDA
IN7
IN17
P326
TXDA
IN8
IN18
Document Number: 002-05679 Rev.*A
I/O Circuit
Type
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
H
H
Functions
General-purpose I/O port
Waveform generator ch.12 output pin
16-bit free-run timer ch.13 external clock input pin
General-purpose I/O port
Waveform generator ch.13 output pin
16-bit free-run timer ch.14 external clock input pin
General-purpose I/O port
Waveform generator ch.14 output pin
16-bit free-run timer ch.15 external clock input pin
General-purpose I/O port
Waveform generator ch.15 output pin
16-bit free-run timer ch.16 external clock input pin
General-purpose I/O port
Waveform generator ch.16 output pin
16-bit free-run timer ch.17 external clock input pin
General-purpose I/O port
Waveform generator ch.17 output pin
General-purpose I/O port
Waveform generator output stop signal input pin 3
Base timer ch.0 TIOA output pin
General-purpose I/O port
Waveform generator ch.18 output pin
Base timer ch.0 TIOB input pin
General-purpose I/O port
Waveform generator ch.19 output pin
Base timer ch.1 TIOA I/O pin
General-purpose I/O port
Waveform generator ch.20 output pin
Base timer ch.1 TIOB input pin
General-purpose I/O port
Waveform generator ch.21 output pin
Base timer ch.2 TIOA output pin
General-purpose I/O port
Waveform generator ch.22 output pin
Base timer ch.2 TIOB input pin
General-purpose I/O port
Waveform generator ch.23 output pin
Base timer ch.3 TIOA I/O pin
General-purpose I/O port
Multi-function serial interface ch.0 serial data input pin
INT3 external interrupt input pin
Base timer ch.3 TIOB input pin
General-purpose I/O port
Multi-function serial interface ch.0 serial data output pin
General-purpose I/O port
Multi-function serial interface ch.0 clock I/O pin
General-purpose I/O port
FlexRay stop watch input pin
16-bit input capture ch.6 external pulse input pin
32-bit input capture ch.0 external pulse input pin
General-purpose I/O port
FlexRay ch.A data input pin
16-bit input capture ch.7 external pulse input pin
32-bit input capture ch.1 external pulse input pin
General-purpose I/O port
FlexRay ch.A data output pin
16-bit input capture ch.8 external pulse input pin
32-bit input capture ch.2 external pulse input pin
Page 19 of 91
MB9D560 Series
Pin Number
208pin
176pin
73
61
74
62
75
63
76
64
77
78
79
80
81
82
84
85
86
87
88
89
65
66
67
68
69
70
72
73
74
75
76
77
90
78
91
79
92
80
93
81
94
82
95
83
96
84
97
85
98
86
99
-
100
-
101
-
102
-
106
-
Pin Name
P327
TXENA
IN9
IN19
P328
RXDB
IN10
IN20
P329
TXDB
IN11
IN21
P330
TXENB
IN12
NMIX
RSTX
MD1
MD0
X0
X1
TRSTX
TCK
TDO
TDI
TMS
nSRST
P406
SIN1
INT4
P407
SOT1
P408
SCK1
P409
RX0
INT0
P410
TX0
P411
RX1
INT1
P412
TX1
P413
RX2
INT2
P414
TX2
P415
TIOA4
P416
TIOB4
P417
TIOA5
P418
TIOB5
P419
SIN2
INT5
Document Number: 002-05679 Rev.*A
I/O Circuit
Type
H
H
H
H
B
B
C
C
A
J
J
I
J
J
J
E
E
E
E
E
E
E
E
E
E
E
E
E
E
Functions
General-purpose I/O port
FlexRay ch.A operation enable output pin
16-bit input capture ch.9 external pulse input pin
32-bit input capture ch.3 external pulse input pin
General-purpose I/O port
FlexRay ch.B data input pin
16-bit input capture ch.10 external pulse input pin
32-bit input capture ch.4 external pulse input pin
General-purpose I/O port
FlexRay ch.B data output pin
16-bit input capture ch.11 external pulse input pin
32-bit input capture ch.5 external pulse input pin
General-purpose I/O port
FlexRay ch.B operation enable output pin
16-bit input capture ch.12 external pulse input pin
Non-maskable interrupt input pin
External reset input pin
Mode pin 1 (with high-voltage control)
Mode pin 0 (with high-voltage control)
Main clock oscillation input pin
Main clock oscillation output pin
JTAG test reset input
JTAG test clock input
JTAG test data output
JTAG test data input
JTAG test mode status input
System reset input for debugger
General-purpose I/O port
Multi-function serial interface ch.1 serial data input pin
INT4 external interrupt input pin
General-purpose I/O port
Multi-function serial interface ch.1 serial data output pin
General-purpose I/O port
Multi-function serial interface ch.1 clock I/O pin
General-purpose I/O port
CAN ch.0 reception data input pin
INT0 external interrupt input pin
General-purpose I/O port
CAN ch.0 transmission data output pin
General-purpose I/O port
CAN ch.1 reception data input pin
INT1 external interrupt input pin
General-purpose I/O port
CAN ch.1 transmission data output pin
General-purpose I/O port
CAN ch.2 reception data input pin
INT2 external interrupt input pin
General-purpose I/O port
CAN ch.2 transmission data output pin
General-purpose I/O port
Base timer ch.4 TIOA output pin
General-purpose I/O port
Base timer ch.4 TIOB input pin
General-purpose I/O port
Base timer ch.5 TIOA I/O pin
General-purpose I/O port
Base timer ch.5 TIOB input pin
General-purpose I/O port
Multi-function serial interface ch.2 serial data input pin
INT5 external interrupt input pin
Page 20 of 91
MB9D560 Series
Pin Number
208pin
176pin
107
-
108
-
109
90
110
91
111
112
113
119
120
121
122
123
124
125
126
127
92
93
94
100
101
102
103
104
105
106
107
108
128
109
129
110
130
111
131
112
132
113
133
114
139
120
140
121
141
122
142
123
145
124
146
125
147
126
148
127
149
128
150
129
151
130
152
-
Pin Name
P420
SOT2
P131
SCK2
P431
ERDS1
P129
DAOUT1
P128
P127
P126
P125
P124
P123
P122
P121
P120
P119
P118
P117
P116
AIN3
P115
BIN3
P114
ZIN3
P113
AIN2
P112
BIN2
P111
ZIN2
P110
4AN7
P109
4AN6
P108
4AN5
P107
4AN4
P106
RTO11
P105
RTO10
P104
RTO9
P103
RTO8
P102
RTO7
P101
RTO6
P100
DTTI1
4ADTG1
P421
SIN3
INT6
FRCK8
Document Number: 002-05679 Rev.*A
I/O Circuit
Type
E
E
E
G
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
F
F
F
F
E
E
E
E
E
E
E
E
Functions
General-purpose I/O port
Multi-function serial interface ch.2 serial data output pin
General-purpose I/O port
Multi-function serial interface ch.2 clock I/O pin
General-purpose I/O port
Error detection output pin ch.1
General-purpose I/O port
D/A converter ch.1 analog output pin
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
Up/Down counter ch.3 AIN input pin
General-purpose I/O port
Up/Down counter ch.3 BIN input pin
General-purpose I/O port
Up/Down counter ch.3 ZIN input pin
General-purpose I/O port
Up/Down counter ch.2 AIN input pin
General-purpose I/O port
Up/Down counter ch.2 BIN input pin
General-purpose I/O port
Up/Down counter ch.2 ZIN input pin
General-purpose I/O port
4ch sample-hold A/D converter unit1 analog 7 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit1 analog 6 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit1 analog 5 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit1 analog 4 input pin
General-purpose I/O port
Waveform generator ch.11 output pin
General-purpose I/O port
Waveform generator ch.10 output pin
General-purpose I/O port
Waveform generator ch.9 output pin
General-purpose I/O port
Waveform generator ch.8 output pin
General-purpose I/O port
Waveform generator ch.7 output pin
General-purpose I/O port
Waveform generator ch.6 output pin
General-purpose I/O port
Waveform generator output stop signal input pin 1
4ch sample-hold A/D converter unit1 external trigger input pin
General-purpose I/O port
Multi-function serial interface ch.3 serial data input pin
INT6 external interrupt input pin
16-bit free-run timer ch.8 external clock input pin
Page 21 of 91
MB9D560 Series
Pin Number
208pin
176pin
153
-
154
-
158
-
159
-
160
-
161
-
162
134
163
135
164
136
165
137
166
138
167
139
168
140
169
141
170
142
173
145
174
146
175
147
176
148
177
149
178
150
179
151
180
152
185
157
186
158
187
159
188
160
Pin Name
P422
SOT3
FRCK9
IN13
P423
SCK3
FRCK10
IN14
P425
TIOA8
P426
TIOB8
P427
TIOA9
P428
TIOB9
P429
MONCLK
MM
P200
AN0
P201
AN1
P202
AN2
P203
AN3
P204
AN4
P205
AN5
P206
AN6
P207
AN7
P208
AN8
P209
AN9
P210
AN10
P211
AN11
P212
AN12
P213
AN13
P214
AN14
P215
AN15
P216
AN16
P217
AN17
P218
AN18
P219
AN19
Document Number: 002-05679 Rev.*A
I/O Circuit
Type
E
E
E
E
E
E
E
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
Functions
General-purpose I/O port
Multi -function serial interface ch.3 serial data output pin
16-bit free-run timer ch.9 external clock input pin
16-bit input capture ch.13 external pulse input pin
General-purpose I/O port
Multi-function serial interface ch.3 clock I/O pin
16-bit free-run timer ch.10 external clock input pin
16-bit input capture ch.14 external pulse input pin
General-purpose I/O port
Base timer ch.8 TIOA output pin
General-purpose I/O port
Base timer ch.8 TIOB input pin
General-purpose I/O port
Base timer ch.9 TIOA I/O pin
General-purpose I/O port
Base timer ch.9 TIOB input pin
General-purpose I/O port
Clock monitor output pin
Clock supervisor main clock error detection output pin
General-purpose I/O port
A/D converter analog 0 input pin
General-purpose I/O port
A/D converter analog 1 input pin
General-purpose I/O port
A/D converter analog 2 input pin
General-purpose I/O port
A/D converter analog 3 input pin
General-purpose I/O port
A/D converter analog 4 input pin
General-purpose I/O port
A/D converter analog 5 input pin
General-purpose I/O port
A/D converter analog 6 input pin
General-purpose I/O port
A/D converter analog 7 input pin
General-purpose I/O port
A/D converter analog 8 input pin
General-purpose I/O port
A/D converter analog 9 input pin
General-purpose I/O port
A/D converter analog 10 input pin
General-purpose I/O port
A/D converter analog 11 input pin
General-purpose I/O port
A/D converter analog 12 input pin
General-purpose I/O port
A/D converter analog 13 input pin
General-purpose I/O port
A/D converter analog 14 input pin
General-purpose I/O port
A/D converter analog 15 input pin
General-purpose I/O port
A/D converter analog 16 input pin
General-purpose I/O port
A/D converter analog 17 input pin
General-purpose I/O port
A/D converter analog 18 input pin
General-purpose I/O port
A/D converter analog 19 input pin
Page 22 of 91
MB9D560 Series
Pin Number
208pin
176pin
189
161
190
162
191
163
192
164
195
167
196
168
197
169
198
170
199
171
200
172
201
173
202
174
203
175
204
-
205
-
206
-
207
-
18
19
20
21
22
14
15
16
17
18
Pin Name
P220
AN20
TIOA6
P221
AN21
TIOB6
P222
AN22
TIOA7
P223
AN23
TIOB7
P224
AN24
P225
AN25
SIN4
INT7
P226
AN26
SOT4
IN0
P227
AN27
SCK4
IN1
P228
AN28
SCS40
IN2
P229
AN29
SCS41
IN3
P230
AN30
SCS42
IN4
P231
AN31
SCS43
IN5
P300
ADTG0
P301
TIOA10
FRCK4
P302
TIOB10
FRCK5
P303
TIOA11
FRCK6
P304
TIOB11
FRCK7
AVRH0
AVRL0
AVR0
AVSS0
AVCC0
Document Number: 002-05679 Rev.*A
I/O Circuit
Type
F
F
F
F
F
F
F
F
F
F
F
F
E
E
E
E
E
-
Functions
General-purpose I/O port
A/D converter analog 20 input pin
Base timer ch.6 TIOA output pin
General-purpose I/O port
A/D converter analog 21 input pin
Base timer ch.6 TIOB input pin
General-purpose I/O port
A/D converter analog 22 input pin
Base timer ch.7 TIOA I/O pin
General-purpose I/O port
A/D converter analog 23 input pin
Base timer ch.7 TIOB input pin
General-purpose I/O port
A/D converter analog 24 input pin
General-purpose I/O port
A/D converter analog 25 input pin
Multi-function serial interface ch.4 serial data input pin
INT7 external interrupt input pin
General-purpose I/O port
A/D converter analog 26 input pin
Multi-function serial interface ch.4 serial data output pin
16-bit input capture ch.0 external pulse input pin
General-purpose I/O port
A/D converter analog 27 input pin
Multi-function serial interface ch.4 clock I/O pin
16-bit input capture ch.1 external pulse input pin
General-purpose I/O port
A/D converter analog 28 input pin
Multi-function serial interface ch.4 serial chip select 0 I/O pin
16-bit input capture ch.2 external pulse input pin
General-purpose I/O port
A/D converter analog 29 input pin
Multi-function serial interface ch.4 serial chip select 1 I/O pin
16-bit input capture ch.3 external pulse input pin
General-purpose I/O port
A/D converter analog 30 input pin
Multi-function serial interface ch.4 serial chip select 2 I/O pin
16-bit input capture ch.4 external pulse input pin
General-purpose I/O port
A/D converter analog 31 input pin
Multi-function serial interface ch.4 serial chip select 3 I/O pin
16-bit input capture ch.5 external pulse input pin
General-purpose I/O port
A/D converter external trigger input pin
General-purpose I/O port
Base timer ch.10 TIOA output pin
16-bit free-run timer ch.4 external clock input pin
General-purpose I/O port
Base timer ch.10 TIOB input pin
16-bit free-run timer ch.5 external clock input pin
General-purpose I/O port
Base timer ch.11 TIOA I/O pin
16-bit free-run timer ch.6 external clock input pin
General-purpose I/O port
Base timer ch.11 TIOB input pin
16-bit free-run timer ch.7 external clock input pin
4ch sample-hold A/D converter unit0 upper limit reference voltage
4ch sample-hold A/D converter unit0 lower limit reference voltage
4ch sample-hold A/D converter unit0 reference voltage
4ch sample-hold A/D converter unit0 analog GND
4ch sample-hold A/D converter unit0 analog power supply
Page 23 of 91
MB9D560 Series
Pin Number
208pin
176pin
134
135
136
137
138
38
39
40
41
42
114
115
116
117
118
181
182
183
184
2
54
68
103
155
172
193
12
52
105
144
157
208
1
13
53
69
83
104
143
156
171
194
Pin Name
I/O Circuit
Type
Functions
115
116
117
118
119
34
35
36
37
38
95
96
97
98
99
153
154
155
156
AVCC1
AVSS1
AVR1
AVRL1
AVRH1
RVRH0
RVRL0
RVR0
RVSS0
RVCC0
RVCC1
RVSS1
RVR1
RVRL1
RVRH1
AVCC2
AVSS2
AVRL2
AVRH2
-
4ch sample-hold A/D converter unit1 analog power supply
4ch sample-hold A/D converter unit1 analog GND
4ch sample-hold A/D converter unit1 reference voltage
4ch sample-hold A/D converter unit1 lower limit reference voltage
4ch sample-hold A/D converter unit1 upper limit reference voltage
*1
*2
*2
*2
*1
*1
*2
*2
*2
*1
A/D converter analog power supply
A/D converter analog GND
A/D converter lower limit reference voltage
A/D converter upper limit reference voltage
2
56
87
131
144
165
VCC12
-
1.2V power supply
44
89
133
176
VCC5
-
5.0V power supply
1
45
57
71
88
132
143
166
VSS
-
GND
*1: The part number without RDC does not use this pin. Connect it with the VCC5 pin.
*2: The part number without RDC does not use this pin. Connect it with the VSS pin.
Document Number: 002-05679 Rev.*A
Page 24 of 91
MB9D560 Series
4. I/O Circuit Type
Type
Circuit
Remarks
X1
Clock input
A
• Oscillation feedback resistor: Approx. 1 M
X0
Standby control signal
Pull-up resistor
• CMOS hysteresis input
• With 50 k pull-up resistor
B
CMOS hysteresis input
Mode input
N-ch
High withstand voltage mode input
N-ch
C
High withstand voltage control
N-ch
• Schmitt input
• With high withstand voltage control
N-ch
P-ch
Digital output
D
N-ch
• CMOS level output
IOH=-1/-2 mA, IOL=1/2 mA
Pull-up control
P-ch
P-ch
Digital output
N-ch
E
R
CMOS hysteresis input
• General-purpose I/O port
• CMOS level output
IOH=-1/-2 mA, IOL=1/2 mA
• With 50 k pull-up resistor
• CMOS hysteresis input (0.7Vcc/0.3Vcc)
• Automotive input (0.8Vcc/0.5Vcc)
Automotive input
Standby control
Document Number: 002-05679 Rev.*A
Page 25 of 91
MB9D560 Series
Type
Circuit
Remarks
Pull-up control
P-ch
P-ch
Digital output
N-ch
F
R
CMOS hysteresis input
Automotive input
• With Analog input, General-purpose I/O port
• CMOS level output
IOH=-1/-2 mA, IOL=1/2 mA
• With 50 k pull-up resistor
• CMOS hysteresis input (0.7Vcc/0.3Vcc)
During standby, the input value retains the
previous value.
• Automotive input (0.8Vcc/0.5Vcc)
During standby, the input value retains the
previous value.
Standby control
Analog input
Pull-up control
P-ch
P-ch
Digital output
N-ch
G
R
CMOS hysteresis input
Automotive input
• With Analog output , General-purpose I/O port
• CMOS level output
IOH=-1/-2 mA, IOL=1/2 mA
• With 50 k pull-up resistor
• CMOS hysteresis input (0.7Vcc/0.3Vcc)
During standby, the input value retains the
previous value.
• Automotive input (0.8Vcc/0.5Vcc)
During standby, the input value retains the
previous value.
Standby control
Analog output
Pull-up control
P-ch
P-ch
Digital output
N-ch
H
R
FlexRay input
• General-purpose I/O port
• CMOS level output
IOH=-1/-2/-4 mA, IOL=1/2/4 mA
• With 50 k pull-up resistor
• FlexRay input (0.7Vcc/0.3Vcc)
During standby, the input value retains the
previous value.
• Automotive input (0.8Vcc/0.5Vcc)
During standby, the input value retains the
previous value.
Automotive input
Standby control
Document Number: 002-05679 Rev.*A
Page 26 of 91
MB9D560 Series
Type
Circuit
Remarks
P-ch
Digital output
I
N-ch
J
TTL hysteresis input
K
Analog input
L
Analog output
Document Number: 002-05679 Rev.*A
• CMOS level output
IOH=-5 mA, IOL=5 mA
• TTL hysteresis input (2V/0.8V)
• Analog input
• Analog output
Page 27 of 91
MB9D560 Series
5. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
5.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-05679 Rev.*A
Page 28 of 91
MB9D560 Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
5.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress’s recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 ˚C
and 30 ˚C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125 ˚C/24 h
Document Number: 002-05679 Rev.*A
Page 29 of 91
MB9D560 Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%.
Use of an apparatus for ion generation may be needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level
of 1 M).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
5.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-05679 Rev.*A
Page 30 of 91
MB9D560 Series
6. Handling Devices
For Latch-up Prevention
If a voltage higher than VCC5 or VCC12, or a voltage lower than VSS is applied to an I/O pin, or if a voltage exceeding the ratings is
applied between VCC5 to VSS and VCC12 to VSS pins, a latch-up may occur in CMOS IC. If the latch-up occurs, the power supply
current increases excessively and device elements may be damaged by heat. Take care to prevent any voltage from exceeding the
maximum ratings in device application.
Also, the analog power supplies (AVCC0, AVCC1, AVCC2, AVRH0, AVRH1, AVRH2, RVCC0, RVCC1,
RVRH0, RVEH1) and analog input must not exceed the digital power supply (VCC5) when the power supply to the analog system is
turned on or off.
In the correct power-on sequence, turn on the digital power supply voltage (VCC5, VCC12) and analog power supply voltages
(AVCC0, AVCC1, AVCC2, AVRH0, AVRH1, AVRH2, RVCC0, RVCC1, RVRH0, RVRH1) simultaneously. Alternatively, turn on the
digital power supply voltage (VCC5) first, and then turn on the analog power supplies (AVCC0, AVCC1, AVCC2, AVRH0, AVRH1,
AVRH2, RVCC0, RVCC1,
RVRH0, RVRH1).
Treatment of Unused Pins
If unused input pins are left open, they may cause a permanent damage to the device due to device malfunction or latch-up.
Connect a 2 k or higher resistor to each of unused input pins for pull-up or pull-down processing.
Also, if I/O pins are not used, they must be set to the output state for releasing or they must be set to the input state and treated in
the same way as for the input pins.
Power Supply Pins
The device is designed to ensure that if the device contains multiple VCC5, VCC12 and VSS pins, the pins that should be at the
same potential are interconnected to prevent latch-up or other malfunctions.
Further, connect these pins to an external power supply or ground to reduce unwanted radiation, prevent strobe signals from
malfunctioning due to a raised ground level, and fulfill the total output current standard, etc. As shown below, all VSS power supply
pins must be treated in the similar way. If multiple VCC5 or
VCC12 or VSS systems are connected, the device cannot operate correctly even within the guaranteed operating range.
Power Supply Input Pin
VCC
VDD
VSS
VCC5
VSS
VCC12
VSS
VCC5
VCC5
VCC12
VCC12
VSS
VCC12
VCC5
VSS
The power supply pins should be connected to VCC5, VCC12 and VSS of this device at the low impedance from the power supply
source.
In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of C pin is recommended to
use as a bypass capacitor between VCC5, VCC12 and VSS pins
Document Number: 002-05679 Rev.*A
Page 31 of 91
MB9D560 Series
Crystal Oscillation Circuit
An external noise to the X0 or X1 pin may cause a device malfunction. The printed circuit board must be designed to lay out X0 and
X1 pins, crystal oscillator (or ceramic resonator), and the bypass capacitor to be grounded to the close position to the device.
The printed circuit board artwork is recommended to surround the X0 and X1 pins by ground circuits.
Mode Pin (MD1, MD0)
Connect the MD1, MD0 mode pin to the VCC5 or VSS pin directly. To prevent an erroneous selection of test mode caused by the
noise, reduce the pattern length between each mode pin and VCC5 or VSS pin on the printed circuit board. Also, use the
low-impedance pin connection.
Notes during PLL Clock Operation
When the PLL clock is selected and if the oscillator is disconnected or if the input is stopped, this clock may continue to operate at
the free running frequency of the self oscillator circuit built in the PLL. This operation is not guaranteed.
Treatment of R/D Converter and A/D Converter Power Supply Pins
If unuse R/D converter and A/D converter, needs connection as follows.
 AVCC0 = AVCC1= AVCC2 = AVRH0= AVRH1 = AVRH2 = RVCC0 = RVCC1 = RVRH0 =RVRH1 = VCC5
 AVSS0 = AVSS1 = AVSS2 = AVRL0 = AVRL1 = AVRL2 = AVR0 = AVR1 = RVSS0 = RVSS1 = RVRL0 = RVRL1 = RVR0 =
RVR1 = VSS
Note on Using External Clock
The external clock is unsupported.
External direct clock input cannot use.
Power-on Sequence of R/D Converter and A/D Converter Power Supply Analog Inputs
Be sure to turn on the digital power supply (VCC5, VCC12) first, and then turn on the R/D converter and A/D converter power
supplies*1 and analog inputs*2. Also, turn off the R/D converter and A/D converter power supplies*1 and analog inputs*2 first, and then
turn off the digital power supply (VCC5, VCC12).
When the AVRH0, AVRH1, AVRH2, RVRH0 and RVRH1 pin voltages are turned on or off, they must not exceed AVCC0, AVCC1,
AVCC2, RVCC0 and RVCC1. Even if a common analog input pin is used as an input port, its input voltage must not exceed AVCC0,
AVCC1 or AVCC2. (However, the analog power supply voltage and digital power supply voltage can be turned on or off
simultaneously.)
*1: AVCC0, AVCC1, AVCC2, AVRH0, AVRH1, AVRH2, AVRL0, AVRL1, AVRL2, RVCC0, RVCC1, RVRH0, RVRH1, RVRL0, RVRL1
*2: MAG_PLUS0, MAG_MINUS0, COS_PLUS0, COS_MINUS0, SIN_PLUS0, SIN_MINUS0, COS_IN0, SIN_IN0, MAG_PLUS1,
MAG_MINUS1, COS_PLUS1, COS_MINUS1, SIN_PLUS1, SIN_MINUS1, COS_IN1, SIN_IN1, 4AN0 to 4AN7, AN0 to AN31
Notes When Writing Data in a Register Having the Status Flag
When writing data in the register that has a status flag (especially, an interrupt request flag) to control function, take care not to clear
its status flag erroneously. The program must be written not to clear the flag to the status bit, and to set the control bits to have the
desired value.
Especially, if multiple control bits are used, the bit instruction cannot be used. (The bit instruction can access to a single bit only.)
The Byte, Half-word, or Word access must be used to write data in the control bits and status flag simultaneously. During this time,
take care not to clear other bits (in this case, the bits of status flag) erroneously.
Note:
• These points can be ignored because the bit instructions already take the points into consideration for registers that are
supported by bit-band unit. These points must be considered when using the bit instruction for registers that are not supported
by bit-band unit.
Document Number: 002-05679 Rev.*A
Page 32 of 91
MB9D560 Series
7. Block Diagram
Debug I/F
(JTAG)
JTAG_SWCLKTCK
JTAG Wakeup
Debug Group
(CoreSightTM)
DAP
Security
Security
APB-M
APB-M
APB-S
APB-S
AHB-M
AHB-M
CLK_DBG
Debug APB
AHB2APB
(Priviledge
Protection)
APB-32
Trace Group
Security
Checker
ETB (Trace Buffer)
ATB
CLK_ATB
Debug APB
ETM
#1
ATB
CLK_PERI0
CLK_ATB
Core Group (2-Core)
AHB-32
ETM
#0
DMAC
(ch.0 to 15)
Processor
CLK_CPU1
CLK_CPU0
CPU #1
TCRAM #1
TCFLASH
#1
Security
CPU #0
CortexTM -R5F
AHB-M
TCRAM #0
CortexTM -R5F
B0TCM
B0TCM
B1TCM
#1
B1TCM
#0
MPU
#1
I$
#1
ATCM
#1
LLPP(AXI32-M) AXI-S
D$
#1
MPU
#0
I$
#0
D$
#0
CLK_PERI0
MPU AHB
Exclusive
Access Memory
(EAM)
AHB2AXI
AXI-S
TCFLASH
Security
#0
ATCM
#0
AXI-M AXI-S LLPP(AXI32-M)
AXI-M
AHB-64
CLK_DMA
AHB-32
AXI2AHB
AHB2AXI
High Performance Matrix (HPM)
AXI-64
AXI2AHB
AXI2AHB
CLK_HPM
AXI2AHB
AXI2AHB
AXI2AHB
AHB-32
CLK_PERI5
BBU
Mode control
System Controller
(SYSC)
WorkFLASH
#0
AHB-32
CLK_SYSC_PD1
Security
BBU
AHB-64
CLK_MEMC
CAN
(ch.0 to 2)
RST manage
Protection
MPU AHB
(Config, Slave)
CAN
Prescaler
DMAC
(Config, Slave)
PONR
TPU#0
State
CR
Calibration
Port Pin Config
(Config, Slave)
CRC
(ch.0 to 1)
CSV
Fast-CR
Resource Input Config
(Config, Slave)
TPU#1
PLL
RAM
AHB2APB
IRC #1
Clock output
APB-32
RAM
CLK_PERI1
NMI
distribution
HW-WDT
IPCU
SW-WDT #0
Wakeup
Request #0
EXT-IRQ
(NMI)
RDC
(unit 0)
RDC
(unit 1)
DAC
(ch.0)
DAC
(ch.1)
WFG
(unit0, ch.0 to 5)
WFG
(unit1, ch.6 to 11)
16-bit OCU
(unit0 to 2, ch.0 to 5)
16-bit OCU
(unit3 to 5, ch.6 to 11)
4ch-SH ADC
(unit0, ch.0 to 3)
4ch-SH ADC
(unit1, ch.4 to 7)
MVA (unit 0)
MVA (unit 1)
16-bit ICU
(unit0 to 1, ch.0 to 3)
16-bit ICU
(unit2 to 3, ch.4 to 7)
8/16bit UDC
(ch.0 to 1)
8/16bit UDC
(ch.2 to 3)
IRC #0
Wakeup
detect
SW-WDT #1
MFS
(ch.0 to 4)
16-bit FRT for RDC
(ch.18)
16-bit FRT for RDC
(ch.19)
16-bit FRT
(ch.0 to 5)
16-bit FRT
(ch.6 to 11)
32-bit FRT
(ch.0 to 4)
AHB2RBus
CLK_PERI7
Wakeup
Request #1
AHB2APB
FlexRay/RDC
Clock Control
32-bit ICU
(unit0 to 2, ch.0 to 5)
Clock Monitor
16-bit FRT
(ch.12 to 17)
WFG
(unit2 to 3, ch.12 to 23)
16-bit ICU
(unit4 to 7, ch.8 to 14)
16-bit Base Timer
[PWM/PPG/RLT/PWC]
(ch.0 to 11)
12-bit A/D Converter
(ch.0 to 31)
TCRAM #1
(Config, Slave)
Memory & Config Group
CLK_PERI6
16bit OCU
(unit6 to 11, ch.12 to 23)
TCFLASH #0
(Config, Slave)
TCRAM #0
(Config, Slave)
TCFLASH #1
(Config, Slave)
MCU Config Group
Application Specific
Peripheral Group A
GPIO
Slow-CR
LVD
BBU
FlexRay
(A+Bch)
AHB-32
CLK_PERI0
BootROM
Clock
AHB-32
CLK_PERI4
Application Specific
Peripheral Group B
BBU
RAM
WorkFLASH
#1
Security
SCT
BBU
Common Peripheral Group
Application Specific Peripheral Group
Resource Input
Configuration
PORT MUX (Port Pin Config)
I/O
Note:
• In the block diagram, block name (Config, Slave) describe bus connection for register setting of control block.
Document Number: 002-05679 Rev.*A
Page 33 of 91
MB9D560 Series
Group
Group Name
Core Group
Debug Group
MCU Config Group
Memory & Config Group _
Common Peripheral Group
Application Specific Peripheral Group
Description
CPU and TCM connected memory group
CoreSight of Debugging group
System control and supervision IP group
CPU related function and memory group
Common peripheral IP group for vehicle application
Product specified peripheral group
Independent IP
Name
HPM
DMAC
EAM
Resource input configuration
Port MUX
I/O
Description
Bus matrix of AXI
Bus bridge (AXI-to-AHB, AHB-to-AXI)
DMA controller
Exclusive access memory
Input selection circuit of MCU peripheral
Port MUX circuit
I/O circuit
Note:
• Each master connects to HPM. Each master has different transaction ID on AXI, Out-Of-Order for transaction completion.
Document Number: 002-05679 Rev.*A
Page 34 of 91
MB9D560 Series
8. Memory Map
Address
Start
Block
End
0x0090_0000
64KB: 0x0000_FFFF
96KB: 0x0001_7FFF
128KB: 0x0001_FFFF
0x007F_FFFF
512KB: 0x0087_FFFF
768KB: 0x008B_FFFF
1024KB: 0x008F_FFFF
0x00FD_FFFF
0x00FE_0000
0x00FF_FFFF
0x0000_0000
0x0002_0000
0x0080_0000
0x0110_0000
512KB: 0x0107_FFFF
768KB: 0x010B_FFFF
1024KB: 0x010F_FFFF
0x01FD_FFFF
0x01FE_0000
0x01FF_FFFF
0x0200_0000
0x0280_0000
0x0280_1000
0x0490_0000
0x027F_FFFF
0x0280_0FFF
0x03FF_FFFF
64KB: 0x0400_FFFF
96KB: 0x0401_7FFF
128KB: 0x0401_FFFF
0x047F_FFFF
512KB: 0x0487_FFFF
768KB: 0x048B_FFFF
1024KB: 0x048F_FFFF
0x04FD_FFFF
0x04FE_0000
0x04FF_FFFF
0x0100_0000
0x0400_0000
0x0402_0000
0x0480_0000
0x0510_0000
512KB: 0x0507_FFFF
768KB: 0x050B_FFFF
1024KB: 0x050F_FFFF
0x05FD_FFFF
0x05FE_0000
0x05FF_FFFF
0x0500_0000
0x0600_0000
0x0602_0000
0x0680_0000
0x0690_0000
64KB: 0x0600_FFFF
96KB: 0x0601_7FFF
128KB: 0x0601_FFFF
0x067F_FFFF
512KB: 0x0687_FFFF
768KB: 0x068B_FFFF
1024KB: 0x068F_FFFF
0x06FD_FFFF
Document Number: 002-05679 Rev.*A
Overview
Function
TCRAM
Memory
(Each CPU exclusive
space)
Reserved
TCFLASH
large sector area
(TCM connection)
Reserved
TCFLASH
small sector area
(TCM connection)
TCFLASH
large sector area
(AXI connection)
Reserved
TCFLASH
small sector area
(AXI connection)
Reserved
EAM
Reserved
CPU0 space TCRAM
Memory
(Common space)
Reserved
CPU0 space TCFLASH
large sector area
(TCM connection)
Reserved
CPU0 space TCFLASH
small sector area
(TCM connection)
CPU0 space TCFLASH
large sector area
(AXI connection)
Reserved
CPU0 space TCFLASH
small sector area
(AXI connection)
CPU1 space TCRAM
Reserved
CPU1 space TCFLASH
large sector area
(TCM connection)
Reserved
Page 35 of 91
MB9D560 Series
Address
Start
0x06FE_0000
Block
End
0x06FF_FFFF
0x0710_0000
512KB: 0x0707_FFFF
768KB: 0x070B_FFFF
1024KB: 0x070F_FFFF
0x07FD_FFFF
0x07FE_0000
0x07FF_FFFF
0x0800_0000
0x0DFF_FFFF
0x0E00_0000
0x0E00_FFFF
0x0E01_0000
0x0E01_FFFF
0x0E02_0000
0x0E0F_FFFF
0x0E10_0000
0x0E10_FFFF
0x0E11_0000
0x0E11_FFFF
0x0E12_0000
0x0E1F_FFFF
0x0E20_0000
0x0E20_FFFF
0x0E21_0000
0x0E21_FFFF
0x0E22_0000
0x1000_0000
0xA000_0000
0x0FFF_FFFF
0x9FFF_FFFF
0xA1FF_FFFF
0xA200_0000
0xA27F_FFFF
0xA280_0000
0xA2FF_FFFF
0xA300_0000
0xA37F_FFFF
0xA380_0000
0xA47F_FFFF
0xA480_0000
0xA7FF_FFFF
0xA800_0000
0xA87F_FFFF
0xA880_0000
0xA8FF_FFFF
0xA900_0000
0xAFFF_FFFF
0xB000_0000
0xBFFF_FFFF
0xC000_0000
0xF000_0000
0xFFFE_E000
0xFFFF_0000
0xEFFF_FFFF
0xFFFE_DFFF
0xFFFE_FFFF
0xFFFF_FFFF
0x0700_0000
Overview
Document Number: 002-05679 Rev.*A
Memory
(Common space)
Reserved
Bit band alias area
I/O area
(Bit band area)
Reserved
BootROM area
Function
CPU1 space TCFLASH
small sector area
(TCM connection)
CPU1 space TCFLASH
large sector area
(AXI connection)
Reserved
CPU1 space TCFLASH
small sector area
(AXI connection)
Reserved
WorkFLASH0
mirror area 1
WorkFLASH1
mirror area 1
Reserved
WorkFLASH0 Reserved
mirror area 2
WorkFLASH1 Reserved
mirror area 2
Reserved
WorkFLASH0
mirror area 3
WorkFLASH1
mirror area 3
Reserved
Reserved
Reserved
Bit band alias area (Memory &
Config Group)
Reserved
Bit band alias area
(MCU Config Group)
Bit band alias area (Common
Peripheral Group)
Reserved
Bit band alias area (Application
Specific Peripheral Group A)
Bit band alias area
(Application Specific Peripheral
Group B)
Reserved
I/O
Reserved
Reserved
Error Config
BootROM
Page 36 of 91
MB9D560 Series
Notes:
• Each CPU exclusive space define memory space for each CPU specified. The other master cannot access (Reserved area). If
the other master access to each CPU exclusive space, access from common space.
• Reserved area access cause bus error.
• However, following access of reserved area will be not bus error.
0x0090_0000 to 0x00FD_FFFF
0x0110_0000 to 0x01FD_FFFF
0x0490_0000 to 0x04FD_FFFF
0x0510_0000 to 0x05FD_FFFF
0x0690_0000 to 0x06FD_FFFF
0x0710_0000 to 0x07FD_FFFF
0x1000_0000 to 0x1FFF_FFFF
0x2000_0000 to 0x2FFF_FFFF
• The following area should be set device attribution or strongly ordered attribution as core access.
1. I/O area
2. Bit band alias area
3. Error Config (BootROM area)
4. WorkFLASH (when program)
5. TCFLASH (when program)
About device attribute and Strongly Ordered attribute, see "ARM®Architecture Reference Manual ARM®v7-A and ARM®v7-R
edition (ARM DDI 0406B)".
• TCFLASH has a TCM-connected region and an AXI-connected region. AXI-connected region is dedicated for flash memory
programming/erasing. When read operation in user mode, use TCM-connected region.
Document Number: 002-05679 Rev.*A
Page 37 of 91
MB9D560 Series
9. I/O Map
I/O Address Map (HPM, etc.)
Address
Start
0xB000_0000
Area
End
0xB03F_FFFF
Overview
Reserved
Function
Reserved
I/O Address Map (Memory & Config Group)
Address
Start
0xB040_0000
0xB040_1000
0xB040_2000
0xB040_7000
0xB040_7400
0xB040_8000
0xB040_8400
0xB040_9000
0xB040_9400
0xB041_0000
0xB041_0400
0xB041_0800
0xB041_1000
0xB041_1400
0xB041_1800
0xB041_2000
0xB041_2400
0xB041_2800
0xB041_5000
0xB041_6000
Area
End
0xB040_0FFF
0xB040_1FFF
0xB040_6FFF
0xB040_73FF
0xB040_7FFF
0xB040_83FF
0xB040_8FFF
0xB040_93FF
0xB040_FFFF
0xB041_03FF
0xB041_07FF
0xB041_0FFF
0xB041_13FF
0xB041_17FF
0xB041_1FFF
0xB041_23FF
0xB041_27FF
0xB041_4FFF
0xB041_5FFF
0xB04F_FFFF
Overview
Memory & Config Group
Function
IRC0
IRC1
Reserved
NMI distributor
Reserved
TPU0
Reserved
TPU1
Reserved
TCRAM0 IF
TCRAM1 IF
Reserved
TCFLASH0 IF
TCFLASH1 IF
Reserved
WorkFLASH0 IF
WorkFLASH1 IF
Reserved
IPCU
Reserved
I/O Address Map (Debug Group)
Address
Start
0xB050_0000
0xB050_1000
0xB050_2000
0xB050_3000
0xB050_4000
0xB050_5000
0xB058_0000
0xB058_1000
0xB059_0000
0xB059_1000
0xB059_2000
0xB059_3000
0xB059_8000
0xB059_9000
0xB059_A000
0xB059_C000
0xB059_D000
0xB059_E000
Area
End
0xB050_0FFF
0xB050_1FFF
0xB050_2FFF
0xB050_3FFF
0xB050_4FFF
0xB057_FFFF
0xB058_0FFF
0xB058_FFFF
0xB059_0FFF
0xB059_1FFF
0xB059_2FFF
0xB059_7FFF
0xB059_8FFF
0xB059_9FFF
0xB059_BFFF
0xB059_CFFF
0xB059_DFFF
0xB05F_FFFF
Document Number: 002-05679 Rev.*A
Overview
Debug Group
Function
DAPROM
ETB
CTI4
TPIU
TRACE_FUNNEL
Reserved
CORTEXROM0
Reserved
CORE0
Reserved
CORE1
Reserved
CTI0
CTI1
Reserved
ETM0
ETM1
Reserved
Page 38 of 91
MB9D560 Series
I/O Address Map (MCU Config Group)
Address
Start
0xB060_0000
0xB060_0800
0xB060_1000
0xB060_8000
0xB060_8400
0xB060_9000
0xB060_9400
0xB060_C000
0xB060_C400
0xB062_0000
0xB062_0400
Area
End
0xB060_07FF
0xB060_0FFF
0xB060_7FFF
0xB060_83FF
0xB060_8FFF
0xB060_93FF
0xB060_BFFF
0xB060_C3FF
0xB061_FFFF
0xB062_03FF
0xB06F_FFFF
Overview
MCU Config Group
Function
SYSC
MODEC
Reserved
SW-WDT0
Reserved
SW-WDT1
Reserved
HW-WDT
Reserved
EXT-IRQ
Reserved
I/O Address Map (Common Peripheral Group)
Address
Start
0xB070_0000
0xB070_4000
0xB071_0000
0xB071_1000
0xB071_8000
0xB071_8800
0xB072_0000
0xB072_0C00
0xB072_8000
0xB072_8400
0xB073_0000
0xB073_0400
0xB073_8000
0xB073_9000
0xB074_0000
0xB074_4000
0xB074_8000
0xB074_9000
0xB080_0000
0xB080_1400
0xB080_8000
0xB080_B000
0xB082_0000
0xB082_1400
0xB082_8000
0xB082_8C00
Area
End
0xB070_3FFF
0xB070_FFFF
0xB071_0FFF
0xB071_7FFF
0xB071_87FF
0xB071_FFFF
0xB072_0BFF
0xB072_7FFF
0xB072_83FF
0xB072_FFFF
0xB073_03FF
0xB073_7FFF
0xB073_8FFF
0xB073_FFFF
0xB074_3FFF
0xB074_7FFF
0xB074_8FFF
0xB07F_FFFF
0xB080_13FF
0xB080_7FFF
0xB080_AFFF
0xB081_FFFF
0xB082_13FF
0xB082_7FFF
0xB080_8BFF
0xB08F_FFFF
Document Number: 002-05679 Rev.*A
Overview
Common Peripheral Group
(AHB32)
Common Peripheral Group
(APB)
Function
DMAC
Reserved
MPU AHB
Reserved
CRC (ch.0 to 1)
Reserved
CAN (ch.0 to 2)
Reserved
CAN prescaler
Reserved
CR calibration
Reserved
GPIO
Reserved
PPC
Reserved
RIC
Reserved
MFS (ch.0 to 4)
Reserved
Base timer (ch.0 to 11)
Reserved
32-bit FRT (ch.0 to 4)
Reserved
32-bit ICU (ch.0 to 5)
Reserved
Page 39 of 91
MB9D560 Series
I/O Address Map (Product Specified Peripheral Bus)
Address
Start
Area
End
0xB090_0000
0xB100_0000
0xB100_0100
0xB100_0200
0xB100_0300
0xB100_0400
0xB100_0500
0xB100_0600
0xB100_0800
0xB100_0A00
0xB100_0C00
0xB100_0D00
0xB100_0E00
0xB101_0000
0xB101_0100
0xB101_0200
0xB101_0300
0xB101_0400
0xB101_0600
0xB101_0700
0xB101_1000
0xB101_3000
0xB101_4000
0xB200_0000
0xB200_0100
0xB200_0200
0xB200_0300
0xB200_0400
0xB200_0500
0xB200_0600
0xB200_0800
0xB200_0A00
0xB200_0C00
0xB200_0D00
0xB200_0E00
0xB200_0F00
0xB200_1000
0xB200_1800
0xB201_0000
0xB0FF_FFFF
0xB100_00FF
0xB100_01FF
0xB100_02FF
0xB100_03FF
0xB100_04FF
0xB100_05FF
0xB100_07FF
0xB100_09FF
0xB100_0BFF
0xB100_0CFF
0xB100_0DFF
0xB100_0FFF
0xB101_00FF
0xB101_01FF
0xB101_02FF
0xB101_03FF
0xB101_05FF
0xB101_06FF
0xB101_0FFF
0xB101_2FFF
0xB101_3FFF
0xB1FF_FFFF
0xB200_00FF
0xB200_01FF
0xB200_02FF
0xB200_03FF
0xB200_04FF
0xB200_05FF
0xB200_07FF
0xB200_09FF
0xB200_0BFF
0xB200_0CFF
0xB200_0DFF
0xB200_0EFF
0xB200_0FFF
0xB200_17FF
0xB200_FFFF
0xB201_00FF
0xB201_0100
0xB201_01FF
0xB201_0200
0xBFFF_FFFF
Overview
Reserved
Application Specific
Peripheral Group A
(AHB-32)
Application Specific
Peripheral Group A
(APB)
Reserved
Application Specific
Peripheral Group B
(AHB-32)
Application Specific
Peripheral Group B
(R-Bus)
Reserved
Function
Reserved
16-bit FRT (ch.6 to 11)
16-bit OCU (ch.6 to 11)
16-bit ICU (ch.4 to 7)
4ch-SH ADC (unit1)
WFG (ch.6 to 11)
UDC (ch.2 to 3)
Reserved
MVA (unit1)
Reserved
RDC (unit1)
DAC (ch.1)
Reserved
16-bit FRT (ch.12 to 17)
16-bit OCU (ch.12 to 23)
16-bit ICU (ch.8 to 14)
Reserved
12-bit ADC (ch.0 to 31)
WFG(ch.12 to 23)
Reserved
Other (WFG)
Other (ADC, CSV)
Reserved
16-bit FRT (ch.0 to 5)
16-bit OCU (ch.0 to 5)
16-bit ICU (ch.0 to 3)
4ch-SH ADC (unit0)
WFG (ch.0 to 5)
UDC (ch.0 to 1)
Reserved
MVA (unit0)
Reserved
RDC (unit0)
DAC (ch.0)
Reserved
Reserved
FlexRay (ch.A/ch.B)
Reserved
FlexRay/RDC clock control
Clock monitor
Reserved
I/O address Map (Error Config)
Address
Start
0xFFFE_E000
0xFFFE_E400
0xFFFE_E800
0xFFFE_F800
0xFFFE_FC00
Area
End
0xFFFE_E3FF
0xFFFE_E7FF
0xFFFE_F7FF
0xFFFE_FBFF
0xFFFE_FFFF
Overview
Error Config
Function
IRC0 (NMIVASBR)
IRC1 (NMIVASBR)
Reserved
*
IRC (NMIVASBR) mirror
BootROM IF
*: CPU0 is IRC0, CPU1 is IRC1 able to access this area. The master of excepted CPU is reserved area.
Document Number: 002-05679 Rev.*A
Page 40 of 91
MB9D560 Series
Notes:
• I/O address map shows maximum area for possibility. It depends on functions. The detail information, see each address map.
• It causes bus error to access to reserved area. However, following reserved area access is not generation of bus error.
0xB018_0000 to 0xB018_03FF
0xB05C_0000 to 0xB05C_0FFF
0xB05E_0000 to 0xB05E_03FF
0xB05E_0400 to 0xB05E_07FF
0xB05E_0800 to 0xB05E_0BFF
0xB05E_0C00 to 0xB05E_0FFF
Document Number: 002-05679 Rev.*A
Page 41 of 91
MB9D560 Series
10. Pin Statuses in CPU Status
Pin Statuses (1/2)
85
P413/RX2/INT2
98
99
100
101
102
86
-
P414/TX2
P415/TIOA4
P416/TIOB4
P417/TIOA5
P418/TIOB5
106
-
107
108
109
90
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
Hi-Z/Input
blocked
Last status
retained
Hi-Z/Input
blocked
Analog output
Analog output
Analog output
Analog output
Analog output
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog output
Analog output
Analog output
Analog output
Analog output
Analog output
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog output
L
Analog output
L
Analog output
L
H/L
Analog output
H/L
Analog output
L
Analog input
Analog input
Analog input
Analog input
Analog input
Analog output
Analog output
Analog output
Analog output
Analog output
Analog output
Hi-Z/Input
blocked
Last status
retained*6
Input enabled
Input enabled
H/L
L*5
Analog output
L
L*5
Analog output
Analog input
Hi-Z/Input blocked
Hi-Z/Input
blocked
Input enabled
H/L
Hi-Z/Input
blocked
Hi-Z/Input blocked
Last status
retained
Hi-Z/Input
blocked
Last status
retained
Hi-Z/Input
blocked
Input enabled
Input enabled
Input enabled
-
-
-
-
-
-
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
-
-
-
-
-
-
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Hi-Z/Input
blocked
Last status
retained*6
Hi-Z/Input blocked
Hi-Z/Input blocked
Hi-Z/Last
status
retained
Hi-Z/Last
status
retained
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
Hi-Z/Input
blocked*4
Hi-Z/Input
blocked
Hi-Z/Input
blocked*4
Hi-Z/Input
blocked
Last status
retained
Hi-Z/Input
blocked*4
Hi-Z/Input
blocked
Hi-Z/Input
blocked*4
Hi-Z/Input
blocked
Hi-Z/Input
blocked*4
Hi-Z/Input
blocked*4
Hi-Z/Input
blocked
Hi-Z/Input
blocked*4
Hi-Z/Input
blocked
Hi-Z/Input
blocked*4
Hi-Z/Input blocked
Hi-Z/Input blocked
Hi-Z/Last
status
retained
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
Hi-Z/Input blocked
Hi-Z/Last
status
retained
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
P419/SIN2/INT5
P420/SOT2
P131/SCK2
P431/ERDS1
High impedance enabled
(SYSC_SSPECFGR:
PSSPADCTRL=1)
97
High impedance disabled
(SYSC_SSPECFGR:
PSSPADCTRL=0)
P412/TX1
High impedance enabled
(SYSC_SSPECFGR:
PSSPADCTRL=1)
84
Watch mode
High impedance disabled
(SYSC_SSPECFGR:
PSSPADCTRL=0)
96
Stop mode
CPU sleep
P411/RX1/INT1
Hi-Z/Input blocked
Internal reset issuance
in progress
83
Hi-Z/
Input
blocked
After internal reset issuance
(Before GPORT setting)
95
Hi-Z/
Last status
retained
After internal reset issuance
(Before GPORT setting)
P410/TX0
Internal reset issuance
in progress
P409/RX0/INT0
82
L*5
Internal reset issuance
in progress
81
94
After internal reset issuance
(Before GPORT setting)
93
Internal reset issuance
in progress
P407/SOT1
P408/SCK1
Internal reset issuance
in progress
P406/SIN1/INT4
79
80
With control
78
91
92
Without control
90
Hi-Z/
Input blocked
Sleep mode
With control
P305/FRCK0
P306/FRCK1
P000/DTTI0/4ADTG0
P001/RTO0
P002/RTO1
P003/RTO2
P004/RTO3
P005/RTO4
P006/RTO5
P007/4AN0
P008/4AN1
P009/4AN2
P010/4AN3
P011/RDC_W0/ZIN0
P012/RDC_V0/BIN0
P013/RDC_U0/AIN0
P014/RDC_Z0/ZIN1
P015/RDC_B0/BIN1
P016/RDC_A0/AIN1
AREF20
SIN_IN0
COS_IN0
SIN_OUT0
SIN_MINUS0
SIN_PLUS0
COS_PLUS0
COS_MINUS0
COS_OUT0
RDC_ACT0/P026
MAG_MINUS0
MAG_PLUS0
MAG_OUT0
P430/ERDS0
P030/DTTI2/FRCK12
P031/RTO12/FRCK13
P309/RTO13/FRCK14
P310/RTO14/FRCK15
P311/RTO15/FRCK16
P312/RTO16/FRCK17
P313/RTO17
P314/DTTI3/TIOA0
P315/RTO18/TIOB0
P316/RTO19/TIOA1
P317/RTO20/TIOB1
P318/RTO21/TIOA2
P319/RTO22/TIOB2
P320/RTO23/TIOA3
P321/SIN0/INT3/TIOB3
P322/SOT0
P323/SCK0
P324/STOPWT/IN6/IN16
P325/RXDA/IN7/IN17
P326/TXDA/IN8/IN18
P327/TXENA/IN9/IN19
P328/RXDB/IN10/IN20
P329/TXDB/IN11/IN21
P330/TXENB/IN12
NMIX
RSTX
MD1
MD0
X0
X1
TRSTX
TCK
TDO
TDI
TMS
nSRST
After external
factor
releasing
*7
3
4
5
6
7
8
9
10
11
12
13
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
39
40
41
42
43
46
47
48
49
50
51
52
53
54
55
58
59
60
61
62
63
64
65
66
67
68
69
70
72
73
74
75
76
77
With
control
3
4
5
6
7
8
9
10
11
14
15
16
17
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
43
44
45
46
47
48
49
50
51
55
56
57
58
59
60
61
62
63
64
65
66
67
70
71
72
73
74
75
76
77
78
79
80
81
82
84
85
86
87
88
89
External factor
generation
in progress
Internal reset
factor*3
With control
176
pin
Without control
208
pin
With control
Pin Name
GPORTEN control
Pin No.
External reset
factor*2
Before internal reset
issuance
External reset
factor*1
After
external
factor
releasing
External
factor
generation
in progress
Document Number: 002-05679 Rev.*A
Last status
retained
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked*4
Hi-Z/Input
blocked*4
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Page 42 of 91
MB9D560 Series
Pin Statuses (2/2)
Internal reset
factor*3
L
Analog output
Analog output
Analog output
Analog output
Analog input
Analog input
Analog input
Analog input
L
H/L
Analog output
H/L
Analog output
*5
L
L
Analog output
H/L
Watch mode
L
High impedance enabled
(SYSC_SSPECFGR:
PSSPADCTRL=1)
Stop mode
High impedance disabled
(SYSC_SSPECFGR:
PSSPADCTRL=0)
CPU sleep
162
-
L
Analog output
After internal reset issuance
(Before GPORT setting)
-
L
Internal reset issuance
in progress
153
154
158
159
160
161
Analog input
After internal reset issuance
(Before GPORT setting)
-
H/L
*5
Analog output
*5
Internal reset issuance
in progress
152
MAG_OUT1
MAG_PLUS1
MAG_MINUS1
RDC_ACT1/P126
COS_OUT1
COS_MINUS1
COS_PLUS1
SIN_PLUS1
SIN_MINUS1
SIN_OUT1
COS_IN1
SIN_IN1
AREF21
P116/RDC_A1/AIN3
P115/RDC_B1/BIN3
P114/RDC_Z1/ZIN3
P113/RDC_U1/AIN2
P112/RDC_V1/BIN2
P111/RDC_W1/ZIN2
P110/4AN7
P109/4AN6
P108/4AN5
P107/4AN4
P106/RTO11
P105/RTO10
P104/RTO9
P103/RTO8
P102/RTO7
P101/RTO6
P100/DTTI1/4ADTG1
Internal reset issuance
in progress
91
92
93
94
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
120
121
122
123
124
125
126
127
128
129
130
Before internal reset
issuance
110
111
112
113
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
139
140
141
142
145
146
147
148
149
150
151
After
external
factor
releasing
External factor
generation
in progress
After internal reset issuance
(Before GPORT setting)
176
pin
After external
factor
releasing
Internal reset issuance
in progress
208
pin
Internal reset issuance
in progress
Pin Name
GPORTEN control
Sleep Mode
External
factor
generation
in progress
High impedance disabled
(SYSC_SSPECFGR:
PSSPADCTRL=0)
External reset
factor*2
High impedance enabled
(SYSC_SSPECFGR:
PSSPADCTRL=1)
External reset
factor*1
Pin No.
Analog output
Analog input
L
L
L
Analog output
Analog output
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog output
Analog output
Analog output
Analog output
Analog output
Analog output
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog output
Analog output
Analog output
Analog output
Analog output
Analog output
Hi-Z/
Last status
retained
Hi-Z/Input
blocked
Hi-Z/Input blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
Hi-Z/Input
blocked
Last status
retained
Hi-Z/Input
blocked
P421/SIN3/INT6/FRCK8
Hi-Z/Input blocked
Hi-Z/
Last status
retained
Hi-Z/Input
blocked
Hi-Z/Input blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
Hi-Z/Input
blocked*4
Last status
retained
Hi-Z/Input
blocked*4
P422/SOT3/FRCK9/IN13
P423/SCK3/FRCK10/IN14
P425/TIOA8
P426/TIOB8
P427/TIOA9
P428/TIOB9
Hi-Z/Input blocked
Hi-Z/
Last status
retained
Hi-Z/Input
blocked
Hi-Z/Input blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
Hi-Z/Input
blocked
Last status
retained
Hi-Z/Input
blocked
134
P429/MONCLK/MM
Hi-Z/Input blocked
Hi-Z/
Last status
retained
Hi-Z/Input
blocked
Hi-Z/Input blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained*8
Hi-Z/Input
blocked
Last status
retained*8
Hi-Z/Input
blocked
163
164
165
166
167
168
169
170
173
174
175
176
177
178
179
180
185
186
187
188
189
190
191
192
195
135
136
137
138
139
140
141
142
145
146
147
148
149
150
151
152
157
158
159
160
161
162
163
164
167
AN0/P200
AN1/P201
AN2/P202
AN3/P203
AN4/P204
AN5/P205
AN6/P206
AN7/P207
AN8/P208
AN9/P209
AN10/P210
AN11/P211
AN12/P212
AN13/P213
AN14/P214
AN15/P215
AN16/P216
AN17/P217
AN18/P218
AN19/P219
AN20/P220/TIOA6
AN21/P221/TIOB6
AN22/P222/TIOA7
AN23/P223/TIOB7
AN24/P224
Hi-Z/Input blocked
Hi-Z/Last
status
retained
Hi-Z/Input
blocked
Hi-Z/Input blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
Hi-Z/Input
blocked
Last status
retained
Hi-Z/Input
blocked
196
168
AN25/P225/SIN4/INT7
Hi-Z/Input blocked
Hi-Z/Last
status
retained
Hi-Z/Input
blocked
Hi-Z/Input blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
Hi-Z/Input
blocked*4
Last status
retained
Hi-Z/Input
blocked*4
197
198
199
200
201
202
203
204
205
206
207
169
170
171
172
173
174
175
-
AN26/P226/SOT4/IN0
AN27/P227/SCK4/IN1
AN28/P228/SCS40/IN2
AN29/P229/SCS41/IN3
AN30/P230/SCS42/IN4
AN31/P231/SCS43/IN5
P300/ADTG0
P301/TIOA10/FRCK4
P302/TIOB10/FRCK5
P303/TIOA11/FRCK6
P304/TIOB11/FRCK7
Hi-Z/Input blocked
Hi-Z/Last
status
retained
Hi-Z/Input
blocked
Hi-Z/Input blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
Hi-Z/Input
blocked
Last status
retained
Hi-Z/Input
blocked
With control
Hi-Z/Input blocked
*1: Power-on reset, internal power supply low-voltage detection and NMIX + RSTX pin are factors.
*2: External power supply low-voltage detection and external reset are factors.
*3: Software reset and software/hardware watchdog reset are factors.
*4: When external interrupt is valid, input blocked is invalid.
*5: When I/O is initialized, "L" is output.
*6: Operation is continued according to the peripheral function.
*7: If GPORTEN bit is 0 and CPORTEN bit is 1, input is enabled.
*8: When clock monitor output pin (MONCLK) is selected, pin state becomes high impedance.
Document Number: 002-05679 Rev.*A
Page 43 of 91
MB9D560 Series
11. Electrical Characteristics
11.1 Absolute Maximum Ratings
Parameter
*1, *2
Power supply voltage
*1, *2
Analog power supply voltage
*1
Analog reference voltage
*1
Input voltage
Analog pin input voltage
*1
*1
Input voltage
*1
Analog pin input voltage
*1
Output voltage
Max clamp current
Max total clamp current
"L" level Max output current
*3
"L" level average output current
"L" level total output current
*4
*5
"H" level Max output current
*3
"H" level average output current
"H" level total output current
Power consumption
Operating temperature
Storage temperature
Rating
Symbol
*4
*5
VCC
VDD
AVCC
RVCC
AVRH
RVRH
VI
VIA
VO
ICLAMP
|ICLAMP|
IOL1
IOL2
IOL3
IOLAV1
IOLAV2
IOLAV3
IOL
IOH1
IOH2
IOH3
IOHAV1
IOHAV2
IOHAV3
IOH
PD
TA
Tstg
Min
VSS-0.3
VSS-0.3
VSS-0.3
VSS-0.3
VSS-0.3
VSS-0.3
VSS-0.3
VSS-0.3
VSS-0.3
-
-40
-55
Max
VSS+6.0
VSS+1.8
VSS+6.0
VSS+6.0
VSS+6.0
VSS+6.0
VCC+0.3
VCC+0.3
VCC+0.3
4
20
3.5
7
14
1
2
4
40
-3.5
-7
-14
-1
-2
-4
-40
1500
+125
+150
Unit
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
C
C
Remarks
AVCCVCC
RVCCVCC
AVRHAVCC
RVRHRVCC
*8
*8
*6
When setting to 1 mA
When setting to 2 mA
*7
When setting to 4 mA
*6
When setting to 1 mA
When setting to 2 mA
*7
When setting to 4 mA
*6
*6
When setting to 1 mA
When setting to 2 mA
*7
When setting to 4 mA
*6
When setting to1 mA
When setting to 2 mA
*7
When setting to 4 mA
*6
*9
*1: These parameters are based on the condition that VSS=AVSS=0.0V.
*2: Caution must be taken that AVCC does not exceed VCC.
*3: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*4: The average output current is defined as the value of the average current flowing through any one of the corresponding pins for a
10 ms period. The average value is the operation current  the operation ratio.
*5: The total output current is defined as the maximum current value flowing through all of corresponding pins.
*6: Corresponding pins: general-purpose ports
*7: Corresponding pins: general-purpose ports of P325 to P330
*8: Corresponding pins: all general-purpose ports and analog input pin
•
•
•
•
•
•
•
•
Use the devices within recommended operating conditions.
Use the devices with direct voltage (current).
The + B signal should always be applied by connecting a limiting resistor between the + B signal and the microcontroller.
The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated values at
any time regardless of instantaneously or constantly when the + B signal is input.
Note that when the microcontroller drive current is low, such as in the low-power consumption modes, the + B input potential can
increase the potential at the VCC pin via a protective diode, possibly affecting other devices.
Note that if the + B signal is input when the microcontroller is off (not fixed at 0V), since the power is supplied through the pin,
the microcontroller may operate incompletely.
Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset may not function
in the power supply voltage.
Do not leave + B input pins open.
Document Number: 002-05679 Rev.*A
Page 44 of 91
MB9D560 Series
Sample Recommended Circuit
MB9D560 series
Protective diode
Limiting resistor current
+Ｂ input(12 to 16V)
*9: To use this product at TA = 125C, equip this on a multilayer board with four or more layers.
To equip this on a single-layer board, change the operating conditions (operating frequency, power supply voltage, etc.) to use
this at the power consumption PD = 780mW or lower, or use this at TA = 100C or lower.
Warning:
• Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
Document Number: 002-05679 Rev.*A
Page 45 of 91
MB9D560 Series
11.2 Recommended Operating Conditions
(VSS = AVSS-RVSS = 0.0V)
Parameter
Power supply voltage
*
Smoothing capacitor
Operating temperature
Value
Symbol
VCC
VDD
AVCC
RVCC
VCC
VDD
AVCC
RVCC
CREF
TA
Min
4.5
1.1
4.5
4.5
3.7
1.09
3.7
3.7
0.33
-40
Max
5.5
1.3
5.5
5.5
5.5
1.3
5.5
5.5
1.0
+125
Unit
V
V
V
V
V
V
V
V
F
C
Remarks
Recommended operation guarantee range
Operation guarantee range
Tolerance within 40%
* : For connection of smoothing capacitor CREF, see the figure below.
CREF pin connection
Decoupling capacitor
(0.01F to 1F)
Wire
MB9D560 series
Pin
AVRH0
AVRL0
CREF
AVR0
AVSS0
AVCC0
It should be used smoothing capacitor for between AVR1 to AVRL1, RVR0 to RVRL0, RVR1 to RVRL1 as well.
CREF capacitor size and A/D converter activation time
It depends on activation time of A/D converter with R/D converter and activation time of 4 channels same time sampling A/D
converter by CREF capacitor seize. The computation expression of activation time is as follows.
Activation time = 9 × CREF × 1.2k + 1μ [s]
Activation time relate with following time from activation trigger, please use smoothing capacitor with system operation conditions.
If A/D converter of 4 channels same time sampling,
Set to "1" for ENBL bit of A/D enable setting register.
If A/D converter with R/D converter,
Set to "1" for RDCEN bit of operation control register 1.
Warning:
• The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of
the device's electrical characteristics are warranted when the device is operated under these conditions.
• Any use of semiconductor devices will be under their recommended operating condition.
• Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device
failure.
• No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are
considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-05679 Rev.*A
Page 46 of 91
MB9D560 Series
11.3 DC Characteristics
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Symbol
VIH1
"H" level input
voltage
VIH2
Pin Name
P000 to P016,
P026,
P030 to P031,
P100 to P116,
P126, P131,
P200 to P231,
P300 toP306,
P309 to P324,
P406 to P423,
P425 to P431
P000 to P016,
P026,
P030 to P031,
P100 to P116,
P126, P131,
P200 to P231,
P300 to P306,
P309 to P330,
P406 to P423,
P425 to P431
VIH3
P325 to P330
VIH4
VIH5
RSTX, NMIX
MD0, MD1
TRSTX,
TCK, TDI,
TMS, nSRST
VIH6
Conditions
Value
Typ
Min
Max
Unit
When CMOS schmitt
input level is selected
0.7VCC
-
Vcc+0.3
V
When automotive
input level is
selected
0.8VCC
-
Vcc+0.3
V
0.7VCC
-
Vcc+0.3
V
0.7VCC
0.7VCC
-
Vcc+0.3
Vcc+0.3
V
V
2.3
-
Vcc+0.3
V
When FlexRay input
level is selected
-
Remarks
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Symbol
VIL1
"L" level input
voltage
VIL2
Pin Name
P000 to P016,
P026,
P030 to P031,
P100 to P116,
P126, P131,
P200 to P231,
P300 toP306,
P309 to P324,
P406 to P423,
P425 to P431
P000 to P016,
P026,
P030 to P031,
P100 to P116,
P126, P131,
P200 to P231,
P300 to P306,
P309 to P330,
P406 to P423,
P425 to P431
VIL3
P325 to P330
VIL4
VIL5
RSTX, NMIX
MD0, MD1
TRSTX,
TCK, TDI,
TMS, nSRST
VIL6
Document Number: 002-05679 Rev.*A
Conditions
Value
Typ
Min
Max
Unit
When CMOS schmitt
input level is selected
VSS-0.3
-
0.3VCC
V
When automotive
input level is
selected
VSS-0.3
-
0.5VCC
V
VSS-0.3
-
0.3VCC
V
VSS-0.3
VSS-0.3
-
0.3VCC
0.3VCC
V
V
VSS-0.3
-
0.8
V
When FlexRay input
level is selected
-
Remarks
Page 47 of 91
MB9D560 Series
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
"H" level output
voltage
Symbol
Pin Name
Conditions
Value
Typ
Min
Max
Unit
VOH1
P000 to P016,
P026,
P030 to P031,
P100 to P116,
P126, P131,
P200 to P231,
P300 toP306,
P309 to P330,
P406 to P423,
P425 to P431
VCC = 4.5V
IOH = -2.0mA
VCC-0.5
-
VCC
V
VOH2
P325 to P330
VCC = 4.5V
IOH = -4.0mA
VCC-0.5
-
VCC
V
VOH3
P000 to P016,
P026,
P030 to P031,
P100 to P116,
P126, P131,
P200 to P231,
P300 toP306,
P309 to P330,
P406 to P423,
P425 to P431
VCC = 4.5V
IOH = -1.0mA
VCC-0.5
-
VCC
V
VOH4
TDO
VCC = 4.5V
IOH = -5mA
VCC-0.5
-
VCC
V
Remarks
When
FlexRay
selected
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
"L" level output
voltage
Symbol
Pin Name
Conditions
Value
Typ
Min
Max
Unit
VOL1
P000 to P016,
P026,
P030 to P031,
P100 to P116,
P126, P131,
P200 to P231,
P300 toP306,
P309 to P330,
P406 to P423,
P425 to P431
VCC = 4.5V
IOL = 2.0mA
0
-
0.4
V
VOL2
P325 to P330
VCC = 4.5V
IOL = 4.0mA
0
-
0.4
V
VOL3
P000 to P016,
P026,
P030 to P031,
P100 to P116,
P126, P131,
P200 to P231,
P300 toP306,
P309 to P330,
P406 to P423,
P425 to P431
VCC = 4.5V
IOL=1.0mA
0
-
0.4
V
VOL4
TDO
VCC = 4.5V
IOL = 5mA
0
-
0.4
V
Document Number: 002-05679 Rev.*A
Remarks
When
FlexRay
selected
Page 48 of 91
MB9D560 Series
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Input leakage
current
Symbol
Pin Name
IIL
All input pin
RUP1
RSTX, NMIX
P000 to P016,
P026,
P030 to P031,
P100 to P116,
P126, P131,
P200 to P231,
P300 to P306,
P309 to P330,
P406 to P423,
P425 to P431
Other than
VCC, VSS,
AVCC, AVSS,
RVCC, RVSS
Pull-up
resistance
RUP2
Input capacitor
CIN
Document Number: 002-05679 Rev.*A
Conditions
VCC = AVCC = RVCC = 5.5V
VSS  VI  VCC
-
Value
Typ
Min
Max
Unit
-5
-
+5
A
25
-
100
k
When pull-up resistance
is selected
25
-
100
k
-
-
5
15
pF
Remarks
Page 49 of 91
MB9D560 Series
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Power supply
current
Symbol
ICC5
Pin Name
Conditions
Min
Value
Typ
Max
Unit
Normal operations
200MHz
-
104
115
mA
Normal
operations
160MHz
-
105
116
mA
-
115
126
mA
-
116
127
mA
VCC5
Flash write/erase
200MHz
*
Flash write/erase
160MHz
*
Remarks
FCD0_CLK = 200 MHz
FCLK_CPUx = 200 MHz,
FCLK_TFCLKx = 66 MHz,
FCLK_HPMPD2 = 200 MHz,
FCLK_DMA = 200 MHz,
FCLK_MEMC = 100 MHz,
FCLK_WFCLKx = 200 MHz,
FCLK_SYSCPD1 = 100 MHz,
FCLK_PERIy = 100 MHz,
FCLK_PERIz = 50 MHz
x = 0, 1 y = 0, 4, 5 z = 1, 6, 7
FCD0_CLK = 160 MHz
FCLK_CPUx = 160 MHz,
FCLK_TFCLKx = 80 MHz,
FCLK_HPMPD2 = 160 MHz,
FCLK_DMA = 160 MHz,
FCLK_MEMC = 80 MHz,
FCLK_WFCLKx = 160 MHz,
FCLK_SYSCPD1 = 80 MHz,
FCLK_PERIy = 80 MHz,
FCLK_PERIz = 40 MHz
x = 0, 1 y = 0, 4, 5 z = 1, 6, 7
FCD0_CLK = 200 MHz
FCLK_CPUx = 200 MHz,
FCLK_TFCLKx = 66 MHz,
FCLK_HPMPD2 = 200 MHz,
FCLK_DMA = 200 MHz,
FCLK_MEMC = 100 MHz,
FCLK_WFCLKx = 200 MHz,
FCLK_SYSCPD1 = 100 MHz,
FCLK_PERIy = 100 MHz,
FCLK_PERIz = 50 MHz
x = 0, 1 y = 0, 4, 5 z = 1, 6, 7
FCD0_CLK = 160 MHz
FCLK_CPUx = 160 MHz,
FCLK_TFCLKx = 80 MHz,
FCLK_HPMPD2 = 160 MHz,
FCLK_DMA = 160 MHz,
FCLK_MEMC = 80 MHz,
FCLK_WFCLKx = 160 MHz,
FCLK_SYSCPD1 = 80 MHz,
FCLK_PERIy = 80 MHz,
FCLK_PERIz = 40 MHz
x = 0, 1 y = 0, 4, 5 z = 1, 6, 7
*: This series has 2 types of flash; TCFLASH (4) and WorkFLASH (2); however, this is the specification when only one of those is
written/erased.
Document Number: 002-05679 Rev.*A
Page 50 of 91
MB9D560 Series
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Power supply
current
Symbol
ICC12
Pin Name
Conditions
Min
Value
Typ
Max
Unit
Normal operations
200MHz
-
310
510
mA
Normal
operations
160MHz
-
290
490
mA
-
312
512
mA
-
292
492
mA
VCC12
Flash write/erase
200MHz
*
Flash write/erase
160MHz
*
Remarks
FCD0_CLK = 200 MHz
FCLK_CPUx = 200 MHz,
FCLK_TFCLKx = 66 MHz,
FCLK_HPMPD2 = 200 MHz,
FCLK_DMA = 200 MHz,
FCLK_MEMC = 100 MHz,
FCLK_WFCLKx = 200 MHz,
FCLK_SYSCPD1 = 100 MHz,
FCLK_PERIy = 100 MHz,
FCLK_PERIz = 50 MHz
x = 0, 1 y = 0, 4, 5 z = 1, 6, 7
FCD0_CLK = 160 MHz
FCLK_CPUx = 160 MHz,
FCLK_TFCLKx = 80 MHz,
FCLK_HPMPD2 = 160 MHz,
FCLK_DMA = 160 MHz,
FCLK_MEMC = 80 MHz,
FCLK_WFCLKx = 160 MHz,
FCLK_SYSCPD1 = 80 MHz,
FCLK_PERIy = 80 MHz,
FCLK_PERIz = 40 MHz
x = 0, 1 y = 0, 4, 5 z = 1, 6, 7
FCD0_CLK = 200 MHz
FCLK_CPUx = 200 MHz,
FCLK_TFCLKx = 66 MHz,
FCLK_HPMPD2 = 200 MHz,
FCLK_DMA = 200 MHz,
FCLK_MEMC = 100 MHz,
FCLK_WFCLKx = 200 MHz,
FCLK_SYSCPD1 = 100 MHz,
FCLK_PERIy = 100 MHz,
FCLK_PERIz = 50 MHz
x = 0, 1 y = 0, 4, 5 z = 1, 6, 7
FCD0_CLK = 160 MHz
FCLK_CPUx = 160 MHz,
FCLK_TFCLKx = 80 MHz,
FCLK_HPMPD2 = 160 MHz,
FCLK_DMA = 160 MHz,
FCLK_MEMC = 80 MHz,
FCLK_WFCLKx = 160 MHz,
FCLK_SYSCPD1 = 80 MHz,
FCLK_PERIy = 80 MHz,
FCLK_PERIz = 40 MHz
x = 0, 1 y = 0, 4, 5 z = 1, 6, 7
*: This series has 2 types of flash; TCFLASH (4) and WorkFlash (2); however, this is the specification when only one of those is
written/erased.
Document Number: 002-05679 Rev.*A
Page 51 of 91
MB9D560 Series
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Symbol
Pin name
Conditions
Min
Value
Typ
Max
Unit
-
40
42
mA
CPU sleep mode
160MHz
-
30
32
mA
-
390
1030
A
When using crystal
TA = 25C
-
380
1010
A
TA = 25C
VCC5
ICCT5
ICCH5
Document Number: 002-05679 Rev.*A
FCD0_CLK = 200 MHz
FCLK_CPUx = 200 MHz,
FCLK_TFCLKx = 66 MHz,
FCLK_HPMPD2 = 200 MHz,
FCLK_DMA = 200 MHz,
FCLK_MEMC = 100 MHz,
FCLK_WFCLKx = 200 MHz,
FCLK_SYSCPD1 = 100 MHz,
FCLK_PERIy = 100 MHz,
FCLK_PERIz = 50 MHz
x = 0, 1 y = 0, 4, 5 z = 1, 6, 7
FCD0_CLK = 160 MHz
FCLK_CPUx = 160 MHz,
FCLK_TFCLKx = 80 MHz,
FCLK_HPMPD2 = 160 MHz,
FCLK_DMA = 160 MHz,
FCLK_MEMC = 80 MHz,
FCLK_WFCLKx = 160 MHz,
FCLK_SYSCPD1 = 80 MHz,
FCLK_PERIy = 80 MHz,
FCLK_PERIz = 40 MHz
x = 0, 1 y = 0, 4, 5 z = 1, 6, 7
CPU sleep mode
200MHz
ICCS5
Power supply
current
Remarks
Watch mode,
4MHz source
oscillation
Stop mode
Page 52 of 91
MB9D560 Series
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Symbol
Pin Name
Conditions
Min
Value
Typ
Max
Unit
-
220
410
mA
CPU sleep mode
160MHz
-
180
360
mA
-
1280
9730
A
When using crystal
TA = 25C
-
860
9530
A
TA = 25C
VCC12
ICCT12
ICCH12
Document Number: 002-05679 Rev.*A
FCD0_CLK = 200 MHz
FCLK_CPUx = 200 MHz,
FCLK_TFCLKx = 66 MHz,
FCLK_HPMPD2 = 200 MHz,
FCLK_DMA = 200 MHz,
FCLK_MEMC = 100 MHz,
FCLK_WFCLKx = 200 MHz,
FCLK_SYSCPD1 = 100 MHz,
FCLK_PERIy = 100 MHz,
FCLK_PERIz = 50 MHz
x = 0, 1 y = 0, 4, 5 z = 1, 6, 7
FCD0_CLK = 160 MHz
FCLK_CPUx = 160 MHz,
FCLK_TFCLKx = 80 MHz,
FCLK_HPMPD2 = 160 MHz,
FCLK_DMA = 160 MHz,
FCLK_MEMC = 80 MHz,
FCLK_WFCLKx = 160 MHz,
FCLK_SYSCPD1 = 80 MHz,
FCLK_PERIy = 80 MHz,
FCLK_PERIz = 40 MHz
x = 0, 1 y = 0, 4, 5 z = 1, 6, 7
CPU sleep mode
200MHz
ICCS12
Power supply
current
Remarks
Watch mode,
4MHz source
oscillation
Stop mode
Page 53 of 91
MB9D560 Series
11.4 AC Characteristics
11.4.1
Source Clock Timing
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Pin
Name
Symbol
Source oscillation clock
frequency
Source oscillation clock
cycle time
CAN PLL jitter
(during lock)
Built-in slow-CR
oscillation frequency
Built-in fast-CR
oscillation frequency
Conditions
Value
Typ
Min
Max
Unit
FC
X0, X1
-
4
-
20
MHz
tCYL
X0, X1
-
50
-
250
ns
tPJ
-
-
-10
-
+10
ns
FCRS
-
-
50
100
150
kHz
FCRF
-
-
4
7.2
8
8
12
8.8
MHz
MHz
Remarks
Without calibration
With calibration
X0, X1 clock timing
tCYL
X0
CAN PLL jitter
Deviation time from the ideal clock is assured per cycle out of 20,000 cycles.
Ideal clock
Slow
PLL output
Fast
Document Number: 002-05679 Rev.*A
Page 54 of 91
MB9D560 Series
11.4.2
Internal Clock Timing
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Internal clock
frequency
Internal clock cycle
time
Symbol
FCD0_CLK
FCD4_CLK
FCLK_CPU0
FCLK_CPU1
FCLK_TFCLK0
FCLK_TFCLK1
FCLK_ATB
FCLK_DBG
FCLK_HPMPD2
FCLK_DMA
FCLK_MEMC
FCLK_WFCLK0
FCLK_WFCLK1
FCLK_SYSCPD1
FCLK_PERI0
FCLK_PERI1
FCLK_PERI4
FCLK_PERI5
FCLK_PERI6
FCLK_PERI7
FCLK_CLKO
tCD0_CLK
tCD4_CLK
tCLK_CPU0
tCLK_CPU1
tCLK_TFCLK0
tCLK_TFCLK1
tCLK_ATB
tCLK_DBG
tCLK_HPMPD2
tCLK_DMA
tCLK_MEMC
tCLK_WFCLK0
tCLK_WFCLK1
tCLK_SYSCPD1
tCLK_PERI0
tCLK_PERI1
tCLK_PERI4
tCLK_PERI5
tCLK_PERI6
tCLK_PERI7
tCLK_CLKO
Document Number: 002-05679 Rev.*A
Pin Name
-
Conditions
-
Value
Typ
Min
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
5
5
5
12.5
12.5
10
20
5
5
5
12.5
12.5
10
10
20
10
10
20
20
5
-
Max
200
200
200
200
80
80
100
50
200
200
200
80
80
100
100
50
100
100
50
50
200
-
Unit
Remarks
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CD0_CLK
CD4_CLK
CLK_CPU0
CLK_CPU1
CLK_TFCLK0
CLK_TFCLK1
CLK_ATB
CLK_DBG
CLK_HPMPD2
CLK_DMA
CLK_MEMC
CLK_WFCLK0
CLK_WFCLK1
CLK_SYSCPD1
CLK_PERI0
CLK_PERI1
CLK_PERI4
CLK_PERI5
CLK_PERI6
CLK_PERI7
CLK_CLKO
CD0_CLK
CD4_CLK
CLK_CPU0
CLK_CPU1
CLK_TFCLK0
CLK_TFCLK1
CLK_ATB
CLK_DBG
CLK_HPMPD2
CLK_DMA
CLK_MEMC
CLK_WFCLK0
CLK_WFCLK1
CLK_SYSCPD1
CLK_PERI0
CLK_PERI1
CLK_PERI4
CLK_PERI5
CLK_PERI6
CLK_PERI7
CLK_CLKO
Page 55 of 91
MB9D560 Series
Guaranteed operation range Internal operation clock frequency vs. Power supply voltage
Recommended guaranteed operation range:
Power supply voltage VDD (V)
Power supply voltage VCC (V)
PLL guaranteed operation range:
5.5
Guaranteed operation range:
4.5
3.7
1.3
1.1
1.09
2
4
200
Internal operation clock frequency FCD0_CLK(MHz)
Note: The CPU will be reset at the power supply voltage of the low-voltage detection setting voltage or less.
Oscillation clock frequency vs. Internal operation clock frequency
Oscillation Clock
PLL Multiplying
Main Clock
Frequency
Setting
4 MHz
4 MHz
100
8 MHz
8 MHz
50
8 MHz
4 MHz
100
16 MHz
16 MHz
25
16 MHz
8 MHz
50
PLL Output Divider
Setting
2
2
2
2
2
PLL Clock
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
Example of oscillation circuit
X0
X1
R
C1
C2
Note: when configuring the oscillator circuit, it is recommended to ask matching evaluation of the circuit to oscillator
manufacturers for the design.
Document Number: 002-05679 Rev.*A
Page 56 of 91
MB9D560 Series
AC characteristics are specified by the following measurement reference voltage values.
Input signal waveform
Hysteresis input pin (Automotive)
Output signal waveform
Output pin
0.8Vcc
2.4V
0.5Vcc
0.8V
Hysteresis input pin (CMOS schmitt)
0.7Vcc
0.3Vcc
Hysteresis input pin (FlexRay)
0.7Vcc
0.3Vcc
Hysteresis input pin (TTL)
2.0V
0.8V
Document Number: 002-05679 Rev.*A
Page 57 of 91
MB9D560 Series
11.4.3
Reset Input
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Reset input time
Width for reset input removal
Symbol
tRSTL
Pin
Name
RSTX
Value
Conditions
Min
10
1
-
Max
-
Unit
Remarks
s
s
tRSTL
RSTX
0.2Vcc
Document Number: 002-05679 Rev.*A
0.2Vcc
Page 58 of 91
MB9D560 Series
11.4.4
Power-on Conditions
(TA: Recommended operating conditions, VSS = 0.0V)
Parameter
Level detection voltage
Level detection
hysteresis width
Level detection time
Power-on time
Power-off time
Symbol
tR5
tR12
tOFF
Pin
Name
Conditions
VCC5
VCC12
VCC5
VCC12
VCC5
VCC12
VCC5
-
Min
2.0
0.4
0.11
0.05
1
Value
Typ
2.2
-
Max
2.4
0.7
150
50
30
30
0.6
-
Unit
V
V
mV
mV
s
ms
ms
ms
Remarks
When turning
on power
During voltage
drop
*1
*2
*1: If the fluctuation of the power supply is faster than the low-voltage detection time, there is the possibility to generate or release
after the power supply voltage has exceeded the detection voltage range.
*2: This time is to start the slope detection at next power on after power down and internal charge loss.
Power-on , Power-off sequence
2.0V
VCC5
0.2Vcc
tR5
0.2Vcc
tOFF
1.1V
VCC12
tR12
NMIX + RSTX
Notes:
• Power supply input procedure
Power supply should input same time VCC5 and VCC12, or VCC5 to up step.
Also, when power supply input, VCC12 is not over voltage of VCC5.
• Power supply shutdown procedure
Power supply should shutdown same time VCC5 and VCC12, or VCC12 to up step.
Also, when power supply shutdown, VCC12 is not over voltage of VCC5.
• Notes: When power supply input and power supply shutdown
When power supply input, power supply voltage until achieve to recommend operation guarantee area, same time input
for NMIX pin + RSTX pin.
When power supply shutdown, power supply voltage until achieve to recommend operation guarantee area, same time
input for NMIX pin + RSTX pin.
Document Number: 002-05679 Rev.*A
Page 59 of 91
MB9D560 Series
11.4.5 Multi-Function Serial Interface
11.4.5.1 CSIO Timing (SMR: MD[2:0] = 0b010)
Normal Synchronous Transfer (SCR: SPI = 0) and Serial Clock Output Signal Detect Level "H"(SMR: SCINV = 0)
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Symbol
Pin Name
Serial clock cycle time
tSCYC
SCK0 to SCK4
SCKSOT
delay time
tSLOVI
SCK0 to SCK4,
SOT0 to SOT4
Valid SINSCK
setup time
tIVSHI
SCKValid SIN
hold time
Value
Conditions
Min
Max
Unit
4tCLK_PERI1
-
ns
-30
+30
ns
30
-
ns
tSHIXI
0
-
ns
Serial clock "H" pulse
width
tSHSL
tCLK_PERI1+10
-
ns
Serial clock "L" pulse
width
tSLSH
2tCLK_PERI1-10
-
ns
SCKSOT
delay time
tSLOVE
-
30
ns
Valid SINSCK
setup time
tIVSHE
10
-
ns
SCKValid SIN
hold time
tSHIXE
20
-
ns
SCK fall time
tF
SCK0 to SCK4
-
5
ns
SCK rise time
tR
SCK0 to SCK4
-
5
ns
-
-
CL = 50pF,
IOL = -2mA, IOH = 2mA
-
5
Mbps
-
-
CL = 20pF,
IOL = -1mA, IOH = 1mA
-
6
Mbps
SCK0 to SCK4,
SIN0 to SIN4
Master mode
(CL = 50pF,
IOL = -2mA, IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
Remarks
SCK0 to SCK4
SCK0 to SCK4,
SOT0 to SOT4
SCK0 to SCK4,
SIN0 to SIN4
Slave mode
(CL = 50pF,
IOL = -2mA, IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
Transfer speed
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
Document Number: 002-05679 Rev.*A
Page 60 of 91
MB9D560 Series
tSCYC
VOH
SCK
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
tSHIXI
VIH
VIL
SIN
VIH
VIL
Master mode
tSLSH
SCK
tSHSL
VIL
VIL
tF
VIH
VIH
VIH
tR
tSLOVE
SOT
VOH
VOL
tIVSHE
SIN
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
Document Number: 002-05679 Rev.*A
Page 61 of 91
MB9D560 Series
Normal Synchronous Transfer (SCR: SPI = 0) and Serial Clock Output Signal Detect Level "L" (SMR: SCINV = 1)
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Symbol
Pin Name
Serial clock cycle time
tSCYC
SCK0 to SCK4
SCKSOT
delay time
tSHOVI
SCK0 to SCK4,
SOT0 to SOT4
Valid SINSCK
setup time
tIVSLI
SCKvalid SIN
hold time
Value
Conditions
Min
Max
Unit
4tCLK_PERI1
-
ns
-30
+30
ns
30
-
ns
tSLIXI
0
-
ns
Serial clock "H" pulse
width
tSHSL
tCLK_PERI1+10
-
ns
Serial clock "L" pulse
width
tSLSH
2tCLK_PERI1-10
-
ns
SCKSOT
delay time
tSHOVE
-
30
ns
valid SINSCK
setup time
tIVSLE
10
-
ns
SCKvalid SIN
hold time
tSLIXE
20
-
ns
SCK fall time
tF
SCK0 to SCK4
-
5
ns
SCK rise time
tR
SCK0 to SCK4
-
5
ns
-
-
CL = 50pF,
IOL = -2mA, IOH = 2mA
-
5
Mbps
-
-
CL = 20pF,
IOL = -1mA, IOH = 1mA
-
6
Mbps
SCK0 to SCK4,
SIN0 to SIN4
Master mode
(CL = 50pF,
IOL = -2mA, IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
Remarks
SCK0 to SCK4
SCK0 to SCK4,
SOT0 to SOT4
SCK0 to SCK4,
SIN0 to SIN4
Slave mode
(CL = 50pF,
IOL = -2mA, IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
Transfer speed
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
Document Number: 002-05679 Rev.*A
Page 62 of 91
MB9D560 Series
tSCYC
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
tSLIXI
VIH
SIN
VIH
VIL
VIL
Master mode
tSHSL
SCK
tSLSH
VIH
VIH
VIL
tR
tF
VIL
VIL
tSHOVE
SOT
VOH
VOL
tIVSLE
SIN
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
Document Number: 002-05679 Rev.*A
Page 63 of 91
MB9D560 Series
SPI Compatible (SCR: SPI = 1) and Serial Clock Output Signal Detect Level "H" (SMR: SCINV = 0)
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Symbol
Pin Name
Serial clock cycle time
tSCYC
SCK0 to SCK4
SCKSOT
delay time
tSHOVI
SCK0 to SCK4,
SOT0 to SOT4
Valid SINSCK
setup time
tIVSLI
SCKvalid SIN
hold time
tSLIXI
SOTSCK
delay time
tSOVLI
Serial clock "H" pulse
width
tSHSL
Serial clock "L" pulse
width
tSLSH
SCKSOT
delay time
tSHOVE
valid SINSCK
setup time
tIVSLE
SCKvalid SIN
hold time
tSLIXE
SCK fall time
tF
SCK rise time
Value
Conditions
Min
Max
Unit
4tCLK_PERI1
-
ns
-30
+30
ns
30
-
ns
0
-
ns
2tCLK_PERI1-30
-
ns
tCLK_PERI1+10
-
ns
2tCLK_PERI1-10
-
ns
-
30
ns
10
-
ns
20
-
ns
SCK0 to SCK4
-
5
ns
tR
SCK0 to SCK4
-
5
ns
-
-
CL = 50pF,
IOL = -2mA, IOH = 2mA
-
5
Mbps
-
-
CL = 20pF,
IOL = -1mA, IOH = 1mA
-
6
Mbps
SCK0 to SCK4,
SIN0 to SIN4
Master mode
(CL = 50pF,
IOL = -2mA, IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
SCK0 to SCK4,
SOT0 to SOT4
Remarks
SCK0 to SCK4
SCK0 to SCK4,
SOT0 to SOT4
SCK0 to SCK4,
SIN0 to SIN4
Slave mode
(CL = 50pF,
IOL = -2mA, IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
Transfer speed
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
Document Number: 002-05679 Rev.*A
Page 64 of 91
MB9D560 Series
tSCYC
VOH
SCK
VOL
VOH
VOL
SOT
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
Master mode
tSLSH
VIL
tF
*
VIL
tR
VOH
VIL
tSHOVE
VOH
VOL
VOL
tIVSLE
SIN
VIH
VIH
VIH
SCK
SOT
tSHSL
tSLIXE
VIH
VIL
VIH
VIL
*: Changes when writing to TDR register
Slave mode
Document Number: 002-05679 Rev.*A
Page 65 of 91
MB9D560 Series
SPI Compatible (SCR: SPI = 1) and Serial Clock Output Signal Detect Level "L" (SMR: SCINV = 1)
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Symbol
Pin Name
Serial clock cycle time
tSCYC
SCK0 to SCK4
SCKSOT
delay time
tSLOVI
SCK0 to SCK4,
SOT0 to SOT4
Valid SINSCK
setup time
tIVSHI
SCKvalid SIN
hold time
tSHIXI
SOTSCK
Delay time
tSOVHI
Serial clock "H" pulse
width
tSHSL
Serial clock "L" pulse
width
tSLSH
SCKSOT
delay time
tSLOVE
valid SINSCK
setup time
tIVSHE
SCKvalid SIN
hold time
tSHIXE
SCK fall time
tF
SCK rise time
Value
Conditions
Min
Max
Unit
4tCLK_PERI1
-
ns
-30
+30
ns
30
-
ns
0
-
ns
2tCLK_PERI1-30
-
ns
tCLK_PERI1+10
-
ns
2tCLK_PERI1-10
-
ns
-
30
ns
10
-
ns
20
-
ns
SCK0 to SCK4
-
5
ns
tR
SCK0 to SCK4
-
5
ns
-
-
CL = 50pF,
IOL = -2mA, IOH = 2mA
-
5
Mbps
-
-
CL = 20pF,
IOL = -1mA, IOH = 1mA
-
6
Mbps
SCK0 to SCK4,
SIN0 to SIN4
Master mode
(CL = 50pF,
IOL = -2mA, IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
SCK0 to SCK4,
SOT0 to SOT4
Remarks
SCK0 to SCK4,
SOT0 to SOT4
SCK0 to SCK4,
SOT0 to SOT4
SCK0 to SCK4,
SIN0 to SIN4
Slave mode
(CL = 50pF,
IOL = -2mA, IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
Transfer speed
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
Document Number: 002-05679 Rev.*A
Page 66 of 91
MB9D560 Series
t SCYC
VOH
VOH
SCK
VOL
t SOVHI
t SLOVI
VOH
VOL
SOT
VOH
VOL
t IVSHI
t SHIXI
VIH
VIL
SIN
VIH
VIL
Master mode
t SHSL
VIH
SCK
VIL
tR
*
SOT
VIH
VIH
VIL
VIL
tF
VOH
VOL
t SLOVE
VOH
VOL
t IVSHE
SIN
t SLSH
VIH
VIL
t SHIXE
VIH
VIL
*: Changes when writing to TDR register
Slave mode
Document Number: 002-05679 Rev.*A
Page 67 of 91
MB9D560 Series
When the Serial Chip Select is Used (SCSCR: CSEN = 1)
 Serial clock output signal detect level "H" (SMR, SCSFR: SCINV = 0)
 Serial chip select inactive level "H" (SCSCR, SCSFR: CSLVL = 1)
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Symbol
SCSSCK
setup time
tCSSI
SCKSCS
hold time
tCSHI
SCS deselect time
tCSDI
SCSSCK
setup time
tCSSE
SCKSCS
hold time
tCSHE
SCS deselect time
tCSDE
SCSSOT
delay time
tDSE
SCSSOT
delay time
tDEE
SCKSCS
clock switch time
Pin Name
Conditions
SCK4,
SCS40 to SCS43
Master mode
(CL = 50pF,
IOL = -2mA, IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
SCS40 to SCS43
Value
Min
Max
Unit
*1
-
ns
*2
-
ns
tCSDS -50
+5 tCLK_PERI1
-
ns
3tCLK_PERI1+30
-
ns
0
-
ns
3tCLK_PERI1+30
-
ns
-
40
ns
0
-
ns
3tCLK_PERI1+0
3tCLK_PERI1
+50
ns
tCSSU -50
tCSHD +0
Remarks
*3
SCK4,
SCS40 to SCS43
SCS40 to SCS43
Slave mode
(CL = 50pF,
IOL = -2mA, IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
SCS40 to SCS43,
SOT4
tSCC
SCK4,
SCS40 to SCS43
Master mode,
Round operation
(CL = 50pF,
IOL = -2mA, IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
-
-
CL = 50pF,
IOL = -2mA, IOH = 2mA
-
5
Mbps
-
-
CL = 20pF,
IOL = -1mA, IOH = 1mA
-
6
Mbps
Transfer speed
*1: tCSSU = SCSTR: CSSU[7:0]  serial chip select timing operation clock
*2: tCSHD = SCSTR: CSHD[7:0]  serial chip select timing operation clock
*3: tCSDS = SCSTR: CSDS[15:0]  serial chip select timing operation clock
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
Document Number: 002-05679 Rev.*A
Page 68 of 91
MB9D560 Series
VOH
SCS output
VOL
VOL
t CSHI
t CSSI
VOH
t CSDI
VOH
SCK output
VOL
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
Master mode
VIH
SCS input
VIL
VIL
t CSHE
t CSSE
VIH
t CSDE
VIH
SCK input
t DEE
SOT
(Normal Sync
transfer)
VOL
t DSE
SOT
(SPI compatible)
VOH
VOL
Slave mode
SCSx output
t SCC
SCSy output
VOL
SCK output
VOL
Clock switching example by master mode round operation
(x, y = 40, 41, 42, 43: x and y are d ifferent value)
Document Number: 002-05679 Rev.*A
Page 69 of 91
MB9D560 Series
When the Serial Chip Select is Used (SCSCR: CSEN = 1)
 Serial clock output signal detect level "L"(SMR, SCSFR: SCINV = 1)
 Serial chip select inactive level "H"(SCSCR, SCSFR: CSLVL = 1)
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
SCSSCK
setup time
SCKSCS
hold time
SCS deselect time
SCSSCK
setup time
SCKSCS
hold time
SCS deselect time
SCSSOT
delay time
SCSSOT
delay time
SCKSCS
clock switch time
Symbol
tCSSI
tCSHI
tCSDI
tCSSE
tCSHE
tCSDE
tDSE
tDEE
Pin Name
SCK4,
SCS40 to SCS43
SCS40 to SCS43
SCK4,
SCS40 to SCS43
SCS40 to SCS43
SCS40 to SCS43,
SOT4
tSCC
SCK4,
SCS40 to SCS43
-
-
-
-
Transfer speed
Conditions
Master mode
(CL = 50pF,
IOL = -2mA, IOH =
2mA),
(CL = 20pF,
IOL = -1mA, IOH =
1mA)
Slave mode
(CL = 50pF,
IOL = -2mA, IOH =
2mA),
(CL = 20pF,
IOL = -1mA, IOH =
1mA)
Master mode,
Round operation
(CL = 50pF,
IOL = -2mA, IOH =
2mA),
(CL = 20pF,
IOL = -1mA, IOH =
1mA)
CL = 50pF,
IOL = -2mA, IOH = 2mA
CL = 20pF,
IOL = -1mA, IOH = 1mA
Value
Min
Max
Unit
*1
-
ns
*2
-
ns
tCSDS -50
+5tCLK_PERI1
-
ns
3tCLK_PERI1+30
-
ns
0
-
ns
3tCLK_PERI1+30
-
ns
-
40
ns
0
-
ns
3tCLK_PERI1+0
3tCLK_PERI1+50
ns
-
5
Mbps
-
6
Mbps
tCSSU -50
tCSHD +0
Remarks
*3
*1: tCSSU = SCSTR: CSSU[7:0]  serial Chip select timing operation clock
*2: tCSHD = SCSTR: CSHD[7:0]  serial Chip select timing operation clock
*3: tCSDS = SCSTR: CSDS[15:0]  serial Chip select timing operation clock
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
Document Number: 002-05679 Rev.*A
Page 70 of 91
MB9D560 Series
SCS output
VOH
VOL
t CSHI
VOL
t CSSI
VOH
t CSDI
VOH
SCK output
VOL
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
Master mode
VIH
SCS input
VIL
VIL
t CSHE
t CSSE
VIH
t CSDE
VIH
SCK input
VIL
SOT
(Normal Sync
transfer)
VOL
t DSE
SOT
(SPI compatible)
t DEE
VOH
VOL
Slave mode
t SCC
SCSx output
SCSy output
VOL
VOH
SCK output
Clock switching example by master mode round operation
(x, y = 40, 41, 42, 43: x and y are different value)
Document Number: 002-05679 Rev.*A
Page 71 of 91
MB9D560 Series
When the Serial Chip Select is Used (SCSCR: CSEN = 1)
 Serial clock output signal detect level "H"(SMR, SCSFR: SCINV = 0)
 Serial Chip select inactive level "L"(SCSCR, SCSFR: CSLVL = 0)
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Symbol
SCSSCK
setup time
tCSSI
SCKSCS
hold time
tCSHI
SCS deselect time
tCSDI
SCSSCK
setup time
tCSSE
SCKSCS
hold time
tCSHE
SCS deselect time
tCSDE
SCSSOT
delay time
tDSE
SCSSOT
delay time
tDEE
SCKSCS
clock switch time
Pin Name
Conditions
SCK4,
SCS40 to SCS43
Master mode
(CL = 50pF,
IOL = -2mA, IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
SCS40 to SCS43
Value
Min
Max
Unit
*1
-
ns
*2
-
ns
tCSDS -50
+5tCLK_PERI1
-
ns
3tCLK_PERI1+30
-
ns
0
-
ns
3tCLK_PERI1+30
-
ns
-
40
ns
0
-
ns
3tCLK_PERI1+0
3tCLK_PERI1
+50
ns
tCSSU -50
tCSHD +0
Remarks
*3
SCK4,
SCS40 to SCS43
SCS40 to SCS43
Slave mode
(CL = 50pF,
IOL = -2mA, IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
SCS40 to SCS43,
SOT4
tSCC
SCK4,
SCS40 to SCS43
Master mode,
round operation
(CL = 50pF,
IOL = -2mA,IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
-
-
CL = 50pF,
IOL = -2mA, IOH = 2mA
-
5
Mbps
-
-
CL = 20pF,
IOL = -1mA, IOH = 1mA
-
6
Mbps
Transfer speed
*1: tCSSU = SCSTR: CSSU[7:0]  serial chip select timing operation clock
*2: tCSHD = SCSTR: CSHD[7:0]  serial chip select timing operation clock
*3: tCSDS = SCSTR: CSDS[15:0]  serial chip select timing operation clock
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
Document Number: 002-05679 Rev.*A
Page 72 of 91
MB9D560 Series
t CSDI
VOH
VOH
SCS output
VOL
t CSHI
t CSSI
VOH
SCK output
VOL
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
Master mode
t CSDE
VIH
VIH
SCS input
VIL
t CSHE
t CSSE
VIH
SCK input
SOT
(Normal Sync
transfer)
SOT
(SPI compatible)
VIL
t DEE
VOL
t DSE
VOH
VOL
Slvae mode
SCSx output
t SCC
VOH
SCSy output
SCK output
VOL
Clock switching example by master mode round operation
(x, y = 40, 41, 42, 43: x and y are different value)
Document Number: 002-05679 Rev.*A
Page 73 of 91
MB9D560 Series
When the Serial Chip Select is Used (SCSCR: CSEN = 1)
 Serial clock output signal detect level "L"(SMR, SCSFR: SCINV = 1)
 Serial Chip select inactive level "L"(SCSCR, SCSFR: CSLVL = 0)
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Symbol
SCSSCK
setup time
tCSSI
SCKSCS
hold time
tCSHI
SCS deselect t time
tCSDI
SCSSCK
setup time
tCSSE
SCKSCS
hold time
tCSHE
SCS deselect time
tCSDE
SCSSOT
delay time
tDSE
SCSSOT
delay time
tDEE
SCKSCS
clock switch time
Pin Name
SCK4,
SCS40 to SCS43
SCS40 to SCS43
Value
Conditions
Master mode
(CL = 50pF,
IOL = -2mA, IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
Min
Max
Unit
*1
-
ns
*2
-
ns
tCSDS -50
+5tCLK_PERI1
-
ns
3tCLK_PERI1+30
-
ns
0
-
ns
3tCLK_PERI1+30
-
ns
-
40
ns
0
-
ns
3tCLK_PERI1+0
3tCLK_PERI1
+50
ns
tCSSU -50
tCSHD +0
Remarks
*3
SCK4,
SCS40 to SCS43
SCS40 to SCS43
Slave mode
(CL = 50pF,
IOL = -2mA, IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
SCS40 to SCS43,
SOT4
tSCC
SCK4,
SCS40 to SCS43
Master mode,
Round operation
(CL = 50pF,
IOL = -2mA,IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
-
-
CL = 50pF,
IOL = -2mA, IOH = 2mA
-
5
Mbps
-
-
CL = 20pF,
IOL = -1mA, IOH = 1mA
-
6
Mbps
Transfer speed
*1: tCSSU = SCSTR:CSSU[7:0]  serial chip select timing operation clock
*2: tCSHD = SCSTR:CSHD[7:0]  serial chip select timing operation clock
*3: tCSDS = SCSTR:CSDS[15:0]  serial chip select timing operation clock
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
Document Number: 002-05679 Rev.*A
Page 74 of 91
MB9D560 Series
t CSDI
VOH
VOH
SCS output
VOL
t CSHI
t CSSI
VOH
SCK output
VOL
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
Master mode
t CSDE
VIH
VIH
SCS input
VIL
VIL
t CSHE
t CSSE
VIH
SCK input
VIL
SOT
(Normal Sync
transfer)
t DEE
VOL
t DSE
VOH
VOL
SOT
(SPI compatible)
Slave mode
t SCC
SCSx output
VOH
SCSy output
VOH
SCK output
Clock switching example by master mode round operation
(x, y = 40, 41, 42, 43: x and y are different value)
Document Number: 002-05679 Rev.*A
Page 75 of 91
MB9D560 Series
11.4.5.2 UART (Async Serial Interface) Timing (SMR: MD[2:0] = 0b000, 0b001)
When the External Clock is Selected (BGR: EXT = 1)
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Symbol
serial clock "L" pulse
width
tSLSH
serial clock "H" pulse
width
tSHSL
SCK fall time
tF
SCK rise time
tR
Pin Name
Min
(CL = 50pF,
IOL = -2mA, IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
SCK0 to SCK4
tR
-
ns
tCLK_PERI1+10
-
ns
-
5
ns
-
5
ns
Remarks
t SLSH
VIH
VIL
Unit
Max
tCLK_PERI1+10
tF
t SHSL
VIH
SCK
Value
Conditions
VIH
VIL
VIL
When the external clock is selected
11.4.5.3 LIN Interface (v2.1) (LIN Communication Control Interface (v2.1)) Timing (SMR: MD[2:0] = 0b011)
When the External Clock is Selected (BGR: EXT = 1)
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Symbol
serial clock "L" pulse
width
tSLSH
serial clock "H" pulse
width
tSHSL
Pin Name
tF
SCK rise time
tR
tR
SCK
Unit
Max
tCLK_PERI1+10
-
ns
tCLK_PERI1+10
-
ns
-
5
ns
-
5
ns
tF
t SHSL
VIH
VIL
Min
(CL = 50pF,
IOL = -2mA, IOH = 2mA),
(CL = 20pF,
IOL = -1mA, IOH = 1mA)
SCK0 to SCK4
SCK fall time
Value
Conditions
Remarks
t SLSH
VIH
VIH
VIL
VIL
When the external clock is selected
Document Number: 002-05679 Rev.*A
Page 76 of 91
MB9D560 Series
11.4.6
Timer Input Timing
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS =
Parameter
Symbol
Pin Name
IN16 to IN21,
TIOA0 to TIOA11,
TIOB0 to TIOB11
IN4 to IN14,
FRCK6 to FRCK10,
FRCK12 to FRCK17
Input pulse width
tTIWH, tTIWL
Value
Conditions
-
Min
4tCLK_PERI1
Max
-
Unit
IN0 to IN3,
FRCK0 to FRCK1,
FRCK4 to FRCK5
-
AIN0, BIN0, ZIN0
-
Remarks
4tCLK_PERI470ns
-
ns
70
4tCLK_PERI470ns
4tCLK_PERI5
4tCLK_PERI570ns
-
ns
4tCLK_PERI570ns
70
4tCLK_PERI570ns
4tCLK_PERI5
-
ns
4tCLK_PERI570ns
70
4tCLK_PERI470ns
4tCLK_PERI4
AIN2, BIN2, ZIN2
RVSS = 0.0V)
ns
4tCLK_PERI4
-
AVSS =
-
70
ns
4tCLK_PERI470ns
Timer input timing
INx
FRCKx
TIOAx,TIOBx
AINx,BINx,ZINx
Document Number: 002-05679 Rev.*A
tTIWH
VIH
tTIWL
VIH
VIL
VIL
Page 77 of 91
MB9D560 Series
11.4.7
Trigger Input Timing
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Symbol
Pin Name
Value
Conditions
Min
Max
Unit
INT0 to INT7
-
200
-
ns
RX0 to RX2
-
5tCLK_SYSCPD1
-
ns
ADTG0,
DTTI2 to DTTI3
-
5tCLK_PERI6
-
ns
5tCLK_PERI570ns
5tCLK_PERI5
Input pulse width
tTRGH,
tTRGL
4ADTG0,
DTTI0
-
4ADTG1,
DTTI1
-
ns
70
5tCLK_PERI570ns
5tCLK_PERI4
5tCLK_PERI470ns
-
-
ns
5tCLK_PERI470ns
70
INT0 to INT7,
ADTG0,
4ADTG0, 4ADTG1,
RX0 to RX2,
DTTI0 to DTTI3
-
Remarks
1
-
s
When stop mode
Trigger input timing
INTx
ADTGx
RXx
4ADTGx
DTTIx
tTRGH
VIH
Document Number: 002-05679 Rev.*A
tTRGL
VIH
VIL
VIL
Page 78 of 91
MB9D560 Series
11.4.8
NMI Input Timing
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Input pulse width
Symbol
tNMIL
Pin Name
NMIX
Value
Conditions
-
Min
200
Max
-
Unit
Remarks
ns
NMIX input timing
tNMIL
NMIX
VIH
VIH
VIL
Document Number: 002-05679 Rev.*A
VIL
Page 79 of 91
MB9D560 Series
11.4.9
External Low-Voltage Detection
(TA: Recommended operating conditions, VSS = AVSS = RVSS = 0.0V)
Parameter
Pin
Name
Symbol
Conditions
Min
Value
Typ
Max
Unit
Power supply voltage
range
VDP5
VCC5
-
-
-
5.5
V
Detection voltage
VDL
VCC5
*1
3.7
3.9
4.1
V
Hysteresis width
Low voltage detection
time
Power supply voltage
fluctuation rate
VHYS
VCC5
-
75
100
150
mV
Td
-
-
-
-
30
s
-
VCC5
-
-4
-
-
V/ms
Remarks
When power supply voltage falls
The original setting of detection
level is 4.1V0.2V
When power supply voltage rises
*2
*1: If the fluctuation of the power supply has exceeded the detection voltage range within the time less than the low-voltage
detection time (Td), there is the possibility to generate or release after the power supply voltage has exceeded the detection
voltage range.
*2: In order to perform the low-voltage detection at the detection voltage (VDL), be sure to suppress fluctuation of the power supply
within the limits of the power supply voltage fluctuation rate.
11.4.10 Internal Low-Voltage Detection
(TA: Recommended operating conditions, VSS = AVSS = RVSS = 0.0V)
Parameter
Power supply voltage
range
Detection voltage
Hysteresis width
Low voltage detection
time
Power supply voltage
fluctuation rate
Pin
Name
Symbol
Conditions
Min
Value
Typ
Max
Unit
VRDP5
VCC12
-
-
-
1.3
V
VRDL
VRHYS
VCC12
VCC12
*1
-
0.8
20
0.9
30
1.0
50
V
mV
TRd
-
-
-
-
30
s
-
VCC12
-
-4
-
-
V/ms
Remarks
When power supply voltage falls
When power supply voltage rises
*2
*1: If the fluctuation of the power supply has exceeded the detection voltage range within the time less than the low-voltage
detection time (TRd), there is the possibility to generate or release after the power supply voltage has exceeded the detection
voltage range.
*2: In order to perform the low-voltage detection at the detection voltage (VRDL), be sure to suppress fluctuation of the power supply
within the limits of the power supply voltage fluctuation rate.
Document Number: 002-05679 Rev.*A
Page 80 of 91
MB9D560 Series
11.5 A/D Converter
11.5.1
Electrical Characteristics
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Resolution
Non linearity error
Differential linearity
error
Zero transition
voltage
Full-scale transition
voltage
Sampling time
Compare time
A/D conversion time
Analog port input
current
Analog input voltage
Reference voltage
Power supply current
Variation between
channels
Symbol
Pin Name
Value
Typ
Min
Unit
Max
-
-
-4.0
-
12
+4.0
bit
LSB
-
-
-1.9
-
+1.9
LSB
VZT
AN0 to AN31
VFST
AN0 to AN31
tSMP
tCMP
tCNV
-
AVRL
+0.5LSB-20
AVRH
-1.5LSB-20
0.3
0.7
1.0
IAIN
AN0 to AN31
VAIN
AVRH
AVRL
IA
IAH
IR
IRH
AN0 to AN31
AVRH2
AVRL2
-
AN0 to AN31
AVCC2
AVRH2
-
AVRL
+0.5LSB+20
AVRH
-1.5LSB+20
12
28
40
-2.0
-
AVSS
4.5
-
-
Remarks
mV
1LSB = (VFST-VZT)/4094
mV
s
s
s
*1
*1
*1
2.0
A
VAVSSVAINVAVCC
0.0
500
1
-
AVRH
5.5
680
17.7
2
2.16
V
V
V
A
A
mA
A
-
4
LSB
AVCCAVRH
*2
*2
*1: Time for each channel.
*2: The power supply current (VCC = AVCC = 5.0V) is specified if the A/D converter is not operating and CPU is stopped.
11.5.2 Notes on Using A/D Converter
<About the output impedance of the analog input of external circuit>
When the external impedance is too high, the sampling time for analog voltages may not be sufficient.
In this case, it is recommended to connect the capacitor (approx. 0.1 F) to the analog input pin.
Analog input circuit model
Comparator
Analog input
R
C
Sampling ON
12bit A/D
R
3.0kΩ (max)
C
8.30pF (max) (4.5V ≤ AVcc ≤ 5.5V)
Note: Listed values must be considered as reference values.
Document Number: 002-05679 Rev.*A
Page 81 of 91
MB9D560 Series
11.6 4 Channels Same Time Sampling A/D Converter
11.6.1
Electrical Characteristics
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Parameter
Symbol
Resolution
Non linearity error
Differential linearity
error
Zero transition
voltage
Full-scale transition
voltage
Sampling time
Compare time
A/D conversion time
Analog port input
current
Analog input voltage
Reference voltage
Power supply current
Variation between
channels
Pin Name
Value
Typ
Min
Unit
Max
-
-
-4.0
-
12
+4.0
bit
LSB
-
-
-1.9
-
+1.9
LSB
VZT
4AN0 to 4AN7
VFST
4AN0 to 4AN7
tSMP
tCMP
tCNV
-
AVRL
+0.5LSB-20
AVRH
-1.5LSB-20
0.6
1.4
2
IAIN
4AN0 to 4AN7
VAIN
AVRH
AVRL
IA
IAH
IR
IRH
-
4AN0 to 4AN7
AVRH0, AVRH1
AVRL0, AVRL1
AVCC0, AVCC1
AVRH0, AVRH1
4AN0 to 4AN3
4AN4 to 4AN7
-
AVRL
+0.5LSB+20
AVRH
-1.5LSB+20
1.2
5.6
6.8
-0.7
-
AVSS
4.5
-
0.0
1.0
0.5
-
-
Remarks
mV
1LSB = (VFST-VZT)/4094
mV
s
s
s
*1
*2
*3
0.7
A
VAVSSVAINVAVCC
AVRH
5.5
1.5
27.5
4.0
4.5
20
20
V
V
V
mA
A
mA
A
mV
mV
AVCCAVRH
1 unit operation
*4
1 unit operation
1 unit operation
*4
1 unit operation
*1: 4 channels same time sampling time.
*2: Compare time for 4 channels.
*3: Conversion time for 4 channels.
*4: The power supply current (VCC = AVCC = 5.0V) is specified if the A/D converter is not operating and CPU is stopped.
11.6.2 Notes on Using A/D converter
<About the output impedance of the analog input of external circuit>
When the external impedance is too high, the sampling time for analog voltages may not be sufficient.
In this case, it is recommended to connect the capacitor (approx. 0.1 F) to the analog input pin.
Analog input circuit model
Comparator
Analog input
R
C
Sampling ON
4-SH 12bit A/D
R
3.8kΩ (max)
C
8.30pF (max) (4.5V ≤ AVcc ≤ 5.5V)
Note: Listed values must be considered as reference values.
Document Number: 002-05679 Rev.*A
Page 82 of 91
MB9D560 Series
11.6.3 Definition of Terms
Resolution:
Analog variation that is recognized by an A/D converter.
Linearity error:
Deviation of the actual conversion characteristics from a straight line that connects the zero transition
point ("0000 0000 0000"  "0000 0000 0001") to the full-scale transition point
("1111 1111 1110"  "1111 1111 1111").
Differential linearity error: Deviation of the input voltage from the ideal value that is required to change the output code by 1LSB.
Linearity error
Differential linearity error
FFF
Digital output
FFD
N+1
VFST
(Actuallymeasured
value)
004
VNT
(Actually-measured value)
Actual conversion
characteristics
003
Digital output
FFE
Ideal characteristics
Actual conversion
characteristics
{1 LSB (N - 1) + VZT}
Actual conversion
characteristics
N
N-1
V(N+1)T
VNT
002
(Actually-measured
value)
(Actually-measured value)
Ideal characteristics
N-2
001
Actual conversion
characteristics
VZT (Actually-measured value)
AVSS
(AVRL)
Analog input
AVRH
AVSS
(AVRL)
Analog input
AVRH
VNT - {1LSB×(N-1) + V ZT}
[LSB]
1LSB
V(N + 1)T - VNT
Differential linearity error of digital output N =
-1 LSB [LSB]
1LSB
VFST - VZT
1LSB =
[V]
4094
Linearity error of digital output N =
VZT: Voltage at which the digital output changes from "0x000" to "0x001".
VFST: Voltage at which the digital output changes from "0xFFE" to "0xFFF".
Document Number: 002-05679 Rev.*A
Page 83 of 91
MB9D560 Series
11.7 Flash Memory
Value
Parameter
Min
Typ
Max
Unit
Remarks
*1
-
200
800
ms
-
300
1100
ms
-
400
2000
ms
-
700
3700
ms
1,000 times /20 years,
10,000 times /10 years,
100,000 times / 5 years
9
12
9
288
384
288
s
s
s
-
-
-
Sector erase time
8bit writing time
16bit writing time
ECC writing time
*2
Erase cycle /
Data retention time
8K Byte sector
Excluding internal preprogramming time
*1
8K Byte sector
Including internal preprogramming time
*1
64K Byte sector
Excluding internal preprogramming time
*1
64K Byte sector
Including internal preprogramming time
*1
Excluding overhead time at system level
*1
Excluding overhead time at system level
*1
Excluding overhead time at system level
Temperature at writing/erasing
*3
Average temperature TA = +85C
*1: The guaranteed value for erase up to 100,000 cycles
*2: Number of erase cycles for each sector
*3: This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into
normalized value at + 85C).
Notes:
• While the Flash memory is written or erased, shutdown of the external power supply (VCC, VDD) is prohibited.
• In the application system where VCC or VDD might disappear while writing, be sure to turn the power off by using an external
low-voltage detector and NMIX pin + RSTX pin for reset input at same time. Concretely, please execute two of the following.
1. After simultaneous input from the NMIX and RSTX pins while VDD is within the recommended operating range, maintain VDD
within the recommended operating range for at least 60 µs.
2. After simultaneous input from the NMIX and RSTX pins while VCC is within the recommended operating range, power off VCC
in observance of the standard regarding the supply voltage fluctuation rate of the external low-voltage detector.
Document Number: 002-05679 Rev.*A
Page 84 of 91
MB9D560 Series
11.8 R/D Converter
(TA: Recommended operating conditions, VCC = 5.0V0.5V, VDD = 1.2V0.1V, VSS = AVSS = RVSS = 0.0V)
Value
Typ
Max
0.4VCC-1%
-0.4VCC+(VCC/2)
AREF20-2.0
AREF21-2.0
-
0.4VCC
10 or 20
-
0.4VCC+1%
0.4VCC+(VCC/2)
1
AREF20+2.0
AREF21+2.0
24
V
V
mA
kHz
V
V
kHz
0
-
RVCC0
V
0
-
RVCC1
V
-45
-
45

-4
-
4
LSB
1.1
12
-
2.1
bit
s
-
-
4000
rps
-
-
3000
rps
RVCC0/2-3%
RVCC1/2-3%
0.261
-
RVCC0/2+3%
RVCC1/2+3%
rps/LSB
V
V
-
-
1.2
kHz
-
-
400
Hz
-
-
1.8
kHz
-
-
600
Hz
-
-
4000
rps
-
-
3000
rps
-
-
4
ms
-
-
12
ms
-
-
1,000,000
rad/s
2
-
-
150,000
rad/s
2
Parameter
Excitation signal
output
Resolver response
*1
signal
Excitation input
*2
signal
Angle output
Angular velocity
output
Output voltage(amplitude)
Output voltage(displacement)
output current
Frequency
Amplitude
Maximum input frequency
Phase difference from resolver
detection signal
Angle accuracy
(conversion accuracy)
Resolution
Output delay
AREF2 output voltage
Tracking loop characteristics
(-3dB cross frequency)
Remarks
Setting with the register
Unit0
Unit1
Unit0
More than 2Vp-p
Unit1
More than 2Vp-p
Variation when
Pausing: 1LSB
When bandwidth
1.8 kHz mode
When bandwidth
600 kHz mode
Maximum Angular velocity
Tracking loop characteristics
(0dB cross frequency)
Operating
characteristics
Unit
Amplitude
Resolution
Reference output
voltage
Min
Maximum tracking rate
Settling time (179 degree step)
Maximum angular velocity
Unit0
Unit1
When bandwidth
*3
1.8 kHz mode
When bandwidth
*3
600 Hz mode
When bandwidth
*3
1.8 kHz mode
When bandwidth
*3
600 Hz mode
When bandwidth
1.8 kHz mode
When bandwidth
600 Hz mode
When bandwidth
1.8 kHz mode
When bandwidth
600 Hz mode
When bandwidth
1.8 kHz mode
When bandwidth
600 Hz mode
*1: Corresponding pin: COS_PLUS, COS_MINUS, SIN_PLUS, SIN_MINUS
*2: Corresponding pin: MAG_PLUS, MAG_MINUS
*3: When signal amplitude is nominal
Document Number: 002-05679 Rev.*A
Page 85 of 91
MB9D560 Series
12. Ordering Information
Part Number
Package
MB9DF564MxEEQ-GTE1
MB9DF565MxEEQ-GTE1
MB9DF566MxEEQ-GTE1
MB9DF564LxEEQ-GTE1
MB9DF565LxEEQ-GTE1
MB9DF566LxEEQ-GTE1
208-pin plastic TEQFP
(LER208)
176-pin plastic TEQFP
(LEP176)
Notes:
• "x" is option number. This option is following table. The detail of package, see "14. Package Dimensions".
13. Part Number Option
Part Number Option
A
G
L
Q
R/D Converter


-
FlexRay


Key Code
-
: Supported
Document Number: 002-05679 Rev.*A
Page 86 of 91
MB9D560 Series
14. Package Dimensions
Document Number: 002-05679 Rev.*A
Page 87 of 91
MB9D560 Series
Document Number: 002-05679 Rev.*A
Page 88 of 91
MB9D560 Series
15. Major Changes
Spansion Publication Number: MB9D560_DS708-00001
Page
Section
Change Results
Revision 1.0
-
-
Initial release
11
3. Product Lineup
Add 176 pin product
14, 15
4. Pin Assignment
Add 176 pin product
16 to 33
5. Pin Description
Add 176 pin product
46, 47
10. Memory Map
Add address information of MB9DF564 and MB9DF565
54, 55
12. Pin Statuses in CPU Status
102
14. Ordering Information
103, 104
16. Package Dimensions
Add 176 pin product
Change package name
Add 176 pin product
Change package dimensions
Add 176 pin product
Revision 2.0
Revision 3.0
102
15. Part Number Option
Add part number option L, Q
Note: Please see “Document History” about later revised information.
Document Number: 002-05679 Rev.*A
Page 89 of 91
MB9D560 Series
Document History
Document Title: MB9D560 Series 32-bit Microcontroller TraveoTM Family
Document Number: 002-05679
Orig. of
Submission
Change
Date
–
KOJM
05/15/2015
5176126
KOJM
03/22/2016
Revision
ECN
**
*A
Document Number: 002-05679 Rev.*A
Description of Change
Migrated to Cypress and assigned document number 002-05679.
No change to document contents or format.
Updated to Cypress format.
Page 90 of 91
MB9D560 Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the
office closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/psoc
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation 2014-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then
Cypress hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form,
to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end
users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license
(without the right to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software
solely to the minimum extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or
compilation of the Software is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in
whole or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall
indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of
Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the
United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-05679 Rev.*A
March 22, 2016
Page 91 of 91