19.8K Configurator Qualification Package Date: January 1, 2000 From: 19.8K Configurator Product Engineering Subj.: Qualification By Similarity 19.8K Devices Dear Valued Customer, The following Configurator devices are all fabricated using Atmel’s 19.8K process. For Qualification purposes, the above process covers all of the following Atmel Configurator devices: AT17C020 AT17C020A AT17LV020 AT17LV020A All of these devices are manufactured based on the same design rules, minimum geometry’s, and Atmel’s standard 19.8K memory cell. In addition, since all these devices are fabricated on the same process, they have the same number of layers, metal passivation, and implant levels. The devices vary in memory density and logic, therefore by qualifying the largest and/or most complex device also covers the qualification of smaller devices. If you have any questions regarding this matter, please feel free to contact us. Once again, thank you for your interest in Atmel Configurators products. • 2325 Orchard Parkway • San Jose CA 95131 • 19.8K PROCESS QUALIFICATION DATA ATMEL Device # AT19843 1. • # Samples Delivered: Units 2. • Product Qualification Policy 3. • Die Fabrication Process Qualification Conditions 4. Die Reliability Test Data • Data Retention • Dynamic Operating Life Test • Latch Up Data • ESD Data 5. • 6. Package Reliability Test Summary Data • 20 Lead PLCC Package Assembly Process Qualification Conditions ATMEL Justification for Qualification by Similarity • 2325 Orchard Parkway • San Jose CA 95131 • Qualification by “similarity” is a standard practice of all major IC suppliers whose product lines are as extensive and diverse as Atmel Corporation's. The general philosophy and practice of qualification by similarity is that product manufactured using the exact same materials and processing (defined as a Die Technology or Package Family) will contain the same level of random defects regardless of the final product. Product to product differences are addressed by selecting the 'worst case' or most complex die or package from the Die Technology or Package Family. By qualifying the 'worst case' die/package from each Family at each fab/assembly location, Atmel can perform more frequent periodic qualifications or Reliability Monitors. This increased frequency is the best assurance of continued high quality and reliability in Atmel's product. • 2325 Orchard Parkway • San Jose CA 95131 • ATMEL - AT19800 Process Dynamic Operating Life Test - Continuous Read PART TYPE LOT NUMBER AT24C128 AT24C128 AT25256 AT25256 AT24C256 AT24C256 AT24C256 AT17C010 AT17C020 7E4350 7G2223 B7G1931 7J06758 9712095b 7J0569 A7J4736 8E3624C 9G4275 DATE CODE SAMPLE TOTAL CKT SIZE HRS (K) AMBIENT TEMP (C) Vcc (V) 9721 100 208 150 5.5 9728 100 91 150 5.5 9742 100 18 150 5.5 9750 100 100 150 5.5 9752 100 101 150 5.5 9809 100 111 150 5.5 9813 100 200 150 5.5 9827 100 18 150 5.5 9942 100 1000 150 5.5 60% Confidence Estimate @ 50C & .5eV = 19 FITs 90% Confidence Estimate @ 50C & .5eV = 49 FITs • 2325 Orchard Parkway • San Jose CA 95131 • FAILURES 0 0 0 0 0 0 0 0 0 SEE NOTE# ATMEL - AT19800 Process Data Retention PART TYPE LOT NUMBER DATE CODE AT24C128 AT24C128 AT25256 AT24C128 AT24C256 AT24C256 AT17C010 AT17CO20 7E4350 7G2223 B7G1931 9712095 7J0570 7J0571 8E3624C 9G4275 9721 9728 9742 9752 9809 9809 9827 9942 SAMPLE TOTAL CKT SIZE HRS (K) 100 100 100 100 100 100 100 50 630 301 328 200 203 203 34 500 AMBIENT TEMP (C) FAILURES 250 250 250 250 250 250 150 150 0 0 0 0 0 0 0 0 60% Confidence Estimate @ 50C & .52eV = .5 FIT 90% Confidence Estimate @ 50C & .5eV = 1.3 FITs • 2325 Orchard Parkway • San Jose CA 95131 • SEE NOTE# Configurator ESD Characterization Device: 17C020 Quantity Tested: 3 Each Voltage Test Method: Mil Std 883, Method 3015 ESD Model: Human Body Test Temperature: 25C ESD Stress Equipment: ORYX Model 11000 ESD Test System Pass/Fail via Final Production Test Program: Sentry 201 Functional Tester 3 Positive & 3 Negative Pulses per The Specified Pin Combinations Max Passing Voltage Qty/Fail Qty/Fail Qty/Fail Qty/Fail Qty/Fail Voltage 500V 1000V 2000V 3500V Pin Name Function Tested As Vcc Gnd Data CLK Reset/OE CE CEO/A2 Power Ground Serial Data Clock Tri-State Control Chip Enable Output Enable/ Device Select Reset Complete Enable Mode Vcc Gnd Input Input Input Input Input/ Output 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3500 3500 3500 3500 3500 3500 3500 Output 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3/0 3500 3500 See Above 3/0 3/0 3/0 3/0 3/0 3500 Ready Ser_En Functional Test Only Failing Pin Not Identified • 2325 Orchard Parkway • San Jose CA 95131 • Configurator Latch-Up Characterization Device: 17C020 Quantity Tested: 5 Test Method: JEDEC 17 Test Temperature: 25C Over Current Test Voltage Vcc = 5.0V Maximum Applied Trigger Current = 150 mA Maximum Applied Trigger Voltage = 7.0 V Pin Name Function Vcc Power Gnd Ground Data Serial Data CLK Clock Reset/OE Tri-State Control CE Chip Enable CEO/A2 Output Enable/ Device Select Ready Reset Complete Ser_En Enable Mode Tested As Vcc Gnd Input Input Input Input Input/ Output Output Input Max Trigger Current Passing Passing Compliance -I (mA) +I (mA) Setting (V) Max Trigger Voltage Passing Passing Compliance -V (V) +V (V) Setting (mA) ----150 150 150 150 150 ----150 150 150 150 150 ----7 7 7 7 7 --------------- 7 ------------- 250 ------------- 150 150 150 150 7 7 ----- ----- ----- • 2325 Orchard Parkway • San Jose CA 95131 • PRODUCT QUALIFICATION POLICY Die Fabrication Process Each Microcircuit Group Is Qualified Quarterly. Microcircuit Groups Are Defined Per Mil-PRF-38535 & JEDEC 26. The Most Complex Product Available Is Used For Qualification. Only Qualified Product May Be Shipped. Package Assembly Process Each Package Family Is Qualified Every 36 Weeks. Each Assembly Subcontractor Is Qualified Every 36 Weeks. Package Families Are Defined Per MIL-PRF-38535 & JEDEC 26. The Worst Case Package Is Used For Qualification. Only Qualified Product May Be Shipped. • 2325 Orchard Parkway • San Jose CA 95131 • DIE FABRICATION PROCESS QUALIFICATION Test Flow & Conditions • Baseline Electrical Parameters Per Device Specification • Dynamic Lifetest Per MS883, M1005 - 77 Dev, Acc on 1 Failure. 0 0 1000 Hours @ 125 C or 184 Hours @150 C. • Data Retention Bake (NVM Only) - 77/1. 0 0 1000 Hours @ 150 C or 336 Hours @ 250 C. • Write Endurance (NVM Only, All Product) - 100/1. 0 100,000 Cycles @ 25 C. • Latchup (All Product) Per JEDEC 17 - 2/0. 150 mA Trigger Current At Maximum Operating Temperature. • ESD Sensitivity (All Product) Per MS883, M3015. Human Body Model (15000, 100pf). • 2325 Orchard Parkway • San Jose CA 95131 • TECHNOLOGY GENERAL 19.8K Process 1. DIE THICKNESS 2. PASSIVATION 20mils PLCC 10 KA° OXINITRIDE 7 KA° TEOS OXIDE 3. TECHNOLOGY NAME 19.8K 4. CELL SIZE 9.7u2 5. METAL PITCH 1.8u metal1, 2.89u metal2 7. N-CH LEFF 1u 8. P-CH LEFF 1.3u 9. METAL LAYERS 2 - 1.1u metal1, 2.04u metal2 (Al/Cu 99.5/0.5%) 10. POLY LAYERS 2 11. TECHNOLOGY CMOS • 2325 Orchard Parkway • San Jose CA 95131 • PACKAGE ASSEMBLY PROCESS QUALIFICATION Plastic - Test Flow & Conditions - Environmental Baseline Electrical Parameters Per Device Specification • Static Biased Lifetest Per JS22, MA101 - 50 Dev, Acc on 0 Fail. 0 1000 Hours @ 85% Relative Humidity & 85 C. • Data Retention Bake (NVM Only) - 50/0. 0 1000 Hours @ 150 C. • Autoclave Per JS22, MA102 - 50/0. 96 Hours @ 100% Relative Humidity & 2 Atm. • Resistance to Soldering Heat Per JS22, MB106 - 22/0. 0 260 C Solder Dip. • Temperature Cycle Per MS883, M1010 - 50/0. 0 0 1000 Cycles, -65 C to 150 C. • 2325 Orchard Parkway • San Jose CA 95131 • PACKAGE ASSEMBLY PROCESS QUALIFICATION Test Flow & Conditions - Mechanical Physical Dimensions Per MS883, M2016. 15/0 • Lead Integrity Per MS883, M2004. 45/0 • Adhesion of Lead Finish Per MS883, M2025. 15/0 • Resistance To Solvents Per JS22, MB107 or MS883, M2015. 3/0 • Solderability Per MS883, M2003. 38/1 8 Hours Steam Age. 260 C Solder Dip. 0 CONFIGURATOR, ASSEMBLY MATERIALS 1/18/99 • 2325 Orchard Parkway • San Jose CA 95131 • 1. ASSEMBLY HOUSES: AAPI 2. LEAD FRAME Cu (C151 3/4H) 3. PLATINGS DIE ATTACH: OUTER LEADS: 4. DIE ATTACH MATERIAL SILVER FILLED EPOXY 5. DIE ATTACH VENDOR AND NUMBER ABLE BOND 6. WIRE BONDING TECHNIQUE AT DIE AND LEAD FRAME THERMOSONIC 7. BOND WIRE MATERIAL AND DIAMETER Au 99.99% 8. K&S 1484 Turbo/Turbo Plus WIRE BONDING EQUIPMENT 9. MOLDING COMPOUND Ag 150 u” 300 u” SOLDER PLATE, Sn/Pb 85+-10% / 15+-10% 84 - 1LMISR4 1.0 OR 1.3 MIL SUMITOMO 63000H UL MATERIAL MOISTURE SENSITIVITY GLASS TRANSITION TEMP. UL 94V - 0 LEVEL 2 per JESD22-A113 155 - 175 DEGR C (7HR CURE, 175 DEGR) • 2325 Orchard Parkway • San Jose CA 95131 • Configurator 20 Lead PLCC Package Qualification DATE: August 18, 1998 TEST SUMMARY 20PLCC Package PQC-6979 TEST DESCRIPTION PASS/FAIL QTY/ACC# TST SPS QUANTITY FAILED STANDARD PRODUCTION SCREEN 495/- 0 BASELINE ELECT PARAMS 479/- 0 PASS PASS Pass 77/1 77/1 77/1 77/1 5 5 5 5 0 0 0 PRECONDITION -Moisture Soak -IR Reflow -Flux/Reflow -Endpt Elect Params PASS 354/0 354/0 354/0 354/0 354/0 0 0 0 0 0 0 C 2 - 85/85 BIASED LIFETEST - 184 Hr Elect Params - 584 Hr Elect Params - 1017 Hr Elect Params PASS PASS PASS 77/1 77/1 77/1 77/1 5 5 5 2 0 0 0 0 C 3 - AUTOCLAVE -96 Hr Elect Params PASS 100/1 100/1 8 8 0 0 PASS 77/1 77/1 77/1 5 5 5 0 0 0 D 5 - THERMAL SHOCK -Visual Inspection -Endpt Elect Params PASS 77/1 77/1 77/1 5 5 5 0 0 0 D 1 - PHYSICAL DIMENSIONS PASS 15/0 1 0 D 2 - LEAD INTEGRITY PASS 3 (45/0) (3) 0 D 7 - ADHESION OF LEAD FINISH PASS 3 (15/0) 0 0 B2 - RESISTANCE TO SOLVENTS B 3 - SOLDERABILITY PASS PASS 3/0 4 (22/0) 0 (2) 0 0 C 4 - DATA RETENTION BAKE -188 HR Elect Params -504 HR Elect Params -1022 HR Elect Params D 4 -TEMPERATURE CYCLE - Visual Inspection - Endpt Elect Params NOTE# Quantities refer to devices unless enclosed in ( ) , Which indicate Sub-Units such as leads or bonds • 2325 Orchard Parkway • San Jose CA 95131 •