High Temperature, 16-Bit, 600 kSPS PulSAR® ADC AD7981 Data Sheet TYPICAL APPLICATION CIRCUIT Extreme high temperature operation Specified temperature range: −55°C to +175°C High performance 16-bit resolution with no missing codes 600 kSPS throughput with no latency/pipeline delay SNR: 91 dB typical at 1 kHz input frequency THD: −102 dB typical at 1 kHz input frequency INL: ±2.0 LSB maximum, DNL: ±0.9 LSB maximum Low power dissipation 2.25 mW typical at 600 kSPS (VDD only) 4.65 mW typical at 600 kSPS (total) 70 µW typical at 10 kSPS Small footprint 10-lead, 3 mm × 5 mm, monometallic wire bonding MSOP Pseudo differential analog input range 0 V to VREF with VREF between 2.4 V and 5.1 V Easy to use Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic interface SPI-/QSPI-/MICROWIRE-/DSP-compatible digital interface Daisy-chain multiple ADCs and busy indicator 2.5V to 5.0V 0V TO VREF IN+ IN– 2.5V REF VDD VIO SDI AD7981 SCK SDO GND 1.8V TO 5.0V 3- OR 4-WIRE INTERFACE (SPI, DAISY CHAIN, CS) CNV Figure 1. APPLICATIONS Downhole drilling and instrumentation Avionics Heavy industrial High temperature environments GENERAL DESCRIPTION The AD79811 is a 16-bit, successive approximation, analog-todigital converter (ADC) designed for high temperature operation. The AD7981 is capable of sample rates up to 600 kSPS while maintaining low power consumption from a single power supply, VDD. It is a fast throughput, high accuracy, high temperature, successive approximation register (SAR) ADC and packaged in a small form factor with a versatile serial port interface (SPI). On the CNV rising edge, the AD7981 samples an analog input, IN+, between 0 V and REF with respect to a ground sense, IN−. The reference voltage, REF, is applied externally and can be set independent of the supply voltage, VDD. The device power scales linearly with throughput. The SPI-compatible serial interface also features the ability, using the SDI input, to daisy-chain several ADCs on a single, 1 3-wire bus and provides an optional busy indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate supply VIO. For space constrained applications, the AD7981 is available in a 10-lead mini small outline package (MSOP) with operation specified from −55°C to +175°C. This package is designed for robustness at extreme temperatures, including monometallic wire bonding, and is qualified for up to 1000 hours of operation at the maximum temperature rating. The AD7981 is a member of a growing series of high temperature qualified products offered by Analog Devices, Inc. For a complete selection of available high temperature products, see the high temperature product list and qualification data available at www.analog.com/hightemp. Protected by U.S. Patent 6,703,961. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 12479-001 FEATURES AD7981 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input ............................................................................... 15 Applications ....................................................................................... 1 Driver Amplifier Choice ........................................................... 15 Typical Application Circuit ............................................................. 1 Voltage Reference Input ............................................................ 16 General Description ......................................................................... 1 Power Supply............................................................................... 16 Revision History ............................................................................... 2 Digital Interface .......................................................................... 16 Specifications..................................................................................... 3 CS Mode, 3-Wire Without Busy Indicator ............................. 17 Timing Specifications .................................................................. 5 CS Mode, 3-Wire with Busy Indicator .................................... 18 Absolute Maximum Ratings ............................................................ 6 CS Mode, 4-Wire Without Busy Indicator ............................. 19 ESD Caution .................................................................................. 6 CS Mode, 4-Wire with Busy Indicator .................................... 20 Pin Configuration and Function Descriptions ............................. 7 Chain Mode Without Busy Indicator ...................................... 21 Typical Performance Characteristics ............................................. 8 Chain Mode with Busy Indicator ............................................. 22 Terminology .................................................................................... 12 Applications Information .............................................................. 23 Theory of Operation ...................................................................... 13 Printed Circuit Board (PCB) Layout ....................................... 24 Circuit Information .................................................................... 13 Outline Dimensions ....................................................................... 25 Converter Operation .................................................................. 13 Ordering Guide .......................................................................... 25 Typical Connection Diagram.................................................... 14 REVISION HISTORY 10/14—Revision 0: Initial Version Rev. 0 | Page 2 of 25 Data Sheet AD7981 SPECIFICATIONS VDD = 2.5 V, VIO = 2.3 V to 5.5 V, VREF = 5 V, TA = −55°C to +175°C, unless otherwise noted. Table 1. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Analog Input Common-Mode Rejection Ratio (CMRR) Leakage Current at 25°C Input Impedance ACCURACY No Missing Codes Differential Nonlinearity Integral Nonlinearity Transition Noise Gain Error 2 Gain Error Temperature Drift Zero Error2 Zero Temperature Drift Power Supply Sensitivity THROUGHPUT Conversion Rate Transient Response AC ACCURACY 3 Dynamic Range Oversampled Dynamic Range 4 Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Signal-to-Noise-and-Distortion (SINAD) Test Conditions/Comments Min 16 IN+ − IN− IN+ IN− fIN = 100 kHz Acquisition phase 0 −0.1 −0.1 VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V TMIN to TMAX TMIN to TMAX Typ Unit Bits VREF VREF + 0.1 +0.1 V V V dB nA 60 1 See the Analog Input section 16 −0.9 −2.0 −1 VDD = 2.5 V ± 5% ±0.4 ±0.5 ±0.7 ±0.6 0.75 1.2 ±2 ±0.35 ±0.08 0.45 ±0.1 0 89 +0.9 +2.0 +1 600 290 Full-scale step VREF = 5 V VREF = 2.5 V OSR = 256 fIN = 1 kHz, VREF = 5 V fIN = 1 kHz, VREF = 2.5 V fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz, VREF = 5 V fIN = 1 kHz, VREF = 2.5 V Max 92 87 110 91 86 104 −102 90.5 85.5 Bits LSB 1 LSB1 LSB1 LSB1 LSB1 LSB1 LSB1 ppm/°C mV ppm/°C LSB1 kSPS ns dB dB dB dB dB dB dB dB dB LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 µV. See the Terminology section. These specifications include full temperature range variation, but not the error contribution from the external reference. 3 All ac accuracy specifications in dB are referred to an input full-scale range (FSR). Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 4 The oversampled dynamic range is the ratio of the peak signal power to the noise power (for a small input) measured in the ADC output FFT from dc up to fS/(2 × OSR), where fS is the ADC sample rate and OSR is the oversampling ratio. 1 2 Rev. 0 | Page 3 of 25 AD7981 Data Sheet VDD = 2.5 V, VIO = 2.3 V to 5.5 V, VREF = 5 V, TA = −55°C to +175°C, unless otherwise noted. Table 2. Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay DIGITAL INPUTS Logic Levels VIL VIH Test Conditions/Comments Min 2.4 VDD Only REF Only VIO Only Energy per Conversion TEMPERATURE RANGE Specified Performance 3 Max Unit 5.1 600 kSPS, VREF = 5 V 330 V µA VDD = 2.5 V 10 2.0 MHz ns VIO > 3 V VIO ≤ 3 V VIO > 3 V VIO ≤ 3 V –0.3 –0.3 0.7 × VIO 0.9 × VIO −1 −1 IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH POWER SUPPLIES VDD VIO VIO Range Standby Current 1, 2 Power Dissipation Total Typ 0.3 × VIO 0.1 × VIO VIO + 0.3 VIO + 0.3 +1 +1 Serial 16 bits straight binary Conversion results available immediately after completed conversion 0.4 VIO − 0.3 ISINK = 500 µA ISOURCE = −500 µA 2.375 2.3 1.8 Specified performance VDD and VIO = 2.5 V VDD = 2.625 V, VREF = 5 V, VIO = 3 V 10 kSPS 600 kSPS 600 kSPS 600 kSPS 600 kSPS TMIN to TMAX 2.5 2.625 5.5 5.5 0.35 70 4.65 2.25 1.5 0.9 7.75 −55 With all digital inputs forced to VIO or GND as required. During the acquisition phase. 3 Qualified for up to 1000 hours of operation at the maximum temperature rating. 1 2 Rev. 0 | Page 4 of 25 7.0 +175 V V V µA µA µA V V V V V µA µW mW mW mW mW nJ/sample °C Data Sheet AD7981 TIMING SPECIFICATIONS TA = −55°C to +175°C, VDD = 2.375 V to 2.625 V, VIO = 3.3 V to 5.5 V, unless otherwise stated. See Figure 2 and Figure 3 for load conditions. Table 3. Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Period (Chain Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V CNV or SDI Low to SDO D15 MSB Valid (CS Mode) VIO Above 3 V VIO Above 2.3 V CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge SDI Valid Hold Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (Chain Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) SCK Valid Hold Time from CNV Rising Edge (Chain Mode) SDI Valid Setup Time from SCK Falling Edge (Chain Mode) SDI Valid Hold Time from SCK Falling Edge (Chain Mode) SDI High to SDO High (Chain Mode with Busy Indicator) tSCKL tSCKH tHSDO tDSDO Unit ns ns ns ns 10.5 12 13 15 ns ns ns ns 11.5 13 14 16 4.5 4.5 3 ns ns ns ns ns ns ns 9.5 11 12 14 ns ns ns ns 10 15 20 ns ns ns ns ns ns ns ns ns ns ns tEN tDIS tSSDICNV tHSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI 5 2 0 5 5 2 3 15 X% VIO1 tDELAY VIH2 VIL2 1.4V CL 20pF VIH2 VIL2 1FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V, X = 70 AND Y = 30. VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS SPECIFICATIONS IN TABLE 2. 12479-002 IOH Max 900 tSCK tDELAY 500µA Typ Y% VIO1 IOL TO SDO Min 625 290 1667 10 2MINIMUM Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. 0 | Page 5 of 25 12479-003 500µA Symbol tCONV tACQ tCYC tCNVH tSCK AD7981 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Analog Inputs IN+, IN− to GND1 Supply Voltage REF, VIO to GND VDD to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature Thermal Impedance (10-Lead MSOP) θJA θJC Lead Temperature Vapor Phase (60 sec) Infrared (15 sec) ESD Ratings Human Body Model Machine Model Field-Induced Charged Device Model 1 Rating −0.3 V to VREF + 0.3 V or ±130 mA −0.3 V to +6 V −0.3 V to +3 V +3 V to −6 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 176.4°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 200°C/W 44°C/W 215°C 220°C 2 kV 200 V 1.25 kV See the Analog Input section. Rev. 0 | Page 6 of 25 Data Sheet AD7981 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 2 IN+ 3 IN– 4 GND 5 AD7981 TOP VIEW (Not to Scale) 9 SDI 8 SCK 7 SDO 6 CNV 12479-004 10 VIO REF 1 VDD Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 Mnemonic REF Type 1 AI 2 3 VDD IN+ P AI 4 5 6 IN− GND CNV AI P DI 7 8 9 SDO SCK SDI DO DI DI 10 VIO P Description Reference Input Voltage. The REF range is from 2.4 V to 5.1 V. It is referred to the GND pin. Decouple REF with a 10 µF capacitor as close as possible to the pin. Power Supply. Analog Input. This pin is referred to IN−. The voltage range, for example, the difference between IN+ and IN−, is 0 V to VREF. Analog Input Ground Sense. Connect this pin to the analog ground plane or to a remote sense ground. Power Supply Ground. Conversion Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the device: chain or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, read the data when CNV is high. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). AI = analog input, DI = digital input, DO = digital output, and P = power. 1 Rev. 0 | Page 7 of 25 AD7981 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5 V, VREF = 5.0 V, VIO = 3.3 V, unless otherwise noted. 0.3 0.4 0.2 0.2 0.1 DNL (LSB) 0.6 0 –0.2 –0.6 –0.3 –0.8 –0.4 6901 13801 20701 27601 34501 41401 48301 55201 62101 –0.5 12479-006 1 1.0 0.5 0.4 0.3 0.4 0.2 0.2 0.1 DNL (LSB) 0.6 0 –0.2 0 –0.1 –0.2 –0.6 –0.3 –0.8 –0.4 –1.0 –0.5 6397 12793 19189 25585 31981 38377 44773 51169 57565 63961 CODE 12479-007 –0.4 1 6901 13801 20701 27601 34501 41401 48301 55201 62101 Figure 8. Differential Nonlinearity (DNL) vs. Code and Temperature, VREF = 5.0 V 25°C 175°C 0.8 1 CODE Figure 5. Integral Nonlinearity (INL) vs. Code and Temperature, VREF = 5.0 V 25°C 175°C 1 6557 13113 19669 26225 32781 39337 45893 52449 59005 CODE Figure 6. Integral Nonlinearity (INL) vs. Code and Temperature, VREF = 2.5 V Figure 9. Differential Nonlinearity (DNL) vs. Code and Temperature, VREF = 2.5 V 0 0 fS = 1 MSPS fIN = 10kHz –20 AMPLITUDE (dB OF FULL SCALE) –40 fS = 1 MSPS fIN = 10kHz SNR = 86.4dB THD = –103.7dB SFDR = 104.2dB SINAD = 86dB –20 SNR = 91.3dB THD = –104.9dB SFDR = 105.5dB SINAD = 90.8dB –60 –80 –100 –120 –140 –160 –40 –60 –80 –100 –120 –140 –180 0 100 200 300 FREQUENCY (kHz) 400 500 12479-038 –160 Figure 7. 10 kHz FFT, VREF = 5.0 V –180 0 100 200 300 FREQUENCY (kHz) Figure 10. 10 kHz FFT, VREF = 2.5 V Rev. 0 | Page 8 of 25 400 500 12479-058 INL (LSB) –0.1 –0.2 CODE AMPLITUDE (dB OF FULL SCALE) 0 –0.4 –1.0 25°C 175°C 0.4 12479-008 0.8 INL (LSB) 0.5 25°C 175°C 12479-009 1.0 Data Sheet AD7981 60k 180k 168591 52212 160k 50k 140k 40k COUNTS COUNTS 120k 100k 80k 60k 32417 31340 30k 20k 52710 38751 40k 10k 7225 6807 20k 27 0 1201 829 33 2 0 0 0 CODE IN HEX 0 0 0 539 16 502 14 0 0 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006 CODE IN HEX 12479-059 0 8003 8004 8005 8006 8007 8008 8009 800A 800B 800C 800D 800E 800F 12479-042 0 Figure 14. Histogram of a DC Input at the Code Center, VREF = 2.5 V Figure 11. Histogram of a DC Input at the Code Center, VREF = 5.0 V 95 70k 94 59691 59404 60k 93 92 SNR (dB) COUNTS 50k 40k 30k 91 90 89 88 20k 87 150 86 93 3 0 7FFF 8000 8001 8002 8003 8004 8005 8006 8007 8008 CODE IN HEX 85 –10 –9 SINAD (dB) 94 92 90 88 SINAD 86 84 82 80 2.00 2.50 3.00 3.50 4.00 4.50 5.00 VREF (V) –118 –5 –4 –3 –2 –1 0 110 –55°C +25°C +175°C SFDR 105 –116 –114 THD (dB) ENOB –120 ENOB (dB) 96 16.00 15.75 15.50 15.25 15.00 14.75 14.50 14.25 14.00 13.75 13.50 13.25 13.00 12.75 12.50 12.25 12.00 11.75 11.50 11.25 11.00 5.50 –6 Figure 15. SNR vs. Input Level 100 –112 –110 95 THD –108 90 –106 –104 85 –102 12479-114 98 –55°C +25°C +175°C –7 INPUT LEVEL (dB OF FULL SCALE) Figure 12. Histogram of a DC Input at the Code Transition, VREF = 5.0 V 100 –8 12479-046 2 SFDR (dB) 0 –100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VREF (V) Figure 16. THD and SFDR vs. Reference Voltage (VREF) Figure 13. SINAD and ENOB vs. Reference Voltage (VREF) Rev. 0 | Page 9 of 25 80 5.5 12479-117 0 6295 5428 12479-043 10k AD7981 Data Sheet –110 100 –55°C +25°C +175°C –55°C +25°C +175°C –105 95 THD (dB) SINAD (dB) –100 90 85 –95 –90 80 10k 100k 1M INPUT FREQUENCY (Hz) –80 1k 12479-118 75 1k 10k Figure 17. SINAD vs. Input Frequency 100 1M Figure 20. THD vs. Frequency –109 SNR AT VREF = 5V SNR AT VREF = 2.5V 98 100k FREQUENCY (Hz) 12479-121 –85 –108 96 –107 –106 92 THD (dB) SNR (dB) 94 90 88 –105 –104 86 –103 84 –102 20 40 60 80 100 120 140 160 180 200 TEMPERATURE (°C) 0.9 OPERATING CURRENT (mA) 0.7 0.6 0.5 0.4 0.3 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.1 2.425 2.475 2.525 2.575 2.625 VDD (V) Figure 19. Operating Currents vs. Supply Voltage (VDD) IVDD IVIO IREF 0.8 0.2 12479-120 OPERATING CURRENT (mA) 1.0 0.8 0 2.375 190 140 Figure 21. THD vs. Temperature IVDD IVIO IREF 0.9 90 TEMPERATURE (°C) Figure 18. SNR vs. Temperature 1.0 40 –10 0 –55 –30 –5 20 45 70 95 120 145 TEMPERATURE (°C) Figure 22. Operating Currents vs. Temperature Rev. 0 | Page 10 of 25 170 12479-123 0 THD AT VREF = 5V THD AT VREF = 2.5V –101 –60 12479-119 80 –60 –40 –20 12479-122 82 Data Sheet 180 IVDD IVIO IVDD + IVIO 160 140 120 100 80 60 40 20 0 –60 –40 –20 0 20 40 60 80 100 120 140 160 180 200 220 TEMPERATURE (°C) 12479-124 TYPICAL POWER-DOWN CURRENT (µA) 200 AD7981 Figure 23. Power-Down Current vs. Temperature Rev. 0 | Page 11 of 25 AD7981 Data Sheet TERMINOLOGY Integral Nonlinearity (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 25). Differential Nonlinearity (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error The first transition occurs at a level ½ LSB above analog ground (38.1 µV for the 0 V to 5 V range). The offset error is the deviation of the actual transition from that point. Gain Error The last transition (from 111 … 10 to 111 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset is adjusted out. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by the following formula: Effective Resolution Effective resolution is calculated as Effective Resolution = log2(2N/RMS Input Noise) and is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. It is measured with a signal at −60 dBFS to include all noise sources and DNL artifacts. The value for dynamic range is expressed in dB. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB. Signal-to-Noise-and-Distortion (SINAD) Ratio SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in dB. Aperture Delay Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and when the input signal is held for a conversion. ENOB = (SINADdB − 1.76)/6.02 and is expressed in bits. Noise-Free Code Resolution Noise-free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is calculated as Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise) and is expressed in bits. Rev. 0 | Page 12 of 25 Data Sheet AD7981 THEORY OF OPERATION IN+ MSB LSB 32,768C 16,384C 4C 2C C SWITCHES CONTROL SW+ C BUSY REF COMP GND 32,768C 16,384C 4C 2C C CONTROL LOGIC OUTPUT CODE C LSB MSB SW– 12479-011 CNV IN– Figure 24. ADC Simplified Schematic CIRCUIT INFORMATION The AD7981 is a fast, low power, single-supply, precise 16-bit ADC that uses a successive approximation architecture. The AD7981 is capable of converting 600,000 samples per second (600 kSPS) and powers down between conversions. When operating at 10 kSPS, for example, it consumes 70 µW typically, ideal for battery-powered applications. The AD7981 provides the user with on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. The AD7981 can be interfaced to any 1.8 V to 5 V digital logic family. It is housed in a 10-lead MSOP that combines space savings and allows flexible configurations. It is pin-for-pin compatible with the 18-bit AD7982. CONVERTER OPERATION The AD7981 is a successive approximation ADC based on a charge redistribution digital-to-analog converter (DAC). Figure 24 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the input of the comparator are connected to GND via the SW+ and SW− switches. All independent switches are connected to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. When the acquisition phase is completed and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the inputs, IN+ and IN−, captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 … VREF/65,536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the device returns to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator. Because the AD7981 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. Rev. 0 | Page 13 of 25 AD7981 Data Sheet Transfer Functions Table 6. Output Codes and Ideal Input Voltages The ideal transfer characteristic for the AD7981 is shown in Figure 25 and Table 6. Description FSR – 1 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB –FSR + 1 LSB –FSR 111 ... 101 1 2 Analog Input Digital Output Code 0xFFFF1 0x8001 0x8000 0x7FFF 0x0001 0x00002 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND). This is also the code for an underranged analog input (VIN+ − VIN− below VGND). TYPICAL CONNECTION DIAGRAM 000 ... 010 Figure 26 shows an example of the recommended connection diagram for the AD7981 when multiple supplies are available. 000 ... 001 000 ... 000 –FSR –FSR + 1LSB –FSR + 0.5LSB +FSR – 1 LSB +FSR – 1.5 LSB 12479-012 ANALOG INPUT Figure 25. ADC Ideal Transfer Function V+ V+ REF1 REFERENCE BUFFER 100nF 100nF 10µF2 2.5V 100nF V– V+ 1.8V TO 5V 100nF 49.9Ω DRIVER AMPLIFIER3 0V TO VREF REF 2.7nF V– VDD VIO SDI IN+ SCK 3- OR 4-WIRE INTERFACE5 AD7981 SDO 4 IN– GND 1SEE CNV THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. (X5R). 2C REF IS USUALLY A 10µF CERAMIC CAPACITOR 3SEE THE DRIVER AMPLIFIER CHOICE SECTION. 4OPTIONAL 5SEE FILTER. SEE THE ANALOG INPUT SECTION. THE DIGITAL INTERFACE FOR THE MOST CONVENIENT INTERFACE MODE. Figure 26. Typical Application Diagram with Multiple Supplies Rev. 0 | Page 14 of 25 12479-013 ADC CODE (STRAIGHT BINARY) 111 ... 111 111 ... 110 VREF = 5 V 4.999924 V 2.500076 V 2.5 V 2.499924 V 76.3 µV 0V Data Sheet AD7981 ANALOG INPUT DRIVER AMPLIFIER CHOICE Figure 27 shows an equivalent circuit of the input structure of the AD7981. Although the AD7981 is easy to drive, the driver amplifier must meet the following requirements: The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN+ and IN−. Ensure that the analog input signal never exceeds the supply rails by more than 0.3 V, because this causes these diodes to become forward-biased and to start conducting current. A transient with a very short duration of 10 ms applied on the analog inputs, IN+ and IN−, during latch-up testing shows that these diodes can then handle a forward-biased current of 130 mA maximum. For instance, these conditions may eventually occur when the supplies of the input buffer (U1) are different from VDD. In such a case (for example, an input buffer with a short circuit), the current limitation can be used to protect the device. • SNRLOSS REF IN+ OR IN– CPIN RIN D2 GND Figure 27. Equivalent Analog Input Circuit The analog input structure allows the sampling of the true differential signal between IN+ and IN−. By using these differential inputs, signals common to both inputs are rejected. During the acquisition phase, the impedance of the analog inputs (IN+ and IN−) can be modeled as a parallel combination of the capacitor, CPIN, and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 400 Ω and is a lumped component made up of some serial resistors and the on resistance of the switches. CIN is typically 30 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are opened, the input impedance is limited to CPIN. RIN and CIN make a onepole, low-pass filter that reduces undesirable aliasing effects and limits the noise. 47.3 = 20 log π 2 2 47.3 + f −3dB (Ne N ) 2 where: f–3dB is the input bandwidth in MHz of the AD7981 (10 MHz) or the cutoff frequency of the input filter, if one is used. N is the noise gain of the amplifier (for example, 1 in buffer configuration). eN is the equivalent input noise voltage of the op amp, in nV/√Hz. CIN 12479-014 D1 The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and transition noise performance of the AD7981. The noise coming from the driver is filtered by the one-pole, low-pass filter of the AD7981 analog input circuit made by RIN and CIN or by the external filter, if one is used. Because the typical noise of the AD7981 is 47.3 µV rms, the SNR degradation due to the amplifier is • • For ac applications, the driver must have a THD performance commensurate with the AD7981. For multichannel multiplexed applications, the driver amplifier and the AD7981 analog input circuit must settle for a full-scale step onto the capacitor array at a 16-bit level (0.0015%, 15 ppm). In an amplifier data sheet, settling times at 0.1% to 0.01% are more commonly specified, and may differ significantly from the settling time at a 16-bit level and must be verified prior to driver selection. The AD8634 is a rail-to-rail output, precision, low power, high temperature qualified, dual amplifier recommended for driving the input of the AD7981. When the source impedance of the driving circuit is low, the AD7981 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. Rev. 0 | Page 15 of 25 AD7981 Data Sheet VOLTAGE REFERENCE INPUT 1 VDD = 2.5V VREF = 5V VIO = 3V When REF is driven by a very low impedance source, a ceramic chip capacitor is appropriate for optimum performance. The high temperature qualified low temperature drift ADR225 2.5 V reference and the low power AD8634 reference buffer are recommended for the AD7981. IVDD 0.1 IREF IVIO 0.01 0.001 10000 The REF pin must be decoupled with a ceramic chip capacitor of at least 10 µF (X5R, 1206 size) for optimum performance. 100000 THROUGHPUT RATE (SPS) 600000 12479-055 OPERATING CURRENTS (mA) The AD7981 voltage reference input, REF, has a dynamic input impedance and must therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Printed Circuit Board (PCB) Layout section. Figure 29. Operating Currents vs. Throughput Rate There is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins. DIGITAL INTERFACE POWER SUPPLY Although the AD7981 has a reduced number of pins, it offers flexibility in its serial interface modes. The AD7981 uses two power supply pins: a core supply, VDD, and a digital input/output interface supply, VIO. VIO allows direct interface with any logic between 1.8 V and 5 V. To reduce the number of supplies needed, tie VIO and VDD together. The AD7981 is independent of power supply sequencing between VIO and VDD. Additionally, it is insensitive to power supply variations over a wide frequency range, as shown in Figure 28. 80 PSRR (dB) 75 The AD7981, when in CS mode, is compatible with SPI, QSPI™, MICROWIRE™, and digital hosts. The AD7981 interface can use either a 3-wire or 4-wire interface. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections and is useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). The 4-wire interface is useful in low jitter sampling or simultaneous sampling applications. The AD7981, when in chain mode, provides a daisy-chain feature using the SDI input for cascading multiple ADCs on a single data line, similar to a shift register. 70 The mode in which the device operates depends on the SDI level when the CNV rising edge occurs. CS mode is selected if SDI is high, and chain mode is selected if SDI is low. The SDI hold time is such that, when SDI and CNV are connected together, chain mode is selected. 65 55 1 10 100 FREQUENCY (kHz) 1000 12479-062 60 Figure 28. PSRR vs. Frequency The AD7981 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate, which makes the device ideal for low sampling rate (even of a few Hz) and low battery-powered applications. In either mode, the AD7981 offers the flexibility to optionally force a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and to trigger the data reading. Otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. The busy indicator feature is enabled • • Rev. 0 | Page 16 of 25 In CS mode if CNV or SDI is low when the ADC conversion ends (see Figure 33 and Figure 37, respectively). In chain mode if SCK is high during the CNV rising edge (see Figure 41). Data Sheet AD7981 CS MODE, 3-WIRE WITHOUT BUSY INDICATOR time elapses and then held high for the maximum conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7981 enters the acquisition phase and powers down. The 3-wire CS mode without busy indicator is typically used when a single AD7981 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 30, and the corresponding timing is given in Figure 31. When CNV goes low, the MSB is output onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that it has an acceptable hold time. After the 16th SCK falling edge or when CNV goes high, whichever is earlier, SDO returns to high impedance. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. When a conversion is initiated, it continues until completion, irrespective of the state of CNV, which can be useful, for instance, for bringing CNV low to select other SPI devices, such as analog multiplexers. However, CNV must return high before the minimum conversion CONVERT DIGITAL HOST CNV VIO SDI AD7981 SDO DATA IN 12479-015 SCK CLK Figure 30. 3-Wire CS Mode Without Busy Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 2 3 14 tHSDO 16 tSCKH tEN SDO 15 tDIS tDSDO D15 D14 D13 D1 D0 Figure 31. 3-Wire CS Mode Without Busy Indicator Serial Interface Timing (SDI High) Rev. 0 | Page 17 of 25 12479-016 1 SCK AD7981 Data Sheet CS MODE, 3-WIRE WITH BUSY INDICATOR When the conversion is complete, SDO goes from high impedance to low. With a pull-up resistor on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD7981 then enters the acquisition phase and powers down. The data bits are clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 17th SCK falling edge or when CNV goes high, whichever is earlier, SDO returns to high impedance. The 3-wire CS mode with busy indicator is typically used when a single AD7981 is connected to an SPI-compatible digital host having an interrupt input. The connection diagram is shown in Figure 32, and the corresponding timing is given in Figure 33. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion, irrespective of the state of CNV. Prior to the minimum conversion time, CNV can be used to select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time elapses and then held low for the maximum conversion time to guarantee the generation of the busy signal indicator. If multiple AD7981 devices are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. It is recommended to keep this contention as short as possible to limit extra power dissipation. CONVERT VIO CNV VIO DIGITAL HOST 47kΩ AD7981 SDO DATA IN SCK IRQ 12479-017 SDI CLK Figure 32. 3-Wire CS Mode with Busy Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 1 2 3 15 tHSDO 16 17 tSCKH tDIS tDSDO SDO D15 D14 D1 D0 Figure 33. 3-Wire CS Mode with Busy Indicator Serial Interface Timing (SDI High) Rev. 0 | Page 18 of 25 12479-018 SCK Data Sheet AD7981 CS MODE, 4-WIRE WITHOUT BUSY INDICATOR time elapses and then held high for the maximum conversion time to avoid the generation of the busy signal indicator. The 4-wire CS mode without busy indicator is typically used when multiple AD7981 devices are connected to an SPI-compatible digital host. A connection diagram example using two AD7981 devices is shown in Figure 34, and the corresponding timing is given in Figure 35. When the conversion is complete, the AD7981 enters the acquisition phase and powers down. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 16th SCK falling edge or when SDI goes high, whichever is earlier, SDO returns to high impedance, and another AD7981 can be read. With SDI high, a rising edge on CNV initiates a conversion, selects CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI can be used to select other SPI devices, such as analog multiplexers, but SDI must be returned high before the minimum conversion CS2 CS1 CONVERT CNV AD7981 SDO SDI DIGITAL HOST AD7981 SCK SDO SCK 12479-019 SDI CNV DATA IN CLK Figure 34. 4-Wire CS Mode Without Busy Indicator Connection Diagram tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI(CS1) tHSDICNV SDI(CS2) tSCK tSCKL SCK 2 3 14 tHSDO SDO 15 16 17 18 30 31 32 tSCKH tEN tDIS tDSDO D15 D14 D13 D1 D0 D15 D14 Figure 35. 4-Wire CS Mode Without Busy Indicator Serial Interface Timing Rev. 0 | Page 19 of 25 D1 D0 12479-020 1 AD7981 Data Sheet CS MODE, 4-WIRE WITH BUSY INDICATOR select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time elapses and then held low for the maximum conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low. The 4-wire CS mode with busy indicator is typically used when a single AD7981 is connected to an SPI-compatible digital host that has an interrupt input, and it is desired to keep CNV, which is used to sample the analog input, independent of the signal used to select the data reading. This requirement is particularly important in applications where low jitter on CNV is desired. With a pull-up resistor on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7981 then enters the acquisition phase and powers down. The data bits are clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time. After the optional 17th SCK falling edge or SDI going high, whichever is earlier, the SDO returns to high impedance. The connection diagram is shown in Figure 36, and the corresponding timing is given in Figure 37. With SDI high, a rising edge on CNV initiates a conversion, selects CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI can be used to CS1 CONVERT VIO CNV DIGITAL HOST 47kΩ AD7981 SDO DATA IN SCK IRQ 12479-021 SDI CLK Figure 36. 4-Wire CS Mode with Busy Indicator Connection Diagram tCYC CNV tCONV ACQUISITION tACQ CONVERSION ACQUISITION tSSDICNV SDI tSCK tHSDICNV tSCKL 2 3 15 tHSDO 16 17 tSCKH tDIS tDSDO tEN SDO D15 D14 D1 Figure 37. 4-Wire CS Mode with Busy Indicator Serial Interface Timing Rev. 0 | Page 20 of 25 D0 12479-022 1 SCK Data Sheet AD7981 CHAIN MODE WITHOUT BUSY INDICATOR during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDO, and the AD7981 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N clocks are required to read back the N ADCs. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and, consequently, more AD7981 devices in the chain, provided the digital host has an acceptable hold time. The total readback time allows a reduction in the maximum conversation rate. Chain mode without busy indicator can be used to daisy-chain multiple AD7981 devices on a 3-wire serial interface. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using two AD7981 devices is shown in Figure 38, and the corresponding timing is given in Figure 39. When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects chain mode, and disables the busy indicator. In this mode, CNV is held high CONVERT CNV AD7981 SDO SDI DIGITAL HOST AD7981 A SCK SDO DATA IN B SCK 12479-023 SDI CNV CLK Figure 38. Chain Mode Without Busy Indicator Connection Diagram SDIA = 0 tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL tSSCKCNV SCK 1 tHSCKCNV 2 3 14 16 17 18 30 31 32 D A1 DA0 tSCKH tHSDISCK tEN SDOA = SDIB 15 tSSDISCK DA15 DA14 DA13 D A1 DA0 DB1 DB0 tHSDO SDOB DB15 DB14 DB13 DA15 DA14 Figure 39. Chain Mode Without Busy Indicator Serial Interface Timing Rev. 0 | Page 21 of 25 12479-024 tDSDO AD7981 Data Sheet CHAIN MODE WITH BUSY INDICATOR data readback. When all ADCs in the chain have completed their conversions, the SDO pin of the ADC closest to the digital host (see the AD7981 ADC labeled C in Figure 40) is driven high. This transition on SDO can be used as a busy indicator to trigger the data readback controlled by the digital host. The AD7981 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N + 1 clocks are required to read back the N ADCs. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and, consequently, more AD7981 devices in the chain, provided the digital host has an acceptable hold time. Chain mode with busy indicator can also be used to daisy-chain multiple AD7981 devices on a 3-wire serial interface while providing a busy indicator. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using three AD7981 devices is shown in Figure 40, and the corresponding timing is given in Figure 41. When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects chain mode, and enables the busy indicator feature. In this mode, CNV is held high during the conversion phase and the subsequent CONVERT SDI AD7981 CNV SDO SDI CNV AD7981 SDO AD7981 SDI A B C SCK SCK SCK DIGITAL HOST SDO DATA IN IRQ 12479-025 CNV CLK Figure 40. Chain Mode with Busy Indicator Connection Diagram tCYC CNV = SDIA tCONV tACQ ACQUISITION CONVERSION ACQUISITION tSCK tSSCKCNV 1 tHSCKCNV 2 4 3 15 16 tSSDISCK SDOA = SDIB DA15 DA14 DB15 DB14 DC15 DC14 DA13 18 19 31 32 33 34 35 tSCKL tHSDISCK tEN 17 DA1 DA0 DB13 DB1 DB0 DA15 DA14 DA1 DA0 DC13 DC1 DC0 DB15 DB14 DB1 DB0 tDSDOSDI SDOC 49 tDSDOSDI tDSDO tDSDOSDI 48 tDSDOSDI tHSDO SDOB = SDIC 47 tDSDOSDI Figure 41. Chain Mode with Busy Indicator Serial Interface Timing Rev. 0 | Page 22 of 25 DA15 DA14 DA1 DA0 12479-026 SCK tSCKH Data Sheet AD7981 APPLICATIONS INFORMATION have information in the audio frequency range and higher. The AD7981 is ideal for sampling data from sensors with varying bandwidth requirements while maintaining power efficiency and accuracy. The small footprint of the AD7981 makes it easy to include multiple channels even in space constrained layouts, such as the very narrow board widths prevalent in downhole tools. In addition, the flexible digital interface allows simultaneous sampling in more demanding applications, while also allowing simple daisy-chained readback for low pin count systems. A growing number of industries demand low power electronics that can operate reliably at temperatures of 175°C and higher. The AD7981 enables precision analog signal processing from the sensor to the processor at high temperatures for these types of applications. Figure 42 shows the simplified signal chain of the data acquisition instrument. In downhole drilling, avionics, and other extreme temperature environment applications, signals from various sensors are sampled to collect information about the surrounding geologic formations. These sensors can take the form of electrodes, coils, piezoelectric, or other transducers. Accelerometers and gyroscopes provide information about the inclination, vibration, and rotation rate. Some of these sensors are very low bandwidth, whereas others can For a complete selection of available high temperature products, see the high temperature product list and qualification data available at www.analog.com/hightemp. ADR225 REFERENCE POWER MANAGEMENT COMMUNICATION TO SURFACE SENSOR SIGNALS ACOUSTIC, TEMPERATURE, RESISTIVITY, PRESSURE AD8634 AMP SENSORS AD8229 INST AMP COMMUNICATIONS INTERFACE AD7981 ADC AD8634 AMP AD7981 ADC PROCESSOR INERTIAL SENSORS INCLINATION, VIBRATION, ROTATION RATE ADXL206 ACCELEROMETER AD8634 AMP AD7981 ADC AD8634 GYROSCOPE AMP AD7981 ADC Figure 42. Simplified Data Acquisition System Signal Chain Rev. 0 | Page 23 of 25 MEMORY 12479-142 ADXRS645 AD7981 Data Sheet PRINTED CIRCUIT BOARD (PCB) LAYOUT Design the PCB that houses the AD7981 so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7981, with all its analog signals on the left side and all its digital signals on the right side, eases this task. AD7981 Use at least one ground plane. It can be common or split between the digital and analog section. If the ground plane is split, join the planes underneath the AD7981. 12479-028 Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7981 is used as a shield. Fast switching signals, such as CNV or clocks, must never run near analog signal paths. Avoid crossover of digital and analog signals. Figure 43. Example PCB Layout of the AD7981 (Top Layer) The AD7981 voltage reference input, REF, has a dynamic input impedance and must be decoupled with minimal parasitic inductances. The reference decoupling ceramic capacitor must be placed close to, ideally right up against, the REF and GND pins and connecting them with wide, low impedance traces. Decouple the AD7981 power supplies, VDD and VIO, with ceramic capacitors, typically 100 nF, placed close to the AD7981 and connected using short and wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. 12479-027 An example of a layout following these rules is shown in Figure 43 and Figure 44. Figure 44. Example PCB Layout of the AD7981 (Bottom Layer) Rev. 0 | Page 24 of 25 Data Sheet AD7981 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.23 0.13 6° 0° COMPLIANT TO JEDEC STANDARDS MO-187-BA 0.70 0.55 0.40 091709-A 0.15 0.05 COPLANARITY 0.10 Figure 45. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model1 AD7981HRMZ 1 Integral Nonlinearity (INL) ±2.0 LSB Temperature Range −55°C to +175°C Ordering Quantity 50 Package Description 10-Lead Mini Small Outline Package [MSOP] Z = RoHS Compliant Part. ©2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12479-0-10/14(0) Rev. 0 | Page 25 of 25 Package Option RM-10 Branding C7C