Title: Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances Project Name: SER Test of Actel, Xilinx and Altera FPGA instances in Dec’03 THE CHIP PROTECTOR Department: Document type: Engineering Test Report Version: 0.08 Date: 25-Oct-04 Confidentiality Level: 2 Distribution list: Eric Dupont Olivier Lauzeral Rémi Gaillard Marcos Olmos Code Reference: GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 iRoC iRoC iRoC iRoC GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR DOCUMENT CONTROL # 281 Released To (Company): ACTEL NDA Reference: 0-20-0002 Rev1 Released to (Person): Jonathan Alexander, Yankin Tanurhan, Ken O'Neill Source document reference: GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Requested By (iRoC Contact): O. Lauzeral Signature Approved By: Olivier Lauzeral Rémi Gaillard Marcos Olmos THIS DOCUMENT IS THE PROPERTY OF iRoC Technologies Before using it for any purpose, please contact iRoC Technologies. The iRoC logo, Product Names (e.g. Roban, Rockit, Smartestbed) are registered trademarks of iRoC Technologies. All other trademarks are property of their respective owners iRoC Technologies, SA World Trade Center, PO Box 1510 38025 Grenoble FRANCE + 33 438 120 763 Fax + 33 438 129 615 E mail [email protected] Web www.iroctech.com This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 2 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances Revision History Version Author Date 0.01 Marcos Olmos 15-Jan-04 0.02 Marcos Olmos 22-Jan-04 0.03 Marcos Olmos 2-Mar-04 0.04 Marcos Olmos 8-Mar-04 0.05 0.06 0.06A 0.07 Marcos Olmos Marcos Olmos Marcos Olmos Marcos Olmos 18-Mar-04 25-Mar-04 31 Mar-04 16-Apr-04 0.08 Marcos Olmos 25-Oct-04 Description of change First release - Added test strategy copied from the Test Plan [3] - Added error definitions copied from the Test Plan [3] - Added Analysis of critical vs non critical SEU in 4.4.2 - Added Bitmaps of errors in 4.4.4 - Added Chip to chip variation in 4.4.5 - Added consistency check in 4.4.6 - Added Special observations in 4.4.7 - Added cosmic ray results of the LANSCE campaign in Feb 04. - Completed cosmic ray results of the LANSCE campaign in Feb 04. - Added FIT at 5,000 ft - Linked excel files copied in appendix A - Added executive summary - Minor typographical errors corrected - Added alpha results for AX1000 and XC3S1000 - Added alpha results for APA1000 - Added alpha results for XC2V3000 - Added alpha results for EP1C20 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 3 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances Applicable Documents [1] Title: Doc. Number: Version: Date: Source: ASER test for FPGAs Commercial Proposal ACTEL 081903 v2 [2] Title: JEDEC Standard - Measurement and Reporting of Alpha Particles and Terrestrial Cosmicray-Induced Soft Errors in Semiconductor Devices JESD89 Doc. Number: Version: Date: Source: Sep 03 iRoC August 2001 JEDEC [3] Title: Doc. Number: Version: Date: Source: Test Plan for the SER Test of Actel, Xilinx and Altera FPGA instances GRE_2_ACTEL_SERTEST_DEC_03_ENG_TP_005 [4] Title: A. Taber and E. Normand, "Single Event Upset in Avionics", IEEE Trans. Nucl. Sci., NS-40, 120, 1993 0.05 24-Nov-03 iRoC Doc. Number: Version: Date: Source: This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 4 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances Table of contents 1 EXECUTIVE SUMMARY ...........................................................................................................11 2 OBJECT .........................................................................................................................................12 2.1 2.2 TEST STRATEGY ..............................................................................................................................12 ERROR DEFINITION ........................................................................................................................14 3 14 MEV TESTS..............................................................................................................................15 3.1 3.2 3.3 TESTED CONDITIONS AND SCHEDULE ...........................................................................................15 DEVICES TESTED.............................................................................................................................16 STABILITY WITHOUT NEUTRON BEAM ..........................................................................................16 4 14 MEV RESULTS........................................................................................................................17 4.1 4.2 4.3 4.3.1 4.3.2 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 CROSS-SECTION AND FIT CALCULATION .....................................................................................17 OVERALL FIT RESULTS .................................................................................................................18 ACCURACY OF RESULTS .................................................................................................................19 ERROR COUNT STATISTICS ...............................................................................................................19 FLUENCE MEASUREMENT ACCURACY ..............................................................................................20 DETAILED ANALYSIS ......................................................................................................................21 VOLTAGE INFLUENCE ON FIT ..........................................................................................................21 ANALYSIS OF CRITICAL VS NON CRITICAL SEU...............................................................................23 ANALYSIS OF SINGLE EVENT LATCHUP ............................................................................................24 BITMAPS OF ERRORS ........................................................................................................................28 CHIP TO CHIP VARIATION .................................................................................................................33 CONSISTENCY CHECK.......................................................................................................................34 SPECIAL OBSERVATIONS ..................................................................................................................34 5 14 MEV CONCLUSIONS.............................................................................................................35 6 LANSCE TESTS............................................................................................................................36 6.1 6.2 6.3 TESTED CONDITIONS AND SCHEDULE ...........................................................................................36 DEVICES TESTED.............................................................................................................................37 STABILITY WITHOUT NEUTRON BEAM ..........................................................................................38 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 5 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 7 LANSCE RESULTS ......................................................................................................................39 7.1 7.2 7.3 7.3.1 7.3.2 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 CROSS-SECTION AND FIT CALCULATION .....................................................................................39 OVERALL FIT RESULTS .................................................................................................................41 ACCURACY OF RESULTS .................................................................................................................42 ERROR COUNT STATISTICS ...............................................................................................................42 FLUENCE MEASUREMENT ACCURACY ..............................................................................................43 DETAILED ANALYSIS ......................................................................................................................44 VOLTAGE INFLUENCE ON FIT ..........................................................................................................44 ANALYSIS OF CRITICAL VS NON CRITICAL SEU...............................................................................48 ANALYSIS OF SINGLE EVENT LATCHUP ............................................................................................50 BITMAPS OF ERRORS ........................................................................................................................55 CHIP TO CHIP VARIATION .................................................................................................................60 CONSISTENCY CHECK.......................................................................................................................62 SPECIAL OBSERVATIONS ..................................................................................................................65 8 LANSCE CONCLUSIONS ...........................................................................................................68 9 ALPHA TESTS ..............................................................................................................................69 9.1 9.2 9.3 9.4 CHARACTERISTICS OF THE ALPHA SOURCES................................................................................69 TESTED CONDITIONS AND SCHEDULE ...........................................................................................70 DEVICES TESTED.............................................................................................................................72 STABILITY WITHOUT ALPHA SOURCE ...........................................................................................72 10 ALPHA RESULTS ........................................................................................................................73 10.1 10.2 10.3 10.3.1 10.3.2 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 10.4.7 CROSS-SECTION AND FIT CALCULATION .....................................................................................73 OVERALL FIT RESULTS .................................................................................................................74 ACCURACY OF RESULTS .................................................................................................................75 ERROR COUNT STATISTICS ...............................................................................................................75 FLUENCE MEASUREMENT ACCURACY ..............................................................................................76 DETAILED ANALYSIS ......................................................................................................................77 VOLTAGE INFLUENCE ON FIT ..........................................................................................................77 ANALYSIS OF CRITICAL VS NON CRITICAL SEU...............................................................................79 ANALYSIS OF SINGLE EVENT LATCHUP ............................................................................................80 BITMAPS OF ERRORS ........................................................................................................................83 CHIP TO CHIP VARIATION .................................................................................................................89 CONSISTENCY CHECK.......................................................................................................................91 SPECIAL OBSERVATIONS ..................................................................................................................93 11 ALPHA CONCLUSIONS .............................................................................................................94 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 6 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances A DETAILS OF CROSS-SECTIONS AND FIT ............................................................................95 A.1 A.2 A.3 14 MEV NEUTRONS ........................................................................................................................95 LANSCE .........................................................................................................................................97 ALPHA ...........................................................................................................................................102 B 95% CONFIDENCE INTERVALS ...........................................................................................106 C GEOMETRY FACTOR CALCULATION FOR ALPHA TESTS .........................................107 D TEST BOARD LAYOUT............................................................................................................110 D.1 D.2 D.3 D.4 D.5 AX1000..........................................................................................................................................110 APA1000 .......................................................................................................................................111 XC2V3000.....................................................................................................................................112 XC3S1000 .....................................................................................................................................113 EP1C20 .........................................................................................................................................114 List of Figures FIGURE 1. FIGURE 2. FIGURE 3. FIGURE 4. FIGURE 5. FIGURE 6. FIGURE 7. FIGURE 8. FIGURE 9. FIGURE 10. FIGURE 11. FIGURE 12. FIGURE 13. FIGURE 14. FIGURE 15. FIGURE 16. FIGURE 17. FIGURE 18. FIGURE 19. FIGURE 20. FIGURE 21. FIGURE 22. TEST CIRCUIT BLOCK DIAGRAM .......................................................................................................13 COSMIC-RAY NEUTRON FLUX AT GROUND LEVEL......................................................................17 NEUTRON FLUX VS ALTITUDE...........................................................................................................19 SEFI FIT OF XC2V3000 VS VDD............................................................................................................22 SEU FIT OF XC2V3000 VS VDD ............................................................................................................23 SEFI VS TOTAL SEU XC2V3000............................................................................................................24 AX1000 VCCA AND VCCIB WAVEFORMS .........................................................................................25 AX1000 VCCDA WAVEFORM ...............................................................................................................25 APA1000 VDD WAVEFORM ..................................................................................................................26 APA1000 VDDP WAVEFORM ...........................................................................................................26 XC2V3000 VCCINT WAVEFORM.....................................................................................................27 XC2V3000 VCCO WAVEFORM.........................................................................................................27 BITMAP FOR RUN#2 OF XC2V3000.................................................................................................29 BITMAP FOR RUN#3 OF XC2V3000.................................................................................................30 BITMAP FOR RUN#4 OF XC2V3000.................................................................................................31 BITMAP FOR RUN#5 OF XC2V3000.................................................................................................32 CHIP TO CHIP FIT VARIATION........................................................................................................33 SEFI CONSISTENCY CHECK FOR XC2V3000 ................................................................................34 COSMIC-RAY NEUTRON FLUX AT GROUND LEVEL .................................................................39 SEFI FIT OF XC2V3000 VS VDD.......................................................................................................45 SEU FIT OF XC2V3000 VS VDD........................................................................................................46 SEFI FIT OF XC3S1000 VS VDD........................................................................................................47 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 7 THE CHIP PROTECTOR FIGURE 23. FIGURE 24. FIGURE 25. FIGURE 26. FIGURE 27. FIGURE 28. FIGURE 29. FIGURE 30. FIGURE 31. FIGURE 32. FIGURE 33. FIGURE 34. FIGURE 35. FIGURE 36. FIGURE 37. FIGURE 38. FIGURE 39. FIGURE 40. FIGURE 41. FIGURE 42. FIGURE 43. FIGURE 44. FIGURE 45. FIGURE 46. FIGURE 47. FIGURE 48. FIGURE 49. FIGURE 50. FIGURE 51. FIGURE 52. FIGURE 53. FIGURE 54. FIGURE 55. FIGURE 56. FIGURE 57. FIGURE 58. FIGURE 59. FIGURE 60. FIGURE 61. FIGURE 62. FIGURE 63. FIGURE 64. FIGURE 65. FIGURE 66. FIGURE 67. FIGURE 68. FIGURE 69. FIGURE 70. GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances SEU FIT OF XC3S1000 VS VDD ........................................................................................................47 SEFI FIT OF EP1C20 VS VDD............................................................................................................48 SEFI VS TOTAL SEU XC2V3000 .......................................................................................................49 SEFI VS TOTAL SEU XC3S1000........................................................................................................50 AX1000 VCCA AND VCCIB WAVEFORMS ....................................................................................51 AX1000 VCCDA WAVEFORM ..........................................................................................................51 APA1000 VDD WAVEFORM .............................................................................................................52 APA1000 VDDP WAVEFORM ...........................................................................................................52 XC2V3000 VCCINT WAVEFORM.....................................................................................................53 XC2V3000 VCCO WAVEFORM.........................................................................................................53 BITMAP FOR RUN#2 OF XC2V3000.................................................................................................55 BITMAP FOR RUN#3 OF XC2V3000.................................................................................................56 BITMAP FOR RUN#4 OF XC2V3000.................................................................................................56 BITMAP FOR RUN#5 OF XC2V3000.................................................................................................57 BITMAP FOR RUN#2 OF XC3S1000 .................................................................................................58 BITMAP FOR RUN#3 OF XC3S1000 .................................................................................................58 BITMAP FOR RUN#4 OF XC3S1000 .................................................................................................59 BITMAP FOR RUN#5 OF XC3S1000 .................................................................................................59 CHIP TO CHIP FIT VARIATION FOR XC2V3000............................................................................60 CHIP TO CHIP FIT VARIATION FOR XC3S1000 ............................................................................61 CHIP TO CHIP FIT VARIATION FOR EP1C20.................................................................................62 SEFI CONSISTENCY CHECK FOR XC2V3000 ................................................................................63 SEFI CONSISTENCY CHECK FOR XC3S1000.................................................................................64 SEFI CONSISTENCY CHECK FOR EP1C20 .....................................................................................65 FLUX UNIFORMITY AT LANSCE (X-AXIS)...................................................................................66 FLUX UNIFORMITY AT LANSCE (Y-AXIS)...................................................................................66 FLUX UNIFORMITY MEASUREMENT AT LANSCE.....................................................................67 SEU FIT OF XC2V3000 VS VDD........................................................................................................77 SEFI FIT OF XC3S1000 VS VDD........................................................................................................78 SEU FIT OF XC3S1000 VS VDD ........................................................................................................78 SEFI FIT OF EP1C20 VS VDD............................................................................................................79 SEFI VS TOTAL SEU XC3S1000........................................................................................................80 AX1000 VCCA AND VCCIB WAVEFORMS ....................................................................................81 AX1000 VCCDA WAVEFORM ..........................................................................................................82 BITMAP FOR RUN#2 OF XC2V3000.................................................................................................84 BITMAP FOR RUN#3 OF XC2V3000.................................................................................................85 BITMAP FOR RUN#4 OF XC2V3000.................................................................................................85 BITMAP FOR RUN#5 OF XC2V3000.................................................................................................86 BITMAP FOR RUN#2 OF XC3S1000 .................................................................................................87 BITMAP FOR RUN#3 OF XC3S1000 .................................................................................................87 BITMAP FOR RUN#4 OF XC3S1000 .................................................................................................88 BITMAP FOR RUN#5 OF XC3S1000 .................................................................................................88 CHIP TO CHIP FIT VARIATION FOR XC2V3000............................................................................89 CHIP TO CHIP FIT VARIATION FOR XC3S1000 ............................................................................90 CHIP TO CHIP FIT VARIATION FOR EP1C20.................................................................................90 SEU CONSISTENCY CHECK FOR XC2V3000.................................................................................91 SEFI CONSISTENCY CHECK FOR XC3S1000.................................................................................92 SEFI CONSISTENCY CHECK FOR EP1C20 .....................................................................................92 List of Tables This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 8 THE CHIP PROTECTOR TABLE 1. TABLE 2. TABLE 3. TABLE 4. TABLE 5. TABLE 6. TABLE 7. TABLE 8. TABLE 9. TABLE 10. TABLE 11. TABLE 12. TABLE 13. TABLE 14. TABLE 15. TABLE 16. TABLE 17. TABLE 18. TABLE 19. TABLE 20. TABLE 21. TABLE 22. TABLE 23. TABLE 24. TABLE 25. TABLE 26. TABLE 27. TABLE 28. TABLE 29. TABLE 30. TABLE 31. TABLE 32. TABLE 33. TABLE 34. TABLE 35. TABLE 36. TABLE 37. TABLE 38. TABLE 39. TABLE 40. TABLE 41. TABLE 42. TABLE 43. TABLE 44. TABLE 45. TABLE 46. TABLE 47. TABLE 48. TABLE 49. TABLE 50. GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances SUMMARY OF TEST CAMPAIGNS ......................................................................................................12 ERROR DEFINITIONS.............................................................................................................................14 CONDITIONS TESTED FOR AX1000 ....................................................................................................15 CONDITIONS TESTED FOR APA1000 ..................................................................................................15 CONDITIONS TESTED FOR XC2V3000................................................................................................15 LOT CODES OF THE AX1000 CHIPS TESTED.....................................................................................16 LOT CODES OF THE APA1000 CHIPS TESTED ..................................................................................16 LOT CODES OF THE XC2V3000 CHIPS TESTED ................................................................................16 OVERALL COSMIC-RAY FIT AT SEA LEVEL IN NYC .....................................................................18 OVERALL COSMIC-RAY FIT AT DIFFERENT ALTITUDES.............................................................18 95% CONFIDENCE LIMITS FOR SMALL NUMBER OF EVENTS.....................................................20 95% CONFIDENCE INTERVALS FOR ALL DEVICES ........................................................................20 DETAILED ANALYSIS FOR 14 MEV TESTS .......................................................................................21 XC2V3000 NUMBER OF SEFI FOR EACH CHIP..................................................................................28 OVERALL COSMIC-RAY FIT AT SEA LEVEL IN NYC .....................................................................35 OVERALL COSMIC-RAY FIT AT DIFFERENT ALTITUDES.............................................................35 CONDITIONS TESTED FOR AX1000 ....................................................................................................36 CONDITIONS TESTED FOR APA1000 ..................................................................................................36 CONDITIONS TESTED FOR XC2V3000................................................................................................37 CONDITIONS TESTED FOR XC3S1000 ................................................................................................37 CONDITIONS TESTED FOR EP1C20.....................................................................................................37 LOT CODES OF THE AX1000 CHIPS TESTED.....................................................................................37 LOT CODES OF THE APA1000 CHIPS TESTED ..................................................................................38 LOT CODES OF THE XC2V3000 CHIPS TESTED ................................................................................38 LOT CODES OF THE XC3S1000 CHIPS TESTED.................................................................................38 LOT CODES OF THE EP1C20 CHIPS TESTED .....................................................................................38 OVERALL COSMIC-RAY FIT AT SEA LEVEL IN NYC .....................................................................41 OVERALL COSMIC-RAY FIT AT DIFFERENT ALTITUDES.............................................................41 95% CONFIDENCE INTERVALS FOR ALL DEVICES ........................................................................43 DETAILED ANALYSIS FOR LANSCE TESTS......................................................................................44 XC2V3000 NUMBER OF SEFI FOR EACH CHIP..................................................................................54 XC3S1000 NUMBER OF SEFI FOR EACH CHIP ..................................................................................54 EP1C20 NUMBER OF SEFI FOR EACH CHIP.......................................................................................54 OVERALL COSMIC-RAY FIT AT SEA LEVEL IN NYC .....................................................................68 OVERALL COSMIC-RAY FIT AT DIFFERENT ALTITUDES.............................................................68 CHARACTERISTICS OF THE ALPHA SOURCES................................................................................69 ALPHA SOURCE UTILIZATION AND GEOMETRY FACTORS FOR EACH DEVICE ....................69 CONDITIONS TESTED FOR AX1000 ....................................................................................................70 CONDITIONS TESTED FOR APA1000 ..................................................................................................70 CONDITIONS TESTED FOR XC2V3000................................................................................................71 CONDITIONS TESTED FOR XC3S1000 ................................................................................................71 CONDITIONS TESTED FOR EP1C20.....................................................................................................71 LOT CODES OF THE AX1000 CHIPS TESTED.....................................................................................72 LOT CODES OF THE APA1000 CHIPS TESTED ..................................................................................72 LOT CODES OF THE XC2V3000 CHIPS TESTED ................................................................................72 LOT CODES OF THE XC3S1000 CHIPS TESTED.................................................................................72 LOT CODES OF THE EP1C20 CHIPS TESTED .....................................................................................72 OVERALL ALPHA PARTICLE FIT FOR 0.001 A/CM²/HOUR.............................................................74 95% CONFIDENCE INTERVALS FOR ALL DEVICES ........................................................................75 ALPHA SOURCE UTILIZATION AND ACCURACY FOR EACH DEVICE .......................................76 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 9 THE CHIP PROTECTOR TABLE 51. TABLE 52. TABLE 53. TABLE 54. TABLE 55. GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances DETAILED ANALYSIS FOR ALPHA TESTS........................................................................................77 XC2V3000 NUMBER OF SEU FOR EACH CHIP ..................................................................................82 XC3S1000 NUMBER OF SEFI FOR EACH CHIP ..................................................................................83 EP1C20 NUMBER OF SEFI FOR EACH CHIP.......................................................................................83 OVERALL ALPHA PARTICLE FIT FOR 0.001 A/CM²/HOUR.............................................................94 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 10 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 1 Executive summary • Cosmic-ray and alpha-particle soft error rates were measured for five different architectures of FPGAs, from three different vendors, using three different programming technologies. • Test methodology was compliant with JESD-89. • SRAM-based FPGAs are liable to configuration SEU and SEFI when exposed to high-energy neutrons and alpha particles. • Antifuse-based and Flash-based FPGAs did not exhibit any configuration SEU or SEFI when exposed to high-energy neutrons and alpha particles. • Test results allowed the calculation of the ratio of SEFIs to SEUs. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 11 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 2 Object This test report provides the cosmic-ray SER of AX1000, APA1000, XC2V3000, XC3S1000 and EP1C20 devices. The cosmic-ray SER was measured at the LANSCE WNR facility at Los Alamos in February 2004. The LANSCE results are compared with the preliminary SER of AX1000, APA1000 and XC2V3000 devices. The preliminary SER was measured using 14 MeV neutrons at the Interfaculty Reactor Institute (IRI) at Delft in The Netherlands in December 2003. This test report also provides the alpha particle SER of AX1000, APA1000, XC2V3000, XC3S1000 and EP1C20 devices. The alpha particle SER was measured at iRoC premises using calibrated Am241 foil sources in April and October 2004. The tests were conducted following the Test Plan [3]. Table 1 summarizes the tests performed for each device. Mfg Family Device Actel Actel Xilinx Xilinx Altera Axcelerator ProASICPLUS Flash Virtex-II Spartan-3 Cyclone AX1000 APA1000 XC2V3000 XC3S1000 EP1C20 14 MeV neutrons √ √ √ Full spectrum neutrons √ √ √ √ √ Alpha particles √ √ √ √ √ Table 1. Summary of test campaigns This test report includes the description of the different tests performed during the experiments, and provides the detailed analysis and explanation of the FIT results. 2.1 Test strategy This section recalls the test strategy. The test strategy is described in the Test Plan [3]. The test approach has special emphasis for the faults affecting the configuration memory. The test strategy is based in the continuous monitoring of the outputs of a combinatorial circuit implemented in the FPGA under test. As soon as a permanent mismatch of the output values is observed, the test is stopped and the configuration memory read back and stored in a file. Additionally, the FPGA configuration memory is periodically read back, even if the output values are correct. The test strategy enables to identify the non critical and the critical SEU in the configuration memory, that is, those SEU in the configuration memory that do not create an error in the output, and those that create an error in the output. The target circuit implemented in the DUT is composed of an array of 16x16-bit binary multipliers. Inputs of the multipliers are connected in parallel, and the outputs are connected to a multiplexer. The tester checks the output of each multiplier sequentially by means of the multiplexer. The main feature of this circuit is that This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 12 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances it is purely combinatorial and uses a large part of the Look-Up Table (LUT) resources. The absence of FlipFlops ensures that fails occur only when the configuration memory is modified. The test of the IO blocks (IOB) is accomplished by connecting a chain of IOB between the outputs of the multiplexer and the tester. In this way all the available IOB of the FPGA can be tested. Figure 1 presents the block diagram of the target circuit. DUT FPGA design INA(0:15) Test vector generator INB(0:15) INA INB 16x16 bit Multiplier 1 OUT IN_1 32-bit N-input Multiplexer OUT INA INB 16x16 bit Multiplier N OUT IN_N OE ADDR(0:6) Figure 1. Test circuit block diagram This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 13 OUT(0:31) OE ADDR(0:6) THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 2.2 Error definition This section recalls the error definitions. Error definitions are included in the Test Plan [3]. Type of error Description SEU in the configuration memory A bit flip in the configuration memory caused by a single particle strike, neutron or alpha. SEFI in the target circuit A permanent mismatch of the output of the target circuit. It is created by a SEU in the configuration memory that alters the Look-Up Tables (LUT) or the routing of signals in the target circuit. Configuration A failure in the controlling circuitry of the FPGA. Configuration and read back circuitry operations fail. failure Latchup The activation of a parasitic structure in the silicon by a single neutron strike. The latchup effects are an increase of the current consumption and failures in the target circuit, the configuration memory or the controlling circuitry of the FPGA. Hard error A permanent failure in the FPGA that cannot be recovered after switching the beam off, switching the power off/on, and reconfiguration. Table 2. Error definitions This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 14 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 3 14 MeV tests 3.1 Tested conditions and schedule The following tables provide the sequence of conditions that were tested. Additionally to the test conditions, stability and consistency checks have been performed at the beginning and the end of each test sequence. A stability test (beam off) has been carried out before irradiation (cf. section 3.3). A consistency test (repetition of the first condition) has been carried out at the end of the test sequence The order of the test conditions follows the Test Plan [3]. The tables are extracted from the campaign logbook files in appendix A.1. Run # Device 1 2 3 4 5 AX1000 AX1000 AX1000 AX1000 AX1000 Energy (MeV) 14 14 14 14 14 Start Date Time Dec-16 14:29:13 Dec-16 14:47:15 Dec-17 8:00:00 Dec-17 9:10:42 Note 1 Note 1 Stop Time 14:44:16 16:59:27 9:08:22 10:21:37 Note 1 Condition Cycle VDD Temp 200ns 1.4 25°C 200ns 1.4 25°C 200ns 1.5 25°C 200ns 1.6 25°C 200ns 1.4 25°C Table 3. Conditions tested for AX1000 Run # Device 1 2 3 4 5 APA1000 APA1000 APA1000 APA1000 APA1000 Energy (MeV) 14 14 14 14 14 Start Date Time Dec-16 14:30:26 Dec-16 14:47:31 Dec-17 8:00:00 Dec-17 9:10:45 Note 1 Note 1 Stop Time 14:44:14 16:59:35 9:08:20 10:21:34 Note 1 Condition Cycle VDD Temp 200ns 2.3 25°C 200ns 2.3 25°C 200ns 2.5 25°C 200ns 2.7 25°C 200ns 2.3 25°C Table 4. Conditions tested for APA1000 Run # Device 1 2 3 4 5 XC2V3000 XC2V3000 XC2V3000 XC2V3000 XC2V3000 Energy (MeV) 14 14 14 14 14 Start Date Time Dec-17 13:31:49 Dec-17 13:36:31 Dec-17 14:31:12 Dec-17 15:08:40 Dec-17 15:52:07 Stop Time 13:36:11 14:29:04 15:08:02 15:46:06 16:34:41 Condition Cycle VDD Temp 200ns 1.425 25°C 200ns 1.425 25°C 200ns 1.500 25°C 200ns 1.575 25°C 200ns 1.425 25°C Table 5. Conditions tested for XC2V3000 Note 1: The consistency check, run #5, was not done for the AX1000 and APA1000 because no errors were observed for any of the conditions tested. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 15 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 3.2 Devices tested The following tables show the lot codes of the chips that were actually tested: Chip 1 DOAAJ1 0320 Chip 4 DOH5S21 0331 Chip 2 DOJC21 0345 Chip 5 DOJC21 0345 Chip 3 DOJC21 0345 Table 6. Lot codes of the AX1000 chips tested Chip 1 MF7G7 0247 Chip 4 MF7G7 0247 Chip 2 MF7G7 0247 Chip 5 MF7G7 0247 Chip 3 MF7G7 0247 Chip 6 MF7G7 0247 Table 7. Lot codes of the APA1000 chips tested Chip 1 AGT0337 F2149925A Chip 4 AGT0337 F2149925A Chip 2 AGT0337 F2149925A Chip 5 AGT0337 F2149925A Chip 3 AGT0337 F2149925A Chip 6 AGT0337 F2149925A Table 8. Lot codes of the XC2V3000 chips tested 3.3 Stability without neutron beam An error rate measurement is performed with the beam off and with the components placed in the target. The components are in the real environment with the real electromagnetic parasitic. This aims at verifying the robustness of both the tester and the DUT boards against the real noisy environment. This experiment was done during 10 minutes for each DUT board and no error occurred (cf run #1 in Table 3 to Table 5). This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 16 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR 4 14 MeV results 4.1 Cross-section and FIT calculation The cross-section defines the sensitivity of a device. The cross-section per chip, as a function of neutron energy E, is defined as σ(E)=N/(F*C) where N is the total number of errors, F is the fluence and C is the number of chips tested. In this document, the cross-section is given in cm²/chip. The cross-section measured with 14 MeV neutrons is directly used to estimate the terrestrial failure rate. We approximate the full energy spectrum cross-section by the cross-section at 14 MeV. The approximation results in a lower estimate of the full spectrum cross-section because of the regular increase of cross-section at high energy. The full spectrum cross-section could be up to 50% higher than the 14 MeV cross-section. Neutron flux 1,000,000 Measured neutron flux at LANSCE n/MeV/cm²/sec 100,000 10,000 1,000 Cosmic-ray neutron flux (multiplied by 1E6) 100 10 Integrated neutron flux above 1 MeV ~ 2.5E6 n/cm²/sec 1 1 10 100 1000 Neutron Energy (MeV) Figure 2. Cosmic-ray neutron flux at ground level According to the JESD89 specification [2], the FIT rate is calculated using the value of neutron flux for the New-York City, fNYC =14 n/cm2/hour for neutrons with energy above 10 MeV. Thus, the FIT is given by the following formula: FIT=σ*fNYC*109 (errors/109 hour) Where σ is the cross-section given in cm²/chip, and fNYC is the flux given in n/cm2/hour. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 17 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances The FIT is calculated using the neutron flux for the New-York City at sea level. The neutron flux depends on the altitude and location. Appendix E of the JESD89 specification [2] shows how to adjust the error rates calculated for the NYC for other locations. 4.2 Overall FIT results Table 9 presents the overall cosmic-ray FIT for each device at sea level in NYC. The overall FIT is calculated as the average of all chips and test conditions for the XC2V3000. Appendix A details the crosssection and FIT for each chip and test condition. Device AX1000 APA1000 XC2V3000 Overall FIT (SEFI) per Device <0.017 <0.026 680 Overall FIT (SEU) per Device <0.017 <0.026 4700 Table 9. Overall cosmic-ray FIT at sea level in NYC In Table 9, it is important to understand that no errors were observed for the AX1000 and APA1000, for anyof the test conditions. The given figure of FIT is an upper bound calculated considering one error for all chips and test conditions. The AX1000 and APA1000, based in Antifuse and Flash processes respectively, are considered insensitive to 14 MeV neutrons, therefore extending the test for longer periods would still produce no errors, and result in lower bounds of FIT. The neutron flux increases with altitude, and has a maximum at approximately 60,000 ft. The FIT at sea level, 5,000 ft, 30,000 ft and 60,000 ft is provided in Table 10: FIT (SEFI) at FIT (SEFI) at FIT (SEFI) at FIT (SEFI) at sea level 5,000 ft 30,000 ft 60,000 ft Device AX1000 APA1000 XC2V3000 <0.017 <0.026 680 <0.058 <0.089 2,300 <2.5 <3.8 99,000 <8.1 <12 320,000 Table 10. Overall cosmic-ray FIT at different altitudes The altitude effect at 5,000 ft and 30,000 ft is evaluated using the formula provided in appendix E of JESD89 [2]: Neutron flux (n/cm²/hour) = 15E3 * e -(A/148) Where the altitude, a, in feet above sea level, is expressed as the areal density of the air column, A, in units of g/cm². The altitude, a, can be converted to the areal density, A using the following equation: A = 1033×exp[-.03813×(a/1000) -.00014×(a/1000)² +6.4E-7×(a/1000)³] This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 18 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances The altitude effect at 60,000 ft is evaluated using Figure 3 from reference [4]. Figure 3. Neutron flux vs altitude 4.3 Accuracy of results The accuracy of the cross-section results is assessed in this section. The accuracy of the cross-section is the sum of the error count and fluence measurement accuracies. 4.3.1 Error count statistics The error count is generally described by a Poisson distribution, cf appendix C.1 in [2]. If N errors occur, the mean error count is approximated by N. The standard deviation is given by √N. The error count can be bounded using the upper and lower limits in Table 11, extracted from appendix C.2 of [2]. In using this table, the first column is the actual number of events observed in the experiment. The upper and lower limits define the 95% confidence interval for the true mean of the distribution. The upper and lower limits for any number of events can be calculated using the formulas given in appendix B. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 19 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR Events 0 1 2 3 4 5 6 7 8 9 10 20 50 100 95% confidence limit Lower limit Upper limit 0.0 3.7 0.0 5.6 0.2 7.2 0.6 8.8 1.1 10.2 1.6 11.7 2.2 13.1 2.8 14.4 3.5 15.8 4.1 17.1 4.8 18.4 12.2 30.9 37.1 65.9 81.4 121.6 Table 11. 95% confidence limits for small number of events The accuracy of the error count is defined in this report using 95% confidence intervals. The 95% confidence limits depend on the number of errors observed. The number of errors is detailed in appendix A for each chip and test condition. The following table summarizes the 95% confidence intervals for each device. For example, the overall number of SEFI per chip and test condition is 18 for the XC2V3000. By using the formulas given in appendix B, we find that the lower and upper limits are 10.7 and 28.4 respectively. The limits in Table 12 are calculated as (Lower limit/Mean error count – 1)*100 = -41%, and (Upper limit/Mean error count – 1)*100 = +58%. Device Error type AX1000 APA1000 SEFI SEFI SEFI XC2V3000 SEU Mean error count 0 0 18 105 420 122 730 Lower limit Upper limit Comment n/a n/a -41% -18% -9% -17% -7% n/a n/a +58% +21% +10% +19% +8% No errors observed No errors observed Errors per chip and test condition Errors for all chips per test condition Errors for all chips and test conditions Errors per chip and test condition Errors for all chips per test condition Table 12. 95% confidence intervals for all devices 4.3.2 Fluence measurement accuracy The accuracy of the fluence measurement is better than 10% for the IRI facility. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 20 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 4.4 Detailed analysis Detailed analysis of the results is presented hereafter. The following table summarizes the analyses presented for each device: Analysis Voltage influence on FIT Analysis of critical vs non critical SEU Analysis of single event latchup Bitmaps of errors Chip to chip variations Special observations AX1000 APA1000 √ √ √ √ XC2V3000 √ √ √ √ √ √ Table 13. Detailed analysis for 14 MeV tests Many of the detailed analysis cannot be performed for the AX1000 and APA1000 because no errors were observed for these devices. 4.4.1 Voltage influence on FIT The SEFI and SEU FIT dependence vs VDD is presented in this section. The FIT is plotted separately for each chip. The FIT average of all chips is also plotted, and the average FIT is used to fit an exponential curve. Figure 4 and Figure 5 show a regular decrease of FIT at the higher VDD, as expected. The FIT dispersion between chips is consistent with the accuracy assessments given in section 4.3. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 21 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances SEFI FIT for XC2V3000 1100 1000 Chip 1 FIT per Chip 900 Chip 2 Chip 3 800 y = 2.0E+03e -7.2E-01x Chip 4 700 Chip 5 Chip 6 600 Average 500 400 1.400 1.450 1.500 1.550 1.600 VDD Figure 4. SEFI FIT of XC2V3000 vs VDD This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 22 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances SEU FIT for XC2V3000 6000 5500 FIT per Chip Chip 1 5000 y = 9.9E+03e -4.9E-01x Chip 2 Chip 3 Chip 4 4500 Chip 5 4000 Chip 6 Average 3500 3000 1.400 1.450 1.500 1.550 1.600 VDD Figure 5. SEU FIT of XC2V3000 vs VDD 4.4.2 Analysis of critical vs non critical SEU The test strategy enables to identify the critical and the non critical SEU in the configuration memory, that is, those SEU in the configuration memory that create an SEFI, and those that do not create an SEFI. Figure 6 presents the ratio SEFI / Total SEU for each chip and test condition. The overall ratio is 15% independent of the test condition. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 23 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR Ratio SEFI / Total SEU for XC2V3000 30% SEFI / Total SEU (%) 25% Chip 1 20% Chip 2 Chip 3 15% Chip 4 Chip 5 Chip 6 10% Average 5% 0% 2 3 4 5 Test condition # Figure 6. SEFI vs Total SEU XC2V3000 4.4.3 Analysis of single event latchup Single event latchup (SEL) consists in the neutron induced activation of parasitic thyristor structures in the CMOS process. In case a process is sensitive to latchup, the latchup rate is higher at the higher voltage, temperature and particle energy. Latchups result in increased current consumption, partial or total configuration memory wipe out, or complete loss of operation. Because the current is limited for protection, latchups lead to voltage shutdown to the DUT. The way the tester detects latchups is by monitoring the DUT supply voltages. In case a latchup is detected, the tester logs the event and switches the power off/on for recovering. A particular case of latchup is the microlatchup. The microlatchup consists in the activation of a parasitic thyristor structure with weak on-resistance and a low increase of current consumption. In case of microlatchup, the voltage and current can find a stability point that cannot be detected by the tester. In this case, one or more chips are partially or totally wiped out, or experience complete loss of operation during the duration of a test condition. No latchups were detected for any of the devices and conditions tested. In the following subsections, the voltage and current waveforms, acquired during the experiments, will be presented for each device and test condition. The sensitivity to microlatchup will be analyzed by inspection of the voltage and current waveforms and correlation with the observed number of errors in each chip. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 24 THE CHIP PROTECTOR 4.4.3.1 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances AX1000 We observe regular voltage and current waveforms in Figure 7 and Figure 8. No errors were observed for any of the chips and conditions tested. Therefore, there is no indication of latchup. Power supply waveforms VCCA, VCCIB (V) VCCA, VCCIB 1.6 0.15 ICCA+ICCIB 1.5 0.10 1.4 0.05 1.3 0.00 ICCA+ICCIB (A) 0.20 1.7 Run# (1 sample per second) Figure 7. AX1000 VCCA and VCCIB waveforms VCCDA (V) 3.40 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.002 0.000 3.35 3.30 VCCDA 3.25 ICCDA 3.20 1 3 2 4 Run # (1 sample per second) Figure 8. AX1000 VCCDA waveform This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 25 ICCDA (A) Power supply waveforms THE CHIP PROTECTOR 4.4.3.2 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances APA1000 We observe regular voltage and current waveforms in Figure 9 and Figure 10. No errors were observed for any of the chips and conditions tested. Therefore, there is no indication of latchup. Power supply waveforms VDD (V) 2.7 VDD 0.25 2.6 IDD 0.20 2.5 0.15 2.4 0.10 2.3 0.05 2.2 0.00 IDD (A) 0.30 2.8 Run# (1 sample per second) Figure 9. APA1000 VDD waveform VDDP (V) 2.60 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 2.55 2.50 VDDP 2.45 IDDP 2.40 1 3 2 4 Run # (1 sample per second) Figure 10. APA1000 VDDP waveform This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 26 IDDP (A) Power supply waveforms THE CHIP PROTECTOR 4.4.3.3 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC2V3000 We observe regular voltage and current waveforms in Figure 11 and Figure 12. The number of errors, presented in the following table is regular across the six chips tested. Therefore, there is no indication of latchup. Power supply waveforms 0.5 0.4 1.55 0.3 1.50 0.2 VCCINT 1.45 ICCINT (A) VCCINT (V) 1.60 0.1 ICCINT 0.0 1.40 Run# (1 sample per second) Figure 11. XC2V3000 VCCINT waveform 3.10 3.5 3.0 3.05 2.5 2.0 1.5 1.0 3.00 VCCO 2.95 ICCO 0.5 0.0 2.90 1 2 3 4 5 Run # (1 sample per second) Figure 12. XC2V3000 VCCO waveform This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 27 ICCO (A) VCCO (V) Power supply waveforms THE CHIP PROTECTOR Run # 1 2 3 4 5 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances Condition Number of SEFI VDD Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Chip 6 1.425 0 0 0 0 0 0 1.425 22 17 25 19 11 11 1.500 21 12 18 21 17 18 1.575 14 16 15 25 13 18 1.425 14 18 23 20 16 16 Table 14. XC2V3000 number of SEFI for each chip Note: run #1 was a test run with the beam switched off, to test that the tester electronics was working correctly (cf section 3.3). 4.4.4 Bitmaps of errors Bitmaps allow to check the expected random distribution of errors in the configuration memory arrays. Each point in the bitmap represents a failing address. The bitmaps are logical bitmaps, not physical bitmaps, because the layout of the configuration memory is not available. In the logical bitmaps, the address LSB are mapped in the x-axis and the address MSB are mapped in the y-axis. The address refers to the location where the verification bitstream is stored in the tester memory. Valid addresses for the XC2V3000 are in the range 0x400069 to 0x5D4329. Each address holds 5 bits. Therefore, the verification bitstream length is 9,588,165 bits. The bitmaps show the expected random distribution of errors. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 28 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC2V3000 bitmap 5120 4096 Chip 1 3072 Chip 2 Y Chip 3 Chip 4 2048 Chip 5 Chip 6 1024 0 0 1024 2048 3072 4096 5120 X Figure 13. Bitmap for run#2 of XC2V3000 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 29 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC2V3000 bitmap 5120 4096 Chip 1 3072 Chip 2 Y Chip 3 Chip 4 2048 Chip 5 Chip 6 1024 0 0 1024 2048 3072 4096 5120 X Figure 14. Bitmap for run#3 of XC2V3000 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 30 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC2V3000 bitmap 5120 4096 Chip 1 3072 Chip 2 Y Chip 3 Chip 4 2048 Chip 5 Chip 6 1024 0 0 1024 2048 3072 4096 5120 X Figure 15. Bitmap for run#4 of XC2V3000 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 31 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC2V3000 bitmap 5120 4096 Chip 1 3072 Chip 2 Y Chip 3 Chip 4 2048 Chip 5 Chip 6 1024 0 0 1024 2048 3072 4096 5120 X Figure 16. Bitmap for run#5 of XC2V3000 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 32 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR 4.4.5 Chip to chip variation This section presents the chip to chip FIT variations observed. The objective of this section is to check the neutron flux uniformity. The FIT variations shown in Figure 17 are defined as the variation relative to the average of the 6 chips tested. ⎛ ⎞ FIT Chip(i) FIT variation for chip(i) (%) = ⎜⎜ − 1⎟⎟ × 100 ⎝ Average FIT Chips(1 to 6) ⎠ The FIT variations observed are within the expected statistical uncertainty: –17% to +19%, see Table 12. Therefore, we verify that the neutron flux is uniform. SEU FIT variation for each chip XC2V3000 20% FIT variation (%) . 15% 10% 5% Chip 1 0% Chip 2 Chip 3 -5% Chip 4 Chip 5 -10% Chip 6 -15% -20% 2 3 4 5 Test condition # Figure 17. Chip to chip FIT variation This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 33 THE CHIP PROTECTOR 4.4.6 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances Consistency check A consistency test (repetition of the first condition) has been carried out at the end of the test sequence. The consistency test verifies the stability of the beam, DUT and tester. Figure 18 verifies that the results of runs #2 and #5 are consistent, taking into account the statistical uncertainty shown by the error bars. SEFI Consistency Check for XC2V3000 1100 1000 Chip 1 FIT per Chip 900 Chip 2 Chip 3 800 Chip 4 700 Chip 5 Chip 6 600 Average 500 400 2 5 Test condition # Figure 18. 4.4.7 SEFI consistency check for XC2V3000 Special observations A verify operation using the Flash Pro programmer was performed for the APA1000 chips, at the end of the radiation tests performed. The verify operation was successful for all the APA1000 chips. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 34 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 5 14 MeV conclusions The preliminary cosmic-ray SER of AX1000, APA1000 and XC2V3000 devices was measured using 14 MeV neutrons at the Interfaculty Reactor Institute (IRI) at Delft in The Netherlands in December 2003. Table 15 presents the overall cosmic-ray FIT for each device at sea level in NYC. The overall FIT is calculated as the average of all chips and test conditions for the XC2V3000. Device AX1000 APA1000 XC2V3000 Overall FIT (SEFI) per Device <0.017 <0.026 680 Overall FIT (SEU) per Device <0.017 <0.026 4700 Table 15. Overall cosmic-ray FIT at sea level in NYC In Table 15, it is important to understand that no errors were observed for the AX1000 and APA1000, for any of the test conditions. The given figure of FIT is an upper bound calculated considering one error for all chips and test conditions. The AX1000 and APA1000, based in Antifuse and Flash processes respectively, are considered insensitive to 14 MeV neutrons, therefore extending the test for longer periods would still produce no errors, and result in lower bounds of FIT. The neutron flux increases with altitude, and has a maximum at approximately 60,000 ft. The FIT at sea level, 5,000 ft, 30,000 ft and 60,000 ft is provided in Table 16. FIT (SEFI) at FIT (SEFI) at FIT (SEFI) at FIT (SEFI) at sea level 5,000 ft 30,000 ft 60,000 ft Device AX1000 APA1000 XC2V3000 <0.017 <0.026 680 <0.058 <0.089 2,300 <2.5 <3.8 99,000 <8.1 <12 320,000 Table 16. Overall cosmic-ray FIT at different altitudes No occurrences of latchup have been observed for any of the devices. No errors in the configuration circuitry of the XC2V3000 were observed. No hard errors were observed for any of the devices. It is important to understand that we approximate the full energy spectrum cross-section by the crosssection at 14 MeV. The approximation results in a lower estimate of the full spectrum cross-section, that could be up to 50% higher than the 14 MeV cross-section. Additionally, devices that are not sensitive to latchup for 14 MeV neutrons, can be sensitive for neutrons of higher energy. Therefore, full spectrum tests at LANSCE will be performed to consolidate these preliminary results. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 35 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR 6 LANSCE tests 6.1 Tested conditions and schedule The following tables provide the sequence of conditions that were tested. Additionally to the test conditions, stability and consistency checks have been performed at the beginning and the end of each test sequence. A stability test (beam off) has been carried out before irradiation (cf. section 6.3). A consistency test (repetition of the first condition) has been carried out at the end of the test sequence The order of the test conditions follows the Test Plan [3]. The tables are extracted from the campaign logbook files in appendix A.2. Run # Device 1 2 3 4 5 AX1000 AX1000 AX1000 AX1000 AX1000 Energy (MeV) LANSCE LANSCE LANSCE LANSCE LANSCE Start Date 17-Feb 17-Feb 17-Feb 18-Feb Note 1 Stop Time 14:27:15 15:46:19 22:41:50 4:28:29 Note 1 Date 17-Feb 17-Feb 18-Feb 18-Feb Note 1 Time 14:38:02 22:40:35 4:27:11 9:46:52 Note 1 Condition Cycle VDD Temp 200ns 1.4 25°C 200ns 1.4 25°C 200ns 1.5 25°C 200ns 1.6 25°C 200ns 1.4 25°C Table 17. Conditions tested for AX1000 Note 1: The consistency check, run #5, was not done for the AX1000 because no errors were observed for any of the conditions tested. Run # Device 1 2 3 4 5 APA1000 APA1000 APA1000 APA1000 APA1000 Energy (MeV) LANSCE LANSCE LANSCE LANSCE LANSCE Start Date 18-Feb 18-Feb 18-Feb 18-Feb 19-Feb Stop Time 10:36:44 10:47:46 15:22:12 21:09:08 5:56:33 Date 18-Feb 18-Feb 18-Feb 19-Feb 19-Feb Time 10:46:44 15:21:14 21:07:56 5:55:00 21:26:26 Condition Cycle VDD Temp 200ns 2.3 25°C 200ns 2.3 25°C 200ns 2.5 25°C 200ns 2.7 25°C 200ns 2.3 25°C Table 18. Conditions tested for APA1000 No errors were observed for any of the conditions tested for the APA1000. The consistency check, run #5, was done because beam time was available, to increase the fluence and thus the accuracy of the FIT bound. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 36 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR Run # Device 1 2 3 4 5 XC2V3000 XC2V3000 XC2V3000 XC2V3000 XC2V3000 Energy (MeV) LANSCE LANSCE LANSCE LANSCE LANSCE Start Date 17-Feb 17-Feb 17-Feb 17-Feb 17-Feb Stop Time 14:28:11 15:46:53 15:59:04 16:10:38 16:23:38 Date 17-Feb 17-Feb 17-Feb 17-Feb 17-Feb Time 14:38:56 15:57:28 16:09:44 16:22:29 16:35:45 Condition Cycle VDD Temp 200ns 1.425 25°C 200ns 1.425 25°C 200ns 1.500 25°C 200ns 1.575 25°C 200ns 1.425 25°C Table 19. Conditions tested for XC2V3000 Run # Device 1 2 3 4 5 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 Energy (MeV) LANSCE LANSCE LANSCE LANSCE LANSCE Start Date 17-Feb 17-Feb 17-Feb 17-Feb 17-Feb Stop Time 17:16:20 17:25:56 17:52:36 19:41:23 20:08:11 Date 17-Feb 17-Feb 17-Feb 17-Feb 17-Feb Time 17:25:22 17:51:15 19:40:45 20:07:31 20:23:55 Condition Cycle VDD Temp 200ns 1.140 25°C 200ns 1.140 25°C 200ns 1.200 25°C 200ns 1.260 25°C 200ns 1.140 25°C Table 20. Conditions tested for XC3S1000 Run # Device 1 2 3 4 5 EP1C20 EP1C20 EP1C20 EP1C20 EP1C20 Energy (MeV) LANSCE LANSCE LANSCE LANSCE LANSCE Start Date 17-Feb 17-Feb 17-Feb 17-Feb 17-Feb Stop Time 20:58:26 21:09:30 21:49:43 22:04:36 22:22:38 Date 17-Feb 17-Feb 17-Feb 17-Feb 17-Feb Time 21:08:40 21:27:50 22:03:20 22:21:21 22:39:26 Condition Cycle VDD Temp 200ns 1.425 25°C 200ns 1.425 25°C 200ns 1.500 25°C 200ns 1.575 25°C 200ns 1.425 25°C Table 21. Conditions tested for EP1C20 6.2 Devices tested The following tables show the lot codes of the chips that were actually tested: Chip 1 DOAAJ1 0320 Chip 4 DOH5S21 0331 Chip 2 DOJC21 0345 Chip 5 DOJC21 0345 Chip 3 DOJC21 0345 Table 22. Lot codes of the AX1000 chips tested This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 37 THE CHIP PROTECTOR Chip 1 MF7G7 0247 Chip 4 MF7G7 0247 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances Chip 2 MF7G7 0247 Chip 5 MF7G7 0247 Chip 3 MF7G7 0247 Table 23. Lot codes of the APA1000 chips tested Chip 1 AGT0337 F2149925A Chip 4 AGT0337 F2149925A Chip 2 AGT0337 F2149925A Chip 5 AGT0337 F2149925A Chip 3 AGT0337 F2149925A Chip 6 AGT0337 F2149925A Table 24. Lot codes of the XC2V3000 chips tested Chip 1 FT256AFQ0341 D13989A Chip 4 FT256AFQ0341 D13989A Chip 2 FT256AFQ0341 D13989A Chip 5 FT256AFQ0341 D13989A Chip 3 FT256AFQ0341 D13990A Chip 6 FT256AFQ0341 D13989A Table 25. Lot codes of the XC3S1000 chips tested Chip 1 EP1C20F324C8 AAD900313A Chip 4 EP1C20F324C8 AAD900313A Chip 2 EP1C20F324C8 AAD900313A Chip 5 EP1C20F324C8 AAD900313A Chip 3 EP1C20F324C8 AAD900313A Chip 6 EP1C20F324C8 AAD900313A Table 26. Lot codes of the EP1C20 chips tested 6.3 Stability without neutron beam An error rate measurement is performed with the beam off and with the components placed in the target. The components are in the real environment with the real electromagnetic parasitic. This aims at verifying the robustness of both the tester and the DUT boards against the real noisy environment. This experiment was done during 10 minutes for each DUT board and no error occurred (cf run #1 in Table 17 to Table 21). This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 38 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR 7 LANSCE results 7.1 Cross-section and FIT calculation The cross-section defines the sensitivity of a device. The cross-section per chip, as a function of neutron energy E, is defined as σ(E)=N/(F*C) where N is the total number of errors, F is the fluence and C is the number of chips tested. In this document, the cross-section is given in cm²/chip. Since the WNR neutron beam has a neutron energy spectrum very similar to the terrestrial neutron energy spectrum, the cross-section per bit obtained at WNR can be used directly to estimate the terrestrial failure rate. Neutron flux 1,000,000 Measured neutron flux at LANSCE n/MeV/cm²/sec 100,000 10,000 1,000 Cosmic-ray neutron flux (multiplied by 1E6) 100 10 Integrated neutron flux above 1 MeV ~ 2.5E6 n/cm²/sec 1 1 10 100 Neutron Energy (MeV) Figure 19. Cosmic-ray neutron flux at ground level This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 39 1000 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances According to the JESD89 specification [2], the FIT rate is calculated using the value of neutron flux for New-York City, fNYC =14 n/cm²/hour for neutrons with energy above 10 MeV. The FIT is calculated in this report for one device. Thus, the FIT is given by the following formula: FIT=σ*fNYC*109 (errors/109 hour) Where σ is the cross-section given in cm²/chip, and fNYC is the flux given in n/cm2/hour. The FIT is calculated using the neutron flux for the New-York City at sea level. The neutron flux depends on the altitude and location. Appendix E of the JESD89 specification [2] shows how to adjust the error rates calculated for the NYC for other locations. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 40 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 7.2 Overall FIT results Table 27 presents the overall cosmic-ray FIT for each device at sea level in NYC. The overall FIT is calculated as the average of all chips and test conditions for the XC2V3000, XC3S1000 and EP1C20 devices. Appendix A details the cross-section and FIT for each chip and test condition. Device AX1000 APA1000 XC2V3000 XC3S1000 EP1C20 Overall FIT (SEFI) per Device <0.082 <0.038 1,150 320 460 Overall FIT (SEU) per Device <0.082 <0.038 8,680 1,240 n/a Table 27. Overall cosmic-ray FIT at sea level in NYC In Table 27, it is important to understand that no errors were observed for the AX1000 and APA1000, for any of the test conditions. The given figure of FIT is an upper bound calculated considering one error for all chips and test conditions. The AX1000 and APA1000, based in Antifuse and Flash processes respectively, are considered insensitive to terrestrial spectrum of neutrons, therefore extending the test for longer periods would still produce no errors, and result in lower bounds of FIT. The readback of the configuration memory is not available for the EP1C20. Therefore, the SEU FIT could not be measured for the EP1C20. The neutron flux increases with altitude, and has a maximum at approximately 60,000 ft. The FIT at sea level, 5,000 ft, 30,000 ft and 60,000 ft is provided in Table 28. FIT (SEFI) at FIT (SEFI) at FIT (SEFI) at FIT (SEFI) at sea level 5,000 ft 30,000 ft 60,000 ft Device AX1000 APA1000 XC2V3000 XC3S1000 EP1C20 <0.082 <0.038 1,150 320 460 <0.28 <0.13 3,900 1,100 1,600 <12 <5.6 170,000 47,000 67,000 <39 <18 540,000 150,000 220,000 Table 28. Overall cosmic-ray FIT at different altitudes The altitude effect at 5,000 ft and 30,000 ft is evaluated using the formula provided in appendix E of JESD89 [2]: Neutron flux (n/cm²/hour) = 15E3 * e -(A/148) This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 41 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances Where the altitude, a, in feet above sea level, is expressed as the areal density of the air column, A, in units of g/cm². The altitude, a, can be converted to the areal density, A using the following equation: A = 1033×exp[-.03813×(a/1000) -.00014×(a/1000)² +6.4E-7×(a/1000)³] The altitude effect at 60,000 ft is evaluated using Figure 3 from reference [4]. 7.3 Accuracy of results The accuracy of the cross-section results is assessed in this section. The accuracy of the cross-section is the sum of the error count and fluence measurement accuracies. 7.3.1 Error count statistics The error count is generally described by a Poisson distribution, cf appendix C.1 in [2]. If N errors occur, the mean error count is approximated by N. The standard deviation is given by √N. The error count can be bounded using the upper and lower limits in Table 11, extracted from appendix C.2 of [2]. In using this table, the first column is the actual number of events observed in the experiment. The upper and lower limits define the 95% confidence interval for the true mean of the distribution. The upper and lower limits for any number of events can be calculated using the formulas given in appendix B. The accuracy of the error count is defined in this report using 95% confidence intervals. The 95% confidence limits depend on the number of errors observed. The number of errors is detailed in appendix A for each chip and test condition. The following table summarizes the 95% confidence intervals for each device. For example, the overall number of SEFI per chip and test condition is 15 for the XC2V3000. By using the formulas given in appendix B, we find that the lower and upper limits are 8.4 and 24.7 respectively. The limits in Table 29 are calculated as (Lower limit/Mean error count – 1)*100 = -44%, and (Upper limit/Mean error count – 1)*100 = +65%. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 42 THE CHIP PROTECTOR Device AX1000 APA1000 Error type SEFI SEFI SEFI XC2V3000 SEU SEFI XC3S1000 SEU EP1C20 SEFI Errors 0 0 15 87 349 144 865 17 101 405 81 484 19 113 453 Lower limit n/a n/a -44% -20% -10% -16% -7% -42% -19% -10% -21% -9% -40% -18% -9% GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances Upper limit n/a n/a 65% 23% 11% 18% 7% 60% 22% 10% 24% 9% 56% 20% 10% Comment No errors observed No errors observed Errors per chip and test condition Errors for all chips per test condition Errors for all chips and test conditions Errors per chip and test condition Errors for all chips per test condition Errors per chip and test condition Errors for all chips per test condition Errors for all chips and test conditions Errors per chip and test condition Errors for all chips per test condition Errors per chip and test condition Errors for all chips per test condition Errors for all chips and test conditions Table 29. 95% confidence intervals for all devices 7.3.2 Fluence measurement accuracy The accuracy of the fluence measurement is better than 5% for the LANSCE facility. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 43 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 7.4 Detailed analysis Detailed analysis of the results is presented hereafter. The following table summarizes the analyses presented for each device: Analysis Voltage influence on FIT Analysis of critical vs non critical SEU Analysis of single event latchup Bitmaps of errors Chip to chip variations Special observations AX1000 APA1000 √ √ √ √ XC2V3000 √ √ √ √ √ √ XC3S1000 √ √ √ √ √ √ EP1C20 √ √ √ √ Table 30. Detailed analysis for LANSCE tests Many of the detailed analysis cannot be performed for the AX1000 and APA1000 because no errors were observed for these devices. 7.4.1 Voltage influence on FIT The SEFI and SEU FIT dependence vs VDD is presented in this section. The FIT is plotted separately for each chip. The FIT average of all chips is also plotted, and the average FIT is used to fit an exponential curve. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 44 THE CHIP PROTECTOR 7.4.1.1 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC2V3000 Figure 20 does not show a regular decrease of SEFI FIT at the higher VDD, as measured with 14 MeV neutrons. This is partially explained because of the statistical uncertainty of SEFI events, ±20% as shown in Table 29. Figure 21 shows a regular decrease of SEU FIT at the higher VDD, as expected. The FIT dispersion between chips is consistent with the accuracy assessments given in section 7.3. SEFI FIT for XC2V3000 2000 1800 1600 y = 4.5E+02e FIT per Chip 1400 Chip 1 6.2E-01x Chip 2 1200 Chip 3 1000 Chip 4 800 Chip 5 600 Chip 6 Average 400 200 0 1.40 1.45 1.50 1.55 1.60 VDD Figure 20. SEFI FIT of XC2V3000 vs VDD This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 45 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances SEU FIT for XC2V3000 12000 10000 FIT per Chip Chip 1 Chip 2 8000 Chip 3 6000 y = 1.8E+04e -4.8E-01x Chip 4 Chip 5 4000 Chip 6 Average 2000 0 1.40 1.45 1.50 1.55 1.60 VDD Figure 21. 7.4.1.2 SEU FIT of XC2V3000 vs VDD XC3S1000 Figure 22 does not show a regular decrease of SEFI FIT at the higher VDD, as expected. This is partially explained because of the statistical uncertainty of SEFI events, ±20% as shown in Table 29. Figure 23 shows a regular decrease of SEU FIT at the higher VDD, as expected. The FIT dispersion between chips is consistent with the accuracy assessments given in section 7.3. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 46 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances SEFI FIT for XC3S1000 600 500 FIT per Chip Chip 1 y = 3.1E+02e 400 2.3E-02x Chip 2 Chip 3 Chip 4 300 Chip 5 200 Chip 6 Average 100 0 1.10 1.15 1.20 1.25 1.30 VDD Figure 22. SEFI FIT of XC3S1000 vs VDD SEU FIT for XC3S1000 1800 FIT per Chip 1600 1400 Chip 1 1200 Chip 2 Chip 3 1000 800 y = 8.2E+03e Chip 4 -1.6E+00x Chip 5 600 Chip 6 400 Average 200 0 1.10 1.15 1.20 1.25 1.30 VDD Figure 23. SEU FIT of XC3S1000 vs VDD This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 47 THE CHIP PROTECTOR 7.4.1.3 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances EP1C20 Figure 24 does not show a regular decrease of SEFI FIT at the higher VDD, as expected. This is partially explained because of the statistical uncertainty of SEFI events, ±20% as shown in Table 29. The FIT dispersion between chips is consistent with the accuracy assessments given in section 7.3. SEFI FIT for EP1C20 800 700 FIT per Chip 600 y = 2.7E+02e Chip 1 3.3E-01x Chip 2 500 Chip 3 400 Chip 4 Chip 5 300 Chip 6 200 Average 100 0 1.40 1.45 1.50 1.55 1.60 VDD Figure 24. 7.4.2 SEFI FIT of EP1C20 vs VDD Analysis of critical vs non critical SEU The test strategy enables to identify the critical and the non critical SEU in the configuration memory, that is, those SEU in the configuration memory that create an SEFI, and those that do not create an SEFI. 7.4.2.1 XC2V3000 Figure 25 presents the ratio SEFI / Total SEU for each chip and test condition. The overall ratio is 10% independent of the test condition. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 48 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR Ratio SEFI / Total SEU for XC2V3000 20% SEFI / Total SEU (% 15% Chip 1 Chip 2 Chip 3 Chip 4 10% Chip 5 Chip 6 Average 5% 0% 2 3 4 5 Test condition # Figure 25. 7.4.2.2 SEFI vs Total SEU XC2V3000 XC3S1000 Figure 26 presents the ratio SEFI / Total SEU for each chip and test condition. The overall ratio is 22% independent of the test condition. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 49 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR Ratio SEFI / Total SEU for XC3S1000 40% 35% SEFI / Total SEU (% 30% Chip 1 Chip 2 25% Chip 3 Chip 4 20% Chip 5 15% Chip 6 Average 10% 5% 0% 2 3 4 5 Test condition # Figure 26. 7.4.3 SEFI vs Total SEU XC3S1000 Analysis of single event latchup Single event latchup (SEL) consists in the neutron induced activation of parasitic thyristor structures in the CMOS process. In case a process is sensitive to latchup, the latchup rate is higher at the higher voltage, temperature and particle energy. Latchups result in increased current consumption, partial or total configuration memory wipe out, or complete loss of operation. Because the current is limited for protection, latchups lead to voltage shutdown to the DUT. The way the tester detects latchups is by monitoring the DUT supply voltages. In case a latchup is detected, the tester logs the event and switches the power off/on for recovering. A particular case of latchup is the microlatchup. The microlatchup consists in the activation of a parasitic thyristor structure with weak on-resistance and a low increase of current consumption. In case of microlatchup, the voltage and current can find a stability point that cannot be detected by the tester. In this case, one or more chips are partially or totally wiped out, or experience complete loss of operation during the duration of a test condition. No latchups were detected for any of the devices and conditions tested. In the following subsections, the voltage and current waveforms, acquired during the experiments, will be presented for each device and test condition. The sensitivity to microlatchup will be analyzed by inspection of the voltage and current waveforms and correlation with the observed number of errors in each chip. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 50 THE CHIP PROTECTOR 7.4.3.1 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances AX1000 We observe regular voltage and current waveforms in Figure 27 and Figure 28. No errors were observed for any of the chips and conditions tested. Therefore, there is no indication of latchup. Power supply waveforms 0.20 VCCA, VCCIB 1.6 0.15 ICCA+ICCIB 1.5 0.10 1.4 0.05 1.3 0.00 ICCA+ICCIB (A) VCCA, VCCIB (V) 1.7 Run # (1 sample per second) Figure 27. AX1000 VCCA and VCCIB waveforms VCCDA (V) 3.40 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.002 0.000 3.35 3.30 VCCDA 3.25 ICCDA 3.20 12 4 3 Run # (1 sample per second) Figure 28. AX1000 VCCDA waveform This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 51 ICCDA (A) Power supply waveforms THE CHIP PROTECTOR 7.4.3.2 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances APA1000 We observe regular voltage and current waveforms in Figure 29 and Figure 30. No errors were observed for any of the chips and conditions tested. Therefore, there is no indication of latchup. Power supply waveforms 0.30 2.7 VDD 2.6 IDD 0.25 0.20 2.5 2.4 IDD (A) VDD (V) 2.8 0.15 2.3 2.2 0.10 Run # (1 sample per second) Figure 29. APA1000 VDD waveform VDDP (V) 2.60 2.50 VDDP IDDP 2.40 12 3 4 5 Run # (1 sample per second) Figure 30. APA1000 VDDP waveform This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 52 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 IDDP (A) Power supply waveforms THE CHIP PROTECTOR 7.4.3.3 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC2V3000 We observe regular voltage and current waveforms in Figure 31 and Figure 32. The number of errors, presented in the following table is regular across the six chips tested. Therefore, there is no indication of latchup. VCCINT (V) 1.60 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0.0 1.55 1.50 VCCINT ICCINT 1.45 1.40 ICCINT (A) Power supply waveforms Run # (1 sample per second) Figure 31. XC2V3000 VCCINT waveform 3.10 3.5 3.0 3.05 2.5 2.0 1.5 1.0 3.00 VCCO 2.95 ICCO 0.5 0.0 2.90 2 1 3 4 5 Run # (1 sample per second) Figure 32. XC2V3000 VCCO waveform This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 53 ICCO (A) VCCO (V) Power supply waveforms THE CHIP PROTECTOR Run # 1 2 3 4 5 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances Condition Number of SEFI VDD Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Chip 6 1.425 0 0 0 0 0 0 1.425 14 10 10 13 12 17 1.500 20 9 16 18 15 14 1.575 14 18 13 15 16 13 1.425 16 11 16 11 20 18 Table 31. XC2V3000 number of SEFI for each chip Note: run #1 was a test run with the beam switched off, to test that the tester electronics was working correctly (cf section 6.3). 7.4.3.4 XC3S1000 The voltage and current waveforms could not be acquired during the experiments for the XC3S1000. The number of errors, presented in the following table is regular across the six chips tested. Therefore, there is no indication of latchup. Run # 1 2 3 4 5 Condition Number of SEFI VDD Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Chip 6 1.14 0 0 0 0 0 0 1.14 21 14 13 10 29 13 1.20 20 20 21 9 27 23 1.26 26 21 14 17 18 12 1.14 13 15 6 11 18 14 Table 32. XC3S1000 number of SEFI for each chip Note: run #1 was a test run with the beam switched off, to test that the tester electronics was working correctly (cf section 6.3). 7.4.3.5 EP1C20 The voltage and current waveforms could not be acquired during the experiments for the EP1C20. The number of errors, presented in the following table is regular across the six chips tested. Therefore, there is no indication of latchup. Run # 1 2 3 4 5 Condition Number of SEFI VDD Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Chip 6 1.425 0 0 0 0 0 0 1.425 24 17 10 14 28 14 1.500 17 16 6 16 27 22 1.575 19 21 21 17 11 19 1.425 29 11 21 28 23 22 Table 33. EP1C20 number of SEFI for each chip This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 54 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances Note: run #1 was a test run with the beam switched off, to test that the tester electronics was working correctly (cf section 6.3). 7.4.4 Bitmaps of errors Bitmaps allow to check the expected random distribution of errors in the configuration memory arrays. Each point in the bitmap represents a failing address. The bitmaps are logical bitmaps, not physical bitmaps, because the layout of the configuration memory is not available. In the logical bitmaps, the address LSB are mapped in the x-axis and the address MSB are mapped in the y-axis. 7.4.4.1 XC2V3000 The address refers to the location where the verification bitstream is stored in the tester memory. Valid addresses for the XC2V3000 are in the range 0x400069 to 0x5D4329. Each address holds 5 bits. Therefore, the verification bitstream length is 9,588,165 bits. The bitmaps show the expected random distribution of errors. XC2V3000 bitmap 4096 3072 Chip 1 Y Chip 2 Chip 3 2048 Chip 4 Chip 5 Chip 6 1024 0 0 1024 2048 3072 4096 X Figure 33. Bitmap for run#2 of XC2V3000 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 55 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC2V3000 bitmap 4096 3072 Chip 1 Y Chip 2 Chip 3 2048 Chip 4 Chip 5 Chip 6 1024 0 0 1024 2048 3072 4096 X Figure 34. Bitmap for run#3 of XC2V3000 XC2V3000 bitmap 4096 3072 Chip 1 Y Chip 2 Chip 3 2048 Chip 4 Chip 5 Chip 6 1024 0 0 1024 2048 3072 4096 X Figure 35. Bitmap for run#4 of XC2V3000 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 56 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC2V3000 bitmap 4096 3072 Chip 1 Y Chip 2 Chip 3 2048 Chip 4 Chip 5 Chip 6 1024 0 0 1024 2048 3072 4096 X Figure 36. 7.4.4.2 Bitmap for run#5 of XC2V3000 XC3S1000 The address refers to the location where the verification bitstream is stored in the tester memory. Valid addresses for the XC3S1000 are in the range 0x400068 to 0x49D349. Each address holds 5 bits. Therefore, the verification bitstream length is 3,219,050 bits. The bitmaps show the expected random distribution of errors. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 57 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC3S1000 bitmap 2048 Chip 1 Y Chip 2 Chip 3 1024 Chip 4 Chip 5 Chip 6 0 0 1024 2048 X Figure 37. Bitmap for run#2 of XC3S1000 XC3S1000 bitmap 2048 Chip 1 Y Chip 2 Chip 3 1024 Chip 4 Chip 5 Chip 6 0 0 1024 2048 X Figure 38. Bitmap for run#3 of XC3S1000 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 58 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC3S1000 bitmap 2048 Chip 1 Y Chip 2 Chip 3 1024 Chip 4 Chip 5 Chip 6 0 0 1024 2048 X Figure 39. Bitmap for run#4 of XC3S1000 XC3S1000 bitmap 2048 Chip 1 Y Chip 2 Chip 3 1024 Chip 4 Chip 5 Chip 6 0 0 1024 2048 X Figure 40. Bitmap for run#5 of XC3S1000 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 59 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR 7.4.5 Chip to chip variation This section presents the chip to chip FIT variations observed. The objective of this section is to check the neutron flux uniformity. The FIT variations are defined as the variation relative to the average of the 6 chips tested. ⎛ ⎞ FIT Chip(i) FIT variation for chip(i) (%) = ⎜⎜ − 1⎟⎟ × 100 ⎝ Average FIT Chips(1 to 6) ⎠ 7.4.5.1 XC2V3000 The FIT variations observed are within the expected statistical uncertainty: –16% to +18%, see Table 29. Therefore, we verify that the neutron flux is uniform. SEU FIT variation for each chip XC2V3000 30% FIT variation (%) 20% 10% Chip 1 0% Chip 2 Chip 3 -10% Chip 4 Chip 5 Chip 6 -20% -30% 2 3 4 5 Test condition # Figure 41. 7.4.5.2 Chip to chip FIT variation for XC2V3000 XC3S1000 The FIT variations observed are within the expected statistical uncertainty: –21% to +24%, see Table 29. Therefore, we verify that the neutron flux is uniform. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 60 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR SEU FIT variation for each chip XC3S1000 40% FIT variation (%) 30% 20% Chip 1 10% Chip 2 Chip 3 0% -10% Chip 4 Chip 5 -20% Chip 6 -30% -40% 2 3 4 5 Test condition # Figure 42. 7.4.5.3 Chip to chip FIT variation for XC3S1000 EP1C20 The FIT variations observed are within the expected statistical uncertainty: –40% to +56%, see Table 29. Therefore, we verify that the neutron flux is uniform. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 61 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR SEFI FIT variation for each chip EP1C20 80% 60% FIT variation (%) 40% Chip 1 20% Chip 2 Chip 3 0% Chip 4 Chip 5 -20% Chip 6 -40% -60% -80% 2 3 4 5 Test condition # Figure 43. 7.4.6 Chip to chip FIT variation for EP1C20 Consistency check A consistency test (repetition of the first condition) has been carried out at the end of the test sequence. The consistency test verifies the stability of the beam, DUT and tester. 7.4.6.1 XC2V3000 Figure 44 verifies that the results of runs #2 and #5 are consistent, taking into account the statistical uncertainty shown by the error bars. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 62 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances SEFI Consistency Check for XC2V3000 1800 FIT per Chip 1600 1400 Chip 1 1200 Chip 2 Chip 3 1000 Chip 4 800 Chip 5 600 Chip 6 400 Average 200 0 2 5 Test condition # Figure 44. 7.4.6.2 SEFI consistency check for XC2V3000 XC3S1000 Figure 45 verifies that the results of runs #2 and #5 are consistent, taking into account the statistical uncertainty shown by the error bars. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 63 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances SEFI Consistency Check for XC3S1000 700 600 Chip 1 FIT per Chip 500 Chip 2 Chip 3 400 Chip 4 300 Chip 5 Chip 6 200 Average 100 0 2 5 Test condition # Figure 45. 7.4.6.3 SEFI consistency check for XC3S1000 EP1C20 Figure 46 verifies that the results of runs #2 and #5 are consistent, taking into account the statistical uncertainty shown by the error bars. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 64 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances SEFI Consistency Check for EP1C20 700 600 Chip 1 FIT per Chip 500 Chip 2 Chip 3 400 Chip 4 300 Chip 5 Chip 6 200 Average 100 0 2 5 Test condition # Figure 46. 7.4.7 SEFI consistency check for EP1C20 Special observations iRoC has measured the flux uniformity at LANSCE using a specific test board. The test board consists in a linear array of 18 SRAM chips evenly spaced by 7.7 mm, as shown in Figure 49. The SRAM chips have the same part number and datecode. Since the chips are assumed identical, the error count variations determine the flux uniformity. An error count of 500 errors per chip, for the chips in the center of the board, was targeted in order to have a good statistical accuracy. The measured flux uniformity is shown in Figure 47 and Figure 48 for the x-axis and y-axis respectively. With relation to Figure 49, the positive x-axis is on the left, the positive y-axis is on the top. The factors in Figure 47 and Figure 48 have been used to correct the fluence for each chip, according to its position on the test board, for the AX1000, APA1000, XC2V3000, XC3S1000 and EP1C20. A verify operation using the Flash Pro programmer was performed for the APA1000 chips, at the end of the radiation tests performed. The verify operation was successful for all the APA1000 chips. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 65 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances Flux uniformity at LANSCE 40% Flux factor (%) 30% 20% Front X, 1st 10% Front X, 2nd 0% Front X, 3rd -10% Front X, Avg -20% -30% -40% -60 -40 -20 0 20 40 60 Offset (mm) Positive offset is on the right Figure 47. Flux uniformity at LANSCE (x-axis) Flux uniformity at LANSCE 40% Flux factor (%) 30% 20% Front Y, 1st 10% Mid Y, 1st 0% Back Y, 1st -10% Avg Y -20% -30% -40% -60 -40 -20 0 20 40 60 Offset (mm) Positive offset is on the bottom Figure 48. Flux uniformity at LANSCE (y-axis) This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 66 THE CHIP PROTECTOR Figure 49. GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances Flux uniformity measurement at LANSCE This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 67 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 8 LANSCE conclusions This test report provides the cosmic-ray SER of AX1000, APA1000, XC2V3000, XC3S1000 and EP1C20 devices. The cosmic-ray SER was measured at the LANSCE WNR facility at Los Alamos in February 2004. Table 34 presents the overall cosmic-ray FIT for each device at sea level in NYC. The overall FIT is calculated as the average of all chips and test conditions for the XC2V3000, XC3S1000 and EP1C20 devices. Appendix A details the cross-section and FIT for each chip and test condition. Device AX1000 APA1000 XC2V3000 XC3S1000 EP1C20 Overall FIT (SEFI) per Device <0.082 <0.038 1,150 320 460 Overall FIT (SEU) per Device <0.082 <0.038 8,680 1,240 n/a Table 34. Overall cosmic-ray FIT at sea level in NYC In Table 34, it is important to understand that no errors were observed for the AX1000 and APA1000, for any of the test conditions. The given figure of FIT is an upper bound calculated considering one error for all chips and test conditions. The AX1000 and APA1000, based in Antifuse and Flash processes respectively, are considered insensitive to terrestrial spectrum of neutrons, therefore extending the test for longer periods would still produce no errors, and result in lower bounds of FIT. The readback of the configuration memory is not available for the EP1C20. Therefore, the SEU FIT could not be measured for the EP1C20. The neutron flux increases with altitude, and has a maximum at approximately 60,000 ft. The FIT at sea level, 5,000 ft, 30,000 ft and 60,000 ft is provided in Table 35. FIT (SEFI) at FIT (SEFI) at FIT (SEFI) at FIT (SEFI) at sea level 5,000 ft 30,000 ft 60,000 ft Device AX1000 APA1000 XC2V3000 XC3S1000 EP1C20 <0.082 <0.038 1,150 320 460 <0.28 <0.13 3,900 1,100 1,600 <12 <5.6 170,000 47,000 67,000 <39 <18 540,000 150,000 220,000 Table 35. Overall cosmic-ray FIT at different altitudes No occurrences of latchup have been observed for any of the devices. No errors in the configuration circuitry of the XC2V3000, XC3S1000 or EP1C20 were observed. No hard errors were observed for any of the devices. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 68 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 9 Alpha tests 9.1 Characteristics of the alpha sources Alpha tests were conducted at iRoC premises using calibrated sources with the following characteristics: Source No. Isotope Active area diameter Flux at the surface Uncertainty 1 Am241 20 mm 2760 α/cm²/s 10% 2 Am241 44 mm 21.3 α/cm²/s 6% Table 36. Characteristics of the alpha sources The radioactive sources were directly placed at the package surface, which is at 1 mm or less from the die surface. In addition, the active area is much larger than the die area to ensure that nearly all angles of incidence are enabled. A geometry factor has been calculated that takes into account the flux reduction resulting from the distance of the source to the die. The calculation of the geometry factor is explained in Appendix C. For a disk shaped source, the formula is: Gdisk= 1 − h h² + ρ ² Where h is the distance from the source to the die, and ρ is the radius of the source. Device Source No. AX1000 APA1000 XC2V3000 XC3S1000 EP1C20 1 1 2 2 2 Radius Distance ρ (mm) h (mm) 10 10 22 22 22 1 1 0.5 0.5 0.5 Gdisk 0.90 0.90 0.98 0.98 0.98 Table 37. Alpha source utilization and geometry factors for each device This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 69 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR 9.2 Tested conditions and schedule The following tables provide the sequence of conditions that were tested. Additionally to the test conditions, stability and consistency checks have been performed at the beginning and the end of each test sequence. A stability test (beam off) has been carried out before irradiation (cf. section 9.4). A consistency test (repetition of the first condition) has been carried out at the end of the test sequence The order of the test conditions follows the Test Plan [3]. The tables are extracted from the campaign logbook files in appendix A.3. Note that chips were irradiated one at a time during alpha tests. Run 21 stands for run 2 and chip 1, run 22 stands for run 2 and chip 2, etc. Run # Device Particle 1 21 22 31 32 41 42 51 52 AX1000 AX1000 AX1000 AX1000 AX1000 AX1000 AX1000 AX1000 AX1000 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 Start Date 9-Apr 9-Apr 12-Apr 10-Apr 13-Apr 10-Apr 14-Apr 11-Apr 14-Apr Stop Time 10:22:02 10:50:02 19:45:04 2:53:03 11:48:04 18:56:03 3:51:04 10:59:03 19:54:05 Date 9-Apr 10-Apr 13-Apr 10-Apr 14-Apr 11-Apr 14-Apr 12-Apr 15-Apr Time 10:34:02 2:50:01 11:45:03 18:53:02 3:48:03 10:56:02 19:51:03 2:59:03 11:54:04 Condition Cycle VDD Temp 200ns 1.4 25°C 200ns 1.4 25°C 200ns 1.4 25°C 200ns 1.5 25°C 200ns 1.5 25°C 200ns 1.6 25°C 200ns 1.6 25°C 200ns 1.4 25°C 200ns 1.4 25°C Table 38. Conditions tested for AX1000 Run # Device 21 22 APA1000 APA1000 Particle Date α−Am241 27-Apr α−Am241 30-Apr Start Stop Time 17:00:00 17:00:00 Date 30-Apr 3-May Time 9:00:00 9:00:00 Condition Cycle VDD Temp 200ns 2.3 25°C 200ns 2.3 25°C Table 39. Conditions tested for APA1000 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 70 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR Run # Device Particle 1 21 22 31 32 41 42 51 52 XC2V3000 XC2V3000 XC2V3000 XC2V3000 XC2V3000 XC2V3000 XC2V3000 XC2V3000 XC2V3000 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 Start Date 8-Oct 8-Oct 9-Oct 8-Oct 10-Oct 9-Oct 10-Oct 9-Oct 10-Oct Stop Time 12:02:15 19:16:10 11:46:14 22:19:11 12:11:21 1:22:11 15:14:22 4:25:12 18:17:23 Date 8-Oct 8-Oct 9-Oct 9-Oct 10-Oct 9-Oct 10-Oct 9-Oct 10-Oct Time 14:31:15 22:17:06 14:47:10 1:20:07 15:12:17 4:23:07 18:15:18 7:26:08 21:18:20 Condition Cycle VDD Temp 200ns 1.43 25°C 200ns 1.43 25°C 200ns 1.43 25°C 200ns 1.50 25°C 200ns 1.50 25°C 200ns 1.58 25°C 200ns 1.58 25°C 200ns 1.43 25°C 200ns 1.43 25°C Table 40. Conditions tested for XC2V3000 Run # Device Particle 1 24 25 26 34 35 36 44 45 46 54 55 56 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 Start Date 9-Apr 9-Apr 10-Apr 11-Apr 9-Apr 10-Apr 11-Apr 10-Apr 11-Apr 12-Apr 10-Apr 11-Apr 12-Apr Stop Time 11:28:01 12:13:02 12:30:02 12:55:03 18:16:02 18:33:02 18:58:02 0:19:02 0:36:03 1:01:03 6:22:02 6:39:02 7:04:03 Date 9-Apr 9-Apr 10-Apr 11-Apr 10-Apr 11-Apr 12-Apr 10-Apr 11-Apr 12-Apr 10-Apr 11-Apr 12-Apr Time 11:38:02 18:13:01 18:30:02 18:55:03 0:16:02 0:33:02 0:58:02 6:19:01 6:36:02 7:01:02 12:22:02 12:39:02 13:04:02 Condition Cycle VDD Temp 200ns 1.14 25°C 200ns 1.14 25°C 200ns 1.14 25°C 200ns 1.14 25°C 200ns 1.20 25°C 200ns 1.20 25°C 200ns 1.20 25°C 200ns 1.26 25°C 200ns 1.26 25°C 200ns 1.26 25°C 200ns 1.14 25°C 200ns 1.14 25°C 200ns 1.14 25°C Table 41. Conditions tested for XC3S1000 Run # Device Particle 1 21 22 31 32 41 42 51 52 EP1C20 EP1C20 EP1C20 EP1C20 EP1C20 EP1C20 EP1C20 EP1C20 EP1C20 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 Start Date 13-Oct 13-Oct 14-Oct 13-Oct 14-Oct 14-Oct 15-Oct 14-Oct 15-Oct Stop Time 14:53:38 16:11:06 17:01:12 22:04:07 23:04:14 4:07:08 5:07:16 10:10:11 11:10:18 Date 13-Oct 13-Oct 14-Oct 14-Oct 15-Oct 14-Oct 15-Oct 14-Oct 15-Oct Time 15:04:27 22:01:04 23:01:10 4:04:06 5:04:12 10:07:07 11:07:14 16:10:09 17:10:15 Condition Cycle VDD Temp 200ns 1.425 25°C 200ns 1.425 25°C 200ns 1.425 25°C 200ns 1.500 25°C 200ns 1.500 25°C 200ns 1.575 25°C 200ns 1.575 25°C 200ns 1.425 25°C 200ns 1.425 25°C Table 42. Conditions tested for EP1C20 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 71 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 9.3 Devices tested The following tables show the lot codes of the chips that were actually tested: Chip 1 DOAAJ1 0320 Chip 2 DOJC21 0345 Table 43. Lot codes of the AX1000 chips tested Chip 1 MF7G7 0247 Chip 2 MF7G7 0247 Table 44. Lot codes of the APA1000 chips tested Chip 1 AGT0413 A2164275A Chip 2 AGT0413 A2164275A Table 45. Lot codes of the XC2V3000 chips tested Chip 1 FT256AFQ0341 D13989A Chip 2 FT256AFQ0341 D13989A Chip 3 FT256AFQ0341 D13990A Table 46. Lot codes of the XC3S1000 chips tested Chip 1 Chip 2 AAD9G0413A AAD9G0413A Table 47. Lot codes of the EP1C20 chips tested 9.4 Stability without alpha source An error rate measurement is performed without the alpha source and with the components placed in the target. The die were covered to avoid ambient light. This aims at verifying the robustness of both the tester and the DUT board in the test environment. This experiment was done during 10 minutes and no error occurred (cf run #1 in Table 38 to Table 42) This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 72 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 10 Alpha results 10.1 Cross-section and FIT calculation The cross-section defines the sensitivity of a device. The cross-section per chip is defined as σ=N/(F*C) where N is the total number of errors, F is the fluence and C is the number of chips tested. In this document, the cross-section is given in cm²/chip. The FIT is calculated by multiplying the cross-section by the alpha flux emitted by the real package F(package). The FIT rate per chip is: FIT = σ(Am241) *F(package) * 109 (error/109hour/chip) The FIT provided in this report is based on an assumption for package emission F(package) equal to 0.001 α/cm²/hour. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 73 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 10.2 Overall FIT results Table 48 presents the overall alpha particle FIT for an emission rate equal to 0.001 α/cm²/hour. The overall FIT is calculated as the average of all chips and test conditions for the XC2V3000, XC3S1000 and EP1C20 devices. Appendix A details the cross-section and FIT for each chip and test condition. Overall FIT (SEFI) per Device AX1000 < 0.00087 APA1000 < 0.00087 XC2V3000 140 (note 1) XC3S1000 260 EP1C20 100 Device Overall FIT (SEU) per Device <0.00087 <0.00087 1040 940 n/a Table 48. Overall alpha particle FIT for 0.001 a/cm²/hour Note 1: the SEFI FIT of XC2V3000 was extrapolated by multiplying the SEU FIT by the SEFI/SEU FIT ratio measured in cosmic-rays tests, 13.5%. In Table 48, it is important to understand that no errors were observed for the AX1000 and APA1000, for any of the test conditions. The given figure of FIT is an upper bound calculated considering one error for all chips and test conditions. The AX1000 and APA1000, based in Antifuse and Flash processes respectively, are considered insensitive to alpha particles emitted from the packaging, therefore extending the test for longer periods would still produce no errors, and result in lower bounds of FIT. The readback of the configuration memory is not available for the EP1C20. Therefore, the SEU FIT could not be measured for the EP1C20. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 74 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 10.3 Accuracy of results The accuracy of the cross-section results is assessed in this section. The accuracy of the cross-section is the sum of the error count and fluence measurement accuracies. 10.3.1 Error count statistics The error count is generally described by a Poisson distribution, cf appendix C.1 in [2]. If N errors occur, the mean error count is approximated by N. The standard deviation is given by √N. The error count can be bounded using the upper and lower limits in Table 11, extracted from appendix C.2 of [2]. In using this table, the first column is the actual number of events observed in the experiment. The upper and lower limits define the 95% confidence interval for the true mean of the distribution. The upper and lower limits for any number of events can be calculated using the formulas given in appendix B. The accuracy of the error count is defined in this report using 95% confidence intervals. The 95% confidence limits depend on the number of errors observed. The number of errors is detailed in appendix A for each chip and test condition. The following table summarizes the 95% confidence intervals for each device. For example, the overall number of SEU per chip and test condition is 235 for the XC2V3000. By using the formulas given in appendix B, we find that the lower and upper limits are 205.9 and 267.0 respectively. The limits in Table 49 are calculated as (Lower limit/Mean error count – 1)*100 = -12%, and (Upper limit/Mean error count – 1)*100 = +14%. Device AX1000 APA1000 Error type SEFI SEFI SEFI XC2V3000 SEU SEFI XC3S1000 SEU EP1C20 SEFI Errors 0 0 n/a n/a n/a 235 471 110 329 1315 395 1186 45 90 359 Lower limit n/a n/a n/a n/a n/a -12% -9% -18% -11% -6% -10% -6% -27% -20% -10% Upper limit n/a n/a n/a n/a n/a +14% +9% +21% +11% +6% +10% +6% +34% +23% +11% Comment No errors observed No errors observed Errors per chip and test condition Errors for all chips per test condition Errors for all chips and test conditions Errors per chip and test condition Errors for all chips per test condition Errors per chip and test condition Errors for all chips per test condition Errors for all chips and test conditions Errors per chip and test condition Errors for all chips per test condition Errors per chip and test condition Errors for all chips per test condition Errors for all chips and test conditions Table 49. 95% confidence intervals for all devices This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 75 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 10.3.2 Fluence measurement accuracy The accuracy of the fluence measurement is indicated in Table 50. Device Source No. Accuracy AX1000 APA1000 XC2V3000 XC3S1000 EP1C20 1 1 2 2 2 10% 10% 6% 6% 6% Table 50. Alpha source utilization and accuracy for each device This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 76 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 10.4 Detailed analysis Detailed analysis of the results is presented hereafter. The following table summarizes the analyses presented for each device: Analysis Voltage influence on FIT Analysis of critical vs non critical SEU Analysis of single event latchup Bitmaps of errors Chip to chip variations Special observations AX1000 APA1000 √ √ XC2V3000 √ √ √ √ √ √ XC3S1000 √ √ √ √ √ √ EP1C20 √ √ √ √ Table 51. Detailed analysis for alpha tests Many of the detailed analysis cannot be performed for the AX1000 and APA1000 because no errors were observed for these devices. 10.4.1 Voltage influence on FIT The SEFI and SEU FIT dependence vs VDD is presented in this section. The FIT is plotted separately for each chip. The FIT average of all chips is also plotted, and the average FIT is used to fit an exponential curve. 10.4.1.1 XC2V3000 Figure 50 shows a regular decrease of FIT at the higher VDD. SEU FIT for XC2V3000 FIT per Chip 1500 1000 500 Chip 1 y = 2.0E+03e Chip 2 -4.5E-01x Average 0 1.40 1.45 1.50 1.55 1.60 VDD Figure 50. SEU FIT of XC2V3000 vs VDD This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 77 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 10.4.1.2 XC3S1000 Figure 51 and Figure 52 show a regular decrease of FIT at the higher VDD, as expected. The SEU FIT of chip no. 3 is higher than the uncertainty assessment made in section 10.3.1. This dispersion will be studied in section 10.4.5.2. FIT per Chip SEFI FIT for XC3S1000 350 300 250 200 150 100 50 0 Chip 1 Chip 2 y = 1.1E+03e 1.10 1.15 Chip 3 -1.2E+00x 1.20 Average 1.25 1.30 VDD Figure 51. SEFI FIT of XC3S1000 vs VDD SEU FIT for XC3S1000 FIT per Chip 2000 y = 2.5E+03e -8.3E-01x Chip 1 1500 Chip 2 1000 Chip 3 Average 500 0 1.10 1.15 1.20 1.25 1.30 VDD Figure 52. SEU FIT of XC3S1000 vs VDD This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 78 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 10.4.1.3 EP1C20 Figure 53 shows a regular decrease of FIT at the higher VDD. SEFI FIT for EP1C20 FIT per Chip 200 y = 9.6E+04e 150 -4.7E+00x Chip 1 100 Chip 2 Average 50 0 1.40 1.45 1.50 1.55 1.60 VDD Figure 53. SEFI FIT of EP1C20 vs VDD 10.4.2 Analysis of critical vs non critical SEU The test strategy enables to identify the critical and the non critical SEU in the configuration memory, that is, those SEU in the configuration memory that create an SEFI, and those that do not create an SEFI. 10.4.2.1 XC3S1000 Figure 54 presents the ratio SEFI / Total SEU for each chip and test condition. The overall ratio is 28% independent of the test condition. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 79 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR SEFI / Total SEU (%) Ratio SEFI / Total SEU for XC3S1000 50% 40% Chip 1 30% Chip 2 20% Chip 3 10% Average 0% 2 3 4 5 Test condition # Figure 54. SEFI vs Total SEU XC3S1000 10.4.3 Analysis of single event latchup Single event latchup (SEL) consists in the radiation induced activation of parasitic thyristor structures in the CMOS process. In case a process is sensitive to latchup, the latchup rate is higher at the higher voltage, temperature and particle energy. Latchups result in increased current consumption, partial or total configuration memory wipe out, or complete loss of operation. Because the current is limited for protection, latchups lead to voltage shutdown to the DUT. The way the tester detects latchups is by monitoring the DUT supply voltages. In case a latchup is detected, the tester logs the event and switches the power off/on for recovering. A particular case of latchup is the microlatchup. The microlatchup consists in the activation of a parasitic thyristor structure with weak on-resistance and a low increase of current consumption. In case of microlatchup, the voltage and current can find a stability point that cannot be detected by the tester. In this case, one or more chips are partially or totally wiped out, or experience complete loss of operation during the duration of a test condition. No latchups were detected for any of the devices and conditions tested. In the following subsections, the voltage and current waveforms, acquired during the experiments, will be presented for each device and test condition. The sensitivity to microlatchup will be analyzed by inspection of the voltage and current waveforms and correlation with the observed number of errors in each chip. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 80 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 10.4.3.1 AX1000 We observe regular voltage and current waveforms in Figure 55 and Figure 56. No errors were observed for any of the chips and conditions tested. Therefore, there is no indication of latchup. 0.15 1.7 1.6 1.5 1.4 VCCA, VCCIB ICCA+ICCIB 0.10 0.05 0.00 1.3 ICCA+ICCIB (A) VCCA, VCCIB (V) Power supply waveforms Run # (1 sample per second) 1.7 0.15 1.6 1.5 VCCA, VCCIB ICCA+ICCIB 1.4 1.3 0.10 0.05 0.00 ICCA+ICCIB (A) VCCA, VCCIB (V) Power supply waveforms Run # (1 sample per second) Figure 55. AX1000 VCCA and VCCIB waveforms This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 81 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 3.35 3.30 VCCDA 3.25 ICCDA 3.20 2 3 0.006 0.005 0.004 0.003 0.002 0.001 0.000 ICCDA (A) VCCDA (V) 3.40 0.006 0.005 0.004 0.003 0.002 0.001 0.000 ICCDA (A) Power supply waveforms 4 Run # (1 sample per second) Power supply waveforms VCCDA (V) 3.40 3.35 3.30 VCCDA 3.25 ICCDA 3.20 4 5 Run # (1 sample per second) Figure 56. AX1000 VCCDA waveform 10.4.3.2 XC2V3000 The voltage and current waveforms could not be acquired during the experiments for the XC2V3000. The number of SEU errors, presented in the following table is regular across the chips tested. Therefore, there is no indication of latchup. Run # 1 2 3 4 5 Condition Number of SEU VDD Chip 1 Chip 2 1.425 0 0 1.425 230 250 1.500 233 218 1.575 222 227 1.425 251 251 Table 52. XC2V3000 number of SEU for each chip This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 82 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 10.4.3.3 XC3S1000 The voltage and current waveforms could not be acquired during the experiments for the XC3S1000. The number of SEFI errors, presented in the following table is regular across the six chips tested. Therefore, there is no indication of latchup. Run # 1 2 3 4 5 Condition Number of SEFI VDD Chip 1 Chip 2 Chip 3 1.14 0 0 0 1.14 131 112 119 1.20 112 97 96 1.26 111 98 107 1.14 104 114 114 Table 53. XC3S1000 number of SEFI for each chip Note: run #1 was a test run with the beam switched off, to test that the tester electronics was working correctly (cf section 9.4). 10.4.3.4 EP1C20 The voltage and current waveforms could not be acquired during the experiments for the EP1C20. The number of SEFI errors, presented in the following table is regular across the chips tested. Therefore, there is no indication of latchup. Run # 1 2 3 4 5 Condition Number of SEFI VDD Chip 1 Chip 2 1.425 0 0 1.425 53 56 1.500 38 47 1.575 24 31 1.425 54 56 Table 54. EP1C20 number of SEFI for each chip 10.4.4 Bitmaps of errors Bitmaps allow to check the expected random distribution of errors in the configuration memory arrays. Each point in the bitmap represents a failing address. The bitmaps are logical bitmaps, not physical bitmaps, because the layout of the configuration memory is not available. In the logical bitmaps, the address LSB are mapped in the x-axis and the address MSB are mapped in the y-axis. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 83 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 10.4.4.1 XC2V3000 The address refers to the location where the verification bitstream is stored in the tester memory. Valid addresses for the XC2V3000 are in the range 0x400069 to 0x5D4329. Each address holds 5 bits. Therefore, the verification bitstream length is 9,588,165 bits. The bitmaps show the expected random distribution of errors. XC2V3000 bitmap 4096 Y 3072 Chip 1 2048 Chip 2 1024 0 0 1024 2048 3072 4096 X Figure 57. Bitmap for run#2 of XC2V3000 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 84 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC2V3000 bitmap 4096 Y 3072 Chip 1 2048 Chip 2 1024 0 0 1024 2048 3072 4096 X Figure 58. Bitmap for run#3 of XC2V3000 XC2V3000 bitmap 4096 Y 3072 Chip 1 2048 Chip 2 1024 0 0 1024 2048 3072 4096 X Figure 59. Bitmap for run#4 of XC2V3000 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 85 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC2V3000 bitmap 4096 Y 3072 Chip 1 2048 Chip 2 1024 0 0 1024 2048 3072 4096 X Figure 60. Bitmap for run#5 of XC2V3000 10.4.4.2 XC3S1000 The address refers to the location where the verification bitstream is stored in the tester memory. Valid addresses for the XC3S1000 are in the range 0x400068 to 0x49D349. Each address holds 5 bits. Therefore, the verification bitstream length is 3,219,050 bits. The bitmaps show the expected random distribution of errors. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 86 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC3S1000 bitmap 2048 Y Chip 1 1024 Chip 2 Chip 3 0 0 1024 2048 X Figure 61. Bitmap for run#2 of XC3S1000 XC3S1000 bitmap 2048 Y Chip 1 1024 Chip 2 Chip 3 0 0 1024 2048 X Figure 62. Bitmap for run#3 of XC3S1000 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 87 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC3S1000 bitmap 2048 Y Chip 1 1024 Chip 2 Chip 3 0 0 1024 2048 X Figure 63. Bitmap for run#4 of XC3S1000 XC3S1000 bitmap 2048 Y Chip 1 1024 Chip 2 Chip 3 0 0 1024 2048 X Figure 64. Bitmap for run#5 of XC3S1000 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 88 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 10.4.5 Chip to chip variation This section presents the chip to chip FIT variations observed. The objective of this section is to compare the sensitivity of different chips. The FIT variations are defined as the variation relative to the average of the chips tested. ⎛ ⎞ FIT Chip(i) FIT variation for chip(i) (%) = ⎜⎜ − 1⎟⎟ × 100 ⎝ Average FIT Chips(1 to 3) ⎠ 10.4.5.1 XC2V3000 The FIT variations observed are within the expected statistical uncertainty: –12% to +14%, see Table 49. FIT variation (%) . SEU FIT variation for each chip XC2V3000 10% 5% Chip 1 0% Chip 2 -5% -10% 2 Figure 65. 3 4 Test condition # 5 Chip to chip FIT variation for XC2V3000 10.4.5.2 XC3S1000 The FIT variation of chip no. 3 exceeds the assessed statistical uncertainty –10% to +10% (cf Table 49). In order to explain this phenomenon, we consider that chips no. 1 and 2, and chip no. 3 come from two different lots (cf Table 46). Process or passivation layer thickness differences between the two lots should be assessed to confirm this explanation. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 89 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances FIT variation (%) . SEU FIT variation for each chip XC3S1000 100% 75% 50% 25% 0% -25% -50% -75% -100% Chip 1 Chip 2 Chip 3 2 Figure 66. 3 4 Test condition # 5 Chip to chip FIT variation for XC3S1000 10.4.5.3 EP1C20 The FIT variations observed are within the expected statistical uncertainty: –27% to +34%, see Table 49. FIT variation (%) . SEFI FIT variation for each chip EP1C20 15% 10% 5% Chip 1 0% Chip 2 -5% -10% -15% 2 Figure 67. 3 4 Test condition # 5 Chip to chip FIT variation for EP1C20 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 90 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 10.4.6 Consistency check A consistency test (repetition of the first condition) has been carried out at the end of the test sequence. The consistency test verifies the stability of the alpha source, DUT and tester. 10.4.6.1 XC2V3000 Figure 68 verifies that the results of runs #2 and #5 are consistent, taking into account the statistical uncertainty shown by the error bars. FIT per Chip SEU Consistency Check for XC2V3000 1400 1200 1000 800 600 400 200 0 Chip 1 Chip 2 Average 2 5 Test condition # Figure 68. SEU consistency check for XC2V3000 10.4.6.2 XC3S1000 Figure 69 verifies that the results of runs #2 and #5 are consistent, taking into account the statistical uncertainty shown by the error bars. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 91 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances FIT per Chip SEFI Consistency Check for XC3S1000 350 300 250 200 150 100 50 0 Chip 1 Chip 2 Chip 3 Average 2 5 Test condition # Figure 69. SEFI consistency check for XC3S1000 10.4.6.3 EP1C20 Figure 70 verifies that the results of runs #2 and #5 are consistent, taking into account the statistical uncertainty shown by the error bars. FIT per Chip SEFI Consistency Check for EP1C20 160 140 120 100 80 60 40 20 0 Chip 1 Chip 2 Average 2 5 Test condition # Figure 70. SEFI consistency check for EP1C20 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 92 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 10.4.7 Special observations One occurrence of an error in the configuration circuitry of XC3S1000 was observed in run no. 3 for chip no 3. As a result, the readback operation failed and the configuration memory appeared to be entirely wiped out. The FIT rate for configuration circuitry failures is calculated using the formula in section 10.1 and considering that the total fluence for XC3S1000 was 5.0E+06 α/cm². Therefore, FIT = (1 event / 5.0E+06 α/cm²) * 0.001 α/cm²/hour * 1E+09 hour = 0.20. A verify operation using the Flash Pro programmer was performed for the APA1000 chips, at the end of the radiation tests performed. The verify operation was successful for all the APA1000 chips. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 93 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances 11 Alpha conclusions This test report provides the alpha particle SER of AX1000, APA1000, XC2V3000, XC3S1000 and EP1C20 devices. The alpha particle SER was measured at iRoC premises using calibrated Am241 foil sources in April and October 2004. Table 55 presents the overall alpha particle FIT for an emission rate equal to 0.001 α/cm²/hour. The overall FIT is calculated as the average of all chips and test conditions for the XC2V3000, XC3S1000 and EP1C20 devices. Appendix A details the cross-section and FIT for each chip and test condition. Overall FIT (SEFI) per Device AX1000 < 0.00087 APA1000 < 0.00087 XC2V3000 140 (note 1) XC3S1000 260 EP1C20 100 Device Overall FIT (SEU) per Device <0.00087 <0.00087 1040 940 n/a Table 55. Overall alpha particle FIT for 0.001 a/cm²/hour Note 1: the SEFI FIT of XC2V3000 was extrapolated by multiplying the SEU FIT by the SEFI/SEU FIT ratio measured in cosmic-rays tests, 13.5%. In Table 55, it is important to understand that no errors were observed for the AX1000 and APA1000, for any of the test conditions. The given figure of FIT is an upper bound calculated considering one error for all chips and test conditions. The AX1000 and APA1000, based in Antifuse and Flash processes respectively, are considered insensitive to alpha particles emitted from the packaging, therefore extending the test for longer periods would still produce no errors, and result in lower bounds of FIT. The readback of the configuration memory is not available for the EP1C20. Therefore, the SEU FIT could not be measured for the EP1C20. No occurrences of latchup were observed for any of the devices. One error in the configuration circuitry of XC3S1000 was observed, and the resulting FIT is 0.20. No hard errors were observed for any of the devices. This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 94 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances A Details of cross-sections and FIT A.1 14 MeV neutrons AX1000 Run # Device 1 2 3 4 5 AX1000 AX1000 AX1000 AX1000 AX1000 Run # 1 2 3 4 5 Energy (MeV) 14 14 14 14 14 Start Date Dec-16 Dec-16 Dec-16 Dec-17 Time 14:29:13 14:47:15 17:00:46 9:10:42 Stop Time 14:44:16 16:59:27 9:08:22 10:21:37 Condition Fluence 1 Fluence 2 Cycle VDD Temp (neutron/cm²) (neutron/cm²) 200ns 1.4 25°C 0.0E+00 0.0E+00 200ns 1.4 25°C 6.5E+10 4.7E+10 200ns 1.5 25°C 5.4E+10 3.9E+10 200ns 1.6 25°C 6.4E+10 4.7E+10 200ns 1.4 25°C Number of SEFI FIT (SEFI/10^9hour/chip) Comments Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 0 0 0 0 0 # # # # # stability check 0 0 0 0 0 0.0 0.0 0.0 0.0 0.0 0 0 0 0 0 0.0 0.0 0.0 0.0 0.0 0 0 0 0 0 0.0 0.0 0.0 0.0 0.0 consistency check, not done APA1000 Run # Device 1 2 3 4 5 APA1000 APA1000 APA1000 APA1000 APA1000 Run # 1 2 3 4 5 Energy (MeV) 14 14 14 14 14 Start Date Dec-16 Dec-16 Dec-16 Dec-17 Time 14:30:26 14:47:31 17:01:35 9:10:45 Stop Time 14:44:14 16:59:35 9:08:20 10:21:34 Condition Fluence 1 Fluence 2 Cycle VDD Temp (neutron/cm²) (neutron/cm²) 200ns 2.3 25°C 0.0E+00 0.0E+00 200ns 2.3 25°C 3.6E+10 2.8E+10 200ns 2.5 25°C 3.0E+10 2.3E+10 200ns 2.7 25°C 3.5E+10 2.8E+10 200ns 2.3 25°C Number of SEFI FIT (SEFI/10^9hour/chip) Comments Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Chip 6 Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Chip 6 0 0 0 0 0 0 # # # # # # stability check 0 0 0 0 0 0 0.0 0.0 0.0 0.0 0.0 0.0 0 0 0 0 0 0 0.0 0.0 0.0 0.0 0.0 0.0 0 0 0 0 0 0 0.0 0.0 0.0 0.0 0.0 0.0 consistency check, not done This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 95 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC2V3000 Run # Device 1 2 3 4 5 XC2V3000 XC2V3000 XC2V3000 XC2V3000 XC2V3000 Run # 1 2 3 4 5 Run # 1 2 3 4 5 Energy (MeV) 14 14 14 14 14 Start Date Dec-17 Dec-17 Dec-17 Dec-17 Dec-17 Time 13:31:49 13:36:31 14:31:12 15:08:40 15:52:07 Number of SEFI Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Chip 6 0 0 0 0 0 0 22 17 25 19 11 11 21 12 18 21 17 18 14 16 15 25 13 18 14 18 23 20 16 16 Chip 1 0 138 131 132 145 Number of SEU Chip 2 Chip 3 Chip 4 Chip 5 0 0 0 0 116 139 118 93 124 133 127 111 117 114 122 108 137 144 112 101 Chip 6 0 97 126 105 130 Stop Time 13:36:11 14:29:04 15:08:02 15:46:06 16:34:41 Condition Fluence 1 Fluence 2 Cycle VDD Temp (neutron/cm²) (neutron/cm²) 200ns 1.425 25°C 0.0E+00 0.0E+00 200ns 1.425 25°C 3.5E+08 3.2E+08 200ns 1.500 25°C 3.8E+08 3.5E+08 200ns 1.575 25°C 3.7E+08 3.4E+08 200ns 1.425 25°C 4.0E+08 3.7E+08 Chip 1 # 887 764 527 491 FIT (SEFI/10^9hour/chip) Chip 2 Chip 3 Chip 4 Chip 5 # # # # 685 1007 836 484 437 655 834 675 602 564 1027 534 631 806 765 612 Comments Chip 6 # stability check 484 715 739 612 consistency check Chip 1 # 5561 4766 4965 5080 FIT (SEU/10^9hour/chip) Chip 2 Chip 3 Chip 4 Chip 5 # # # # 4675 5601 5191 4091 4512 4839 5044 4409 4401 4288 5010 4435 4800 5045 4284 3863 Comments Chip 6 # stability check 4267 5005 4312 4972 consistency check This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 96 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR A.2 LANSCE AX1000 Run # Device 1 2 3 4 5 AX1000 AX1000 AX1000 AX1000 Run # 1 2 3 4 5 Run # 1 2 3 4 5 Chip 1 0.0E+00 1.2E+10 1.0E+10 1.2E+10 Energy (MeV) LANSCE LANSCE LANSCE LANSCE Chip 2 0.0E+00 1.2E+10 1.0E+10 1.1E+10 Start Date 17-Feb 17-Feb 17-Feb 18-Feb Stop Time 14:27:15 15:46:19 22:41:50 4:28:29 Fluence (n/cm²) Chip 3 0.0E+00 1.2E+10 1.0E+10 1.1E+10 Date 17-Feb 17-Feb 18-Feb 18-Feb Chip 4 0.0E+00 1.3E+10 1.1E+10 1.2E+10 Time 14:38:02 22:40:35 4:27:11 9:46:52 Condition Cycle VDD Temp 200ns 1.4 25°C 200ns 1.4 25°C 200ns 1.5 25°C 200ns 1.6 25°C Chip 5 0.0E+00 1.2E+10 1.0E+10 1.1E+10 Number of SEFI FIT (SEFI/10^9hour/chip) Comments Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 0 0 0 0 0 # # # # # stability check 0 0 0 0 0 0.0 0.0 0.0 0.0 0.0 0 0 0 0 0 0.0 0.0 0.0 0.0 0.0 0 0 0 0 0 0.0 0.0 0.0 0.0 0.0 consistency check not done This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 97 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR APA1000 Run # Device 1 2 3 4 5 APA1000 APA1000 APA1000 APA1000 APA1000 Energy (MeV) LANSCE LANSCE LANSCE LANSCE LANSCE Chip 1 0.0E+00 1.2E+10 1.3E+10 1.3E+10 4.1E+10 Chip 2 0.0E+00 1.1E+10 1.2E+10 1.2E+10 3.7E+10 Run # 1 2 3 4 5 Run # 1 2 3 4 5 Start Date 18-Feb 18-Feb 18-Feb 18-Feb 19-Feb Stop Time 10:36:44 10:47:46 15:22:12 21:09:08 5:56:33 Fluence (n/cm²) Chip 3 0.0E+00 1.1E+10 1.2E+10 1.1E+10 3.7E+10 Date 18-Feb 18-Feb 18-Feb 19-Feb 19-Feb Chip 4 0.0E+00 1.2E+10 1.3E+10 1.3E+10 4.0E+10 Time 10:46:44 15:21:14 21:07:56 5:55:00 21:26:26 Condition Cycle VDD Temp 200ns 2.3 25°C 200ns 2.3 25°C 200ns 2.5 25°C 200ns 2.7 25°C 200ns 2.3 25°C Chip 5 0.0E+00 1.1E+10 1.1E+10 1.1E+10 3.7E+10 Number of SEFI FIT (SEFI/10^9hour/chip) Comments Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 0 0 0 0 0 # # # # # stability check 0 0 0 0 0 0.0 0.0 0.0 0.0 0.0 0 0 0 0 0 0.0 0.0 0.0 0.0 0.0 0 0 0 0 0 0.0 0.0 0.0 0.0 0.0 0 0 0 0 0 0.0 0.0 0.0 0.0 0.0 consistency check This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 98 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR XC2V3000 Run # Device 1 2 3 4 5 XC2V3000 XC2V3000 XC2V3000 XC2V3000 XC2V3000 Run # 1 2 3 4 5 Run # 1 2 3 4 5 Run # 1 2 3 4 5 Chip 1 0.0E+00 1.9E+08 1.6E+08 2.0E+08 1.9E+08 Energy (MeV) LANSCE LANSCE LANSCE LANSCE LANSCE Start Date 17-Feb 17-Feb 17-Feb 17-Feb 17-Feb Stop Time 14:28:11 15:46:53 15:59:04 16:10:38 16:23:38 Fluence SEFI (n/cm²) Chip 2 Chip 3 Chip 4 Chip 5 0.0E+00 0.0E+00 0.0E+00 0.0E+00 1.7E+08 1.9E+08 1.8E+08 1.7E+08 1.5E+08 1.6E+08 1.6E+08 1.5E+08 1.8E+08 2.0E+08 2.0E+08 1.8E+08 1.7E+08 1.9E+08 1.9E+08 1.7E+08 Date 17-Feb 17-Feb 17-Feb 17-Feb 17-Feb Chip 6 0.0E+00 1.8E+08 1.6E+08 2.0E+08 1.9E+08 Time 14:38:56 15:57:28 16:09:44 16:22:29 16:35:45 Chip 1 0.0E+00 2.4E+08 2.2E+08 2.6E+08 2.5E+08 Condition Cycle VDD Temp 200ns 1.425 25°C 200ns 1.425 25°C 200ns 1.500 25°C 200ns 1.575 25°C 200ns 1.425 25°C Fluence SEU (n/cm²) Chip 2 Chip 3 Chip 4 Chip 5 0.0E+00 0.0E+00 0.0E+00 0.0E+00 2.2E+08 2.4E+08 2.4E+08 2.1E+08 2.0E+08 2.2E+08 2.2E+08 2.0E+08 2.3E+08 2.5E+08 2.5E+08 2.3E+08 2.3E+08 2.5E+08 2.5E+08 2.3E+08 Number of SEFI Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Chip 6 0 0 0 0 0 0 14 10 10 13 12 17 20 9 16 18 15 14 14 18 13 15 16 13 16 11 16 11 20 18 Chip 1 # 1045 1723 979 1173 FIT (SEFI/10^9hour/chip) Chip 2 Chip 3 Chip 4 Chip 5 # # # # 825 754 984 1003 856 1391 1571 1446 1390 918 1064 1253 890 1184 817 1640 Number of SEU Chip 2 Chip 3 Chip 4 Chip 5 0 0 0 0 101 167 130 135 127 126 136 111 137 151 148 127 147 195 136 125 Chip 1 # 9053 10614 7978 9417 FIT (SEU/10^9hour/chip) Chip 2 Chip 3 Chip 4 Chip 5 # # # # 6514 9847 7696 8824 8860 8037 8709 7848 8266 8329 8196 7766 8938 10841 7591 7704 Chip 1 0 155 168 146 171 Chip 6 0 168 157 142 153 Comments Chip 6 # stability check 1299 1234 931 1350 consistency check Comments Chip 6 # stability check 10040 10149 7939 8621 consistency check This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 99 Chip 6 0.0E+00 2.3E+08 2.2E+08 2.5E+08 2.5E+08 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR XC3S1000 Run # Device 1 2 3 4 5 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 Run # 1 2 3 4 5 Run # 1 2 3 4 5 Run # 1 2 3 4 5 Chip 1 0.0E+00 7.8E+08 8.5E+08 8.4E+08 4.4E+08 Energy (MeV) LANSCE LANSCE LANSCE LANSCE LANSCE Start Date 17-Feb 17-Feb 17-Feb 17-Feb 17-Feb Stop Time 17:16:20 17:25:56 17:52:36 19:41:23 20:08:11 Fluence SEFI (n/cm²) Chip 2 Chip 3 Chip 4 Chip 5 0.0E+00 0.0E+00 0.0E+00 0.0E+00 7.4E+08 6.7E+08 7.0E+08 7.7E+08 8.1E+08 7.3E+08 7.7E+08 8.5E+08 8.0E+08 7.2E+08 7.5E+08 8.3E+08 4.2E+08 3.8E+08 4.0E+08 4.4E+08 Number of SEFI Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Chip 6 0 0 0 0 0 0 21 14 13 10 29 13 20 20 21 9 27 23 26 21 14 17 18 12 13 15 6 11 18 14 Number of SEU Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Chip 6 0 0 0 0 0 0 96 73 52 70 95 97 87 67 71 47 81 90 89 59 54 78 77 75 104 100 82 93 104 95 Date 17-Feb 17-Feb 17-Feb 17-Feb 17-Feb Chip 6 0.0E+00 8.1E+08 8.9E+08 8.7E+08 4.6E+08 Time 17:25:22 17:51:15 19:40:45 20:07:31 20:23:55 Chip 1 0.0E+00 8.4E+08 9.3E+08 9.1E+08 4.9E+08 Condition Cycle VDD Temp 200ns 1.140 25°C 200ns 1.140 25°C 200ns 1.200 25°C 200ns 1.260 25°C 200ns 1.140 25°C Fluence SEU (n/cm²) Chip 2 Chip 3 Chip 4 Chip 5 0.0E+00 0.0E+00 0.0E+00 0.0E+00 8.0E+08 7.2E+08 7.5E+08 8.3E+08 8.9E+08 8.0E+08 8.3E+08 9.2E+08 8.7E+08 7.8E+08 8.1E+08 9.0E+08 4.7E+08 4.2E+08 4.4E+08 4.9E+08 Chip 6 0.0E+00 8.7E+08 9.6E+08 9.4E+08 5.1E+08 Chip 1 # 378 328 435 411 FIT (SEFI/10^9hour/chip) Chip 2 Chip 3 Chip 4 Chip 5 # # # # 264 273 201 527 344 401 165 447 368 273 317 304 497 221 388 574 Comments Chip 6 # stability check 225 363 193 426 consistency check Chip 1 # 1598 1311 1371 2971 FIT (SEU/10^9hour/chip) Chip 2 Chip 3 Chip 4 Chip 5 # # # # 1276 1009 1300 1597 1060 1246 790 1232 954 969 1341 1198 2999 2729 2965 3000 Comments Chip 6 # stability check 1556 1307 1113 2616 consistency check This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 100 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR EP1C20 Run # Device 1 2 3 4 5 EP1C20 EP1C20 EP1C20 EP1C20 EP1C20 Run # 1 2 3 4 5 Run # 1 2 3 4 5 Chip 1 0.0E+00 6.4E+08 4.9E+08 6.2E+08 6.2E+08 Energy (MeV) LANSCE LANSCE LANSCE LANSCE LANSCE Start Date 17-Feb 17-Feb 17-Feb 17-Feb 17-Feb Stop Time 20:58:26 21:09:30 21:49:43 22:04:36 22:22:38 Date 17-Feb 17-Feb 17-Feb 17-Feb 17-Feb Fluence SEFI (n/cm²) Chip 2 Chip 3 Chip 4 Chip 5 0.0E+00 0.0E+00 0.0E+00 0.0E+00 5.9E+08 5.5E+08 6.2E+08 6.7E+08 4.5E+08 4.2E+08 4.7E+08 5.1E+08 5.7E+08 5.3E+08 5.9E+08 6.5E+08 5.6E+08 5.3E+08 5.9E+08 6.5E+08 Number of SEFI Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Chip 6 0 0 0 0 0 0 24 17 10 14 28 14 17 16 6 16 27 22 19 21 21 17 11 19 29 11 21 28 23 22 Time 21:08:40 21:27:50 22:03:20 22:21:21 22:39:26 Condition Cycle VDD Temp 200ns 1.425 25°C 200ns 1.425 25°C 200ns 1.500 25°C 200ns 1.575 25°C 200ns 1.425 25°C Chip 6 0.0E+00 6.9E+08 5.2E+08 6.6E+08 6.6E+08 Chip 1 # 522 488 430 656 FIT (SEFI/10^9hour/chip) Chip 2 Chip 3 Chip 4 Chip 5 # # # # 405 254 317 581 503 201 478 740 520 555 400 237 273 555 659 497 Comments Chip 6 # stability check 285 592 403 467 consistency check This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 101 THE CHIP PROTECTOR A.3 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances Alpha AX1000 Run # Device Particle 1 21 22 31 32 41 42 51 52 AX1000 AX1000 AX1000 AX1000 AX1000 AX1000 AX1000 AX1000 AX1000 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 Run # 1 21 22 31 32 41 42 51 52 Fluence (α/cm²) Chip 1 Chip 2 0.0E+00 0.0E+00 1.4E+08 1.4E+08 1.4E+08 1.4E+08 1.4E+08 1.4E+08 1.4E+08 1.4E+08 Start Date 9-Apr 9-Apr 12-Apr 10-Apr 13-Apr 10-Apr 14-Apr 11-Apr 14-Apr Time 10:22:02 10:50:02 19:45:04 2:53:03 11:48:04 18:56:03 3:51:04 10:59:03 19:54:05 Stop Date 9-Apr 10-Apr 13-Apr 10-Apr 14-Apr 11-Apr 14-Apr 12-Apr 15-Apr Number of FIT SEFI SEFI Chip 1 Chip 2 Chip 1 Chip 2 0 0 # # 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Time 10:34:02 2:50:01 11:45:03 18:53:02 3:48:03 10:56:02 19:51:03 2:59:03 11:54:04 Condition Cycle VDD Temp 200ns 1.4 25°C 200ns 1.4 25°C 200ns 1.4 25°C 200ns 1.5 25°C 200ns 1.5 25°C 200ns 1.6 25°C 200ns 1.6 25°C 200ns 1.4 25°C 200ns 1.4 25°C Comments stability check consistency check consistency check APA1000 Run # Device 21 22 APA1000 APA1000 Run # 21 22 Particle Date α−Am241 27-Apr α−Am241 30-Apr Start Time 17:00:00 17:00:00 Stop Date 30-Apr 3-May Time 9:00:00 9:00:00 Condition Cycle VDD Temp n/a n/a n/a n/a n/a n/a Number of FIT SEFI SEFI Comments Chip 1 Chip 2 Chip 1 Chip 2 Chip 1 Chip 2 5.7E+08 0 0 # 5.7E+08 0 # 0 Fluence (α/cm²) This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 102 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances THE CHIP PROTECTOR XC2V3000 Run # Device Particle 1 21 22 31 32 41 42 51 52 XC2V3000 XC2V3000 XC2V3000 XC2V3000 XC2V3000 XC2V3000 XC2V3000 XC2V3000 XC2V3000 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 Run # 1 21 22 31 32 41 42 51 52 Start Date 8-Oct 8-Oct 9-Oct 8-Oct 10-Oct 9-Oct 10-Oct 9-Oct 10-Oct Fluence SEU Number of SEU (α/cm²) Chip 1 Chip 2 Chip 1 Chip 2 0.0E+00 0.0E+00 0 0 2.3E+05 230 2.3E+05 250 2.3E+05 233 2.3E+05 218 2.3E+05 222 2.3E+05 227 2.3E+05 251 2.3E+05 251 Stop Time 12:02:15 19:16:10 11:46:14 22:19:11 12:11:21 1:22:11 15:14:22 4:25:12 18:17:23 Date 8-Oct 8-Oct 9-Oct 9-Oct 10-Oct 9-Oct 10-Oct 9-Oct 10-Oct Time 14:31:15 22:17:06 14:47:10 1:20:07 15:12:17 4:23:07 18:15:18 7:26:08 21:18:20 Condition Cycle VDD Temp 200ns 1.43 25°C 200ns 1.43 25°C 200ns 1.43 25°C 200ns 1.50 25°C 200ns 1.50 25°C 200ns 1.58 25°C 200ns 1.58 25°C 200ns 1.43 25°C 200ns 1.43 25°C FIT SEU Comments Chip 1 Chip 2 # # stability check 1015 # # 1103 1028 # # 962 980 # # 1002 1108 # consistency check # 1108 consistency check This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 103 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC3S1000 Run # Device Particle 1 24 25 26 34 35 36 44 45 46 54 55 56 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 XC3S1000 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 Run # 1 24 25 26 34 35 36 44 45 46 54 55 56 Start Date 9-Apr 9-Apr 10-Apr 11-Apr 9-Apr 10-Apr 11-Apr 10-Apr 11-Apr 12-Apr 10-Apr 11-Apr 12-Apr Time 11:28:01 12:13:02 12:30:02 12:55:03 18:16:02 18:33:02 18:58:02 0:19:02 0:36:03 1:01:03 6:22:02 6:39:02 7:04:03 Stop Date 9-Apr 9-Apr 10-Apr 11-Apr 10-Apr 11-Apr 12-Apr 10-Apr 11-Apr 12-Apr 10-Apr 11-Apr 12-Apr Time 11:38:02 18:13:01 18:30:02 18:55:03 0:16:02 0:33:02 0:58:02 6:19:01 6:36:02 7:01:02 12:22:02 12:39:02 13:04:02 Condition Cycle VDD Temp 200ns 1.14 25°C 200ns 1.14 25°C 200ns 1.14 25°C 200ns 1.14 25°C 200ns 1.20 25°C 200ns 1.20 25°C 200ns 1.20 25°C 200ns 1.26 25°C 200ns 1.26 25°C 200ns 1.26 25°C 200ns 1.14 25°C 200ns 1.14 25°C 200ns 1.14 25°C Number of SEFI FIT SEFI Fluence SEFI (α/cm²) Comments Chip 1 Chip 2 Chip 3 Chip 1 Chip 2 Chip 3 Chip 1 Chip 2 Chip 3 0.0E+00 0.0E+00 0.0E+00 0 0 0 # # # stability check 0.0E+00 131 307 # # 0.0E+00 112 # 262 # 0.0E+00 119 # # 279 0.0E+00 112 262 # # 0.0E+00 97 # 226 # 0.0E+00 96 # # 320 0.0E+00 111 259 # # 0.0E+00 98 # 229 # 0.0E+00 107 # # 250 0.0E+00 104 243 # # consistency check 0.0E+00 114 # 266 # consistency check 0.0E+00 114 # # 266 consistency check This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 104 THE CHIP PROTECTOR Run # 1 24 25 26 34 35 36 44 45 46 54 55 56 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances Fluence SEU (α/cm²) Number of SEU FIT SEU Chip 1 Chip 2 Chip 3 Chip 1 Chip 2 Chip 3 Chip 1 Chip 2 0.0E+00 0.0E+00 0.0E+00 0 0 0 # # 4.3E+05 712 # 307 4.3E+05 # 775 335 4.3E+05 # # 629 4.3E+05 618 # 267 4.3E+05 # 708 307 3.0E+05 # # 445 4.3E+05 594 # 257 4.3E+05 # 690 299 4.3E+05 # # 597 4.3E+05 647 # 280 4.3E+05 # 853 369 4.3E+05 # # 650 Comments Chip 3 # stability check # # 1457 # # 1468 # # 1380 # consistency check # consistency check 1503 consistency check EP1C20 Run # Device Particle 1 21 22 31 32 41 42 51 52 EP1C20 EP1C20 EP1C20 EP1C20 EP1C20 EP1C20 EP1C20 EP1C20 EP1C20 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 α−Am241 Run # 1 21 22 31 32 41 42 51 52 Start Date 13-Oct 13-Oct 14-Oct 13-Oct 14-Oct 14-Oct 15-Oct 14-Oct 15-Oct Time 14:53:38 16:11:06 17:01:12 22:04:07 23:04:14 4:07:08 5:07:16 10:10:11 11:10:18 Stop Date 13-Oct 13-Oct 14-Oct 14-Oct 15-Oct 14-Oct 15-Oct 14-Oct 15-Oct Fluence SEFI Number of SEFI FIT SEFI (α/cm²) Chip 1 Chip 2 Chip 1 Chip 2 Chip 1 Chip 2 0.0E+00 0.0E+00 0 0 # # 4.4E+05 53 121 # 4.5E+05 56 # 124 4.5E+05 38 84 # 4.5E+05 47 # 104 4.5E+05 24 53 # 4.5E+05 31 # 69 4.5E+05 54 120 # 4.5E+05 56 # 124 Time 15:04:27 22:01:04 23:01:10 4:04:06 5:04:12 10:07:07 11:07:14 16:10:09 17:10:15 Condition Cycle VDD Temp 200ns 1.425 25°C 200ns 1.425 25°C 200ns 1.425 25°C 200ns 1.500 25°C 200ns 1.500 25°C 200ns 1.575 25°C 200ns 1.575 25°C 200ns 1.425 25°C 200ns 1.425 25°C Comments stability check consistency check consistency check This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 105 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances B 95% confidence intervals Let x be a single observation from a Poisson distribution with mean µ. Then 95% confidence limits for µ are given by the formula: ( CHIINV(0.975, 2*x))/2, CHIINV(0.025, 2*(x+1))/2 ) Where CHIINV returns the inverse of the one-tailed probability of the chi-squared distribution. x 0 1 2 3 4 5 6 7 8 9 10 20 50 100 95% limits Lower limit Upper limit 0.0 3.7 0.0 5.6 0.2 7.2 0.6 8.8 1.1 10.2 1.6 11.7 2.2 13.1 2.8 14.4 3.5 15.8 4.1 17.1 4.8 18.4 12.2 30.9 37.1 65.9 81.4 121.6 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 106 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances C Geometry factor calculation for alpha tests This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 107 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 108 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 109 THE CHIP PROTECTOR GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances D Test board layout D.1 AX1000 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 110 THE CHIP PROTECTOR D.2 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances APA1000 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 111 THE CHIP PROTECTOR D.3 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC2V3000 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 112 THE CHIP PROTECTOR D.4 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances XC3S1000 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 113 THE CHIP PROTECTOR D.5 GRE_2_ACTEL_SERTEST_DEC_03_ENG_TR_008 Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances EP1C20 This document is an iRoC Technologies document © copyright 2004 – The information it contains may change without notice. iRoC Technologies Confidentiality level – Release date: Apr-04 114