DS0130: RTG4 FPGA Pin Descriptions

DS0130
Revision 3
RTG4 FPGA Pin Descriptions
User I/Os
The RTG4™ field programmable gate array (FPGA) devices have different types of I/O structures that
support a range of mixed voltages (1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V) through I/O bank selection. The
MSIO and MSIOD can be configured as differential I/Os or single-ended I/Os. The DDRIOs do not
support true differential outputs. All these I/Os use one pin to implement single-ended standards and two
pins for differential standards.
For functional block diagrams of MSIO, MSIOD, and DDRIO, refer to the UG0574: RTG4 FPGA Fabric
User Guide.
Bank Location Diagrams
I/Os are grouped based on the I/O voltage standard. The grouped I/Os of each voltage standard form an
I/O bank. Each I/O bank has dedicated I/O supply and ground voltages. Therefore, only buffer types with
compatible standards can be assigned to the same I/O voltage bank.
Figure 1 shows the bank locations of RT4G150-CG1657.
Bank‐3
JTAG
North
Bank‐7
MSIOD (72)
Bank‐8
MSIOD (78)
Bank‐4
MSIO (72)
Bank‐5
MSIO (96)
Bank‐6
MSIO (72)
A1
Bank‐2
MSIOD (72)
RTG4 FPGA
RT4G150 ‐ CG1657
West
Bank‐9
DDRIO (90)
FDDR_W
East
Bank‐1
MSIOD (78)
Bank‐0
DDRIO (90)
FDDR_E
South
SERDES_PCIE_5
SERDES_4
SERDES_3
SERDES_2
SERDES_1
SERDES_PCIE_0
Figure 1 • RT4G150-CG1657 I/O Bank Locations
May 2016
© 2016 Microsemi Corporation
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RTG4 FPGA Pin Descriptions
Table 1 describes the types of multi-standard I/Os.
Table 1 • Multi-Standard I/O Types
Name
Type
Description
In/Out
MSIOs provide programmable drive strength, weak pull-up, and weak-pull-down.
In single-ended mode, the I/O pair operates as two separate I/Os named P and N (described
in the y field of the naming convention). The RTG4 MSIO include ESD protection. MSIO I/O
cells operate at up to 3.3 V and are capable of LVDS operation. MSIOs do not support a user
programmable slew rate.
MSIODxyBz In/Out
Similar to MSIO, but operates only up to 2.5 V, and adds pre-emphasis, to achieve higher
speeds. MSIODs provide programmable drive strength, weak pull-up, and weak pull-down.
MSIOD I/Os are capable of high-speed LVDS2V5 operation and include ESD protection.
MSIODs do not support a user programmable slew rate and have pre-emphasis on the
differential output.
DDRIOxyBz In/Out
The double data rate input output (DDRIO) is a multi-standard I/O optimized for
LPDDR/DDR/DDR2/DDR3 performance. These I/Os also operate up to 2.5 V like MSIOD.
They have ESD protection. If the FDDR interface block is utilized, the Libero® System-onChip (SoC) software automatically connects the FDDR signals to the DDRIOs. Depending on
the memory configuration, Libero uses the required DDRIOs. Unused DDRIOs are available
to access the FPGA fabric. DDRIOs support programmable slew control on the nondifferential drive outputs.
MSIOxyBz
For information about hot-swap and cold-spare applications, refer to the UG0574: RTG4 FPGA Fabric
User Guide.
For information about I/O utilization of the RTG4 device corresponding to the supported DDR bus widths,
refer to "I/O Utilization for RTG4 Devices" table of the UG0573: RTG4 FPGA High Speed DDR Interfaces
User Guide.
Supported I/O Standards
Table 2 shows the supported voltage standards for various I/O types.
Table 2 • Supported I/O Standards
Single-ended
Differential
MSIO
(Max 3.3 V)
MSIOD
(Max 2.5 V)
DDRIO
(Max 2.5 V)
LVTTL
Yes
–
Yes
–
–
PCI
Yes
–
Yes
–
–
LVPECL (input only)
–
Yes
Yes
–
–
LVDS33
–
Yes
Yes
–
–
LVCMOS33
Yes
–
Yes
–
–
LVCMOS25
Yes
–
Yes
Yes
Yes
LVCMOS18
Yes
–
Yes
Yes
Yes
LVCMOS15
Yes
–
Yes
Yes
Yes
LVCMOS12
Yes
–
Yes
Yes
Yes
SSTL2I
Yes
Yes
Yes
Yes
Yes (DDR1)
SSTL2II
Yes
Yes
Yes
–
Yes (DDR1)
SSTL18I
Yes
Yes
–
–
Yes (DDR2)
SSTL18II
Yes
Yes
–
–
Yes (DDR2)
I/O Standards
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Revision 3
RTG4 FPGA Pin Descriptions
Table 2 • Supported I/O Standards (continued)
Single-ended
Differential
MSIO
(Max 3.3 V)
MSIOD
(Max 2.5 V)
DDRIO
(Max 2.5 V)
SSTL15I (only for I/Os
used by MDDR/FDDR)
Yes
Yes
–
–
Yes (DDR3)
SSTL15II (only for I/Os
used by MDDR/FDDR)
Yes
Yes
–
–
Yes (DDR3)
HSTLI
Yes
Yes
–
–
Yes
HSTLII
Yes
Yes
–
–
Yes
LVDS
–
Yes
Yes
Yes
–
RSDS
–
Yes
Yes
Yes
–
Mini LVDS
–
Yes
Yes
Yes
–
BUSLVDS
–
Yes
Yes
Yes (input only)
–
MLVDS
–
Yes
Yes
Yes (input only)
–
SUBLVDS (output only)
–
Yes
Yes
Yes
–
I/O Standards
Naming Convention
User I/O Naming Convention
The naming convention used for FPGA user I/O is IOxyBz, where:
•
IO: Type of I/O—MSIO, MSIOD, or DDRIO.
•
x: I/O pair number in bank z.
•
y: P (positive) or N (negative).
In single-ended mode, the I/O pair operates as two separate I/Os named P and N. Differential
mode is implemented with a fixed I/O pair and cannot be split with an adjacent I/O.
•
B: Bank.
•
z: Bank number (0-9 for RT4G150-CG1657).
Differential I/O standards are implemented as true differential outputs and complementary single-ended
outputs for stub series terminated logic (SSTL) or high speed transceiver logic (HSTL). In single-ended
mode, the I/O pair operates as two separate I/Os named P and N. All the configurations and data
inputs/outputs are different and use names ending with P and N to differentiate between the two I/Os.
For more information about I/Os, refer to the I/Os chapter of the UG0574: RTG4 FPGA Fabric User
Guide.
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RTG4 FPGA Pin Descriptions
Dedicated Global I/O Naming Convention
Dedicated global I/Os are dual-use I/Os, which can drive the global blocks directly or through clock
conditioning circuits (CCC). They can also be used as regular user I/Os. These global I/Os are the
primary source to bring external clock inputs into the RTG4 device. Unused global pins are configured as
inputs with pull-up resistors by the Libero software.
The RTG4 devices have 36 I/Os which are dedicated for global clocks. Out of these 36 global clocks, 12
are dedicated for SERDES clocks.
Dedicated global I/Os that drive the global blocks (GB) directly are named as GBx, where x is 0 to 23.
Dedicated global I/Os that drive GBs through CCCs are named CCC_xyz_CLKlw, where:
•
xy: Individual CCC block located at specific chip corner NE, SE, SW, or NW.
•
z: CCC number (0 or 1) for the corresponding corner (NE, SE, SW, or NW) of the RTG4 device.
•
I: Input clock.
•
w: Four dedicated global inputs (0, 1, 2, or 3) of the associated CCC_xyz_CLKI.
The behavior of the unused dedicated global I/Os and the unused regular user I/Os (MSIO, MSIOD, and
DDRIO) is the same.
Libero tool configures unused user I/Os as input buffer disabled and output buffer tristated with weak
pull-up.
For more information on Global I/Os, refer to the "Fabric Global Routing Resources" chapter of the
UG0586: RTG4 FPGA Clocking Resources User Guide.
GRESET generates a global asynchronous reset signal during power-up / programming, and allows the
user to apply an asynchronous reset on the fabric flip-flops globally if required. For more information on
GREST, refer to the UG0574: RTG4 FPGA Fabric User Guide.
Fabric DDR Interface
The RTG4 devices have two FDDR blocks. The FDDR subsystem is a hardened ASIC block for
interfacing the LPDDR1, DDR2, and DDR3 memories. It supports 8/16/32-bit data bus width modes. The
DDRIO uses fixed impedance calibration for different drive strengths. These values can be programmed
using Libero SoC software for the selected I/O standard. The values are fed to the pull-up/pull-down
reference network to match the impedance with an external resistor. For more information about
reference resistor values (for different drive modes), refer to the UG0574: RTG4 FPGA Fabric User
Guide.
FDDR Controller Pins
Table 3 shows the FDDR Controller pins.
Table 3 • FDDR Controller Pins
Pin Name
Type
Reference Resistor ()
FDDR_x_CAS_N
Out
DRAM CASN.
FDDR_x_CKE
Out
DRAM CKE.
FDDR_x_CLK
Out
DRAM single-ended clock for differential pads.
FDDR_x_CLK_N
Out
DRAM single-ended clock for differential pads.
FDDR_x_CS_N
Out
DRAM CSN.
FDDR_x_ODT
Out
DRAM on-die termination (ODT).
0: Termination Off
1: Termination On
Note: Though calibration is not required, it is recommended to use the corresponding resistor placeholder to
connect the FDDR_x_IMP_CALIB to the ground with or without a resistor.
x represents East or West.
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RTG4 FPGA Pin Descriptions
Table 3 • FDDR Controller Pins (continued)
Pin Name
Type
Reference Resistor ()
FDDR_x_RAS_N
Out
DRAM RASN.
FDDR_x_RESET_N
Out
DRAM reset for DDR3.
FDDR_x_WE_N
Out
DRAM WEN.
FDDR_x_ADDR[15:0]
Out
DRAM address bits.
FDDR_x_BA[2:0]
Out
DRAM bank address.
FDDR_x_DM_RDQS[3:0]
In/out DRAM data mask from bidirectional pads.
FDDR_x_DQS[3:0]
In/out DRAM single-ended data strobe output for bidirectional pads.
FDDR_x_DQS[3:0]_N
In/out DRAM single-ended data strobe output for bidirectional pads.
FDDR_x_DQ[31:0]
In/out DRAM data input or output for bidirectional pads.
FDDR_x_DQ_ECC[3:0]
In/out DRAM data input or output for SECDED.
FDDR_x_DM_RDQS_ECC
In/out DRAM single-ended data strobe output for bidirectional pads.
FDDR_x_DQS_ECC
In/out DRAM single-ended data strobe output for bidirectional pads.
FDDR_x_DQS_ECC_N
In/out DRAM data input or output for bidirectional pads.
FDDR_x_TMATCH_[0/1]_IN
In
DQS enable input for timing match between DQS and system clock.
For simulations, tie to FDDR_x_TMATCH_[0/1]_OUT.
FDDR_x_TMATCH_[0/1]_OUT
Out
DQS enable output for timing match between DQS and system clock.
For simulations, tie to FDDR_x_TMATCH_[0/1]_IN.
FDDR_x_TMATCH_ECC_[IN]
In
DQS enable input for timing match between DQS and system clock.
For simulations, tie to FDDR_x_TMATCH_ECC_[OUT].
FDDR_x_TMATCH_ECC_[OUT]
Out
DQS enable output for timing match between DQS and system clock.
For simulations, tie to FDDR_x_TMATCH_ECC_[IN].
FDDR_x_IMP_CALIB
Ref
Pull-down with resistor depending on voltage/standard:
• DDR2 - 150 
•
DDR3 (1.5 V) - 240 
•
LPDDR - 150 
Here, x represents East or West.
FDDR_x_RESERVED
—
For FDDR0, the reserved pin (bank0) is AK35.
For FDDR1, the reserved pin (bank9) is AK7.
FDDR_x_RESERVED_8_16
—
In 18-bit, 16-bit, 9-bit, 8-bit DDR bus width modes, five additional pins
are reserved.
For FDDR0 the reserved pins (bank0) are AK35, AJ31, AK32, AK33,
AL35.
For FDDR1 the reserved pins (bank9) are AK7, J11, AK9, AK10, AL7.
Note: Though calibration is not required, it is recommended to use the corresponding resistor placeholder to
connect the FDDR_x_IMP_CALIB to the ground with or without a resistor.
x represents East or West.
For more information about FDDR memory configurations, refer to the UG0573: RTG4 FPGA High
Speed DDR Interfaces User Guide.
If FDDR is not used, the Libero SoC v11.7 software connects the unused FDDR blocks by adding CFG0
instances and nets to user netlist. You cannot use AL2, AE1, AE41, and AL40 pins with OUT_REG or
EN_REG macros.
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RTG4 FPGA Pin Descriptions
I/O Standards
Table 4 shows the supported I/O standards for different DDR memories.
Table 4 • Supported I/O Standards for Different DDR Memories
Memory Type
I/O Standard
DDR3
SSTL15I, SSTL15II
DDR2
SSTL18I, SSTL18II
LPDDR
LVCMOS18
SpaceWire Interface
SpaceWire is a standard for high-speed point-to-point data links with the following characteristics:
•
Operation between 2 Mbps and 400 Mbps.
•
Capable of full duplex operation.
In the RTG4 device, only the receiving Clock Recovery blocks are implemented in silicon (in the CCC
block). The rest of the SpaceWire IP can be acquired from third-party vendors and implemented as soft
IP in the FPGA fabric. Each CCC block has two Clock and Data Recovery blocks.
The SpaceWire clocks are generated from external Data and Strobe I/O pins.
Table 5 describes the SpaceWire pins.
Table 5 • SpaceWire Pins
Pin Name
Description
SPWR_xyz_w_RX_STROBE_[P/N] Differential Input Strobe signal from I/O pad.
SPWR_xyz_w_RX_DATA_[P/N]
Differential Input Data signal from I/O pad.
Notes:
1. xy represents individual SpaceWire block located at specific chip corner—NE, SE, SW, or NW.
2. z is CCC number of either 0 or 1 for the corresponding corner of the RTG4 chip.
3. w refers to one of the two possible input pins associated with SPWR_xyz_[0,1].
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Revision 3
RTG4 FPGA Pin Descriptions
Supply Pins
The RTG4 device supports MSIOs, MSIODs, DDRIOs, high speed serial interfaces, SpaceWire interface
and a debugging JTAG interface. It requires the power supplies listed in Table 6.
Table 6 • Supply Pins
Name
Operating Voltage
Description
VDD
1.2 V
DC core supply voltage. Must always power this pin.
VPP
3.3 V
Power supply for charge pumps (for normal operation and
programming). Must always power this pin.
VDDIx
1.2 V, 1.5 V, 1.8 V,
where x is the bank number 2.5 V, or 3.3 V
I/O bank supplies for MSIO, MSIOD and DDRIO banks.
For MSIO banks: 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V
For MSIOD banks: 1.2 V, 1.5 V, 1.8 V, 2.5 V
For DDRIO banks: 1.2 V, 1.5 V, 1.8 V, 2.5 V
For JTAG bank: 1.8 V, 2.5 V, or 3.3 V
To power-up the device, all I/O banks must be powered (to exit
from power-on-reset state).
There is no power-up sequence requirement between VDDI,
VPP, and VDD supplies.
VDDPLL
3.3 V
Power for Eight corner PLLs, PLLs in SERDES PCIe/PCS
blocks, and FDDR PLL.
When in use, the supply must be connected to a common PLL
supply (3.3 V) of the corresponding PLL return path (VSS) onboard through an RC filter.
When not in use, the supply must be directly connected to
3.3 V (without the filter circuit).
VREF0
0.5 * VDDI
VERF9
SERDES_x_Lyz_VDDAIO
Reference voltages must be powered with the appropriate bank
supplies through voltage divider circuitry. If I/O banks are used
as single-ended I/Os (and FDDR functionalities are not used),
VREF0, VREF9 can be left floating (DNC).
1.2 V
where,
•
x refers to 1, 2, 3, 4,
PCIE_0 or PCIE_5
•
yz refers to lanes 0 and
1, or lanes 2 and 3
Reference voltage for FDDR signals.
TX/RX analog I/O voltage for SERDES lanes. Low voltage
power for Lane-y and Lane-z of SERDES_x. All of the nominal
1.2 V power supply pins for the SERDES block such as
SERDES_x_Lyz_VDDAIO are driven from the same supply as
the FPGA core (VDD) supply.
If SERDES is not used, it must be connected to 1.2 V (VDD).
SERDES_x_Lyz_VDDAPLL 2.5 V
Analog power for SERDES lanes.
where,
•
x refers to 1, 2, 3, 4,
PCIE_0 or PCIE_5
If SERDES is used, all SERDES PLL pins must be connected to
the appropriate supply (2.5 V) of the corresponding return path
on-board (SERDES_x_Lyz_REFRET) through an RC filter.
•
yz refers to lanes 0 and
1, or lanes 2 and 3
If SERDES is not used, they must connect directly to 2.5 V or
1.2V without the RC filter circuit.
SERDES_x_Lyz_REFRET
where,
•
x refers to 1, 2, 3, 4,
PCIE_0 or PCIE_5
•
yz refers to lanes 0 and
1, or lanes 2 and 3
—
Local on-chip ground return path for SERDES lanes.
If SERDES is not used, it must be grounded (VSS).
Re vi s i o n 3
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RTG4 FPGA Pin Descriptions
Table 6 • Supply Pins (continued)
Name
Operating Voltage
SERDES_x_Lyz_REXT
—
where,
•
x refers to 1, 2, 3, 4,
PCIE_0 or PCIE_5
•
yz refers to lanes 0 and
1, or lanes 2 and 3
Description
External reference resistor (1.21 k) connected to calibrate
TX/RX termination value. Each SERDES_x consists of two
REXT signals—one for Lane0 and Lane1, and another for
Lane2 and Lane3.
If the SERDES is not used, it must remain floating (DNC).
SERDES_VDDI
1.8 V, 2.5 V, or 3.3 V
Power for SERDES reference clock receiver supply. The supply
voltage depends on SERDES reference clock source. Must
always power this pin.
SERDES_VREF
0.5 * SERDES_VDDI External differential receiver reference voltage for SERDES
Reference Clocks.
Reference voltage must be powered with the SERDES_VDDI
supply through voltage divider circuitry.
If SERDES reference clock uses an I/O reference standard
such as SSTL, HSTL on the board, SERDES_VREF must be
connected to SERDES_VDDI through a voltage divider circuit.
If SERDES is not used or SERDES reference clock uses a non
reference standard such as LVDS, LVCMOS, and LVTTL on the
board, SERDES_VREF must be connected to Ground through
a 1 k–10 k resistor.
VSS
Ground
Ground pad for core and I/Os. Always connect to ground.
JTAG Pins
JTAG pins can operate at 1.8 V / 2.5 V / 3.3 V (nominal).
Table 7 • JTAG Pin Names and Descriptions
Name
JTAG_TCK
Type
In
Description
Test clock.
Serial input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal
pull-up/pull-down resistor. Connect TCK to GND or +3.3 V through a resistor
(500–1 k placed close to the FPGA pin to prevents totem-pole current on the input buffer
and TMS from entering into an undesired state.
If JTAG is not used, connect it to GND.
JTAG_TDI
In
Test data in.
Serial input for JTAG boundary scan. There is an internal weak pull-up resistor on the TDI pin.
JTAG_TDO
Out
Test data out.
Serial output for JTAG boundary scan. The TDO pin does not have an internal
pull-up/pull-down resistor.
JTAG_TMS
In
Test mode select.
The TMS pin controls the use of the IEEE1532 boundary scan pins (TCK, TDI, TDO, and
TRST). There is an internal weak pull-up resistor on the TMS pin.
JTAG_TRSTB In
Test reset.
The TRSTB pin is an active low input. It asynchronously initializes (or resets) the boundary
scan circuitry. There is an internal weak pull-up resistor on the TRSTB pin.
To hold the JTAG in reset mode and prevent it from entering into undesired states in critical
applications, connect TRSTB to GND through a 1 k resistor (placed close to the FPGA pin).
8
Revision 3
RTG4 FPGA Pin Descriptions
Programming SPI
The system controller contains a dedicated SPI block for programming. The RTG4 SPI operates only in
SPI-slave mode. It communicates with a remote device that initiates download of the programming data
to the RTG4 device.
Table 8 • Programming SPI Interface
Name
Type
Description
SC_SPI_SS
In
SPI slave select
SC_SPI_SDO
Out
SPI data output
SC_SPI_SDI
In
SPI data input
SC_SPI_CLK
In
SPI clock
Note: If unused, SPI programming pins must be left floating.
SERDES I/Os
The SERDES I/Os available in the RTG4 device are dedicated for high speed serial communication
protocols. The SERDES I/Os support protocols such as PCIe Gen1, XAUI, serial giga-bit media
independent interface (SGMII), EPCS, serial rapid I/O (SRIO), and user-defined high speed serial
protocol implementations in the fabric.
Table 9 shows the SERDES I/O pins.
Table 9 • SERDES I/O Pins
Port Name
SERDES_x_RXDy_P/N
Type
In
SERDES differential positive/negative input.
Each SERDES interface consists of four receiving differential
RXD signals.
where,
•
x refers to 1, 2, 3, 4, PCIE_0 or PCIE_5
•
y refers to 0, 1, 2 or 3
SERDES_x_TXDy_P/N
Description
If SERDES is not used, it must be connected to VSS through
a 1 k–10 k resistor.
Out
SERDES differential positive/negative output.
•
x refers to 1, 2, 3, 4, PCIE_0 or PCIE_5
Each SERDES interface consists of four transmitting
differential TXD signals.
•
y refers to 0, 1, 2 or 3
If SERDES is not used, it must be floating (DNC).
where,
SERDES_x_REFCLK_P/N
where, x refers to 1, 2, 3, 4, PCIE_0 or
PCIE_5
Clock
Reference clock differential positive/negative.
If SERDES is not used, it must be connected to
SERDES_VDDI through a 10 kresistor.
Re vi s i o n 3
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RTG4 FPGA Pin Descriptions
Special Pins
Table 10 • Special Pins
Name
Type
DEVRST_N
In
Description
Device reset.
External active low input only signal. Powered by VPP.
Once asserted, DEVRST_n resets the system controller, starts up the
device, and drives GRESET. It is an asynchronous signal and Schmitt
trigger input with a pulse width requirement of at least 1 µs.
In unused condition, connect it to VPP through a 10 k pull-up resistor.
TEMP_MONITOR
In
PROBE_READ_DATA
An internal temperature sensing diode has a dedicated pin Temp_Monitor
connected to the anode. The cathode is connected to VSS of the die.
These I/Os allow the user to specify the flip-flop output signals for probing
using SmartDebug feature.
These pins can be used as user I/Os or probe I/Os.
PROBE_CAPTURE
In/Out
If probing is not used, the user can configure these I/Os as input, output, or
bidirectional I/Os. To perform live switching between user I/O and probing,
these I/Os must be configured only as outputs.
If configured as input for general purpose and then switched to probe
operation, the probe circuitry drives out onto these I/Os, and the I/Os may
get damaged.
If unused, it must be connected to ground through a 10 kresistor.
DNC
—
Do not connect.
This pin should not be connected to any signals on the PCB.
NC
—
No connect.
This pin is not connected to circuitry within the device. It can be driven to
any voltage or left floating with no effect on the operation of the device.
I/O Programmable Features
The RTG4 device supports different I/O programmable features for MSIO, MSIOD, and DDRIO.
Each I/O pair (P, N) supports the following programmable features:
•
Programmable drive strength
•
Programmable weak pull-up and pull-down
•
Configurable ODT and driver impedance
•
Programmable input delay
•
Programmable Schmitt input and receiver
For more information about RTG4 I/O programmable features, refer to the "RTG4 I/O Features" table of
the UG0574: RTG4 FPGA Fabric User Guide.
10
R ev i sio n 3
RTG4 FPGA Pin Descriptions
Packaging Information
CG1657
Figure 2 • CG1657 Package Drawing
For Package Manufacturing and Environmental information, visit the Resource Center at
Packaging Resource Center.
Pin Tables
The following devices are available in the CG1657 package:
•
RT4G150
Pin tables for the CG1657 package will be available soon.
R evis i o n 3
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RTG4 FPGA Pin Descriptions
List of Changes
The following table shows important changes made in this document for each revision.
Revision*
Revision 3
(May 2016)
Revision 2
(April 2015)
Revision 1
(November 2014)
Changes
Page
Updated "CG1657" by removing C1 pin (SAR 78574).
11
Updated "Dedicated Global I/O Naming Convention".
4
Updated "Fabric DDR Interface" (SAR 73567).
4
Updated Table 6 (SAR 75640).
7
Updated Table 10 (SAR 71145).
10
Updated "Bank Location Diagrams"
1
Added "Supported I/O Standards"
2
Updated "Dedicated Global I/O Naming Convention" (SAR 70427).
4
Updated "FDDR Controller Pins"
4
Updated "SpaceWire Interface"
6
Updated "Supply Pins" (SAR 66310).
7
Updated "JTAG Pins"
8
Updated "Programming SPI"
9
Updated "SERDES I/Os" (SAR 65805)
9
Updated "Special Pins"
10
Initial release.
N/A
Note: *The revision number is located in the part number after the hyphen. The part number is displayed at the bottom
of the last page of the document. The digits following the slash indicate the month and year of publication.
12
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RTG4 FPGA Pin Descriptions
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR).
They could require an approved export license prior to export from the United States. An export includes
release of product or disclosure of technology to a foreign national inside or outside the United States.
Safety Critical, Life Support, and High-Reliability Applications
Policy
The products described in this advance status document may not have completed the Microsemi
qualification process. Products may be amended or enhanced during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the responsibility of
each customer to ensure the fitness of any product (but especially a new product) for a particular
purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications.
Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating
to life-support applications. A reliability report covering all of the SoC Products Group’s products is
available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety
of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for
additional reliability information.
R evis i o n 3
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Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
E-mail: [email protected]
www.microsemi.com
© 2016 Microsemi Corporation. All
rights reserved. Microsemi and the
Microsemi logo are trademarks of
Microsemi Corporation. All other
trademarks and service marks are the
property of their respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of
its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the
application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have
been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any
performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all
performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not
rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to
independently determine suitability of any products and to test and verify the same. The information provided by Microsemi
hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely
with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP
rights, whether with regard to such information itself or anything described by such information. Information provided in this
document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
About Microsemi
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for
aerospace & defense, communications, data center and industrial markets. Products include high-performance and
radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products;
timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing
devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and
scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design
capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 4,800 employees
globally. Learn more at www.microsemi.com.
51700130-3/05.16
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