ISL97519A ® Data Sheet June 30, 2008 600kHz/1.2MHz PWM Step-Up Regulator Features The ISL97519A is a high frequency, high efficiency step-up voltage regulator operated at constant frequency PWM mode. With an internal 2.0A, 200mΩ MOSFET, it can deliver up to 1A output current at over 90% efficiency. Two selectable frequencies, 600kHz and 1.2MHz, allow trade offs between smaller components and faster transient response. An external compensation pin gives the user greater flexibility in setting frequency compensation allowing the use of low ESR Ceramic output capacitors. • >90% Efficiency When shut down, it draws <1µA of current and can operate down to 2.3V input supply. These features along with 1.2MHz switching frequency makes it an ideal device for portable equipment and TFT-LCD displays. The ISL97519A is available in an 8 Ld MSOP package with a maximum height of 1.1mm. The device is specified for operation over the full -40°C to +85°C temperature range. FN6683.2 • 2.0A, 200mΩ Power MOSFET • 2.3V to 5.5V Input • Up to 25V Output • 600kHz/1.2MHz Switching Frequency Selection • Adjustable Soft-Start • Internal Thermal Protection • 1.1mm Max Height 8 Ld MSOP Package • Pb-Free (RoHS compliant) • Halogen Free Applications • TFT-LCD displays • DSL modems Pinout • PCMCIA cards ISL97519A (8 LD MSOP) TOP VIEW • Digital cameras • GSM/CDMA phones COMP 1 8 SS FB 2 7 FSEL EN 3 6 VDD GND 4 5 LX • Portable equipment • Handheld devices Ordering Information PART NUMBER (Note) PART MARKING PACKAGE (Pb-Free) PKG. DWG. # ISL97519AIUZ 7519A 8 Ld MSOP MDP0043 ISL97519AIUZ-T* 7519A 8 Ld MSOP MDP0043 ISL97519AIUZ-TK* 7519A 8 Ld MSOP MDP0043 *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL97519A Absolute Maximum Ratings (TA = +25°C) Thermal Information LX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27V VDD to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V COMP, FB, EN, SS, FSEL to GND . . . . . . . . . -0.3V to (VDD +0.3V) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . See Curves on page 5 Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VIN = 3.3V, VOUT = 12V, IOUT = 0mA, FSEL = GND, TA = -40°C to +85°C unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 1 5 µA IQ1 Quiescent Current - Shutdown EN = 0V IQ2 Quiescent Current - Not Switching EN = VDD, FB = 1.3V 0.7 IQ3 Quiescent Current - Switching EN = VDD, FB = 1.0V 3 4.5 mA VFB Feedback Voltage 1.24 1.252 V IB-FB Feedback Input Bias Current 0.01 0.5 µA VDD Input Voltage Range 5.5 V DMAX-600kHz Maximum Duty Cycle FSEL = 0V 85 92 % DMAX-1.2MHz Maximum Duty Cycle FSEL = VDD 85 90 % ILIM1 Current Limit - Max Peak Input Current VDD < 2.8V 1.0 A ILIM2 Current Limit - Max Peak Input Current VDD > 2.8V 2.0 A Shutdown Input Bias Current EN = 0V 0.01 rDS(ON) Switch ON-Resistance VDD = 2.7V, ILX = 1A 0.2 ILX-LEAK Switch Leakage Current VSW = 27V 0.01 ΔVOUT/ΔVIN Line Regulation 3V < VIN < 5.5V, VOUT = 12V 0.2 % ΔVOUT/ΔIOUT Load Regulation VIN = 3.3V, VOUT = 12V, IO = 30mA to 200mA 0.3 % FOSC1 Switching Frequency Accuracy FSEL = 0V 500 620 740 kHz FOSC2 Switching Frequency Accuracy FSEL = VDD 1000 1250 1500 kHz 0.5 V IEN VIL EN, FSEL Input Low Level VIH EN, FSEL Input High Level GM Error Amp Tranconductance VDD-ON 1.228 2.3 1.5 mA 0.5 Ω 3 1.5 ΔI = 5µA VDD UVLO On Threshold µA µA V 70 130 150 1µ/Ω 1.95 2.1 2.25 V HYS VDD UVLO Hysteresis ISS Soft-Start Charge Current 2 3 4 µA VSS-en Minimum Soft-Start Enable Voltage 40 65 150 mV ILIM-VSS-en Current Limit Around SS Enable V 300 350 400 mA OTP Over-Temperature Protection 2 140 SS = 200mV 150 mV °C FN6683.2 June 30, 2008 ISL97519A Block Diagram EN FSEL REFERENCE GENERATOR VDD OSCILLATOR SS SHUTDOWN AND START-UP CONTROL LX PWM LOGIC CONTROLLER FET DRIVER COMPARATOR CURRENT SENSE GND FB GM AMPLIFIER COMP Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1 COMP Compensation pin. Output of the internal error amplifier. Capacitor and resistor from COMP pin to ground. 2 FB Voltage feedback pin. Internal reference is 1.24V nominal. Connect a resistor divider from VOUT. VOUT = 1.24V (1 + R1/R2). See “Typical Application Circuit” on page 3. 3 EN Shutdown control pin. Pull EN low to turn off the device. 4 GND 5 LX 6 VDD Analog power supply input pin. 7 FSEL Frequency select pin. When FSEL is set low, switching frequency is set to 620kHz. When connected to high or VDD, switching frequency is set to 1.25MHz. 8 SS Analog and power ground. Power switch pin. Connected to the drain of the internal power MOSFET. Soft-start control pin. Connect a capacitor to control the converter start-up. Typical Application Circuit 1 COMP R3 1kΩ OPEN C5 C5 4.7nF R1 R2 10kΩ 2 FB FSEL 7 3 EN VDD 6 4 GND S1 3 SS 8 85.2kΩ LX 5 C4 27nF C2 2.3V TO 5.5V + C1 0.1µF 22µF 10µH D1 + C3 12V 22µF FN6683.2 June 30, 2008 ISL97519A Typical Performance Curves 95 92 90 90 VIN = 3.3V, VO = 9V, fs = 620kHz 88 EFFICIENCY (%) EFFICIENCY (%) 85 VIN = 5V, VO = 12V, fs = 1.25 MHz 80 VIN = 5V, VO = 12V, fs = 620 kHz 75 VIN = 5V, VO = 9V, fs = 620 kHz 70 86 84 82 VIN = 3.3V, VO = 12V, fs = 620kHz VIN = 3.3V, VO = 12V, 80 fs = 1.25MHz 78 65 VIN = 5V, VO = 9V, fs = 1.25MHz 60 74 0 200 400 600 800 VIN = 3.3V, VO = 9V, fs = 1.25MHz 76 1000 0 100 200 300 400 500 IOUT (mA) IOUT (mA) FIGURE 1. BOOST EFFICIENCY vs IOUT FIGURE 2. BOOST EFFICIENCY vs IOUT 0.7 0.9 0.8 VIN = 5V, VO = 12V, VIN = 5V, VO = 9V, fs = 1.25MHz fs = 1.25MHz 0.6 VIN = 3.3V, VO = 12V, VIN = 3.3V, VO = 9V, fs = 1.25MHz fs = 1.25MHz 0.6 LOAD REGULATION (%) LOAD REGULATION (%) 0.7 VIN = 5V, VO = 9V, fs = 620kHz 0.5 0.4 0.3 0.2 fs = 620kHz 200 400 fs = 620kHz 0.3 0.2 VIN = 3.3, VO = 12V, fs = 620kHz 0 0 0 VIN = 3.3, VO = 9V, 0.4 0.1 VIN = 5V, VO = 12V, 0.1 0.5 600 800 1000 0 100 IOUT (mA) 200 300 400 500 IOUT (mA) FIGURE 3. LOAD REGULATION vs IOUT FIGURE 4. LOAD REGULATION vs IOUT 0.6 VO = 12V VO = 9V, IO = 80mA 0.5 IO = 50mA TO 300mA LINE REGULATION (%) fs = 1.25MHz 0.4 VO = 9V, IO = 100mA fs = 620kHz 0.3 VIN = 3.3V fs = 600kHz VO = 12V, IO = 80mA fs = 1.25MHz 0.2 0.1 0 VO = 12V, IO = 80mA fs = 620kHz -0.1 2 3 4 VIN (V) 5 FIGURE 5. LINE REGULATION vs VIN 4 6 FIGURE 6. TRANSIENT RESPONSE FN6683.2 June 30, 2008 ISL97519A Typical Performance Curves (Continued) IO = 50mA to 300mA VO = 12V VIN = 3.3V fs = 1.2MHz FIGURE 7. TRANSIENT RESPONSE FIGURE 8. SS DELAY AND LX DELAY DURING EN = VDD START- UP JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.6 1.0 POWER DISSIPATION (W) POWER DISSIPATION (W) 0.9 870mW 0.8 0.7 M θ SO JA = +1 P 8 15 °C /W 0.6 0.5 0.4 0.3 0.2 0.5 486mW 0.4 θ JA = 0.3 M SO +2 P8 06 °C /W 0.2 0.1 0.1 0.0 0 0 25 75 85 50 100 0 125 Applications Information 75 85 100 125 FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE the boost converter operates in two cycles. During the first cycle, as shown in Figure 12, the internal power FET turns on and the Schottky diode is reverse biased and cuts off the current flow to the output. The output current is supplied from the output capacitor. The voltage across the inductor is VIN and the inductor current ramps up in a rate of VIN/L, L is the inductance. The inductance is magnetized and energy is stored in the inductor. The change in inductor current is shown in Equation 1: The ISL97519A is a high frequency, high efficiency boost regulator operated at constant frequency PWM mode. The boost converter stores energy from an input voltage source and delivers it to a higher output voltage. The input voltage range is 2.3V to 5.5V and output voltage range is 5V to 25V. The switching frequency is selectable between 600kHz and 1.2MHz allowing smaller inductors and faster transient response. An external compensation pin gives the user greater flexibility in setting output transient response and tighter load regulation. The converter soft-start characteristic can also be controlled by external CSS capacitor. The EN pin allows the user to completely shutdown the device. D ΔT1 = -----------F SW Boost Converter Operations D = Duty Cycle Figure 11 shows a boost converter with all the key components. In steady state operating and continuous conduction mode where the inductor current is continuous, I OUT ΔV O = ---------------- × ΔT 1 C OUT 5 50 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) FIGURE 9. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 25 V IN ΔI L1 = ΔT1 × --------L (EQ. 1) FN6683.2 June 30, 2008 ISL97519A During the second cycle, the power FET turns off and the Schottky diode is forward biased, (see Figure 13). The energy stored in the inductor is pumped to the output supplying output current and charging the output capacitor. The Schottky diode side of the inductor is clamped to a Schottky diode above the output voltage. So the voltage drop across the inductor is VIN - VOUT. The change in inductor current during the second cycle is shown in Equation 2: L D VOUT VIN COUT CIN ISL97519A IL ΔIL2 ΔT2 ΔVO V IN – V OUT ΔI L = ΔT2 × -------------------------------L FIGURE 13. BOOST CONVERTER - CYCLE 2, POWER SWITCH OPEN 1–D ΔT2 = ------------F SW (EQ. 2) For stable operation, the same amount of energy stored in the inductor must be taken out. The change in inductor current during the two cycles must be the same as shown in Equation 3. ΔI1 + ΔI2 = 0 V IN 1 – D V IN – V OUT D ------------ × --------+ ------------- × -------------------------------- = 0 L F SW L F SW V OUT 1 ---------------- = ------------1–D V IN (EQ. 3) Output Voltage An external feedback resistor divider is required to divide the output voltage down to the nominal 1.24V reference voltage. The current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network less than 100k is recommended. The boost converter output voltage is determined by the relationship in Equation 4: R 1⎞ ⎛ V OUT = V FB × ⎜ 1 + -------⎟ R 2⎠ ⎝ (EQ. 4) The nominal VFB voltage is 1.24V. Inductor Selection L D VOUT VIN CIN COUT ISL97519A FIGURE 11. BOOST CONVERTER The inductor selection determines the output ripple voltage, transient response, output current capability, and efficiency. Its selection depends on the input voltage, output voltage, switching frequency, and maximum output current. For most applications, the inductance should be in the range of 2µH to 33µH. The inductor maximum DC current specification must be greater than the peak inductor current required by the regulator.The peak inductor current can be calculated in Equation 5: V IN × ( V OUT – V IN ) I OUT × V OUT I L ( PEAK ) = ------------------------------------ + 1 ⁄ 2 × ----------------------------------------------------V IN L × V OUT × FREQ (EQ. 5) L VOUT VIN CIN COUT ISL97519A IL ΔIL1 ΔT1 ΔVO FIGURE 12. BOOST CONVERTER - CYCLE 1, POWER SWITCH CLOSE 6 Output Capacitor Low ESR capacitors should be used to minimized the output voltage ripple. Multi-layer ceramic capacitors (X5R and X7R) are preferred for the output capacitors because of their lower ESR and small packages. Tantalum capacitors with higher ESR can also be used. The output ripple can be calculated as shown in Equation 6: I OUT × D ΔV O = --------------------------- + I OUT × ESR F SW × C O (EQ. 6) For noise sensitive application, a 0.1µF placed in parallel with the larger output capacitor is recommended to reduce the switching noise coupled from the LX switching node. FN6683.2 June 30, 2008 ISL97519A Schottky Diode The total soft-start time is calculated in Equation 7: In selecting the Schottky diode, the reverse break down voltage, forward current and forward voltage drop must be considered for optimum converter performance. The diode must be rated to handle 2.0A, the current limit of the ISL97519A. The breakdown voltage must exceed the maximum output voltage. Low forward voltage drop, low leakage current, and fast reverse recovery will help the converter to achieve the maximum efficiency. 5 Css × 0.6V t ss = ------------------------------ = Css × 2 × 10 3μA (EQ. 7) The full current is available after the soft-start period is finished. The soft-start capacitor should be selected to be big enough that it doesn't reach 0.6V before the output voltage reaches the final value. When the ISL97519A is disabled, the soft-start capacitor will be discharged to ground. Input Capacitor The value of the input capacitor depends the input and output voltages, the maximum output current, the inductor value and the noise allowed to put back on the input line. For most applications, a minimum 10µF is required. For applications that run close to the maximum output current limit, input capacitor in the range of 22µF to 47µF is recommended. The ISL97519A is powered from the VIN. A high frequency 0.1µF bypass capacitor is recommended to be close to the VIN pin to reduce supply line noise and ensure stable operation. Loop Compensation The ISL97519A incorporates a transconductance amplifier in its feedback path to allow the user some adjustment on the transient response and better regulation. The ISL97519A uses current mode control architecture which has a fast current sense loop and a slow voltage feedback loop. The fast current feedback loop does not require any compensation. The slow voltage loop must be compensated for stable operation. The compensation network is a series RC network from COMP pin to ground. The resistor sets the high frequency integrator gain for fast transient response and the capacitor sets the integrator zero to ensure loop stability. For most applications, the compensation resistor in the range of 0.5k to 7.5k and the compensation capacitor in the range of 3nF to 10nF. Frequency Selection The ISL97519A switching frequency can be user selected to operate at either constant 620kHz or 1.25MHz. Connecting FSEL pin to ground sets the PWM switching frequency to 620kHz. When connecting FSEL high or VDD, the switching frequency is set to 1.25MHz. Shutdown Control When the EN pin is pulled down, the ISL97519A is shutdown reducing the supply current to <1µA. Maximum Output Current The MOSFET current limit is nominally 2.0A and guaranteed 1.5A when VDD is greater than 2.8V. This restricts the maximum output current, IOMAX, based on Equation 8: I L = I L-AVG + ( 1 ⁄ 2 × ΔI L ) (EQ. 8) where: IL = MOSFET current limit IL-AVG = average inductor current ΔIL = inductor ripple current V IN × [ ( V O + V DIODE ) – V IN ] ΔI L = -----------------------------------------------------------------------------L × ( V O + V DIODE ) × F S (EQ. 9) VDIODE = Schottky diode forward voltage, typically, 0.6V FS = switching frequency, 600kHz or 1.2MHz Soft-Start During power-up, assuming EN is tied to VDD, as VDD rises above VDD UVLO, the SS capacitor begins to charge up with a constant 3µA current. During the time the part takes to rise to 60mV the boost will not be enabled. Depending on the value of the capacitor on the SS pin, this provides sufficient (540µs for a 27nf capacitor or 2ms for a 100nf capacitor) time for the passive in-rush current to settle down, allowing the output capacitors to be charged to a diode drop below VDD. I OUT I L-AVG = ------------1–D (EQ. 10) D = MOSFET turn-on ratio: V IN D = 1 – -------------------------------------------V OUT + V DIODE (EQ. 11) Table 1 gives typical maximum IOUT values for 1.2MHz switching frequency and 10µH inductor. After the SS pin passes above the threshold beyond which the part is enabled (60mV) the part begins to switch. The linearly rising SS voltage, at a charge rate proportional to 3µA, has a direct effect on the current limit allowing the current limit to linearly ramp-up to full current limit. SS voltage of 200mV corresponds to a current limit around 350mA and 0.6V corresponds to full current limit. 7 FN6683.2 June 30, 2008 ISL97519A DC PATH BLOCK APPLICATION TABLE 1. TYPICAL MAXIMUM IOUT VALUES VIN (V) VOUT (V) IOMAX (mA) 3.3 5 1150 3.3 9 655 3.3 12 500 5 9 990 5 12 750 TO INDUCTOR Cascaded MOSFET Application A 25V N-Channel MOSFET is integrated in the boost regulator. For applications where the output voltage is greater than 25V, an external cascaded MOSFET is needed as shown in Figure 14. The voltage rating of the external MOSFET should be greater than AVDD. AVDD VIN Note that there is a DC path in the boost converter from the input to the output through the inductor and diode. The input voltage will be seen at the output less a forward voltage drop of the diode before the part is enabled. If this direct connection is not desired, the following circuit can be inserted between input and inductor to disconnect the DC path when the part is disabled (see Figure 15). INPUT EN FIGURE 15. CIRCUIT TO DISCONNECT THE DC PATH OF BOOST CONVERTER LX FB INTERSIL ISL97519A FIGURE 14. CASCADED MOSFET TOPOLOGY FOR HIGH OUTPUT VOLTAGE APPLICATIONS 8 FN6683.2 June 30, 2008 ISL97519A Mini SO Package Family (MSOP) 0.25 M C A B D MINI SO PACKAGE FAMILY (N/2)+1 N E MDP0043 A E1 MILLIMETERS PIN #1 I.D. 1 B (N/2) e H C SEATING PLANE 0.10 C N LEADS SYMBOL MSOP8 MSOP10 TOLERANCE NOTES A 1.10 1.10 Max. - A1 0.10 0.10 ±0.05 - A2 0.86 0.86 ±0.09 - b 0.33 0.23 +0.07/-0.08 - c 0.18 0.18 ±0.05 - D 3.00 3.00 ±0.10 1, 3 E 4.90 4.90 ±0.15 - E1 3.00 3.00 ±0.10 2, 3 e 0.65 0.50 Basic - L 0.55 0.55 ±0.15 - L1 0.95 0.95 Basic - N 8 10 Reference - 0.08 M C A B b Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. L1 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. A 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c SEE DETAIL "X" A2 GAUGE PLANE L A1 0.25 3¬¨Ðó DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN6683.2 June 30, 2008