AN-1286: ADuCM350 Analog Front End Accuracy in a Noisy Digital Environment (Rev. 0) PDF

AN-1286
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
ADuCM350 Analog Front End Accuracy in a Noisy Digital Environment
INTRODUCTION
to support portable meters with display, USB communication
and active sensors. The ADuCM350 is available in a 120-pin,
8 mm × 8 mm CSP_BGA, and operates from −40 °C to +85°C.
The ADuCM350 is a complete, coin cell powered, high
precision, meter-on-chip for portable device applications,
such as point-of-care diagnostics and body-worn vital signs
monitoring devices.
The ADuCM350 is specifically designed for high precision
analysis of electrochemical reactions.
The ADuCM350 analog front end (AFE) features a 16-bit
precision, 160 kSPS ADC, 0.2% precision voltage reference,
12-bit no missing codes DAC, and a reconfigurable ultralow
leakage switch matrix. The ADuCM350 also includes a
Cortex™-M3 based processor, memory, and all I/O connectivity
This application note documents the robustness of the analog
front end of the ADuCM350 in the presence of four separate
intensive digital noise environments.
FUNCTIONAL BLOCK DIAGRAM
PLL
SW/JTAG
1 x 256kB
LF XTAL
1 x 128kB
CORTEX M3
HF XTAL
FLASH
HF OSC
NVIC
LF OSC
16Kb
EEPROM
TRACE
DMA
SIGNAL
GENERATION
AFE
CONTROLLER
• 16-BIT PRECISION ADC
AMBA
BUS
MATRIX
SRAM1
(16Kb)
• PRECISION REFERENCE
• SWITCH MATRIX
• TIA
POR
DFT
PSM
USB
USB PHY
• 12-BIT DAC
• IN-AMP CONTROL LOOP
SRAM0
(16Kb)
PDI
RECEIVE
FILTERS
LP LDO
CAPTOUCH
HP LDO
SPIH
UART
SPI0
SPI1
I2C
AHB-APB
BRIDGE
APB-0
I2S
LCD
TMR0
GPIO
CRC
Figure 1.
Rev. 0 | Page 1 of 12
TMR1
PMU
BEEP
APB-1
TMR2
WDT
RTC
MISC
12022-001
AFE
AN-1286
Application Note
TABLE OF CONTENTS
Introduction ...................................................................................... 1
Digital Stress Tests .............................................................................6
Functional Block Diagram .............................................................. 1
CRC Stress Test ..............................................................................6
Revision History ............................................................................... 2
Parallel Display Interface Stress Test...........................................7
Sequencer/AFE Controller .............................................................. 3
Serial Peripheral Interface Stress Test .........................................8
Digital Filtering ............................................................................. 4
I2S Stress Test..................................................................................9
Discrete Fourier Transform Block.............................................. 5
REVISION HISTORY
3/14—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
Application Note
AN-1286
SEQUENCER/AFE CONTROLLER
channels for transferring data to and from the sequencer. There
are two fail safe operations for operational integrity; a sequence
counter which tallies the number of commands executed by the
sequencer and a CRC-8 applied on all commands executed.
Once the sequence begins, it operates independently of the core
and can only be aborted using specific commands.
The Cortex-M3 processor runs a sequence using the
RunSequence command. There are two independent DMA
This functionality allows the ADuCM350 to perform high
precision robust measurements in a digitally noisy environment
12022-002
The ADuCM350 utilizes an autonomous sequencer to control
the analog front end of the device. This allows the AFE to
perform cycle accurate operations in an asynchronous manner
to the Cortex-M3 processor. The sequencer handles the precision and timing critical operations without being subjected to
system load.
Figure 2. ADuCM350 Example of Amperometric Type Sequence in Software Development Kit
Rev. 0 | Page 3 of 12
AN-1286
Application Note
DIGITAL FILTERING
The block diagram is shown in Figure 3.
This block implements a low-pass supply rejection filter for
output data rates of 900 SPS. The requirement is to reject
50 Hz/60 Hz tones in the dc amperometric phase.
The sinc2hf filter decimates the 160 kSPS input data by 178 for
a target output data rate of 900 Hz. The reason behind choosing
900 Hz was to allow the optimal placement of the 50 Hz and
60 Hz notches.
The filter block consists of two cascaded sinc2 filters. The first
filter (sinc2hf) decimates the input data (ADC data sampled at
160 kHz) down to ~900 Hz. The second filter (sinc2lf) adds
notches at 50 Hz and 60 Hz for supply rejection. Typically, the
filtered data (sinc2lf) is supplied to the Cortex-M3, but the
option exists to read back the unfiltered data (sinc2hf output).
The selectivity achieved with this configuration makes it very
robust for high precision measurement in a digitally noisy
environment. See Figure 4 for plot of signal-to-noise ratio of
TIA measurement channel.
The filter settling time is 1/50 + 1/60 = 36.667 ms.
SINC2HF
SINC2LF
160kSPS
900SPS
900SPS
178
SUPPLY_LPF_RESULT
Figure 3. ADuCM350 Supply Rejection Filter Block Diagram
–98
–97
–96
–94
–93
–92
–91
–90
12022-004
SNR (dB)
–95
2.4 3.0 3.6 2.4 3.0 3.6 2.4 3.0 3.6 2.4 3.0 3.6 2.4 3.0 3.6
–20
0
25
50
SUPPLY (V) & TEMPERATURE (°C)
70
Figure 4. TIA Channel Signal-to-Noise Ratio
Rev. 0 | Page 4 of 12
12022-003
POWER LINE REJECT FILTER
Application Note
AN-1286
DISCRETE FOURIER TRANSFORM BLOCK
This block performs a 2048-point single frequency discrete
Fourier transform (DFT). It takes the 16-bit ADC output as
input and outputs the real and imaginary parts of the complex
result.
40
20
MAGNITUDE (dB)
–20
–40
–80
12022-005
–60
The DFT engine outputs the results as a complex number. The
magnitude and phase of the impedance at the excitation
frequency are calculated by the Cortex-M3 using the following
formulas:
0
500
1000
1500
2000
2500
Figure 5. Modeled ADuCM350 DFT Frequency Response
180
160
140
ACQUISITION
TIME OF
ADuCM350
120
60Hz ATTEN 20kHz
50Hz ATTEN 20kHz
60Hz ATTEN 10kHz
50Hz ATTEN 10kHz
100
80
60Hz ATTEN 2kHz
50Hz ATTEN 2kHz
60Hz ATTEN 1kHz
50Hz ATTEN 1kHz
60
40
0
0.008 0.010 0.012 0.014 0.016 0.018 0.020 0.022 0.024 0.026 0.028 0.030
ACQUISITION TIME/S (Seconds)
Figure 6. Mathematical Modeling of DFT Narrow
Band-Pass Capability
Rev. 0 | Page 5 of 12
3000
FREQUENCY (Hz)
ATTENUATION (dB)
 = �2 +  2

ℎ =  � �

The DFT function is optimized to be very immune to noise
because it is highly selective with a very narrow pass-band filter
performance. See Figure 6 for simulations performed on DFT
performance
0
12022-006
The DFT engine calculates the signal power at a single
frequency bin, which is the bin corresponding to the excitation
frequency. As such, there is a tight coupling between the sinusoid waveform generator and the DFT engine. The frequency
control word (AFE_WG_FCW) is used by the DFT engine to
determine the required frequency bin.
60
AN-1286
Application Note
DIGITAL STRESS TESTS
NO STRESS
CRC STRESS
100
80
60
40
For each test, the first set of measurements are done with only
the ADC converting and no stress enabled. The second set of
measurements are done with the ADC converting using the
sequencer while the digital noise source is being excited in
parallel.
20
12022-010
Due to the high selectivity of the DFT, the decimated ADC with
Sinc2LPF enabled was used for these measurements
120
FREQUENCY
The measurements described in this section are targeted to
generate digital noise that may interfere with the precision
analog measurements. There are many digital blocks on the
ADuCM350 that cannot generate a lot of digital noise, such as
UART, RTC, and timers. These tests are intended to be practical
and application specific.
0
1.7998
VOLTAGE (V)
Figure 7. REF_EXCITE Measurement Internally Through ADC Mux
Measurements were taken at ambient temperature.
CRC STRESS TEST
100
NO STRESS
Purpose
90
This is a data transfer test where the DMA performs a 512
32-bit transfer from SRAM0 (source) to CRC (destination) with
no wait states. This is repeated using SRAM1. This test is looped
while precision analog measurements are being made using the
AFE sequencer.
80
70
FREQUENCY
Digital Blocks Exercised
CRC STRESS
60
50
40
CRC
20
•
DMA
10
•
Bus matrix
0
1.8141
•
SRAM0
•
SRAM1
12022-008
30
•
1.8142
1.8143
1.8145
1.8144
VOLTAGE (V)
Figure 8. ½ DVDD Measurement Internally Through ADC Mux
Results
120
Results show that the CRC stress noise has negligible impact on
the analog precision measurements.
100
NO STRESS
CRC STRESS
FREQUENCY
80
60
40
0
1.79988
12022-009
20
1.79991
VOLTAGE (V)
Figure 9. REF_EXCITE Measured Through Pin An_B
Rev. 0 | Page 6 of 12
1.79994
Application Note
AN-1286
PARALLEL DISPLAY INTERFACE STRESS TEST
Purpose
100
NO STRESS
PDI STRESS
80
70
60
50
40
30
20
10
0
1.80592
Digital Blocks Exercised
PDI
•
DMA
•
Bus matrix
•
General-purpose flash
1.805953
1.805975
1.805997
1.80603
VOLTAGE (V)
Figure 11. ½ DVDD Measurements Internally Through ADC Mux
120
NO STRESS
PDI STRESS
100
Results
80
Results show that the PDI stress noise has negligible impact on
the analog precision measurements.
120
FREQUENCY
•
12022-011
Data is prepared in the general-purpose (GP) flash and this is
used as a DMA source. Data is transferred, through the DMA,
from GP flash (source) to PDI (destination) using the DMA.
This test is run at the maximum data rate possible. This transfer
is looped while a precision AFE measurement is made.
90
FREQUENCY
The parallel display interface (PDI), similar to the CRC, can
transfer large amounts of 32-bit data internally. In addition,
the PDI also switches a wide parallel port (16 bits) with the
potential for noise during basic display operations. The PDI
represents the most number of pins a single interface can switch
simultaneously.
60
40
NO STRESS
PDI STRESS
100
FREQUENCY
80
12022-012
20
0
1.80592
1.80603
VOLTAGE (V)
60
Figure 12. REF_EXCITE Measured Through Pin An_B
40
12022-010
20
0
1.80592
1.80603
VOLTAGE (V)
Figure 10. REF_EXCITE Measurement Internally Through ADC Mux
Rev. 0 | Page 7 of 12
AN-1286
Application Note
SERIAL PERIPHERAL INTERFACE STRESS TEST
NO STRESS
90
SPI STRESS
80
70
60
50
40
•
SPIH
30
•
DMA
20
•
Bus matrix
10
0
1.80592
Results
Results show that the SPI stress noise has negligible impact on
the analog precision measurements.
12022-014
Digital Blocks Exercised
100
FREQUENCY
The high speed SPI bus (SPIH) is suitable for flash storage
of video or audio data. It can be accessed at 8 MHz and run in
bursts.
In this stress test, the SPIH is set up to transfer 512 byte blocks
of data to and from SRAM 1 at 8 MHz SCLK speed. The DMA
is used for data transfers to and from the SPIH.
1.80603
1.805975
VOLTAGE (V)
Figure 14. ½ DVDD Measurement Internally Through ADC Mux
100
120
NO STRESS
NO STRESS
90
SPI STRESS
100
SPI STRESS
80
70
FREQUENCY
60
40
60
50
40
30
0
1.80592
12022-015
20
20
12022-013
FREQUENCY
80
10
0
1.80603
VOLTAGE (V)
1.799939
VOLTAGE (V)
Figure 13. REF_EXCITE Measurement Internally Through ADC Mux
Figure 15. REF_EXCITE Measured Through Pin An_B
Rev. 0 | Page 8 of 12
Application Note
AN-1286
I2S STRESS TEST
NO STRESS
90
I2S STRESS
80
70
60
50
•
I2S
•
DMA
30
•
SRAM1
20
40
Results
10
Results show that the I2S stress noise has negligible impact on
the analog precision measurements.
0
1.80592
12022-017
Digital Blocks Exercised
100
FREQUENCY
I2S represents a continuous 8k bits/second data transfer rate
through the system at low performance audio rates. This
represents 8 kHz sample rate, mono sound, with 8-bits/sample.
It is a combination of a steady stream of data using the DMA,
SRAM, I2S, and I/O pins.
1.80603
1.805975
VOLTAGE (V)
Figure 17. ½ DVDD Measurement Internally Through ADC Mux
100
NO STRESS
90
I2S STRESS
100
NO STRESS
80
90
60
70
50
40
30
20
60
50
40
12022-016
30
20
12022-018
10
0
I2S STRESS
80
FREQUENCY
FREQUENCY
70
10
1.799939
VOLTAGE (V)
0
Figure 16. REF_EXCITE Measurement Internally Through ADC Mux
1.799939
VOLTAGE (V)
Figure 18. REF_EXCITE Measured Through Pin An_B
Rev. 0 | Page 9 of 12
AN-1286
Application Note
NOTES
Rev. 0 | Page 10 of 12
Application Note
AN-1286
NOTES
Rev. 0 | Page 11 of 12
AN-1286
Application Note
NOTES
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
AN12022-0-3/14(0)
Rev. 0 | Page 12 of 12
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