ADuCM360/ADuCM361: Silicon Anomaly Sheet (Rev. A) PDF

Low Power Precision Analog Microcontroller,
ARM Cortex-M3, with Dual Sigma-Delta ADCs
ADuCM360/ADuCM361
Silicon Anomaly
This anomaly list describes the known bugs, anomalies, and workarounds for the ADuCM360/ADuCM361 MicroConverter® Revision D
silicon. The anomalies listed apply to all ADuCM360/ADuCM361 packaged material branded as follows:
First Line
Second Line
Third Line
ADuCM360 or ADuCM361
BCPZ
D30 (revision identifier)
Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries
to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended
workarounds outlined here.
ADuCM360/ADuCM361 FUNCTIONALITY ISSUES
Silicon
Revision
Identifier
D
Kernel
Revision
Identifier
0
Chip Marking
All silicon branded
D30
Silicon
Status
Release
Anomaly Sheet
Rev. A
No. of Reported Anomalies
4
Silicon
Status
Release
Anomaly Sheet
Rev. A
No. of Reported Anomalies
1
Anomaly Sheet
Rev. A
No. of Reported Anomalies
0
ADuCM360/ADuCM361 PERFORMANCE ISSUES
Silicon
Revision
Identifier
D
Kernel
Revision
Identifier
0
Chip Marking
All silicon branded
D30
ADuCM360/ADuCM361 SILICON FUTURE ENHANCEMENTS
Silicon
Revision
Identifier
D
Rev. A
Kernel
Revision
Identifier
0
Chip Marking
All silicon branded
D30
Silicon
Status
Release
Document Feedback
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Tel: 781.329.4700 ©2012–2014 Analog Devices, Inc. All rights reserved.
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ADuCM360/ADuCM361
Silicon Anomaly
PERFORMANCE ISSUES
Table 1. ADC Gain = 1, ADC Input Buffers Enabled [pr008]
Background
Issue
Workaround
Related Issues
When ADCs are configured for Gain = 1, the PGA is disabled. ADC input buffers may be enabled or disabled when
ADC gain = 1.
The ADC data output accuracy is not linear and does not meet the ADC specifications when the ADC input buffers are
enabled.
The issue is not present when ADC gain ≥ 2.
When using Gain = 1, ensure the input buffers are bypassed and powered down, for example: ADCxCON[17:14] = [1111].
None.
FUNCTIONALITY ISSUES
Table 2. External Interrupts in Debug Mode and Cortex-M3 in Deep Sleep Mode [er007]
Background
Issue
Workaround
Related Issues
The ADuCM360/ADuCM361 has various low power modes. External interrupts can wake up the Cortex-M3 core from
any of these low power modes.
When in debug mode, placing the ADuCM360/ADuCM361 in Mode 4 or Mode 5 forces the Cortex-M3 core into deep
sleep mode, however the high power LDO, oscillator, and clocks remain active.
The interrupt detection unit, external interrupt 0 to 7, will not wake the Cortex-M3 core from deep sleep (Mode 4
and Mode 5) when the debug logic is active, specifically if the debug software has set either the CDBGPWRUP or
CSYSPWRUP bits in the CTRL/STAT register. These are Cortex-M3 debug logic bits not visible from user code; these
bits can only be cleared by a write via the ARM serial wire download or a power on reset.
None.
None.
Table 3. Debug Mode and Deep Sleep Mode [er008]
Background
Issue
Workaround
Related Issues
The ADuCM360/ADuCM361 has various low power modes. When in debug mode, placing the ADuCM360/ADuCM361
in Mode 4 or Mode 5 forces the Cortex-M3 core into deep sleep mode; the rest of the device remains active.
After serial wire debug access, the serial wire logic may prevent a complete power down of the device. The debug logic
is cleared by a power cycle.
Power cycle the device after serial wire debug access.
None.
Table 4. I2C Slave not Releasing the Bus [er009]
Background
Issue
Workaround
Related Issues
When an I2C read request happens, if the TX FIFO of the slave is empty, the slave must NACK the request from the
master. Then it must release the bus, allowing the master to generate a STOP condition.
If the TX FIFO of the slave is loaded with a byte with an MSB of 0, just on the rising edge of SCL for the ACK/NACK, the
slave will pull the SDA low and hold the line until the device is reset.
Make sure the TX FIFO is always loaded on time by preloading TX FIFO in the preceding RX interrupt.
None.
Table 5. I2C Clock Stretch Issue [er010]
Background
Issue
Workaround
Related Issues
Clock stretching is a feature that allows a device to halt the I2C bus temporarily by holding SCL low.
Register I2CxSCON Bit 6 enables clock stretching in slave mode.
Register I2CxMCON Bit 3 enables clock stretching in master mode.
Writing to I2CxSCON Bit 6 or to I2CxMCON Bit 3 on the rising edge of SCL can cause a glitch that can be interpreted by
other devices as a real clock edge and might hang the bus.
Do not enable clock stretching.
None.
Rev. A | Page 2 of 4
Silicon Anomaly
ADuCM360/ADuCM361
SECTION 1. ADuCM360/ADuCM361 PERFORMANCE ISSUES
Reference Number
pr001
pr002
pr003
pr004
pr005
pr006
pr007
pr008
Description
ADC0/ADC1 INL specification
ADC0/ADC1 noise specification
ADC0/ADC1 noise specification at sampling rates ≥ 500 Hz
Current specification
ADC1–internal channels issue
Current–power down specification
DAC–offset error ( DAC output buffer enabled)
ADC gain = 1, ADC input buffers enabled
Status
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Open
SECTION 2. ADuCM360/ADuCM361 FUNCTIONALITY ISSUES
Reference Number
er001
er002
er003
er004
er005
er006
er007
er008
er009
er010
Description
ADC0/ADC1 input voltage–limitation on maximum input voltage
ADC0/ADC1–step detection circuit
External reference buffer–power down
ADC0/ADC1– Both ADCs sampling the same input
ADC0/ADC1– ADC output code issue
Power supply monitor (PSM)
External interrupts in debug mode and Cortex-M3 in deep sleep mode
Debug mode and deep sleep mode
I2C slave not releasing the bus
I2C clock stretch issue
Status
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Open
Open
Open
Open
SECTION 3. ADuCM360/ADuCM361 SILICON FUTURE ENHANCEMENTS
Reference Number
fr001
fr002
fr003
Description
Ground switch–maximum current
ADC0/ADC1 PGA–output voltage from PGA limited to 1 V maximum
Change of pins used for UART downloader
Rev. A | Page 3 of 4
Status
Fixed
Fixed
Fixed
ADuCM360/ADuCM361
Silicon Anomaly
NOTES
©2012–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
S09743-0-10/14(A)
Rev. A | Page 4 of 4
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