THE ANALOG DEVICES SOLUTIONS BULLETIN Volume 11, Issue 5 DIGITAL-TO-ANALOG CONVERTER ICS Contents DAC with Dynamic Power Control . . . . 1 Loop-Powered DAC Conserves Power . . . 2 DAC with Dynamic Power Control Optimizes Thermal Management in Multichannel Industrial Control Applications Breakthrough 1 ppm DAC . . . . . . . . . . . 2 As the density of factory process control terminals increases, the system power dissipation reaches levels where thermal issues begin to undermine equipment performance, reliability, and safety. IF DAC Solution in Base Station Transmit Architectures . . . . . . . . . . . . . . 3 Solution New DDS ICs Deliver Power and Size Savings . . . . . . . . . . . . . . . . . . . . . . 4 The AD5755 is a complete, multichannel control IC that incorporates on-chip dynamic power control with four precision 16-bit programmable voltage, or 4 mA to 20 mA current, output DACs. The dynamic power control works by continually sensing the load impedance and delivering the required power to the load while minimizing power loss in the rest of the system. This reduces self-heating and temperature elevation in dense, multichannel systems by 75% and lowers overall power consumption by 80% compared to other control technologies. The AD5755 offers fully specified performance with maximum total unadjusted error of 0.05% and a relative accuracy of ±0.006% max—meaning system calibration is no longer required. Supporting standard industrial voltage and current output ranges, the AD5755 can be used with standard HART protocol modems. Watch a brief video at www.analog.com/AD5755 for more information on this device and its features. Multioutput Low Jitter Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . 4 Data Conversion Knowledge Resource . . 5 Low Power Precision Op Amp Serves as a DAC Buffer . . . . . . . . . . . . 5 Selection Guide . . . . . . . . . . . . . . . . . . . 6 RF DACs Enable Bits-to-RF Conversion in a Single Package . . . . . . . 8 Mixed-Signal Front-End IC for Wireless Communications Equipment . . . . . . . . . 10 ® Octal denseDAC in WLCSP Package . . 11 Versatile, Easy to Use, Precision DAC in Compact Package . . . . . . . . . . . 11 New System Demonstration Platform Facilitates Quick Prototyping and Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . 12 AD5755 Features •Quad DAC with 16-bit resolution and monotonicity •Dynamic power control for thermal management •Integrated on-chip internal reference •Diagnostics and real-time fault analysis •9 mm × 9 mm, 64-lead LFCSP •Pricing: $13.65 Integrated Industrial Multichannel DACs Number of Channels Resolution (Bits) Output Type AD5755 AD5755-1 4 4 16 16 V or I V or I AD5735 4 12 V or I AD5757 AD5737 4 4 16 12 I I Part Number Visit our website for data sheets, samples, and additional resources. www.analog.com/v11bulletin01 HART Compliant • • • Loop-Powered DAC Conserves Power in Remote Industrial Applications Smart transmitters are powered from the 4 mA to 20 mA loop and, hence, operate within a limited power budget. As a result, the development of systems that accurately and efficiently monitor and transmit remote system measurements is an imposing challenge. Solution To address this, system designers require a 4 mA to 20 mA loop-powered communication solution that is power efficient, highly accurate, and, ultimately, compact. The AD5421 has been specifically engineered to address this challenge by integrating on-board programmable power management circuitry with precision converter technology to bolster available system power. A complete transmitter solution, the AD5421 combines a precision, 16-bit, loop-powered digital to 4 mA to 20 mA transmitter with on-board voltage regulation circuitry. The on-chip regulator is designed to power the AD5421 and the peripheral components within the smart transmitter and generates a user-programmable 1.8 V to 12 V output voltage. Consuming only 250 μA of quiescent current, the AD5421 conserves the system power budget, enabling the selection of more accurate, higher power sensor electronics. Housed in 28-lead TSSOP and 32-lead LFCSP (5 mm × 5 mm), the AD5421 offers a complete single chip solution that reduces the overall PCB component count, providing a 55% footprint savings over alternative solutions. The high linearity and low drift performance offered by the AD5421 enable the development of high performance, feature-rich designs. The AD5421 can be used with standard HART protocol circuitry and offers NAMUR-compliant output ranges. Watch the AD5421 DAC video for more information on its features at www.analog.com/AD5421Overview. AD5421 Features Applications •16-bit resolution and monotonicity •Smart transmitters •Output ranges: 4 mA to 20 mA, 3.8 mA to 21 mA, 3.2 mA to 24 mA •4 mA to 20 mA loop-powered transmitters •On-chip fault alerts via FAULT pin or ALARM current Recommended Complementary Components •On-chip 2.5 V reference (4 ppm/°C max) •Low power precision analog microcontroller: ADuC7060 •Pricing: $5.90 •Low noise, low power, Σ-∆ ADC: AD7794 Breakthrough 1 PPM Digital-to-Analog Converter Across a range of applications from MRI systems to precision instrumentation there has long been a need for more accurate, simpler, and cost-effective DACs with guaranteed specifications that don’t require calibration or constant monitoring. Solution The AD5791 is the industry’s first single chip DAC to feature true 1 ppm resolution and accuracy, providing 4× greater accuracy and 4× more resolution than competing converters. The 20-bit AD5791 offers a relative accuracy specification of ±1 ppm INL maximum. Operation is guaranteed monotonic with a ±1 ppm DNL maximum specification. The product delivers 0.025 ppm low frequency noise, 7.5 nV/√Hz noise spectral density, 1 µs settling time, and 0.05 ppm/°C output drift. In addition, the device features sub-1 ppm lifetime drift. The AD5791 DAC incorporates a power-on reset circuit that ensures the DAC powers up at 0 V output and in a known output impedance state. The low noise, low drift, and fast refresh rate of the AD5791 maximizes operational up-time by eliminating costly calibration cycles and enabling faster system response times, thereby reducing cost of test. For more on the specific features of the AD5791, watch the video at www.analog.com/AD5791Overview. For details on the design of a 1 ppm system, read our technical article at www.analog.com/AD5791Article. Recommended Complementary Components AD5791 Features •20-bit resolution •1 ppm linearity without adjustments •20-lead TSSOP package •Pricing: •36 V precision, 2.8 nV/√Hz, rail-torail output op amps: AD8675 and AD8676 • AD5791 (A grade)—$46.10 • AD5791 (B grade)—$64.58 Reference Circuits 20-Bit, Linear, Low Noise, Precision, Bipolar ±10 V DC Voltage Source Using the AD5791 DAC. Complete documentation available at www.analog.com/CN0191. 2 For data sheets, samples, and additional resources, visit www.analog.com/v11bulletin01 IF DAC Solutions in Base Station Transmit Architectures In W-CDMA, CDMA2000, TD-SCDMA, GSM, and WiMAX base station transmit applications, high performance DACs are commonly used to synthesize the I/Q intermediate frequency (IF) in the transmit signal chain architecture. As service providers are continually requiring more performance and functional integration delivered in a shrinking amount of space, it is incumbent upon system designers to choose optimal components for the task. Having a broad portfolio from which to choose the optimal component is mandatory. Solution As the market leader in high speed data conversion, Analog Devices offers a deep and unique portfolio of TxDAC® IF transmit DAC solutions that allows the designer to optimize product selection and meet all critical system criteria, whether it be bandwidth, dynamic performance, power, package size, data interface, level of integration, etc. ADI fully understands transmit architectures and communications requirements and has engineered an IF DAC product portfolio to match the needs of any application. Premiere products include: AD9148—Quad, 16-Bit, 1 GSPS, TxDAC+ Transmit DAC AD9125—Dual, 16-Bit, 1 GSPS TxDAC+ Transmit DAC •On-chip 32-bit NCO for complex modulation schemes with 2×, 4×, and 8× interpolation •Single-carrier W-CDMA ACLR = 80 dBc at 122.88 MHz IF •Noise spectral density of –158 dBm/Hz •Novel 2×/4×/8× interpolator/complex modulator allows carrier placement anywhere in the DAC bandwidth •3rd-order IMD = 85 dBc •Gain and phase adjustment for sideband suppression •ACLR = 78 dBc •Multichip synchronization interface •12 mm × 12 mm flip-chip package technology •10 mm × 10 mm exposed paddle LFCSP •Pricing: $56.80 •Pricing: $30.00 AD9146—16-Bit, 1.2 GSPS, TxDAC+ Transmit DAC •Noise specification of –164 dBm/Hz AD9117 and AD9717—14-Bit, 125 MSPS, TxDAC+ Transmit DACs with 20 mA and 4 mA IOUT •2× and 4× interpolators with fine NCO modulation control •NSD @ 10 MHz output, 125 MSPS, −157 dBc/Hz •IMD of 81 dBc @ 100 MHz •SPI interface for device configuration and status register readback •Single-carrier W-CDMA ACLR = 82 dBc @ 122.88 MHz IF •7 mm × 7 mm LFCSP •PDISS of 220 mW while operating at maximum speed •6 mm × 6 mm LFCSP •Pricing: $29.95 •Pricing: $9.50 Easy High Speed DAC Evaluation Using DPG ADI provides a unique set of hardware and software tools to evaluate a DAC’s functionality and test its performance within a full complex-IF signal chain. Analog Devices evaluation boards integrate clock generation and a quadrature modulator with the DAC solutions to demonstrate real-world signal chain performance. The Data Pattern Generator hardware and software allow the user to generate and stimulate the DAC input data port with multiple CW tones, multicarrier W-CDMA or LTE, or other customer-generated waveforms. For more information, please visit www.analog.com/dpg. Transmit system evaluation platform. For data sheets, samples, and additional resources, visit www.analog.com/v11bulletin01 3 New Direct Digital Synthesis (DDS) IC Delivers Power and Size Savings for Industrial and Communications Applications Large communication and instrumentation systems, such as wireless base stations and test and measurement equipment, have been taking advantage of fine frequency tuning, fast frequency hopping and settling times, and other performance benefits of DDS technology for over a decade. Now, designers of low power devices also seek to incorporate the benefits of DDS technology into their products without board space and power penalties. Solution The AD9838 is a complete, low power, small package DDS specifically engineered for wireless, handheld, and sensory equipment. The first DDS with sub-11 mW power consumption for a 16 MHz master clock, the AD9838 settles in nanoseconds with granularity well below 100 mHz. With an on-chip, low power DAC, it provides 28-bit fine frequency tuning and high SFDR that enables the user to more quickly and accurately generate a stable signal in the band of interest. Integration of various communication and modulation features enables the devices to support single-tone, 2FSK, 2PSK, QPSK, sweep capability, and amplitude modulation, simplifying the design of communications systems and reducing development risk and cost. AD9838 Features •Narrow-band SFDR > 66 dB •Low 11 mW operating power •Supports 16 MHz clock speed •Sine, square, and triangular output Recommended Complementary Components •Voltage feedback amplifiers: AD8038, AD8065 •Current output DACs: AD5543, AD5443 •4 mm × 4 mm, 20-lead LFCSP •Pricing: $2.10 Applications •Industrial sensory excitation applications •Impedance spectroscopy •Battery-enabled diagnostic and communications equipment Multioutput Clock Distribution Function with Serial On-Chip PLLs Delivers <200 fs RMS Jitter to Enhance Data Converter SNR Performance The clock signals provided to high speed, high performance DACs are often one of the primary limiting factors for the performance achieved by that DAC. In order to achieve their rated performance specifications, high speed data converters require a fast rising, low jitter sampling clock. In large complex systems where there are many digital chips requiring clock signals as a reference, it can be a significant challenge to maintain a good low noise/low jitter clock signal throughout the entirety of the clock tree. The AD9523 is designed to support the clocking requirements for data conversion stages in long-term evolution (LTE) and multicarrier GSM base station designs, medical instrumentation, ATE, and other wireless transceiver systems. It relies on an external VCXO to provide the oscillator source for a jitter cleanup PLL to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance. When connected to a recovered system reference clock and a VCXO, the device generates 14 low noise outputs with a range of 1 MHz to 1 GHz and one dedicated buffered output from the input PLL (PLL1). In addition, Analog Devices has developed a broad portfolio of discrete clock buffers that feature jitter on the order of 75 fs for LVPECL fanout buffers with skew on the order of 9 ps (picoseconds). These buffers can be situated near the data converter to revitalize the clock signal. When a very sharp edge for just one or two DACs is needed, the ADCLK905, ADCLK907, ADCLK914, ADCLK925, and ADCLK944 clock buffers provide very fast edges with little impact on the noise of the clock signal. AD9523 Features •Output frequency: <1 MHz to 1 GHz •14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS •Absolute output jitter: <200 fs @ 122.88 MHz •Distribution phase noise floor: –160 dBc/Hz • Integration range: 12 kHz to 20 MHz 4 •Pricing: $8.34 For data sheets, samples, and additional resources, visit www.analog.com/v11bulletin01 Data Conversion Knowledge Resource Designing analog and mixed-signal circuits is usually tougher than designing purely digital circuits, and high performance analogto-digital or digital-to-analog conversion stages can be one of the toughest challenges of all. Data conversion involves many critical analog-oriented circuit considerations that directly impact the success of your design. To help with this challenge, Analog Devices has launched its new Data Conversion Knowledge Resource, which is an easyto-navigate library of in-depth technical material focusing on all aspects of a conversion stage design. It comprises the best of the design and applications engineering knowledge that ADI has accumulated over our 45-year span of pioneering work in data conversion. It is material that you need to know, and who better to learn from than the experts at the company that literally wrote the book on the subject? For instance, among the 17 items in the ADC Noise Analysis and Filtering category are two articles authored by renowned ADI data converter technologist Walt Kester: •“The Good, the Bad, and the Ugly Aspects of ADC Input Noise—Is No Noise Good Noise?” •“Understand SINAD, ENOB, SNR, THD, THD + N, and SFDR so You Don’t Get Lost in the Noise Floor” The Data Conversion Knowledge Resource site provides easy browsing in a library of technical content sorted to specific areas of the data conversion function. Become part of a growing online design community where you can get answers to your toughest data conversion design questions in real time at ez.analog.com. The library’s rich and varied content was compiled from the best of ADI’s seminar notes, tutorials, Analog Dialogue articles, and technical webcasts. We welcome you to visit www.analog.com/TheKnowledgeResource and learn. DAC Buffer: Low Power, Precision, Rail-to-Rail Input and Output Amplifier Digital-to-analog converters are often designed with outputs that need a buffer in order to drive low impedance loads or to convert their current output into a voltage output. Often, the design engineers need this function over a wide variety of products, and it is time-consuming to select different op amps for the various supply voltages and output configurations required for each product. Solution The ADA4096-2 operational amplifier operates with voltage supplies compatible with nominal supply voltages from 3 V to 30 V (±1.5 V to ±15 V), and with its rail-to-rail input and output capability, it is a flexible op amp that is useful in a wide variety of applications. With its low input bias current, input offset voltage, and temperature drift specifications, it is well suited for 10-bit to 14-bit DACs where its voltage offset is less than an LSB. As an example, it will support the 14-bit AD5640 DAC with its LSB weight of 300 µV. The ADA4096-2 device’s stability when driving low impedance and high capacitance loads also contributes to the usefulness of this product as a DAC driver. ADA4096-2 Features • Wide voltage supply: 3 V to 30 V nominal • Wide unity gain bandwidth: • Rail-to-rail input and output • 800 kHz typical @ VSY = 30 V • Useable in single and dual supply voltage applications • 50 kHz typical @ VSY = 10 V • Low offset voltage and temperature drift: 35 µV and 1 µV/°C typical • 475 kHz typical @ VSY = 3 V • Low input bias current: 3 nA typical • Input overvoltage protection for 32 V above/below voltage supply • Low supply current: 60 µA/amp typical • Pricing: $1.87 For data sheets, samples, and additional resources, visit www.analog.com/v11bulletin01 5 Selection Guide Integrated Industrial Single-Channel DACs Part Number AD5421 AD5420 AD5410 AD5422 AD5412 No. of Resolution Output Type Current Range Voltage Package (Bits) (V, I, V or I) (mA) Channels Range (V) 4 to 20, 3.8 to 21, 3.2 to 24 N/A 28-lead TSSOP 1 16 I 1 16 I 4 to 20, 0 to 20, 0 to 24 N/A 40-lead LFCSP, 24-TSSOP 1 12 I 4 to 20, 0 to 20, 0 to 24 N/A 40-lead LFCSP, 24-lead TSSOP 0 to 5, 0 to 10, ±5, ±10 40-lead LFCSP, 24 lead-TSSOP 1 16 V or I 4 to 20, 0 to 20, 0 to 24 0 to 5, 0 to 10, ±5, ±10 40-lead LFCSP, 24-lead TSSOP 1 12 V or I 4 to 20, 0 to 20, 0 to 24 Price ($U.S.) 5.90 4.95 3.75 5.60 4.38 Integrated Industrial Multichannel DACs Part Number AD5755 No. of Channels 4 Resolution (Bits) 16 Output Type (V, I, V or I) V or I Current Range (mA) 4 to 20, 0 to 20, 0 to 24 Voltage Range (V) 0 to 5, 0 to 10, ±5, ±10, ±6, ±12 64-lead LFCSP Price ($U.S.) 13.65 AD5755-1* 4 16 V or I 4 to 20, 0 to 20, 0 to 24 0 to 5, 0 to 10, ±5, ±10, ±6, ±12 64-lead LFCSP 15.88 AD5735 4 12 V or I 4 to 20, 0 to 20, 0 to 24 0 to 5, 0 to 10, ±5, ±10, ±6, ±12 64-lead LFCSP 10.85 AD5757* 4 16 I 4 to 20, 0 to 20, 0 to 24 N/A 64-lead LFCSP 12.14 AD5737* 4 12 I 4 to 20, 0 to 20, 0 to 24 N/A 64-lead LFCSP 8.95 Package *HART compliant. Precision DACs Temperature Settling Noise Spectral Density (nV/√Hz) Drift (ppm/°C) Time (µs) Part Number Resolution (Bits) INL Output Range AD5791 20 1 VREFN to VREFP (VREFP = 5 V to 14 V, (VREFN = –14 V to 0 V) AD5781 18 1 AD5541A 16 1 AD5542A 16 1 AD5512A 12 1 ±VREF, 0 to VREF, (VREFP/N = 5 V to 14 V) 0 to VREF (VREF = 2 V to 5.5 V) 0 to VREF, ±VREF (VREF = 2 V to 5.5 V) 0 to VREF, ±VREF (VREF = 2 V to 5.5 V) Package Price ($U.S.) 7.5 0.04 1 20-lead TSSOP 37.86 7.5 0.04 1 20-lead TSSOP 16.42 11.8 ±0.1 1 11.8 ±0.2 1 11.8 ±0.2 1 10-lead LFCSP, 8-lead LFCSP, 10-lead MSOP 16-lead LFCSP, 10-lead LFCSP, 16-lead TSSOP 16-lead LFCSP, 10-lead LFCSP, 16-lead TSSOP 6.25 6.25 3.12 Transmit IF DACs Part Number AD9122 AD9146 Resolution Max DAC Max Output Signal Max Output Interface (Bits) Update Rate Channels Bandwidth (MHz) Frequency (MHz) 1.23 GSPS 2 LVDS 500 614 16 16 1.23 GSPS 2 LVDS 307.5 615 Power Dissipation (W) 1.1 1.2 Price ($U.S.) 34.50 29.95 AD9125 16 1 GSPS 2 CMOS 250 500 1.1 30.00 AD9148 AD9783/AD9781/ AD9780 AD9717/AD9716/ AD9715/AD9714 AD9117/AD9116/ AD9115/AD9114 16 1 GSPS 4 LVDS 310 500 3 16/14/12 500 MSPS 2 LVDS 250 500 462.3 mW 14/12/10/8 125 MSPS 2 CMOS 62.5 62.5 86 mW 14/12/10/8 125 MSPS 2 CMOS 62.5 62.5 232 mW 56.80 22.77/20.24/ 16.19 9.50/8.75/ 6.90/5.95 9.50/8.75/ 6.90/5.95 RF DACs Part Number AD9739A AD9739 AD9789 6 Resolution (Bits) 14 14 14 Max Update Rate (GSPS) 2.5 2.5 2.4 Multichip Interface Synchronization No LVDS Yes LVDS No CMOS Max Output Signal Bandwidth (MHz) 1250 1250 150 Max Output Frequency (MHz) 3000 3000 3000 For data sheets, samples, and additional resources, visit www.analog.com/v11bulletin01 Power Dissipation (W) 960 mW 1.16 1.7 Price ($U.S.) 43.69 43.69 58.54 Selection Guide (continued) denseDAC High Channel Count DACs Resolution (Bits) Part Number Interface Reference (V) Channels Price ($U.S.) Package AD5668 16 SPI 1.25 8 16-lead WLCSP 11.39 AD5668 16 SPI 1.25/2.5 8 16-lead LFCSP/16-lead TSSOP 11.39 AD5648 14 SPI 1.25/2.5 8 16-lead TSSOP 10.63 AD5628 12 SPI 1.25/2.5 8 16-lead LFCSP/16-lead TSSOP 7.70 AD5628 12 SPI 1.25 8 16-lead WLCSP 7.70 AD5669R 16 2 IC 1.25/2.5 8 16-lead LFCSP/16-lead TSSOP 12.30 AD5629R 12 I2C 1.25/2.5 8 16-lead LFCSP/16-leadTSSOP 7.95 Output Buffer Amplifiers Nominal VSY Range (V) VOS Max @ 25°C TCVOS Typ Unity Gain Bandwidth (Typ) ISY Max @ 25°C (µA) IB Max @ 25°C RRIO Price ($U.S.) ADA4096-2 3 to 30 300 μV 1.0 μV/°C 800 kHz 75 10 nA Yes 1.87 ADA4091-2 3 to 30 250 μV 3.0 μV/°C 1.27 MHz 250 60 nA Yes 2.22 ADA4084-2 3 to 30 100 μV 0.2 μV/°C 8.3 MHz 750 450 nA Yes 2.85 AD8622 3 to 30 125 μV 0.5 μV/°C 560 kHz 250 200 pA RRO 2.30 AD8606 3 to 5 65 μV 1.0 μV/°C 10 MHz 1.2 ma 1 pA Yes 1.19 ADA4665-2 5 to 16 4 mV 3.0 μV/°C 1.2 MHz 400 1 pA Yes 0.70 Part Number Clock Generator Part Number No. of Inputs Description No. of Outputs Max fOUT (GHz) Output Logic Random Jitter (fs) Price ($U.S.) AD9523-1 Low jitter, dual loop clock generator 2 14 1 CMOS, HSTL, LVDS, LVPECL 187 8.34 AD9523 Low jitter, dual loop clock generator 2 14 1 CMOS, HSTL, LVDS, LVPECL 225 9.27 AD9516-0 Multioutput clock generator 2 14 2.25 CMOS, LVDS, LVPECL 400 11.39 AD9520-1 Multioutput clock generator 1 12 2.65 CMOS, LVPECL 225 12.65 AD9524 Low jitter, dual loop clock generator 2 14 1 CMOS, HSTL, LVDS, LVPECL 225 6.57 Clock Buffers and Distribution ICs Part Number Input/Output Input/Output Logistics Input Output Toggle Rate RMS Jitter (ps) Typ Output-toOutput Skew (ps) Price ($U.S.) AD9512/AD9513/ AD9514/AD9515 1 to 2/3/5 Differential LVDS/CMOS 800 MHz LVDS/ 250 MHz CMOS 0.3 — 9.06/5.35/ 6.02/4.81 ADCLK905/ADCLK907 1 to 1 Dual 1 to 1 Differential LVPECL 7.5 GHz 0.06 — 5.27/8.04 ADCLK925 1 to 2 Differential LVPECL 7.5 GHz 0.06 9 6.29 ADCLK944 1 to 4 Differential LVPECL 7 GHz 0.05 9 5.95 1 or 2 to 6/8/10/12 LVPECL/CML/ CMOS/LVDS LVPECL 4.8 GHz 0.075 9 6.25/6.50/ 6.58/6.95 1 to 1 LVPECL/CML/CMOS/ LVTTL/LVDS HVDS 7.5 GHz 0.11 — 8.18 ADCLK846/ADCLK854 1 or 2 to 6/8 LVPECL/LVDS/ HSTL/CML/CMOS LVDS/CMOS 1.2 GHz LVDS/ 250 MHz CMOS 0.1 65 4.75/5.35 ADN4670 1 or 2 to 10 Differential LVDS 1.1 GHz 0.1 30 5.50 ADCLK946/ADCLK948/ ADCLK950/ADCLK954 ADCLK914 For data sheets, samples, and additional resources, visit www.analog.com/v11bulletin01 7 When Synthesizing Large Bandwidths or Narrow-Band Waveforms Below 2.7 GHz, RF DACs Provide Unique Technology That Allows Direct Bits-to-RF Conversion in a Single Package In wired and wireless communication applications, multicarrier transmitters are becoming the norm. To modulate and combine multiple carriers to form the transmit output, system engineers are challenged by complex analog signal processing and power-inefficient combiners, as shown in the traditional multiple carrier transmit signal chain below. Solution TxDAC COMPLEX A traditional solution for this challenge in wireless communication systems is to utilize discrete dual DACs and a quadrature modulation function to generate signals above 300 MHz. Although flexible, this solution requires specific clock and power circuitry. As can be seen in the complex IF transmit signal chain below, stringent RF filtering is required to correct analog imperfections such as unsuppressed sideband and LO feedthrough. When combining these architecture limitations with infrastructure equipment’s trending requirements for smaller and lower power solutions, the RF system engineer is challenged to provide a solution meeting market demand. LO FEEDTHROUGH 3.5dB LOSS 3.5dB LOSS UNSUPPRESSED SIDEBAND TxDAC –FDAC –2FS 3.5dB LOSS TxDAC –3FDAC/4 –3FS/2 –FDAC/2 –FS LPF TxDAC –FDAC/4 –FS/2 –FDAC/2 –3FDAC/4 –FS –3FS/2 –FDAC –2FS DAC DSP CLUSTER 90 DUC AND PAPR 0 TxDAC LPF TUNING CONTROL DAC DSP NETWORK INTERFACE DSP CLOCK DISTRIBUTION Complex IF transmit signal chain. AD9739—14-Bit, 2.5 GSPS RF DAC with Multichip Synchronization AD9739A—14-Bit, 2.5 GSPS RF DAC •Direct RF synthesis at 2.5 GSPS AD9789 —14-Bit, 2.4 GSPS RF DAC with 4-Channel Signal Processing •DOCSIS 3.0 performance •Update rate: dc to 1.25 GHz in baseband mode, 1.25 GHz to 3.0 GHz in mix mode •On-chip and bypassable 4 QAM encoders with SRRC filters •Industry-leading single/multicarrier IF or RF synthesis •16× to 512× interpolation, rate converters, and modulators •Dual-port LVDS data interface up to 1.25 GSPS operation •DOCSIS 3.0 performance: 4 QAM carriers • 8 QAM carriers @ 400 MHz IF: −71 dBc • 16 QAM carriers @ 400 MHz IF: −68 dBc • 32 QAM carriers @ 400 MHz IF: −65 dBc •ACLR over full band (47 MHz to 1 GHz) •Source-synchronous DDR clocking • −75 dBc @ fOUT = 200 MHz •Pin-compatible with the AD9739 • −72 dBc @ fOUT = 800 MHz (noise) •RF synthesis support: FS mix, RZ modes •Programmable output current: 8.7 mA to 31.7 mA • −67 dBc @ fOUT = 800 MHz •Dual-port LVDS data interface with on-chip 100 Ω terminations •Low power: 1.1 W at 2.5 GSPS • 72 QAM carriers @ 600 MHz IF: −61 dBc •12 mm × 12 mm, 160-ball CSP_BGA •Pricing: $43.69 8 0 0 CHANNEL SELECT FILTER BPF Traditional multiple carrier transmit signal chain. –FDAC/4 –FS (harmonics) •12 mm × 12 mm, 160-ball CSP_BGA •Flexible data interface: 4, 8, 16, or 32 bits wide with parity •Pricing: $43.69 •12 mm × 12 mm, 164-ball CSP_BGA •Pricing: $58.54 For data sheets, samples, and additional resources, visit www.analog.com/v11bulletin01 Solution RF DAC Solution As the market leader in high speed data conversion, Analog Devices provides unique technology to solve the bandwidth and transmit architecture challenges for RF frequencies below 2.7 GHz. RF DAC technology from Analog Devices can not only synthesize up to 1 GHz of modulated signal bandwidth, but with its proprietary mixed-mode sampling capability, it enables the use of the second Nyquist zone to provide bits-to-RF conversion of frequencies up to 2.7 GHz, in a single package. Analog Devices provides three such RF DACs with bit-to-RF capability. The AD9739 and AD9739A are high performance, high frequency 14-bit DACs that provide sampling rates of up to 2.5 GSPS. These devices permit multicarrier generation at up to the Nyquist frequency in baseband mode, and utilizing their unique mix-mode functionality, they can generate carriers of up to 2.7 GHz in the second and third Nyquist zones. They include a dual-port LVDS interface to readily interface with existing FGPA/ASIC technology to facilitate the maximum baseband signal synthesis bandwidth of 1.25 GHz. Unlike the AD9739A, the AD9739 features a multichip synchronization feature that allows the synchronization of multiple transmit channels (see block diagrams below). With 1.1 W power consumption at the full sampling rate, the AD9739 and AD9739A RF DAC IC devices provide the lowest power and smallest package-size solution for synthesizing up to 1 GHz of bandwidth and output frequencies below 2.5 GHz in multicarrier transmit systems. They eliminate the need for discrete multichannel or multistage design by integrating all the bandwidth and output frequency capabilities in a single chip. RESET DACCLK_P DACCLK_N RESET IRQ AD9739A AD9739 LVDS RECEIVER DB0[13:0]P DB0[13:0]N DB1[13:0]P DB1[13:0]N IOUTP IOUTN REFERENCE CURRENT S2 DCO SPI VREF DATA LATCH 4-TO-1 DATA ASSEMBLER 14-, 12-, 10-BIT DAC CORE LVDS DDR RECEIVER DB0[13:0] DCI BAND GAP DAC BIAS VREF I120 LVDS DDR RECEIVER SYNC_IN_P SYNC_IN_N 1.2V SPI DATA CONTROLLER LVDS RECEIVER DCI_P DCI_N CLOCK DISTRIBUTION SYNCHRONIZER LVDS DRIVER SYNC_OUT_P SYNC_OUT_N LVDS DRIVER SPI DCO_P DCO_N SDIO SDO CS SCLK DB1[13:0] SDIO SDO CS SCLK CLK DISTRIBUTION (DIV-BY-4) TxDAC CORE IOUTN IOUTP DLL (MU CONTROLLER) DACCLK I120 AD9739 block diagram. AD9739A block diagram. The AD9789 is a flexible QAM encoder/interpolator/upconverter combined with a high performance 2400 MSPS, 14-bit RF DAC. The flexible digital interface can accept up to four channels of complex data, and the QAM encoder supports constellation sizes of 16, 32, 64, 128, and 256 with SRRC filter coefficients for all standards. The on-chip rate converter supports a wide range of baud rates with a fixed DAC clock. The digital upconverter can place the channels anywhere from 0 to 0.5 × fDAC. This permits four contiguous channels to be synthesized and placed anywhere from dc to fDAC/2 (see AD9789 block diagram below). With 1.6 W power consumption at full rate, the AD9789 provides the most integrated solution for multicarrier transmit systems required to modulate and synthesize independently up to four channels for output frequencies below 2.5 GHz. The AD9789 eliminates the need for multichannel or multistage design by integrating the modulation and output frequency capabilities in a single chip. 32 INPUT PINS AND 2 PARITY PINS DCO FS CMOS 0 TO 15 LVDS RISE 150MHz LVDS/CMOS CMOS 16 TO 31 LVDS FALL DATA QAM/ FILTER/ NCO DATA QAM/ FILTER/ NCO RETIMER DATA FORMATTER/ ASSEMBLER DATA QAM/ FILTER/ NCO DATA QAM/ FILTER/ NCO AD9789 16 INTERPOLATOR AND BPF + SCALARS SPI IRQ 14-BIT 2.4GSPS DAC RS AD9789 block diagram. For data sheets, samples, and additional resources, visit www.analog.com/v11bulletin01 9 Mixed-Signal Front-End ICs Combine Dual Transmit DAC and Wideband ADC to Reduce Power and PC Board Space in Wireless Communications Equipment Cost- and space-sensitive wireless equipment, such as femtocell and picocell base stations and portable radios, require high levels of integration in their transmit-and-receive signal paths to reduce board space and system cooling requirements. Solution Mixed-signal front-end ICs (MxFE® devices), pioneered by ADI, provide that solution by integrating the required high performance transmit DACs and receive ADCs onto a single chip, while tailoring their dynamic range for compliance with multicarrier applications. The 12-bit AD9963 and pin-compatible 10-bit AD9961 MxFE devices use 40% less power and 25% less printed circuit board area and enable up to 10 dB better ACLR (adjacent-channel leakage ratio) performance than competing devices. AD9963 and AD9961 Features •Dual-channel, 10-bit (AD9961) and 12-bit (AD9963), 170 MSPS digital-to-analog converter Tx path configurable for 1×, 2×, 4×, and 8× interpolation •ACLR = 74 dBc (12 bits) •Dual-channel, 10-/12-bit, 100 MSPS analog-to-digital converter Rx path includes a bypassable 2× decimating low-pass filter •SNR = 67 dB (12 bits), FIN = 30.1 MHz •5 channels of analog auxiliary input/output (two 12-bit DACs, two 10-bit DACs, and a 12-bit ADC) •1.8 V single-supply operation; <425 mW at maximum sample rates •Supports full- and half-duplex data interfaces •Small 72-lead LFCSP lead-free package •Pricing: • AD9963—$29.50 • AD9961— $25.75 Applications •Wireless infrastructure •Picocell, femtocell base stations •Medical instrumentation •Ultrasound AFE •Portable instrumentation •Signal generators, signal analyzers Recommended Complementary Components in Femtocell Base Stations •ADF4602 3G multiband transceiver •ADL5501 rms power detector •RF amplifiers: ADL5320, ADL5542, and ADL5601 10 For data sheets, samples, and additional resources, visit www.analog.com/v11bulletin01 Octal 16-/12-Bit denseDAC Devices Available in Tiny 2.645 mm × 2.645 mm Package ADI’s denseDAC® digital-to-analog converter portfolio offers products that combine high DAC channel count with a small package and low power, at low cost. The AD5668/AD5628 denseDAC devices are octal 16-/12-bit SPI rail-to-rail DACs with an integrated reference, which are now available in a 2.645 mm × 2.645 mm, 16-lead WLCSP package, as well as 4 mm × 4 mm, 16-lead LFCSP and 16-lead TSSOP. With the AD5668/AD5628 there is no need to let space constraints force you to accept lower performance. These parts offer eight buffered voltage output DAC channels and integrated 1.25 V reference with 5 ppm/°C tempco in a tiny package. They are ideally suited to applications such as optical transceivers, base stations, and instruments. The AD5668/AD5628 DNL spec of ±1 LSB max meets the performance requirements for closed-loop systems. The related AD5669R/ AD5629R products offer an I2C rather than SPI interface. Easy Precision DAC Evaluation Using SDP The AD5668 can be evaluated using the System Demonstration Platform (SDP), which is designed to be low cost, reusable, and versatile. The platform is compatible with a growing number of precision ADI components. Applications AD5668/AD5628 Features •Tiny 2.645 mm × 2.645 mm WLCSP package •Power-down to 400 nA @ 5 V, 200 nA @ 3 V •Optical transceivers •8 DAC channels •Pricing: •Process control • AD5668—$11.39 •On-chip 1.25 V reference with 5 ppm/°C tempco •Base station power amplifier control •Portable battery-powered instruments • AD5628—$7.70 •2.7 V to 5.5 V power supply •Guaranteed monotonic by design Versatile, Easy to Use, Precision DAC Building Block Components in a Compact Package Across a range of applications from instrumentation to communications, system developers require easy to use versatile DACs, which provide true 16-bit precision to facilitate their use as a core building block component. Solution This challenge is addressed by the AD5541A (16-bit), AD5542A (16-bit), and AD5512A (12-bit) family of core building block DAC devices. These single-channel, high performance, unbuffered voltage output DACs operating from a single supply are ideally suited for a wide range of applications where precision is required. They deliver full 16-bit resolution and accuracy, low noise performance (11.8 nV/√Hz), low drift (0.05 ppm/°C), and low glitch impulse (1.1 nV/sec). Specified over a wide temperature range from −40°C to +125°C, this family is classified for 5 kV HBM ESD, making these devices highly robust solutions in any environment. Their fast settling time of 1μs with low offset errors makes them ideal for high speed open-loop control. The AD5512A/AD5542A incorporate a bipolar mode of operation that generates a ±VREF output swing via integrated internal feedback resistors, while also including Kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity. AD5541A/AD5542A/AD55121A Features •16-bit and 12-bit resolution SPI/QSPI™/MICROWIRE®/ •11.8 nV/√Hz noise spectral density •50 MHz DSP-compatible interface •1 μs settling time •Pricing: •0.375 mW power consumption at 3 V • AD5541A/AD5542A—$6.25 Recommended Complementary Components •AD8628/AD820 single-supply RRIO amplifier •ADR421 low noise 2.5 V reference • AD5512A—$3.12 Reference Circuits Precision, 16-Bit, Voltage Level Setting with Less than 5 mW Total Power Dissipation Using the AD5542A/AD5541A. Complete documentation available at www.analog.com/CN0181. For data sheets, samples, and additional resources, visit www.analog.com/v11bulletin01 11 Mailroom Supervisor: Send removals (in separate envelope) to address shown on left. Analog Devices, Inc. 600 North Bedford Street East Bridgewater, MA 02333-1122 PRSRT STD U.S. Postage PAID Gallery Return Service Requested New System Demonstration Platform Facilitates Quick Prototyping and Evaluation System design can be a complex problem with many different elements to comprehend, but the ability to prototype and quickly demonstrate subsections of the solution can simplify the process and, more importantly, reduce the risks faced by designers. Analog Devices’ System Demonstration Platform (SDP) is comprised of a series of controller boards, interposer boards, and daughter boards that implement an easy to use evaluation system for ADI components and reference circuits. With the SDP, system designers can reuse central elements, allowing subsections of their designs to be evaluated and demonstrated prior to the final system implementation. Familiarity gained from prior use of the platform makes it easy for users to evaluate new categories of components in an environment they already know and understand. Analog Devices, Inc. Worldwide Headquarters Analog Devices, Inc. One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 (800.262.5643, U.S.A. only) Fax: 781.461.3113 Analog Devices, Inc. Europe Headquarters Analog Devices, Inc. Wilhelm-Wagenfeld-Str. 6 80807 Munich Germany Tel: 49.89.76903.0 Fax: 49.89.76903.157 SDP-B controller board connects to AD5421 DAC evaluation board. Sample of SDP-Compatible DAC Evaluation Boards •AD5421: 16-bit, serial input, loop-powered, 4 mA to 20 mA DAC •AD5791/AD5781: 1 ppm 20-bit, ±1 LSB INL, voltage output DAC •AD5755-1: quad channel, 16-bit, serial input, 4 mA to 20 mA and voltage output DAC, dynamic power control, HART connectivity •AD9837: low power, 8.5 mW, 2.3 V to 5.5 V, programmable waveform generator •AD9838: 11 mW power, 2.3 V to 5.5 V, complete DDS To learn more about the SDP and to view a full list of compatible products and circuits, please visit: www.analog.com/sdp. Quick Technical Support Available from Our Experienced Applications Engineers Around the Globe Europe Tel: 00800.266.822.82 Email: [email protected] All prices in this bulletin are in USD in quantities greater than 1000 (unless otherwise noted), recommended lowest grade resale, FOB U.S.A. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). China America Tel: 4006.100.006 Tel: 781.937.1428 Email: [email protected] (800.262.5643) ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Printed in the U.S.A. SB10244-0-11/11(A) www.analog.com Analog Devices, Inc. Japan Headquarters Analog Devices, KK New Pier Takeshiba South Tower Building 1-16-1 Kaigan, Minato-ku, Tokyo, 105-6891 Japan Tel: 813.5402.8200 Fax: 813.5402.1064 Analog Devices, Inc. Southeast Asia Headquarters Analog Devices 22/F One Corporate Avenue 222 Hu Bin Road Shanghai, 200021 China Tel: 86.21.2320.8000 Fax: 86.21.2320.8222