LAN9252 2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs Highlights Key Benefits • 2/3-port EtherCAT slave controller with 3 Fieldbus Memory Management Units (FMMUs) and 4 SyncManagers • Interfaces to most 8/16-bit embedded controllers and 32-bit embedded controllers with an 8/16-bit bus • Integrated Ethernet PHYs with HP Auto-MDIX • Wake on LAN (WoL) support • Low power mode allows systems to enter sleep mode until addressed by the Master • Cable diagnostic support • 1.8V to 3.3V variable voltage I/O • Integrated 1.2V regulator for single 3.3V operation • Low pin count and small body size package • Integrated high-performance 100Mbps Ethernet transceivers Target Applications • • • • • • Motor Motion Control Process/Factory Automation Communication Modules, Interface Cards Sensors Hydraulic & Pneumatic Valve Systems Operator Interfaces - Compliant with IEEE 802.3/802.3u (Fast Ethernet) 100BASE-FX support via external fiber transceiver Loop-back modes Automatic polarity detection and correction HP Auto-MDIX • EtherCAT slave controller - Supports 3 FMMUs - Supports 4 SyncManagers - Distributed clock support allows synchronization with other EtherCAT devices - 4K bytes of DPRAM • 8/16-Bit Host Bus Interface - Indexed register or multiplexed bus - Allows local host to enter sleep mode until addressed by EtherCAT Master - SPI / Quad SPI support • Digital I/O Mode for optimized system cost • 3rd port for flexible network configurations • Comprehensive power management features - 3 power-down levels - Wake on link status change (energy detect) - Magic packet wakeup, Wake on LAN (WoL), wake on broadcast, wake on perfect DA - Wakeup indicator event signal • Power and I/O - Integrated power-on reset circuit - Latch-up performance exceeds 150mA per EIA/JESD78, Class II - JEDEC Class 3A ESD performance - Single 3.3V power supply (integrated 1.2V regulator) • Additional Features - Multifunction GPIOs - Ability to use low cost 25MHz crystal for reduced BOM • Packaging - Pb-free RoHS compliant 64-pin QFN or 64-pin TQFPEP • Available in commercial, industrial, and extended industrial* temp. ranges *Extended temp. (105ºC) is supported only in the 64-QFN with an external voltage regulator (internal regulator must be disabled) and 2.5V (typ) Ethernet magnetics. 2015 Microchip Technology Inc. DS00001909A-page 1 LAN9252 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at [email protected]. We welcome your feedback. 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To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS00001909A-page 2 2015 Microchip Technology Inc. LAN9252 1.0 Preface ............................................................................................................................................................................................ 4 2.0 General Description ........................................................................................................................................................................ 8 3.0 Pin Descriptions and Configuration ............................................................................................................................................... 11 4.0 Power Connections ....................................................................................................................................................................... 29 5.0 Register Map ................................................................................................................................................................................. 32 6.0 Clocks, Resets, and Power Management ..................................................................................................................................... 37 7.0 Configuration Straps ..................................................................................................................................................................... 51 8.0 System Interrupts .......................................................................................................................................................................... 53 9.0 Host Bus Interface ........................................................................................................................................................................ 62 10.0 SPI/SQI Slave ........................................................................................................................................................................... 102 11.0 Ethernet PHYs .......................................................................................................................................................................... 120 12.0 EtherCAT .................................................................................................................................................................................. 196 13.0 EEPROM Interface ................................................................................................................................................................... 295 14.0 Chip Mode Configuration .......................................................................................................................................................... 296 15.0 General Purpose Timer & Free-Running Clock ........................................................................................................................ 297 16.0 Miscellaneous ........................................................................................................................................................................... 301 17.0 JTAG ......................................................................................................................................................................................... 305 18.0 Operational Characteristics ....................................................................................................................................................... 307 19.0 Package Outlines ...................................................................................................................................................................... 322 20.0 Revision History ........................................................................................................................................................................ 325 2015 Microchip Technology Inc. DS00001909A-page 3 LAN9252 1.0 PREFACE 1.1 General Terms TABLE 1-1: GENERAL TERMS Term Description 10BASE-T 10 Mbps Ethernet, IEEE 802.3 compliant 100BASE-TX 100 Mbps Fast Ethernet, IEEE802.3u compliant ADC Analog-to-Digital Converter ALR Address Logic Resolution AN Auto-Negotiation BLW Baseline Wander BM Buffer Manager - Part of the switch fabric BPDU Bridge Protocol Data Unit - Messages which carry the Spanning Tree Protocol information Byte 8 bits CSMA/CD Carrier Sense Multiple Access/Collision Detect CSR Control and Status Registers CTR Counter DA Destination Address DWORD 32 bits EPC EEPROM Controller FCS Frame Check Sequence - The extra checksum characters added to the end of an Ethernet frame, used for error detection and correction. FIFO First In First Out buffer FSM Finite State Machine GPIO General Purpose I/O Host External system (Includes processor, application software, etc.) IGMP Internet Group Management Protocol Inbound Refers to data input to the device from the host Level-Triggered Sticky Bit This type of status bit is set whenever the condition that it represents is asserted. The bit remains set until the condition is no longer true and the status bit is cleared by writing a zero. lsb Least Significant Bit LSB Least Significant Byte LVDS Low Voltage Differential Signaling MDI Medium Dependent Interface MDIX Media Independent Interface with Crossover MII Media Independent Interface MIIM Media Independent Interface Management MIL MAC Interface Layer MLD Multicast Listening Discovery MLT-3 Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method where a change in the logic level represents a code bit “1” and the logic output remaining at the same level represents a code bit “0”. msb Most Significant Bit MSB Most Significant Byte DS00001909A-page 4 2015 Microchip Technology Inc. LAN9252 TABLE 1-1: GENERAL TERMS (CONTINUED) Term Description NRZI Non Return to Zero Inverted. This encoding method inverts the signal for a “1” and leaves the signal unchanged for a “0” N/A Not Applicable NC No Connect OUI Organizationally Unique Identifier Outbound Refers to data output from the device to the host PISO Parallel In Serial Out PLL Phase Locked Loop PTP Precision Time Protocol RESERVED Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must always be zero for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to reserved addresses. RTC Real-Time Clock SA Source Address SFD Start of Frame Delimiter - The 8-bit value indicating the end of the preamble of an Ethernet frame. SIPO Serial In Parallel Out SMI Serial Management Interface SQE Signal Quality Error (also known as “heartbeat”) SSD Start of Stream Delimiter UDP User Datagram Protocol - A connectionless protocol run on top of IP networks UUID Universally Unique IDentifier WORD 16 bits 2015 Microchip Technology Inc. DS00001909A-page 5 LAN9252 1.2 Buffer Types TABLE 1-2: BUFFER TYPES Buffer Type IS Description Schmitt-triggered input VIS Variable voltage Schmitt-triggered input VO8 Variable voltage output with 8 mA sink and 8 mA source VOD8 Variable voltage open-drain output with 8 mA sink VO12 Variable voltage output with 12 mA sink and 12 mA source VOD12 Variable voltage open-drain output with 12 mA sink VOS12 Variable voltage open-source output with 12 mA source VO16 Variable voltage output with 16 mA sink and 16 mA source PU 50 µA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pullups are always enabled. Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the device. When connected to a load that must be pulled high, an external resistor must be added. PD 50 µA (typical) internal pull-down. Unless otherwise noted in the pin description, internal pull-downs are always enabled. Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the device. When connected to a load that must be pulled low, an external resistor must be added. AI Analog input AIO Analog bidirectional ICLK Crystal oscillator input pin OCLK Crystal oscillator output pin ILVPECL Low voltage PECL input pin OLVPECL Low voltage PECL output pin P DS00001909A-page 6 Power pin 2015 Microchip Technology Inc. LAN9252 1.3 Register Nomenclature TABLE 1-3: REGISTER NOMENCLATURE Register Bit Type Notation R Register Bit Description Read: A register or bit with this attribute can be read. W Read: A register or bit with this attribute can be written. RO Read only: Read only. Writes have no effect. WO Write only: If a register or bit is write-only, reads will return unspecified data. WC Write One to Clear: Writing a one clears the value. Writing a zero has no effect WAC Write Anything to Clear: Writing anything clears the value. RC Read to Clear: Contents is cleared after the read. Writes have no effect. LL Latch Low: Clear on read of register. LH Latch High: Clear on read of register. SC Self-Clearing: Contents are self-cleared after the being set. Writes of zero have no effect. Contents can be read. SS Self-Setting: Contents are self-setting after being cleared. Writes of one have no effect. Contents can be read. RO/LH Read Only, Latch High: Bits with this attribute will stay high until the bit is read. After it is read, the bit will either remain high if the high condition remains, or will go low if the high condition has been removed. If the bit has not been read, the bit will remain high regardless of a change to the high condition. This mode is used in some Ethernet PHY registers. NASR Not Affected by Software Reset. The state of NASR bits do not change on assertion of a software reset. RESERVED Reserved Field: Reserved fields must be written with zeros to ensure future compatibility. The value of reserved bits is not guaranteed on a read. 2015 Microchip Technology Inc. DS00001909A-page 7 LAN9252 2.0 GENERAL DESCRIPTION The LAN9252 is a 2/3-port EtherCAT slave controller with dual integrated Ethernet PHYs which each contain a fullduplex 100BASE-TX transceiver and support 100Mbps (100BASE-TX) operation. The LAN9252 supports HP AutoMDIX, allowing the use of direct connect or cross-over LAN cables. 100BASE-FX is supported via an external fiber transceiver. The LAN9252 includes an EtherCAT slave controller with 4K bytes of Dual Port memory (DPRAM) and 3 Fieldbus Memory Management Units (FMMUs). Each FMMU performs the task of mapping logical addresses to physical addresses. The EtherCAT slave controller also includes 4 SyncManagers to allow the exchange of data between the EtherCAT master and the local application. Each SyncManager's direction and mode of operation is configured by the EtherCAT master. Two modes of operation are available: buffered mode or mailbox mode. In the buffered mode, both the local microcontroller and EtherCAT master can write to the device concurrently. The buffer within the LAN9252 will always contain the latest data. If newer data arrives before the old data can be read out, the old data will be dropped. In mailbox mode, access to the buffer by the local microcontroller and the EtherCAT master is performed using handshakes, guaranteeing that no data will be dropped. Two user selectable host bus interface options are available: • Indexed register access This implementation provides three index/data register banks, each with independent Byte/WORD to DWORD conversion. Internal registers are accessed by first writing one of the three index registers, followed by reading or writing the corresponding data register. Three index/data register banks support up to 3 independent driver threads without access conflicts. Each thread can write its assigned index register without the issue of another thread overwriting it. Two 16-bit cycles or four 8-bit cycles are required within the same 32-bit index/data register however, these access can be interleaved. Direct (non-indexed) read and write accesses are supported to the process data FIFOs. The direct FIFO access provides independent Byte/WORD to DWORD conversion, supporting interleaved accesses with the index/data registers. • Multiplexed address/data bus This implementation provides a multiplexed address and data bus with both single phase and dual phase address support. The address is loaded with an address strobe followed by data access using a read or write strobe. Two back to back 16-bit data cycles or 4 back to back 8-bit data cycles are required within the same 32-bit DWORD. These accesses must be sequential without any interleaved accesses to other registers. Burst read and write accesses are supported to the process data FIFOs by performing one address cycle followed by multiple read or write data cycles. The HBI supports 8/16-bit operation with big, little, and mixed endian operations. Two process data RAM FIFOs interface the HBI to the EtherCAT slave controller and facilitate the transferring of process data information between the host CPU and the EtherCAT slave. A configurable host interrupt pin allows the device to inform the host CPU of any internal interrupts. An SPI / Quad SPI slave controller provides a low pin count synchronous slave interface that facilitates communication between the device and a host system. The SPI / Quad SPI slave allows access to the System CSRs, internal FIFOs and memories. It supports single and multiple register read and write commands with incrementing, decrementing and static addressing. Single, Dual and Quad bit lanes are supported with a clock rate of up to 80 MHz. The LAN9252 supports numerous power management and wakeup features. The LAN9252 can be placed in a reduced power mode and can be programmed to issue an external wake signal (IRQ) via several methods, including “Magic Packet”, “Wake on LAN”, wake on broadcast, wake on perfect DA, and “Link Status Change”. This signal is ideal for triggering system power-up using remote Ethernet wakeup events. The device can be removed from the low power state via a host processor command or one of the wake events. For simple digital modules without microcontrollers, the LAN9252 can also operate in Digital I/O Mode where 16 digital signals can be controlled or monitored by the EtherCAT master. To enable star or tree network topologies, the device can be configured as a 3-port slave, providing an additional MII port. This port can be connected to an external PHY, forming a tap along the current daisy chain, or to another LAN9252 creating a 4-port solution. The MII port can point upstream (as Port 0) or downstream (as Port 2). LED support consists of a standard RUN indicator and a LINK / Activity indicator per port. A 64-bit distributed clock is included to enable high-precision synchronization and to provide accurate information about the local timing of data acquisition. The LAN9252 can be configured to operate via a single 3.3V supply utilizing an integrated 3.3V to 1.2V linear regulator. The linear regulator may be optionally disabled, allowing usage of a high efficiency external regulator for lower system power dissipation. DS00001909A-page 8 2015 Microchip Technology Inc. LAN9252 The LAN9252 is available in commercial, industrial, and extended industrial temperature ranges. Figure 2-1 details a typical system application, while Figure 2-2 provides an internal block diagram of the LAN9252. FIGURE 2-1: SYSTEM BLOCK DIAGRAM EtherCAT Slave EtherCAT Master EEPROM Microprocessor/ Microcontroller Local Bus LAN9252 Magnetics RJ45 Magnetics RJ45 PHY RJ45 EtherCAT Slave EtherCAT Slave 25MHz FIGURE 2-2: EtherCAT Slave INTERNAL BLOCK DIAGRAM LAN9252 Registers / RAM ESC Address Space Ethernet SyncManager 100 PHY w/ fiber FMMU Registers Port 0 Ethernet 100 PHY Auto Fowarder Loopback Auto Fowarder Loopback Auto Fowarder Loopback To 8/16-bit Host Bus, MII, SPI, Digital IOs, GPIOs w/ fiber Port 2 Registers Parallel Data Interface Port 1 EtherCAT Slave Controller MII LED Controller I2C EEPROM System Interrupt Controller To optional LEDs To I2C IRQ System Clocks/ Reset Controller External 25MHz Crystal The LAN9252 can operate in Microcontroller, Expansion, or Digital I/O mode: 2015 Microchip Technology Inc. DS00001909A-page 9 LAN9252 Microcontroller Mode: The LAN9252 communicates with the microcontroller through an SRAM-like slave interface. The simple, yet highly functional host bus interface provides a glue-less connection to most common 8 or 16-bit microprocessors and microcontrollers as well as 32-bit microprocessors with an 8 or 16-bit external bus. Alternatively, the device can be accessed via SPI or Quad SPI, while also providing up to 16 inputs or outputs for general purpose usage. Expansion Mode: While the device is in SPI or Quad SPI mode, a third networking port can be enabled to provide an additional MII port. This port can be connected to an external PHY, to enable star or tree network topologies, or to another LAN9252 to create a four port solution. This port can be configured for the upstream or downstream direction. Digital I/O Mode: For simple digital modules without microcontrollers, the LAN9252 can operate in Digital I/O Mode where 16 digital signals can be controlled or monitored by the EtherCAT master. Six control signals are also provided. Figure 2-3 provides a system level overview of each mode of operation. FIGURE 2-3: MODES OF OPERATION Microcontroller Mode Digital I/O Mode (via Host Bus Interface) Microprocessor/ Microcontroller RJ45 Host Bus Interface or Fiber RJ45 or Fiber Magnetics or Fiber Xcvr LAN9252 Magnetics or Fiber Xcvr Magnetics or Fiber Xcvr LAN9252 RJ45 Magnetics or Fiber Xcvr or Fiber Magnetics or Fiber Xcvr or Fiber RJ45 or Fiber Digital I/Os Microcontroller Mode Expansion Mode (via SPI) Microprocessor/ Microcontroller Microprocessor/ Microcontroller SPI / Quad SPI SPI / Quad SPI RJ45 or Fiber RJ45 or Fiber Magnetics or Fiber Xcvr LAN9252 Magnetics or Fiber Xcvr Magnetics or Fiber Xcvr LAN9252 RJ45 RJ45 or Fiber MII PHY GPIOs DS00001909A-page 10 Magnetics or Fiber Xcvr RJ45 or Fiber 2015 Microchip Technology Inc. LAN9252 3.0 PIN DESCRIPTIONS AND CONFIGURATION 3.1 64-QFN Pin Assignments RXPA RXNA TXPA TXNA VDD33TXRX1 D5/AD5/OUTVALID/SCS# D4/AD4/DIGIO3/GPI3/GPO3/MII_LINK 53 52 51 50 49 VDD33BIAS 54 VDD12TX2 58 55 RXPB 59 RBIAS RXNB 60 VDD12TX1 TXPB 61 56 TXNB 62 57 VDD33TXRX2 63 64-QFN PIN ASSIGNMENTS (TOP VIEW) 64 FIGURE 3-1: OSCI 1 48 LINKACTLED0/TDO/CHIP_MODE0 OSCO 2 47 VDDIO OSCVDD12 3 46 LINKACTLED1/TDI/CHIP_MODE1 OSCVSS 4 45 RUNLED/E2PSIZE VDD33 5 44 IRQ VDDCR 6 43 EESCL/TCK REG_EN 7 42 EESDA/TMS 41 TESTMODE 40 D8/AD8/DIGIO2/GPI2/GPO2/MII_MDIO D7/AD7/DIGIO1/GPI1/GPO1/MII_MDC LAN9252 FXLOSEN 8 FXSDA/FXLOSA/FXSDENA 9 FXSDB/FXLOSB/FXSDENB 10 39 RST# 11 38 VDDCR D2/AD2/SOF/SIO2 12 37 VDDIO D1/AD1/EOF/SO/SIO1 13 36 D6/AD6/DIGIO0/GPI0/GPO0/MII_RXCLK VDDIO 14 35 D3/AD3/WD_TRIG/SIO3 D14/AD14/DIGIO8/GPI8/GPO8/MII_TXD3/TX_SHIFT1 15 34 SYNC0/LATCH0 D13/AD13/DIGIO7/GPI7/GPO7/MII_TXD2/TX_SHIFT0 16 33 A0/D15/AD15/DIGIO9/GPI9/GPO9/MII_RXER 64-QFN ( To p V i e w) VSS 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 D9/AD9/LATCH_IN/SCK VDDIO D12/AD12/DIGIO6/GPI6/GPO6/MII_TXD1 D11/AD11/DIGIO5/GPI5/GPO5/MII_TXD0 D10/AD10/DIGIO4/GPI4/GPO4/MII_TXEN VDDCR A1/ALELO/OE_EXT/MII_CLK25 A3/DIGIO11/GPI11/GPO11/MII_RXDV A4/DIGIO12/GPI12/GPO12/MII_RXD0 CS/DIGIO13/GPI13/GPO13/MII_RXD1 A2/ALEHI/DIGIO10/GPI10/GPO10/ LINKACTLED2/MII_LINKPOL WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD2 RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD3 VDDIO 17 D0/AD0/WD_STATE/SI/SIO0 SYNC1/LATCH1 (Connect exposed pad to ground with a via field) Note: Exposed pad (VSS) on bottom of package must be connected to ground with a via field. Note: When a “#” is used at the end of the signal name, it indicates that the signal is active low. For example, RST# indicates that the reset signal is active low. The buffer type for each signal is indicated in the “Buffer Type” column of the pin description tables in Section 3.3, "Pin Descriptions". A description of the buffer types is provided in Section 1.2, "Buffer Types". 2015 Microchip Technology Inc. DS00001909A-page 11 LAN9252 Table 3-1 details the 64-QFN package pin assignments in table format. As shown, select pin functions may change based on the device’s mode of operation. For modes where a specific pin has no function, the table cell will be marked with “-”. TABLE 3-1: Pin Number 64-QFN PACKAGE PIN ASSIGNMENTS HBI Indexed Mode Pin Name HBI Multiplexed Mode Pin Name Digital I/O Mode Pin Name SPI with GPIO Mode Pin Name 1 OSCI 2 OSCO 3 OSCVDD12 4 OSCVSS 5 VDD33 6 VDDCR 7 REG_EN 8 FXLOSEN 9 FXSDA/FXLOSA/FXSDENA 10 FXSDB/FXLOSB/FXSDENB 11 RST# SPI with MII Mode Pin Name 12 D2 AD2 SOF SIO2 13 D1 AD1 EOF SO/SIO1 14 VDDIO 15 D14 AD14 DIGIO8 GPI8/GPO8 MII_TXD3/ TX_SHIFT1 16 D13 AD13 DIGIO7 GPI7/GPO7 MII_TXD2/ TX_SHIFT0 17 D0 AD0 WD_STATE 18 SI/SIO0 SYNC1/LATCH1 19 D9 AD9 20 LATCH_IN SCK VDDIO 21 D12 AD12 DIGIO6 GPI6/GPO6 MII_TXD1 22 D11 AD11 DIGIO5 GPI5/GPO5 MII_TXD0 23 D10 AD10 DIGIO4 GPI4/GPO4 MII_TXEN 24 VDDCR 25 A1 ALELO OE_EXT - MII_CLK25 26 A3 - DIGIO11 GPI11/GPO11 MII_RXDV 27 A4 - DIGIO12 GPI12/GPO12 MII_RXD0 DIGIO13 GPI13/GPO13 MII_RXD1 DIGIO10 GPI10/GPO10 LINKACTLED2/ MII_LINKPOL DIGIO14 GPI14/GPO14 MII_RXD2 28 29 30 DS00001909A-page 12 CS A2 ALEHI WR/ENB 2015 Microchip Technology Inc. LAN9252 TABLE 3-1: Pin Number 64-QFN PACKAGE PIN ASSIGNMENTS (CONTINUED) HBI Indexed Mode Pin Name 31 HBI Multiplexed Mode Pin Name RD/RD_WR 32 33 Digital I/O Mode Pin Name SPI with GPIO Mode Pin Name SPI with MII Mode Pin Name DIGIO15 GPI15/GPO15 MII_RXD3 GPI9/GPO9 MII_RXER VDDIO A0/D15 AD15 34 DIGIO9 SYNC0/LATCH0 35 D3 AD3 WD_TRIG 36 D6 AD6 DIGIO0 37 VDDIO 38 VDDCR SIO3 GPI0/GPO0 MII_RXCLK 39 D7 AD7 DIGIO1 GPI1/GPO1 MII_MDC 40 D8 AD8 DIGIO2 GPI2/GPO2 MII_MDIO 41 TESTMODE 42 EESDA/TMS 43 EESCL/TCK 44 IRQ 45 RUNLED/E2PSIZE 46 LINKACTLED1/TDI/CHIP_MODE1 47 VDDIO 48 LINKACTLED0/TDO/CHIP_MODE0 49 D4 AD4 DIGIO3 50 D5 AD5 OUTVALID 51 VDD33TXRX1 52 TXNA 53 TXPA 54 RXNA 55 RXPA 56 VDD12TX1 57 RBIAS 58 VDD33BIAS 59 VDD12TX2 60 RXPB 61 RXNB 62 TXPB 63 TXNB 64 VDD33TXRX2 Exposed Pad VSS 2015 Microchip Technology Inc. GPI3/GPO3 MII_LINK SCS# DS00001909A-page 13 LAN9252 64-TQFP-EP Pin Assignments LINKACTLED0/TDO/CHIP_MODE0 VDDIO LINKACTLED1/TDI/CHIP_MODE1 RUNLED/E2PSIZE IRQ EESCL/TCK EESDA/TMS TESTMODE D8/AD8/DIGIO2/GPI2/GPO2/MII_MDIO D7/AD7/DIGIO1/GPI1/GPO1/MII_MDC VDDCR VDDIO D6/AD6/DIGIO0/GPI0/GPO0/MII_RXCLK D3/AD3/WD_TRIG/SIO3 SYNC0/LATCH0 A0/D15/AD15/DIGIO9/GPI9/GPO9/MII_RXER 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64-TQFP-EP PIN ASSIGNMENTS (TOP VIEW) 47 FIGURE 3-2: 48 3.2 D4/AD4/DIGIO3/GPI3/GPO3/MII_LINK 49 32 VDDIO D5/AD5/OUTVALID/SCS# 50 31 RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD3 VDD33TXRX1 51 30 WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD2 TXNA 52 29 A2/ALEHI/DIGIO10/GPI10/GPO10/ LINKACTLED2/MII_LINKPOL TXPA 53 28 CS/DIGIO13/GPI13/GPO13/MII_RXD1 RXNA 54 27 A4/DIGIO12/GPI12/GPO12/MII_RXD0 RXPA 55 26 A3/DIGIO11/GPI11/GPO11/MII_RXDV VDD12TX1 56 25 A1/ALELO/OE_EXT/MII_CLK25 RBIAS 57 24 VDDCR VDD33BIAS 58 23 D10/AD10/DIGIO4/GPI4/GPO4/MII_TXEN VDD12TX2 59 22 D11/AD11/DIGIO5/GPI5/GPO5/MII_TXD0 RXPB 60 21 D12/AD12/DIGIO6/GPI6/GPO6/MII_TXD1 RXNB 61 20 VDDIO TXPB 62 19 D9/AD9/LATCH_IN/SCK TXNB 63 18 SYNC1/LATCH1 VDD33TXRX2 64 17 D0/AD0/WD_STATE/SI/SIO0 LAN9252 64-TQFP-EP ( T o p V i e w) VSS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OSCVDD12 OSCVSS VDD33 VDDCR REG_EN FXLOSEN FXSDA/FXLOSA/FXSDENA FXSDB/FXLOSB/FXSDENB RST# D2/AD2/SOF/SIO2 D1/AD1/EOF/SO/SIO1 VDDIO D14/AD14/DIGIO8/GPI8/GPO8/MII_TXD3/TX_SHIFT1 D13/AD13/DIGIO7/GPI7/GPO7/MII_TXD2/TX_SHIFT0 1 OSCI OSCO (Connect exposed pad to ground with a via field) Note: Exposed pad (VSS) on bottom of package must be connected to ground with a via field. . Note: When an “#” is used at the end of the signal name, it indicates that the signal is active low. For example, RST# indicates that the reset signal is active low. The buffer type for each signal is indicated in the “Buffer Type” column of the pin description tables in Section 3.3, "Pin Descriptions". A description of the buffer types is provided in Section 1.2, "Buffer Types". DS00001909A-page 14 2015 Microchip Technology Inc. LAN9252 Table 3-2 details the 64-TQFP-EP package pin assignments in table format. As shown, select pin functions may change based on the device’s mode of operation. For modes where a specific pin has no function, the table cell will be marked with “-”. TABLE 3-2: Pin Number 64-TQFP-EP PACKAGE PIN ASSIGNMENTS HBI Indexed Mode Pin Name HBI Multiplexed Mode Pin Name Digital I/O Mode Pin Name SPI with GPIO Mode Pin Name 1 OSCI 2 OSCO 3 OSCVDD12 4 OSCVSS 5 VDD33 6 VDDCR 7 REG_EN 8 FXLOSEN 9 FXSDA/FXLOSA/FXSDENA 10 FXSDB/FXLOSB/FXSDENB 11 RST# SPI with MII Mode Pin Name 12 D2 AD2 SOF SIO2 13 D1 AD1 EOF SO/SIO1 14 VDDIO 15 D14 AD14 DIGIO8 GPI8/GPO8 MII_TXD3/ TX_SHIFT1 16 D13 AD13 DIGIO7 GPI7/GPO7 MII_TXD2/ TX_SHIFT0 17 D0 AD0 WD_STATE 18 19 SI/SIO0 SYNC1/LATCH1 D9 AD9 20 LATCH_IN SCK VDDIO 21 D12 AD12 DIGIO6 GPI6/GPO6 MII_TXD1 22 D11 AD11 DIGIO5 GPI5/GPO5 MII_TXD0 23 D10 AD10 DIGIO4 GPI4/GPO4 MII_TXEN 24 VDDCR 25 A1 ALELO OE_EXT - MII_CLK25 26 A3 - DIGIO11 GPI11/GPO11 MII_RXDV 27 A4 - DIGIO12 GPI12/GPO12 MII_RXD0 DIGIO13 GPI13/GPO13 MII_RXD1 DIGIO10 GPI10/GPO10 LINKACTLED2/ MII_LINKPOL DIGIO14 GPI14/GPO14 MII_RXD2 28 29 30 CS A2 ALEHI WR/ENB 2015 Microchip Technology Inc. DS00001909A-page 15 LAN9252 TABLE 3-2: Pin Number 64-TQFP-EP PACKAGE PIN ASSIGNMENTS (CONTINUED) HBI Indexed Mode Pin Name 31 HBI Multiplexed Mode Pin Name RD/RD_WR 32 33 Digital I/O Mode Pin Name SPI with GPIO Mode Pin Name SPI with MII Mode Pin Name DIGIO15 GPI15/GPO15 MII_RXD3 GPI9/GPO9 MII_RXER VDDIO A0/D15 AD15 34 DIGIO9 SYNC0/LATCH0 35 D3 AD3 WD_TRIG 36 D6 AD6 DIGIO0 37 VDDIO 38 VDDCR SIO3 GPI0/GPO0 MII_RXCLK 39 D7 AD7 DIGIO1 GPI1/GPO1 MII_MDC 40 D8 AD8 DIGIO2 GPI2/GPO2 MII_MDIO 41 TESTMODE 42 EESDA/TMS 43 EESCL/TCK 44 IRQ 45 RUNLED/E2PSIZE 46 LINKACTLED1/TDI/CHIP_MODE1 47 VDDIO 48 LINKACTLED0/TDO/CHIP_MODE0 49 D4 AD4 DIGIO3 50 D5 AD5 OUTVALID 51 VDD33TXRX1 52 TXNA 53 TXPA 54 RXNA 55 RXPA 56 VDD12TX1 57 RBIAS 58 VDD33BIAS 59 VDD12TX2 60 RXPB 61 RXNB 62 TXPB 63 TXNB 64 VDD33TXRX2 Exposed Pad VSS DS00001909A-page 16 GPI3/GPO3 MII_LINK SCS# 2015 Microchip Technology Inc. LAN9252 3.3 Pin Descriptions This section contains descriptions of the various LAN9252 pins. The pin descriptions have been broken into functional groups as follows: • • • • • • • • • • • • • LAN Port A Pin Descriptions LAN Port B Pin Descriptions LAN Port A & B Power and Common Pin Descriptions EtherCAT MII Port & Configuration Strap Pin Descriptions Host Bus Pin Descriptions SPI/SQI Pin Descriptions EtherCAT Distributed Clock Pin Descriptions EtherCAT Digital I/O and GPIO Pin Descriptions EEPROM Pin Descriptions LED & Configuration Strap Pin Descriptions Miscellaneous Pin Descriptions JTAG Pin Descriptions Core and I/O Power Pin Descriptions TABLE 3-3: Num Pins 1 1 1 1 LAN PORT A PIN DESCRIPTIONS Name Port A TP TX/RX Positive Channel 1 Symbol Buffer Type AIO OLVPECL Port A TP TX/RX Negative Channel 1 AIO Port A Fiber Transmit Positive. Port A Twisted Pair Transmit/Receive Negative Channel 1. See Note 1. TXNA Port A FX TX Negative OLVPECL Port A TP TX/RX Positive Channel 2 AIO Port A Fiber Transmit Negative. Port A Twisted Pair Transmit/Receive Positive Channel 2. See Note 1. RXPA Port A FX RX Positive AI Port A TP TX/RX Negative Channel 2 AIO 2015 Microchip Technology Inc. Port A Twisted Pair Transmit/Receive Positive Channel 1. See Note 1 TXPA Port A FX TX Positive Port A FX RX Negative Description Port A Fiber Receive Positive. Port A Twisted Pair Transmit/Receive Negative Channel 2. See Note 1. RXNA AI Port A Fiber Receive Negative. DS00001909A-page 17 LAN9252 TABLE 3-3: Num Pins LAN PORT A PIN DESCRIPTIONS (CONTINUED) Name Port A FX Signal Detect (SD) Symbol FXSDA Buffer Type ILVPECL Description Port A Fiber Signal Detect. When FX-LOS mode is not selected, this pin functions as the Signal Detect input from the external transceiver. A level above 2 V (typ.) indicates valid signal. When FX-LOS mode is selected, the input buffer is disabled. Port A FX Loss Of Signal (LOS) 1 FXLOSA IS (PU) Port A Fiber Loss of Signal. When FX-LOS mode is selected (via fx_los_strap_1), this pin functions as the Loss of Signal input from the external transceiver. A high indicates LOS while a low indicates valid signal. When FX-LOS mode is not selected, the input buffer and pull-up are disabled. Port A FX-SD Enable Strap Port A FX-SD Enable. When FX-LOS mode is not selected, this strap input selects between FX-SD and copper twisted pair mode. A level above 1 V (typ.) selects FX-SD. FXSDENA AI When FX-LOS mode is selected, the input buffer is disabled. See Note 2. Note 1: In copper mode, either channel 1 or 2 may function as the transmit pair while the other channel functions as the receive pair. The pin name symbols for the twisted pair pins apply to a normal connection. If HP AutoMDIX is enabled and a reverse connection is detected or manually selected, the RX and TX pins will be swapped internally. Note 2: Configuration strap pins are identified by an underlined symbol name. Configuration strap values are latched on power-on reset or RST# de-assertion. Refer to Section 7.0, "Configuration Straps," on page 51 for more information. Note: Port A is connected to the EtherCAT port 0 or 2. TABLE 3-4: Num Pins 1 1 LAN PORT B PIN DESCRIPTIONS Name Port B TP TX/RX Positive Channel 1 Symbol Buffer Type AIO OLVPECL Port B TP TX/RX Negative Channel 1 AIO DS00001909A-page 18 Port B Twisted Pair Transmit/Receive Positive Channel 1. See Note 3 TXPB Port B FX TX Positive Port B FX TX Negative Description Port B Fiber Transmit Positive. Port B Twisted Pair Transmit/Receive Negative Channel 1. See Note 3. TXNB OLVPECL Port B Fiber Transmit Negative. 2015 Microchip Technology Inc. LAN9252 TABLE 3-4: Num Pins 1 1 LAN PORT B PIN DESCRIPTIONS (CONTINUED) Name Port BTP TX/RX Positive Channel 2 Symbol Buffer Type AIO Port B Twisted Pair Transmit/Receive Positive Channel 2. See Note 3. RXPB Port B FX RX Positive AI Port B TP TX/RX Negative Channel 2 AIO Port B Fiber Receive Positive. Port B Twisted Pair Transmit/Receive Negative Channel 2. See Note 3. RXNB Port B FX RX Negative Port B FX Signal Detect (SD) Description AI FXSDB ILVPECL Port B Fiber Receive Negative. Port B Fiber Signal Detect. When FX-LOS mode is not selected, this pin functions as the Signal Detect input from the external transceiver. A level above 2 V (typ.) indicates valid signal. When FX-LOS mode is selected, the input buffer is disabled. 1 Port B FX Loss Of Signal (LOS) FXLOSB IS (PU) Port B Fiber Loss of Signal. When FX-LOS mode is selected (via fx_los_strap_2), this pin functions as the Loss of Signal input from the external transceiver. A high indicates LOS while a low indicates valid signal. When FX-LOS mode is not selected, the input buffer and pull-up are disabled. Port B FX-SD Enable Strap Port B FX-SD Enable. When FX-LOS mode is not selected, this strap input selects between FX-SD and copper twisted pair mode. A level above 1 V (typ.) selects FX-SD. FXSDENB AI When FX-LOS mode is selected, the input buffer is disabled. See Note 4. Note 3: In copper mode, either channel 1 or 2 may function as the transmit pair while the other channel functions as the receive pair. The pin name symbols for the twisted pair pins apply to a normal connection. If HP AutoMDIX is enabled and a reverse connection is detected or manually selected, the RX and TX pins will be swapped internally. Note 4: Configuration strap pins are identified by an underlined symbol name. Configuration strap values are latched on power-on reset or RST# de-assertion. Refer to Section 7.0, "Configuration Straps," on page 51 for more information. Note: Port B is connected to EtherCAT port 1. 2015 Microchip Technology Inc. DS00001909A-page 19 LAN9252 TABLE 3-5: Num Pins LAN PORT A & B POWER AND COMMON PIN DESCRIPTIONS Name Symbol Buffer Type Description Used for internal bias circuits. Connect to an external 12.1 kΩ, 1% resistor to ground. 1 Bias Reference RBIAS AI Refer to the device reference schematic for connection information. Note: The nominal voltage is 1.2 V and the resistor will dissipate approximately 1 mW of power. Port A and B FX-LOS Enable. This 3 level strap input selects between FX-LOS and FX-SD / copper twisted pair mode. 1 Port A and B FX-LOS Enable Strap FXLOSEN AI A level below 1 V (typ.) selects FX-SD / copper twisted pair for ports A and B, further determined by FXSDENA and FXSDENB. A level of 1.5 V selects FX-LOS for port A and FXSD / copper twisted pair for port B, further determined by FXSDENB. A level above 2 V (typ.) selects FX-LOS for ports A and B. 1 +3.3 V Port A Analog Power Supply VDD33TXRX1 P See Note 5. 1 +3.3 V Port B Analog Power Supply VDD33TXRX2 P 1 +3.3 V Master Bias Power Supply VDD33BIAS P 1 Port A Transmitter +1.2 V Power Supply See Note 5. See Note 5. VDD12TX1 P This pin is supplied from either an external 1.2 V supply or from the device’s internal regulator via the PCB. This pin must be tied to the VDD12TX2 pin for proper operation. See Note 5. 1 Port B Transmitter +1.2 V Power Supply VDD12TX2 P This pin is supplied from either an external 1.2 V supply or from the device’s internal regulator via the PCB. This pin must be tied to the VDD12TX1 pin for proper operation. See Note 5. Note 5: Refer to Section 4.0, "Power Connections," on page 29, the device reference schematics, and the device LANCheck schematic checklist for additional connection information. DS00001909A-page 20 2015 Microchip Technology Inc. LAN9252 TABLE 3-6: ETHERCAT MII PORT & CONFIGURATION STRAP PIN DESCRIPTIONS Num Pins Name Symbol Buffer Type Description 1 25 MHz Clock MII_CLK25 VO12 Note 6 This pin is a free-running 25 MHz clock that can be used as the clock input to the PHY. 4 Receive Data MII Port MII_RXD[3:0] VIS (PD) These pins are the receive data from the external PHY. 1 Receive Data Valid MII Port MII_RXDV VIS (PD) This pin is the receive data valid signal from the external PHY. 1 Receive Error MII Port MII_RXER VIS (PD) This pin is the receive error signal from the external PHY. 1 Receive Clock MII Port MII_RXCLK VIS (PD) This pin is the receive clock from the external PHY. Transmit Data MII Port MII_TXD[3:0] VO8 MII Transmit Timing Shift Configuration Strap TX_SHIFT[1:0] VIS (PU) Note 7 1 Transmit Data Enable MII Port MII_TXEN VO8 This pin is the transmit data enable signal to the external PHY. 1 Link Status MII Port MII_LINK VIS This pin is the provided by the PHY to indicate that a 100 Mbit/s Full Duplex link is established. The polarity is configurable via the link_pol_strap_mii strap. 1 SMI Clock MII_MDC VO8 This pin is the serial management clock to the external PHY. 4 These pins are the transmit data to the external PHY. These straps configure the value of the external MII Bus TX timing shift hard-strap. See Note 8. TX_SHIFT[1] is on MII_TXD[3] and TX_SHIFT[0] is on MII_TXD[2]. This pin is the serial management interface data input/output to the external PHY. 1 SMI Data MII_MDIO VIS/VO8 Note: An external pull-up is required to ensure that the non-driven state of the MDIO signal is a logic one. Note 6: A series terminating resistor is recommended for the best PCB signal integrity. Note 7: An external supplemental pull-up may be needed, depending upon the input current loading of the external MAC/PHY device. Note 8: Configuration strap pins are identified by an underlined symbol name. Configuration strap values are latched on power-on reset or RST# de-assertion. Refer to Section 7.0, "Configuration Straps," on page 51 for more information. 2015 Microchip Technology Inc. DS00001909A-page 21 LAN9252 TABLE 3-7: Num Pins HOST BUS PIN DESCRIPTIONS Name Symbol Buffer Type Description This pin is the host bus read strobe. Read RD VIS Normally active low, the polarity can be changed via the HBI Read, Read/Write Polarity bit of the PDI Configuration Register (HBI Modes). This pin is the host bus direction control. Used in conjunction with the ENB pin, it indicates a read or write operation. 1 Read or Write RD_WR VIS The normal polarity is read when 1, write when 0 (R/ nW) but can be changed via the HBI Read, Read/ Write Polarity bit of the PDI Configuration Register (HBI Modes). This pin is the host bus write strobe. Write WR VIS Normally active low, the polarity can be changed via the HBI Write, Enable Polarity bit of the PDI Configuration Register (HBI Modes). This pin is the host bus data enable strobe. Used in conjunction with the RD_WR pin it indicates the data phase of the operation. 1 Enable ENB VIS Normally active low, the polarity can be changed via the HBI Write, Enable Polarity bit of the PDI Configuration Register (HBI Modes). This pin is the host bus chip select and indicates that the device is selected for the current transfer. 1 5 Chip Select Address CS A[4:0] VIS VIS Normally active low, the polarity can be changed via the HBI Chip Select Polarity bit of the PDI Configuration Register (HBI Modes). These pins provide the address for non-multiplexed address mode. In 16-bit data mode, bit 0 is not used. DS00001909A-page 22 2015 Microchip Technology Inc. LAN9252 TABLE 3-7: Num Pins HOST BUS PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Description These pins are the host bus data bus for non-multiplexed address mode. Data D[15:0] VIS/VO8 In 8-bit data mode, bits 15-8 are not used and their input and output drivers are disabled. These pins are the host bus address / data bus for multiplexed address mode. Bits 15-8 provide the upper byte of address for single phase multiplexed address mode. 16 Address & Data AD[15:0] VIS/VO8 Bits 7-0 provide the lower byte of address for single phase multiplexed address mode and both bytes of address for dual phase multiplexed address mode. In 8-bit data dual phase multiplexed address mode, bits 15-8 are not used and their input and output drivers are disabled. 1 1 Address Latch Enable High Address Latch Enable Low This pin indicates the address phase for multiplexed address modes. It is used to load the higher address byte in dual phase multiplexed address mode. ALEHI VIS Normally active low (address saved on rising edge), the polarity can be changed via the HBI ALE Polarity bit of the PDI Configuration Register (HBI Modes). ALELO VIS This pin indicates the address phase for multiplexed address modes. It is used to load both address bytes in single phase multiplexed address mode and the lower address byte in dual phase multiplexed address mode. Normally active low (address saved on rising edge), the polarity can be changed via the HBI ALE Polarity bit of the PDI Configuration Register (HBI Modes). 2015 Microchip Technology Inc. DS00001909A-page 23 LAN9252 TABLE 3-8: SPI/SQI PIN DESCRIPTIONS Num Pins Name Symbol Buffer Type Description 1 SPI/SQI Slave Chip Select SCS# VIS (PU) This pin is the SPI/SQI slave chip select input. When low, the SPI/SQI slave is selected for SPI/SQI transfers. When high, the SPI/SQI serial data output(s) is(are) 3-stated. 1 SPI/SQI Slave Serial Clock SCK VIS (PU) SPI/SQI Slave Serial Data Input/Output SIO[3:0] VIS/VO8 (PU) SPI Slave Serial Data Input SI VIS (PU) SPI Slave Serial Data Output SO VO8 (PU) Note 9 4 This pin is the SPI/SQI slave serial clock input. These pins are the SPI/SQI slave data input and output for multiple bit I/O. This pin is the SPI slave serial data input. SI is shared with the SIO0 pin. This pin is the SPI slave serial data output. SO is shared with the SIO1 pin. Note 9: Although this pin is an output for SPI instructions, it includes a pull-up since it is also SIO bit 1. TABLE 3-9: Num Pins ETHERCAT DISTRIBUTED CLOCK PIN DESCRIPTIONS Name Symbol Buffer Type Description Sync SYNC[1] SYNC[0] VO8 These pins are the Distributed Clock Sync (OUT) or Latch (IN) signals. The direction is bitwise configurable. Latch LATCH[1] LATCH[0] VIS 2 TABLE 3-10: Num Pins Note: These signals are not driven (high impedance) until the EEPROM is loaded. ETHERCAT DIGITAL I/O AND GPIO PIN DESCRIPTIONS Name General Purpose Input Symbol GPI[15:0] Buffer Type Description VIS These pins are the general purpose inputs and are directly mapped into the General Purpose Inputs Register. Consistency of the general purpose inputs is not provided. 16 General Purpose Output GPO[15:0] VO8 These pins are the general purpose outputs and reflect the values of the General Purpose Outputs Register without watchdog protection. Note: These signals are not driven (high impedance) until the EEPROM is loaded. These pins are the input/output or bidirectional data. 16 1 Digital I/O Output Valid DS00001909A-page 24 DIGIO[15:0] OUTVALID VIS/VO8 VO8 Note: These signals are not driven (high impedance) until the EEPROM is loaded. This pin indicates that the outputs are valid and can be captured into external registers. Note: The signal is not driven (high impedance) until the EEPROM is loaded. 2015 Microchip Technology Inc. LAN9252 TABLE 3-10: ETHERCAT DIGITAL I/O AND GPIO PIN DESCRIPTIONS (CONTINUED) Num Pins Name Symbol Buffer Type 1 Latch In LATCH_IN VIS 1 Watchdog Trigger 1 Watchdog State 1 Start of Frame VO8 WD_TRIG VO8 WD_STATE VO8 SOF 1 End of Frame EOF VO8 1 Output Enable OE_EXT VIS TABLE 3-11: Num Pins Description This pin is the external data latch signal. The input data is sampled each time a rising edge of LATCH_IN is recognized. This pin is the SyncManager Watchdog Trigger output. Note: The signal is not driven (high impedance) until the EEPROM is loaded. This pin is the SyncManager Watchdog State output. A 0 indicates the watchdog has expired. Note: The signal is not driven (high impedance) until the EEPROM is loaded. This pin is the Start of Frame output and indicates the start of an Ethernet/EtherCAT frame. Note: The signal is not driven (high impedance) until the EEPROM is loaded. This pin is the End of Frame output and indicates the end of an Ethernet/EtherCAT frame. Note: The signal is not driven (high impedance) until the EEPROM is loaded. This pin is the Output Enable input. When low, it clears the output data. EEPROM PIN DESCRIPTIONS Name Symbol I2C 1 EEPROM Serial Data Input/Output 1 EEPROM I2C Serial Clock 2015 Microchip Technology Inc. EESDA EESCL Buffer Type Description When the device is accessing an external EEPROM this pin is the I2C serial data input/open-drain outVIS/VOD8 put. Note: This pin must be pulled-up by an external resistor at all times. VOD8 When the device is accessing an external EEPROM this pin is the I2C clock open-drain output. Note: This pin must be pulled-up by an external resistor at all times. DS00001909A-page 25 LAN9252 TABLE 3-12: Num Pins LED & CONFIGURATION STRAP PIN DESCRIPTIONS Name Symbol Buffer Type Description This pin is the Link/Activity LED output (off=no link, on=link without activity, blinking=link and activity) for port 2. Link/Activity LED Port 2 LINKACTLED2 VOD12/ VOS12 1 This pin is configured to be an open-drain/opensource output. The choice of open-drain vs. opensource as well as the polarity of this pin depends upon the strap value sampled at reset. Note: MII Port Link Polarity Configuration Strap MII_LINKPOL VIS (PU) Refer to Section 12.10, "LEDs," on page 208 to additional information. This strap configures the polarity of the MII_LINK pin by setting the value of link_pol_strap_mii. See Note 10. This pin is the Run LED output and is controlled by the AL Status Register. Run LED RUNLED VOD12/ VOS12 This pin is configured to be open-drain/open-source output. The choice of open-drain vs. open-source as well as the polarity of this pin depends upon the strap value sampled at reset. Note: 1 Refer to Section 12.10, "LEDs," on page 208 to additional information. This strap configures the value of the EEPROM size hard-strap. See Note 10. EEPROM Size Configuration Strap E2PSIZE VIS (PU) A low selects 1K bits (128 x 8) through 16K bits (2K x 8). A high selects 32K bits (4K x 8) through 4Mbits (512K x 8). This pin is the Link/Activity LED output (off=no link, on=link without activity, blinking=link and activity) for port 1. Link / Activity LED Port 1 LINKACTLED1 VOD12/ VOS12 1 This pin is configured to be open-drain/open-source output. The choice of open-drain vs. open-source as well as the polarity of this pin depends upon the strap value sampled at reset. Note: Chip Mode Configuration Strap 1 DS00001909A-page 26 CHIP_MODE1 VIS (PU) Refer to Section 12.10, "LEDs," on page 208 to additional information. This strap, along with CHIP_MODE0, configures the value of the Chip Mode hard-strap. See Note 10. 2015 Microchip Technology Inc. LAN9252 TABLE 3-12: Num Pins LED & CONFIGURATION STRAP PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Description This pin is the Link/Activity LED output (off=no link, on=link without activity, blinking=link and activity) for port 0. Link / Activity LED Port 0 LINKACTLED0 VOD12/ VOS12 1 This pin is configured to be open-drain/open-source output. The choice of open-drain vs. open-source as well as the polarity of this pin depends upon the strap value sampled at reset. Note: Chip Mode Configuration Strap 0 CHIP_MODE0 VIS (PU) Refer to Section 12.10, "LEDs," on page 208 to additional information. This strap, along with CHIP_MODE1, configures the value of the Chip Mode hard-strap. See Note 10. Note 10: Configuration strap pins are identified by an underlined symbol name. Configuration strap values are latched on power-on reset or RST# de-assertion. Refer to Section 7.0, "Configuration Straps," on page 51 for more information. TABLE 3-13: Num Pins 1 1 MISCELLANEOUS PIN DESCRIPTIONS Name Interrupt Output System Reset Input Symbol IRQ RST# Buffer Type Description Interrupt request output. The polarity, source and buffer type of this signal is programmable via the VO8/VOD8 Interrupt Configuration Register (IRQ_CFG). For more information, refer to Section 8.0, "System Interrupts," on page 53. As an input, this active low signal allows external hardware to reset the device. The device also contains an internal power-on reset circuit. Thus this signal may be left unconnected if an external hardware reset is not needed. When used this signal must adhere to the reset timing requirements as VIS/VOD8 detailed in the Section 18.0, "Operational Character(PU) istics," on page 307. As an output, this signal is driven low during POR or in response to an EtherCAT reset command sequence from the Master Controller or Host interface. 1 Regulator Enable REG_EN AI 1 Test Mode TESTMODE VIS (PD) When tied to 3.3 V, the internal 1.2 V regulators are enabled. This pin must be tied to VSS for proper operation. 1 Crystal Input OSCI ICLK External 25 MHz crystal input. This signal can also be driven by a single-ended clock oscillator. When this method is used, OSCO should be left unconnected. 1 Crystal Output OSCO OCLK External 25 MHz crystal output. 1 Crystal +1.2 V Power Supply OSCVDD12 P Supplied by the on-chip regulator unless configured for regulator off mode via REG_EN. 1 Crystal Ground OSCVSS P Crystal ground. 2015 Microchip Technology Inc. DS00001909A-page 27 LAN9252 TABLE 3-14: JTAG PIN DESCRIPTIONS Num Pins Name Symbol Buffer Type 1 JTAG Test Mux Select TMS VIS 1 JTAG Test Clock TCK VIS 1 JTAG Test Data Input TDI VIS 1 JTAG Test Data Output TDO VO12 TABLE 3-15: JTAG test mode select JTAG test clock JTAG data input JTAG data output CORE AND I/O POWER PIN DESCRIPTIONS Num Pins Name 1 Regulator +3.3 V Power Supply VDD33 P 5 +1.8 V to +3.3 V Variable I/O Power VDDIO P 3 +1.2 V Digital Core Power Supply VDDCR Ground VSS 1 pad Description Symbol Buffer Type Description +3.3 V power supply for internal regulators. See Note 11. Note: +3.3 V must be supplied to this pin even if the internal regulators are disabled. +1.8 V to +3.3 V variable I/O power. See Note 11. Supplied by the on-chip regulator unless configured for regulator off mode via REG_EN. P 1 µF and 470 pF decoupling capacitors in parallel to ground should be used on pin 6. See Note 11. P Common ground. This exposed pad must be connected to the ground plane with a via array. Note 11: Refer to Section 4.0, "Power Connections," on page 29, the device reference schematic, and the device LANCheck schematic checklist for additional connection information. DS00001909A-page 28 2015 Microchip Technology Inc. LAN9252 4.0 POWER CONNECTIONS Figure 4-1 and Figure 4-2 illustrate the device power connections for regulator enabled and disabled cases, respectively. Refer to the device reference schematic and the device LANCheck schematic checklist for additional information. Section 4.1 provides additional information on the devices internal voltage regulators. FIGURE 4-1: POWER CONNECTIONS - REGULATORS ENABLED +1.8 V to +3.3 V VDDIO IO Pads VDDIO VDDCR VDDCR VDDIO VDDIO VDDIO Core Logic & PHY digital +3.3 V VDD33 Internal 1.2 V Core Regulator +1.2 V (OUT) +3.3 V (IN) VDDCR (Pin 6) enable 470 pF REG_EN Internal 1.2 V Oscillator Regulator +1.2 V (OUT) +3.3 V +3.3 V (IN) enable 1.0 µF 0.1 ESR OSCVDD12 VSS Crystal Oscillator VSS OSCVSS To PHY1 Magnetics (or separate 2.5V) VDD33TXRX1 Ethernet PHY 1 Analog VDD33BIAS Ethernet Master Bias VDD33TXRX2 Ethernet PHY 2 Analog VDD12TX1 To PHY2 Magnetics (or separate 2.5V) VSS (exposed pad) VDD12TX2 PLL Note: Bypass and bulk caps as needed for PCB 2015 Microchip Technology Inc. DS00001909A-page 29 LAN9252 FIGURE 4-2: POWER CONNECTIONS - REGULATORS DISABLED +1.2 V +1.8 V to +3.3 V VDDIO IO Pads VDDIO VDDCR VDDCR VDDIO VDDIO Core Logic & PHY digital VDDIO +3.3 V VDD33 Internal 1.2 V Core Regulator +1.2 V (OUT) +3.3 V (IN) VDDCR (Pin 6) enable REG_EN Internal 1.2 V Oscillator Regulator +1.2 V (OUT) +3.3 V +3.3 V (IN) enable OSCVDD12 VSS Crystal Oscillator VSS OSCVSS To PHY1 Magnetics (or separate 2.5V) VDD33TXRX1 Ethernet PHY 1 Analog VDD33BIAS Ethernet Master Bias VDD33TXRX2 Ethernet PHY 2 Analog VDD12TX1 To PHY2 Magnetics (or separate 2.5V) VSS (exposed pad) VDD12TX2 PLL Note: Bypass and bulk caps as needed for PCB DS00001909A-page 30 2015 Microchip Technology Inc. LAN9252 4.1 Internal Voltage Regulators The device contains two internal 1.2 V regulators: • 1.2 V Core Regulator • 1.2 V Crystal Oscillator Regulator 4.1.1 1.2 V CORE REGULATOR The core regulator supplies 1.2 V volts to the main core digital logic, the I/O pads, and the PHYs’ digital logic and can be used to supply the 1.2 V power to the PHY analog sections (via an external connection). When the REG_EN input pin is connected to 3.3 V, the core regulator is enabled and receives 3.3 V on the VDD33 pin. A 1.0 uF 0.1 ESR capacitor must be connected to the VDDCR pin associated with the regulator. When the REG_EN input pin is connected to VSS, the core regulator is disabled. However, 3.3 V must still be supplied to the VDD33 pin. The 1.2 V core voltage must then be externally input into the VDDCR pins. 4.1.2 1.2 V CRYSTAL OSCILLATOR REGULATOR The crystal oscillator regulator supplies 1.2 V volts to the crystal oscillator. When the REG_EN input pin is connected to 3.3 V, the crystal oscillator regulator is enabled and receives 3.3 V on the VDD33 pin. An external capacitor is not required. When the REG_EN input pin is connected to VSS, the crystal oscillator regulator is disabled. However, 3.3 V must still be supplied to the VDD33 pin. The 1.2 V crystal oscillator voltage must then be externally input into the OSCVDD12 pin. 2015 Microchip Technology Inc. DS00001909A-page 31 LAN9252 5.0 REGISTER MAP This chapter details the device register map and summarizes the various directly addressable System Control and Status Registers (CSRs). Detailed descriptions of the System CSRs are provided in the chapters corresponding to their function. Additional indirectly addressable registers are available in the various sub-blocks of the device. These registers are also detailed in their corresponding chapters. Directly Addressable Registers • Section 12.13, "EtherCAT CSR and Process Data RAM Access Registers (Directly Addressable)," on page 214 • Section 5.1, "System Control and Status Registers," on page 34 Indirectly Addressable Registers • Section 11.2.16, "PHY Registers," on page 142 • Section 12.14, "EtherCAT Core CSR Registers (Indirectly Addressable)," on page 223 Figure 5-1 contains an overall base register memory map of the device. This memory map is not drawn to scale, and should be used for general reference only. Table 5-1 provides a summary of all directly addressable CSRs and their corresponding addresses. Note: Register bit type definitions are provided in Section 1.3, "Register Nomenclature," on page 7. Not all device registers are memory mapped or directly addressable. For details on the accessibility of the various device registers, refer the register sub-sections listed above. DS00001909A-page 32 2015 Microchip Technology Inc. LAN9252 FIGURE 5-1: REGISTER ADDRESS MAP 3FFh 318h 314h EtherCAT 300h 0FCh Test 0E0h 09Ch GP Timer and Free Run Counter 08Ch 05Ch 054h Interrupts 03Ch EtherCAT Process RAM Write FIFO 020h 01Ch EtherCAT Process RAM Read FIFO 000h Note: Not all registers are shown 2015 Microchip Technology Inc. DS00001909A-page 33 LAN9252 5.1 System Control and Status Registers The System CSRs are directly addressable memory mapped registers with a base address offset range of 050h to 314h. These registers are addressable by the Host via the Host Bus Interface (HBI) or SPI/SQI. For more information on the various device modes and their corresponding address configurations, see Section 2.0, "General Description," on page 8. Table 5-1 lists the System CSRs and their corresponding addresses in order. All system CSRs are reset to their default value on the assertion of a chip-level reset. The System CSRs can be divided into the following sub-categories. Each of these sub-categories is located in the corresponding chapter and contains the System CSR descriptions of the associated registers. The register descriptions are categorized as follows: • • • • • Section 6.2.3, "Reset Registers," on page 42 Section 6.3.5, "Power Management Registers," on page 47 Section 8.3, "Interrupt Registers," on page 56 Section 12.13, "EtherCAT CSR and Process Data RAM Access Registers (Directly Addressable)," on page 214 Section 16.1, "Miscellaneous System Configuration & Status Registers," on page 301 Note: Unlisted registers are reserved for future use. TABLE 5-1: SYSTEM CONTROL AND STATUS REGISTERS Address Register Name (Symbol) 000h-01Ch EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA) 020h-03Ch EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA) 050h Chip ID and Revision (ID_REV) 054h Interrupt Configuration Register (IRQ_CFG) 058h Interrupt Status Register (INT_STS) 05Ch Interrupt Enable Register (INT_EN) 064h Byte Order Test Register (BYTE_TEST) 074h Hardware Configuration Register (HW_CFG) 084h Power Management Control Register (PMT_CTRL) 08Ch General Purpose Timer Configuration Register (GPT_CFG) 090h General Purpose Timer Count Register (GPT_CNT) 09Ch Free Running 25MHz Counter Register (FREE_RUN) 1F8h Reset Control Register (RESET_CTL) 300h EtherCAT CSR Interface Data Register (ECAT_CSR_DATA) 304h EtherCAT CSR Interface Command Register (ECAT_CSR_CMD) 308h EtherCAT Process RAM Read Address and Length Register (ECAT_PRAM_RD_ADDR_LEN) 30Ch EtherCAT Process RAM Read Command Register (ECAT_PRAM_RD_CMD) 310h EtherCAT Process RAM Write Address and Length Register (ECAT_PRAM_WR_ADDR_LEN) 314h EtherCAT Process RAM Write Command Register (ECAT_PRAM_WR_CMD) Reset Register EtherCAT Registers DS00001909A-page 34 2015 Microchip Technology Inc. LAN9252 5.2 Special Restrictions on Back-to-Back Cycles 5.2.1 BACK-TO-BACK WRITE-READ CYCLES It is important to note that there are specific restrictions on the timing of back-to-back host write-read operations. These restrictions concern reading registers after any write cycle that may affect the register. In all cases there is a delay between writing to a register and the new value becoming available to be read. In other cases, there is a delay between writing to a register and the subsequent side effect on other registers. In order to prevent the host from reading stale data after a write operation, minimum wait periods have been established. These periods are specified in Table 5-2. The host processor is required to wait the specified period of time after writing to the indicated register before reading the resource specified in the table. Note that the required wait period is dependent upon the register being read after the write. Performing “dummy” reads of the Byte Order Test Register (BYTE_TEST) register is a convenient way to guarantee that the minimum write-to-read timing restriction is met. Table 5-2 shows the number of dummy reads that are required before reading the register indicated. The number of BYTE_TEST reads in this table is based on the minimum cycle timing of 45ns. For microprocessors with slower busses the number of reads may be reduced as long as the total time is equal to, or greater than the time specified in the table. Note that dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met. Note that depending on the host interface mode in use, the basic host interface cycle may naturally provide sufficient time between writes and read. It is required of the system design and register access mechanisms to ensure the proper timing. For example, a write and read to the same register may occur faster than a write and read to different registers. For 8 and 16-bit write cycles, the wait time for the back-to-back write-read operation applies only to the writing of the last BYTE or WORD of the register, which completes a single DWORD transfer. For Indexed Address mode HBI operation, the wait time for the back-to-back write-read operation applies only to access to the internal registers and FIFOs. It does not apply to the Host Bus Interface Index Registers or the Host Bus Interface Configuration Register. TABLE 5-2: READ AFTER WRITE TIMING RULES After Writing... wait for this many nanoseconds... or Perform this many Reads of BYTE_TEST… (assuming Tcyc of 45ns) any register 45 1 the same register or any other register affected by the write Interrupt Configuration Register (IRQ_CFG) 60 2 Interrupt Configuration Register (IRQ_CFG) Interrupt Enable Register (INT_EN) 90 2 Interrupt Configuration Register (IRQ_CFG) 60 2 Interrupt Status Register (INT_STS) 180 4 Interrupt Configuration Register (IRQ_CFG) 170 4 Interrupt Status Register (INT_STS) 165 4 Power Management Control Register (PMT_CTRL) 170 4 Interrupt Configuration Register (IRQ_CFG) 160 4 Interrupt Status Register (INT_STS) Interrupt Status Register (INT_STS) Power Management Control Register (PMT_CTRL) 2015 Microchip Technology Inc. before reading... DS00001909A-page 35 LAN9252 TABLE 5-2: READ AFTER WRITE TIMING RULES (CONTINUED) After Writing... General Purpose Timer Configuration Register (GPT_CFG) EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA) 5.2.2 wait for this many nanoseconds... or Perform this many Reads of BYTE_TEST… (assuming Tcyc of 45ns) 55 2 General Purpose Timer Configuration Register (GPT_CFG) 170 4 General Purpose Timer Count Register (GPT_CNT) 50 2 EtherCAT Process RAM Write Command Register (ECAT_PRAM_WR_CMD) before reading... BACK-TO-BACK READ CYCLES There are also restrictions on specific back-to-back host read operations. These restrictions concern reading specific registers after reading a resource that has side effects. In many cases there is a delay between reading the device, and the subsequent indication of the expected change in the control and status register values. In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have been established. These periods are specified in Table 5-3. The host processor is required to wait the specified period of time between read operations of specific combinations of resources. The wait period is dependent upon the combination of registers being read. Performing “dummy” reads of the Byte Order Test Register (BYTE_TEST) register is a convenient way to guarantee that the minimum wait time restriction is met. Table 5-3 below also shows the number of dummy reads that are required for back-to-back read operations. The number of BYTE_TEST reads in this table is based on the minimum timing for Tcyc (45ns). For microprocessors with slower busses the number of reads may be reduced as long as the total time is equal to, or greater than the time specified in the table. Dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met. Note that depending on the host interface mode in use, the basic host interface cycle may naturally provide sufficient time between reads. It is required of the system design and register access mechanisms to ensure the proper timing. For example, multiple reads to the same register may occur faster than reads to different registers. For 8 and 16-bit read cycles, the wait time for the back-to-back read operation is required only after the reading of the last BYTE or WORD of the register, which completes a single DWORD transfer. There is no wait requirement between the BYTE or WORD accesses within the DWORD transfer. TABLE 5-3: READ AFTER READ TIMING RULES After reading... EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA) DS00001909A-page 36 wait for this many nanoseconds... or Perform this many Reads of BYTE_TEST… (assuming Tcyc of 45ns) 50 2 before reading... EtherCAT Process RAM Read Command Register (ECAT_PRAM_RD_CMD) 2015 Microchip Technology Inc. LAN9252 6.0 CLOCKS, RESETS, AND POWER MANAGEMENT 6.1 Clocks The device provides generation of all system clocks as required by the various sub-modules of the device. The clocking sub-system is comprised of the following: • Crystal Oscillator • PHY PLL 6.1.1 CRYSTAL OSCILLATOR The device requires a fixed-frequency 25 MHz clock source for use by the internal clock oscillator and PLL. This is typically provided by attaching a 25 MHz crystal to the OSCI and OSCO pins as specified in Section 18.7, "Clock Circuit," on page 320. Optionally, this clock can be provided by driving the OSCI input pin with a single-ended 25 MHz clock source. If a single-ended source is selected, the clock input must run continuously for normal device operation. Power savings modes allow for the oscillator or external clock input to be halted. The crystal oscillator can be disabled as describe in Section 6.3.4, "Chip Level Power Management," on page 45. For system level verification, the crystal oscillator output can be enabled onto the IRQ pin. See Section 8.2.7, "Clock Output Test Mode," on page 56. Power for the crystal oscillator is provided by a dedicated regulator or separate input pin. See Section 4.1.2, "1.2 V Crystal Oscillator Regulator," on page 31. Note: 6.1.2 Crystal specifications are provided in Table 18-12, “Crystal Specifications,” on page 320. PHY PLL The PHY module receives the 25 MHz reference clock and, in addition to its internal clock usage, outputs a main system clock that is used to derive device sub-system clocks. The PHY PLL can be disabled as describe in Section 6.3.4, "Chip Level Power Management," on page 45. The PHY PLL will be disabled only when requested and if the PHY ports are in a power down mode. Power for PHY PLL is provided by an external input pin, usually sourced by the device’s 1.2V core regulator. See Section 4.0, "Power Connections," on page 29. 2015 Microchip Technology Inc. DS00001909A-page 37 LAN9252 6.2 Resets The device provides multiple hardware and software reset sources, which allow varying levels of the device to be reset. All resets can be categorized into three reset types as described in the following sections: • Chip-Level Resets - Power-On Reset (POR) - RST# Pin Reset - EtherCAT System Reset • Multi-Module Resets - DIGITAL RESET (DIGITAL_RST) • Single-Module Resets - Port A PHY Reset - Port B PHY Reset - EtherCAT Controller Reset The device supports the use of configuration straps to allow automatic custom configurations of various device parameters. These configuration strap values are set upon de-assertion of all chip-level resets and can be used to easily set the default parameters of the chip at power-on or pin (RST#) reset. Refer to Section 6.3, "Power Management," on page 43 for detailed information on the usage of these straps. Table 6-1 summarizes the effect of the various reset sources on the device. Refer to the following sections for detailed information on each of these reset types. TABLE 6-1: RESET SOURCES AND AFFECTED DEVICE FUNCTIONALITY Module/ Functionality POR 25 MHz Oscillator Voltage Regulators EtherCAT Core PHY A PHY B PHY Common Voltage Supervision PLL SPI/SQI Slave Host Bus Interface Power Management General Purpose Timer Free Running Counter System CSR Config. Straps Latched EEPROM Loader Run Tristate Output Pins(5) RST# Pin Driven Low (1) (2) X X X (3) (3) (3) X X X X X X YES YES YES YES Note 1: 2: 3: 4: 5: RST# Pin EtherCAT System Reset Digital Reset EtherCAT Module Reset X X X X X X X X X X X X X X YES YES YES X X X X X X YES YES YES YES X X X X X X NO(4) YES YES POR is performed by the XTAL voltage regulator, not at the system level POR is performed internal to the voltage regulators POR is performed internal to the PHY Strap inputs are not re-latched Only those output pins that are used for straps DS00001909A-page 38 2015 Microchip Technology Inc. LAN9252 6.2.1 CHIP-LEVEL RESETS A chip-level reset event activates all internal resets, effectively resetting the entire device. A chip-level reset is initiated by assertion of any of the following input events: • Power-On Reset (POR) • RST# Pin Reset • EtherCAT System Reset Chip-level reset/configuration completion can be determined by first polling the Byte Order Test Register (BYTE_TEST). The returned data will be invalid until the Host interface resets are complete. Once the returned data is the correct byte ordering value, the Host interface resets have completed. The completion of the entire chip-level reset must be determined by polling the READY bit of the Hardware Configuration Register (HW_CFG) or Power Management Control Register (PMT_CTRL) until it is set. When set, the READY bit indicates that the reset has completed and the device is ready to be accessed. With the exception of the Hardware Configuration Register (HW_CFG),Power Management Control Register (PMT_CTRL), Byte Order Test Register (BYTE_TEST), and Reset Control Register (RESET_CTL), read access to any internal resources should not be done by S/W while the READY bit is cleared. Writes to any address are invalid until the READY bit is set. A chip-level reset involves tuning of the variable output level pads, latching of configuration straps and generation of the master reset. CONFIGURATION STRAPS LATCHING During POR, EtherCAT reset or RST# pin reset, the latches for the straps are open. Following the release of POR, EtherCAT reset or RST# pin reset, the latches for the straps are closed. VARIABLE LEVEL I/O PAD TUNING Following the release of the EtherCAT, POR or RST# pin resets, a 1 uS pulse (active low), is sent into the VO tuning circuit. 2 uS later, the output pins are enabled. The 2 uS delay allows time for the variable output level pins to tune before enabling the outputs and also provides input hold time for strap pins that are shared with output pins. MASTER RESET AND CLOCK GENERATION RESET Following the enabling of the output pins, the reset is synchronized to the main system clock to become the master reset. Master reset is used to generate the local resets and to reset the clocks generation. 6.2.1.1 Power-On Reset (POR) A power-on reset occurs whenever power is initially applied to the device or if the power is removed and reapplied to the device. This event resets all circuitry within the device. Configuration straps are latched and EEPROM loading is performed as a result of this reset. The POR is used to trigger the tuning of the Variable Level I/O Pads as well as a chip-level reset. The POR can also used as a system level reset. RST# becomes an open-drain output and is asserted for the POR time. Its purpose is to perform a complete reset of the EtherCAT slave and/or to hold an external PHY in reset while the EtherCAT core is in reset. As an open-drain output, RST is intended to be wired OR’d into the system reset. Note: The Ethernet PHY should be connected to the RST# pin so that the PHY is held in reset until the EtherCAT Slave is ready. Otherwise, the far end Link Partner would detect valid link signals from the PHY and would “open” its port assuming that the local EtherCAT Slave was ready. The RST# pin is not driven until all voltages are operational. External, system level solutions are necessary if the system needs to be held in reset during power ramp-up. Following valid voltage levels, a POR reset typically takes approximately 21 ms. 6.2.1.2 RST# Pin Reset Driving the RST# input pin low initiates a chip-level reset. This event resets all circuitry within the device. Use of this reset input is optional, but when used, it must be driven for the period of time specified in Section 18.6.3, "Reset and Configuration Strap Timing," on page 317. Configuration straps are latched, and EEPROM loading is performed as a result of this reset. 2015 Microchip Technology Inc. DS00001909A-page 39 LAN9252 A RST# pin reset typically takes approximately 760 s. Note: The RST# pin is pulled-high internally. If unused, this signal can be left unconnected. Do not rely on internal pull-up resistors to drive signals external to the device. Please refer to Table 3-13, “Miscellaneous Pin Descriptions,” on page 27 for a description of the RST# pin. 6.2.1.3 EtherCAT System Reset An EtherCAT system reset, initiated by a special sequence of three independent and consecutive frames/commands, is functionally identical to a RST# pin reset, except that during an EtherCAT system reset, the RST# pin becomes an open-drain output and is asserted for the minimum required time of 80 ms. The RST# is an open-drain output intended to be wired OR’d into the system reset. Note: 6.2.2 The purpose of connecting the RST# pin into the system reset is to perform a complete reset of the EtherCAT slave. The EtherCAT master issues this reset in rare and extreme cases when the local microcontroller is seriously halted and can not be otherwise informed to reinitialize. BLOCK-LEVEL RESETS The block level resets contain an assortment of reset register bit inputs and generate resets for the various blocks. Block level resets can affect one or multiple modules. 6.2.2.1 Multi-Module Resets Multi-module resets activate multiple internal resets, but do not reset the entire chip. Configuration straps are not latched upon multi-module resets. A multi-module reset is initiated by assertion of the following: • DIGITAL RESET (DIGITAL_RST) Multi-module reset/configuration completion can be determined by first polling the Byte Order Test Register (BYTE_TEST). The returned data will be invalid until the Host interface resets are complete. Once the returned data is the correct byte ordering value, the Host interface resets have completed. The completion of the entire chip-level reset must be determined by polling the READY bit of the Hardware Configuration Register (HW_CFG) or Power Management Control Register (PMT_CTRL) until it is set. When set, the READY bit indicates that the reset has completed and the device is ready to be accessed. With the exception of the Hardware Configuration Register (HW_CFG),Power Management Control Register (PMT_CTRL), Byte Order Test Register (BYTE_TEST), and Reset Control Register (RESET_CTL), read access to any internal resources should not be done by S/W while the READY bit is cleared. Writes to any address are invalid until the READY bit is set. Note: The digital reset does not reset register bits designated as NASR. DIGITAL RESET (DIGITAL_RST) A digital reset is performed by setting the DIGITAL_RST bit of the Reset Control Register (RESET_CTL). A digital reset will reset all device sub-modules except the Ethernet PHYs. EEPROM loading is performed following this reset. Configuration straps are not latched as a result of a digital reset. A digital reset typically takes approximately 760 s. 6.2.2.2 Single-Module Resets A single-module reset will reset only the specified module. Single-module resets do not latch the configuration straps. A single-module reset is initiated by assertion of the following: • Port A PHY Reset • Port B PHY Reset • EtherCAT Controller Reset DS00001909A-page 40 2015 Microchip Technology Inc. LAN9252 Port A PHY Reset A Port A PHY reset is performed by setting the PHY_A_RST bit of the Reset Control Register (RESET_CTL) or the Soft Reset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x). Upon completion of the Port A PHY reset, the PHY_A_RST and Soft Reset bits are automatically cleared. No other modules of the device are affected by this reset. Port A PHY reset completion can be determined by polling the PHY_A_RST bit in the Reset Control Register (RESET_CTL) or the Soft Reset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) until it clears. Under normal conditions, the PHY_A_RST and Soft Reset bit will clear approximately 102 uS after the Port A PHY reset occurrence. Note: When using the Soft Reset bit to reset the Port A PHY, register bits designated as NASR are not reset. In addition to the methods above, the Port A PHY is automatically reset after returning from a PHY power-down mode. This reset differs in that the PHY power-down mode reset does not reload or reset any of the PHY registers. Refer to Section 11.2.8, "PHY Power-Down Modes," on page 131 for additional information. Refer to Section 11.2.10, "Resets," on page 135 for additional information on Port A PHY resets. If Port A PHY is in 100BASE-FX mode, it is reset when the Enhanced link detection function detects errors on port 0 (2 port mode or 3 port downstream mode) or on port 2 (3 port upstream mode). Port B PHY Reset A Port B PHY reset is performed by setting the PHY_B_RST bit of the Reset Control Register (RESET_CTL) or the Soft Reset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x). Upon completion of the Port B PHY reset, the PHY_B_RST and Soft Reset bits are automatically cleared. No other modules of the device are affected by this reset. Port B PHY reset completion can be determined by polling the PHY_B_RST bit in the Reset Control Register (RESET_CTL) or the Soft Reset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) until it clears. Under normal conditions, the PHY_B_RST and Soft Reset bit will clear approximately 102 us after the Port B PHY reset occurrence. Note: When using the Soft Reset bit to reset the Port B PHY, register bits designated as NASR are not reset. In addition to the methods above, the Port B PHY is automatically reset after returning from a PHY power-down mode. This reset differs in that the PHY power-down mode reset does not reload or reset any of the PHY registers. Refer to Section 11.2.8, "PHY Power-Down Modes," on page 131 for additional information. Refer to Section 11.2.10, "Resets," on page 135 for additional information on Port B PHY resets. If Port B PHY is in 100BASE-FX mode, it is reset when the Enhanced link detection function detects errors on port 1. EtherCAT Controller Reset A compete device and system reset can be initiated by either the EtherCAT master or by the local host by writing the value sequence of 0x52 (‘R’), 0x45 (‘E’) and 0x53 (‘S’) into the ESC Reset ECAT Register (for the master) or the ESC Reset PDI Register (for the local host). This will trigger the reset described in Section 6.2.1.3, "EtherCAT System Reset". A reset of just the EtherCAT Controller may be performed by setting the ETHERCAT_RST bit in the Reset Control Register (RESET_CTL). This will reset the EtherCAT Core and its registers. It will also reset the EtherCAT CSR and Process Data RAM Access logic described in Section 12.11, on page 208 and will reset the registers described in Section 12.13, "EtherCAT CSR and Process Data RAM Access Registers (Directly Addressable)," on page 214. Since the EtherCAT module will reconfigure the device from the EEPROM, the Host interfaces will be disabled until reset is complete. Completion of the reset must be determined by using the methods described in Section 9.4.2.2, on page 64 and Section 9.5.3.2, on page 85 for HBI and Section 10.2.1.1, on page 104 for SPI/SQI. 2015 Microchip Technology Inc. DS00001909A-page 41 LAN9252 6.2.3 6.2.3.1 RESET REGISTERS Reset Control Register (RESET_CTL) Offset: 1F8h Size: 32 bits This register contains software controlled resets. Note: This register can be read while the device is in the reset or not ready / power savings states without leaving the host interface in an intermediate state. If the host interface is in a reset state, returned data may be invalid. It is not necessary to read all four bytes of this register. DWORD access rules do not apply to this register. Bits Type Default RESERVED RO - 6 EtherCAT Reset (ETHERCAT_RST) Setting this bit resets the EtherCAT core. When the EtherCAT core is released from reset, this bit is automatically cleared. All writes to this bit are ignored while this bit is set. R/W SC 0b 5 RESERVED RO - 4 RESERVED RO - 3 RESERVED RO - 2 Port B PHY Reset (PHY_B_RST) Setting this bit resets the Port B PHY. The internal logic automatically holds the PHY reset for a minimum of 102uS. When the Port B PHY is released from reset, this bit is automatically cleared. All writes to this bit are ignored while this bit is set. R/W SC 0b 1 Port A PHY Reset (PHY_A_RST) Setting this bit resets the Port A PHY. The internal logic automatically holds the PHY reset for a minimum of 102uS. When the Port A PHY is released from reset, this bit is automatically cleared. All writes to this bit are ignored while this bit is set. R/W SC 0b 0 Digital Reset (DIGITAL_RST) Setting this bit resets the complete chip except the PLL, Port B PHY and Port A PHY. All system CSRs are reset except for any NASR type bits. R/W SC 0b 31:7 Description When the chip is released from reset, this bit is automatically cleared. All writes to this bit are ignored while this bit is set. DS00001909A-page 42 2015 Microchip Technology Inc. LAN9252 6.3 Power Management The device supports several block and chip level power management features as well as wake-up event detection and notification. 6.3.1 6.3.1.1 WAKE-UP EVENT DETECTION PHY A & B Energy Detect Energy Detect Power Down mode reduces PHY power consumption. In energy-detect power-down mode, the PHY will resume from power-down when energy is seen on the cable (typically from link pulses) and set the ENERGYON interrupt bit in the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x). Refer to Section 11.2.8.2, "Energy Detect Power-Down," on page 131 for details on the operation and configuration of the PHY energy-detect power-down mode. Note: If a carrier is present when Energy Detect Power Down is enabled, then detection will occur immediately. If enabled, via the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x), the PHY will generate an interrupt. This interrupt is reflected in the Interrupt Status Register (INT_STS), bit 26 (PHY_INT_A) for PHY A and bit 27 (PHY_INT_B) for PHY B. The INT_STS register bits will trigger the IRQ interrupt output pin if enabled, as described in Section 8.2.1, "Ethernet PHY Interrupts," on page 54. The energy-detect PHY interrupts will also set the appropriate Energy-Detect / WoL Status Port A (ED_WOL_STS_A) or Energy-Detect / WoL Status Port B (ED_WOL_STS_B) bit of the Power Management Control Register (PMT_CTRL). The Energy-Detect / WoL Enable Port A (ED_WOL_EN_A) and Energy-Detect / WoL Enable Port B (ED_WOL_EN_B) bits will enable the corresponding status bits as a PME event. Note: 6.3.1.2 Any PHY interrupt will set the above status bits. The Host should only enable the appropriate PHY interrupt source in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x). PHY A & B Wake on LAN (WoL) PHY A and B provide WoL event detection of Perfect DA, Broadcast, Magic Packet, and Wakeup frames. When enabled, the PHY will detect WoL events and set the WoL interrupt bit in the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x). If enabled via the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x), the PHY will generate an interrupt. This interrupt is reflected in the Interrupt Status Register (INT_STS), bit 26 (PHY_INT_A) for PHY A and bit 27 (PHY_INT_B) for PHY B. The INT_STS register bits will trigger the IRQ interrupt output pin if enabled, as described in Section 8.2.1, "Ethernet PHY Interrupts," on page 54. Refer to Section 11.2.9, "Wake on LAN (WoL)," on page 132 for details on the operation and configuration of the PHY WoL. The WoL PHY interrupts will also set the appropriate Energy-Detect / WoL Status Port A (ED_WOL_STS_A) or EnergyDetect / WoL Status Port B (ED_WOL_STS_B) bit of the Power Management Control Register (PMT_CTRL). The Energy-Detect / WoL Enable Port A (ED_WOL_EN_A) and Energy-Detect / WoL Enable Port B (ED_WOL_EN_B) bits enable the corresponding status bits as a PME event. Note: 6.3.2 Any PHY interrupt will set the above status bits. The Host should only enable the appropriate PHY interrupt source in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x). WAKE-UP (PME) NOTIFICATION A simplified diagram of the logic that controls the PME interrupt can be seen in Figure 6-1. The PME module handles the latching of the PHY B Energy-Detect / WoL Status Port B (ED_WOL_STS_B) bit and the PHY A Energy-Detect / WoL Status Port A (ED_WOL_STS_A) bit in the Power Management Control Register (PMT_CTRL). 2015 Microchip Technology Inc. DS00001909A-page 43 LAN9252 This module also masks the status bits with the corresponding enable bits (Energy-Detect / WoL Enable Port B (ED_WOL_EN_B) and Energy-Detect / WoL Enable Port A (ED_WOL_EN_A)) and combines the results together to generate the Power Management Interrupt Event (PME_INT) status bit in the Interrupt Status Register (INT_STS). The PME_INT status bit is then masked with the Power Management Event Interrupt Enable (PME_INT_EN) bit and combined with the other interrupt sources to drive the IRQ output pin. Note: The PME interrupt status bit (PME_INT) in the INT_STS register is set regardless of the setting of PME_INT_EN. When the PM_WAKE bit of the Power Management Control Register (PMT_CTRL) is set, the PME event will automatically wake up the system in certain chip level power modes, as described in Section 6.3.4.2, "Exiting Low Power Modes," on page 46. FIGURE 6-1: PME INTERRUPT SIGNAL GENERATION ED_WOL_EN_A (bit 14) of PMT_CTRL register INT8 (bit 8) of PHY_INTERRUPT_SOURCE_A register INT8_MASK (bit 8) of PHY_INTERRUPT_MASK_A register PM_WAKE (bit 28) of PMT_CTRL register ED_WOL_STS_A (bit 16) of PMT_CTRL register PME wake-up PHYs A & B INT7 (bit 7) of PHY_INTERRUPT_SOURCE_A register INT7_MASK (bit 7) of PHY_INTERRUPT_MASK_A register Other PHY Interrupts ED_WOL_EN_B (bit 15) of PMT_CTRL register INT8 (bit 8) of PHY_INTERRUPT_SOURCE_B register INT8_MASK (bit 8) of PHY_INTERRUPT_MASK_B register ED_WOL_STS_B (bit 17) of PMT_CTRL register INT7 (bit 7) of PHY_INTERRUPT_SOURCE_B register INT7_MASK (bit 7) of PHY_INTERRUPT_MASK_B register Other PHY Interrupts PME_INT (bit 17) of INT_STS register Other System Interrupts Polarity & Buffer Type Logic Denotes a level-triggered "sticky" status bit PME_INT_EN (bit 17) of INT_EN register IRQ IRQ_EN (bit 8) of IRQ_CFG register 6.3.3 BLOCK LEVEL POWER MANAGEMENT The device supports software controlled clock disabling of various modules in order to reduce power consumption. Note: 6.3.3.1 Disabling individual blocks does not automatically reset the block, it only places it into a static non-operational state in order to reduce the power consumption of the device. If a block reset is not performed before re-enabling the block, then care must be taken to ensure that the block is in a state where it can be disabled and then re-enabled. Disabling The EtherCAT Core The entire EtherCAT Core may be disabled by setting the ECAT_DIS bit in the Power Management Control Register (PMT_CTRL). As a safety precaution, in order for this bit to be set, it must be written as a 1 two consecutive times. A write of a 0 will reset the count. DS00001909A-page 44 2015 Microchip Technology Inc. LAN9252 6.3.3.2 PHY Power Down A PHY may be placed into power-down as described in Section 11.2.8, "PHY Power-Down Modes," on page 131. 6.3.3.3 LED Pins Power Down All LED outputs may be disabled by setting the LED_DIS bit in the Power Management Control Register (PMT_CTRL) Open-drain / open-source LEDs are un-driven. Push-pull LEDs are still driven but are set to their inactive state. 6.3.4 CHIP LEVEL POWER MANAGEMENT The device supports power-down modes to allow applications to minimize power consumption. Power is reduced by disabling the clocks as outlined in Table 6-2, "Power Management States". All configuration data is saved when in any power state. Register contents are not affected unless specifically indicated in the register description. There is one normal operating power state, D0, and three power saving states: D1, D2 and D3. Although appropriate for various wake-up detection functions, the power states do not directly enable and are not enforced by these functions. D0: Normal Mode - This is the normal mode of operation of this device. In this mode, all functionality is available. This mode is entered automatically on any chip-level reset (POR, RST# pin reset, EtherCAT system reset). D1: System Clocks Disabled, XTAL, PLL and network clocks enabled - In this low power mode, all clocks derived from the PLL clock are disabled. The network clocks remain enabled if supplied by the PHYs or externally. The crystal oscillator and the PLL remain enabled. Exit from this mode may be done manually or automatically. This mode could be used for PHY General Power Down mode, PHY WoL mode and PHY Energy Detect Power Down mode. D2: System Clocks Disabled, PLL disable requested, XTAL enabled - In this low power mode, all clocks derived from the PLL clock are disabled. The PLL is allowed to be disabled (and will disable if both of the PHYs are in either Energy Detect or General Power Down). The network clocks remain enabled if supplied by the PHYs or externally. The crystal oscillator remains enabled. Exit from this mode may be done manually or automatically. This mode is useful for PHY Energy Detect Power Down mode and PHY WoL mode. This mode could be used for PHY General Power Down mode. D3: System Clocks Disabled, PLL disabled, XTAL disabled - In this low power mode, all clocks derived from the PLL clock are disabled. The PLL will be disabled. External network clocks are gated off. The crystal oscillator is disabled. Exit from this mode may be only be done manually. This mode is useful for PHY General Power Down mode. The Host must place the PHYs into General Power Down mode by setting the Power Down (PHY_PWR_DWN) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) before setting this power state. TABLE 6-2: POWER MANAGEMENT STATES Clock Source 25 MHz Crystal Oscillator PLL system clocks (100 MHz, 50 MHz, 25 MHz and others) network clocks Note 1: 2: 3: 6.3.4.1 D0 ON ON ON available(1) D1 ON ON OFF available(1) D2 ON OFF(2) OFF available(1) D3 OFF OFF OFF OFF(3) If supplied by the PHYs or externally PLL is requested to be turned off and will disable if both of the PHYs are in either Energy Detect or General Power Down PHY clocks are off, external clocks are gated off Entering Low Power Modes To enter any of the low power modes (D1 - D3) from normal mode (D0), follow these steps: 1. 2. 3. Write the PM_MODE and PM_WAKE fields in the Power Management Control Register (PMT_CTRL) to their desired values Set the wake-up detection desired per Section 6.3.1, "Wake-Up Event Detection". Set the appropriate wake-up notification per Section 6.3.2, "Wake-Up (PME) Notification". 2015 Microchip Technology Inc. DS00001909A-page 45 LAN9252 4. 5. Ensure that the device is in a state where it can safely be placed into a low power mode (all packets transmitted, receivers disabled, packets processed / flushed, etc.) Set the PM_SLEEP_EN bit in the Power Management Control Register (PMT_CTRL). Note: The PM_MODE field cannot be changed at the same time as the PM_SLEEP_EN bit is set and the PM_SLEEP_EN bit cannot be set at the same time that the PM_MODE field is changed. Upon entering any low power mode, the Device Ready (READY) bit in the Hardware Configuration Register (HW_CFG) and the Power Management Control Register (PMT_CTRL) is forced low. Note: 6.3.4.2 Upon entry into any of the power saving states the host interfaces are not functional. Exiting Low Power Modes Exiting from a low power mode can be done manually or automatically. An automatic wake-up will occur based on the events described in Section 6.3.2, "Wake-Up (PME) Notification". Automatic wake-up is enabled with the Power Management Wakeup (PM_WAKE) bit in the Power Management Control Register (PMT_CTRL). A manual wake-up is initiated by the host when: • an HBI write (CS and WR or CS, RD_WR and ENB) is performed to the device. Although all writes are ignored until the device has been woken and a read performed, the host should direct the write to the Byte Order Test Register (BYTE_TEST). Writes to any other addresses should not be attempted until the device is awake. • an SPI/SQI cycle (SCS# low and SCK high) is performed to the device. Although all reads and writes are ignored until the device has been woken, the host should direct the use a read of the Byte Order Test Register (BYTE_TEST) to wake the device. Reads and writes to any other addresses should not be attempted until the device is awake. To determine when the host interface is functional, the Byte Order Test Register (BYTE_TEST) should be polled. Once the correct pattern is read, the interface can be considered functional. At this point, the Device Ready (READY) bit in the Hardware Configuration Register (HW_CFG) or the Power Management Control Register (PMT_CTRL) can be polled to determine when the device is fully awake. For both automatic and manual wake-up, the Device Ready (READY) bit will go high once the device is returned to power savings state D0 and the PLL has re-stabilized. The PM_MODE and PM_SLEEP_EN fields in the Power Management Control Register (PMT_CTRL) will also clear at this point. Under normal conditions, the device will wake-up within 2 ms. DS00001909A-page 46 2015 Microchip Technology Inc. LAN9252 6.3.5 6.3.5.1 POWER MANAGEMENT REGISTERS Power Management Control Register (PMT_CTRL) Offset: 084h Size: 32 bits This read-write register controls the power management features of the device. The ready state of the device be determined via the Device Ready (READY) bit of this register. Note: This register can be read while the device is in the reset or not ready / power savings states without leaving the host interface in an intermediate state. If the host interface is in a reset state, returned data may be invalid. It is not necessary to read all four bytes of this register. DWORD access rules do not apply to this register. Bits 31:29 Description Power Management Mode (PM_MODE) This register field determines the chip level power management mode that will be entered when the Power Management Sleep Enable (PM_SLEEP_EN) bit is set. Type Default R/W/SC 000b R/W/SC 0b 000: D0 001: D1 010: D2 011: D3 100: Reserved 101: Reserved 110: Reserved 111: Reserved Writes to this field are ignored if Power Management Sleep Enable (PM_SLEEP_EN) is also being written with a 1. This field is cleared when the device wakes up. 28 Power Management Sleep Enable (PM_SLEEP_EN) Setting this bit enters the chip level power management mode specified with the Power Management Mode (PM_MODE) field. 0: Device is not in a low power sleep state 1: Device is in a low power sleep state This bit can not be written at the same time as the PM_MODE register field. The PM_MODE field must be set, and then this bit must be set for proper device operation. Writes to this bit with a value of 1 are ignored if Power Management Mode (PM_MODE) is being written with a new value. Note: Although not prevented by H/W, this bit should not be written with a value of 1 while Power Management Mode (PM_MODE) has a value of “D0”. This field is cleared when the device wakes up. 2015 Microchip Technology Inc. DS00001909A-page 47 LAN9252 Bits 27 Description Type Default R/W 0b R/W 0b RESERVED RO - EtherCAT Core Clock Disable (ECAT_DIS) This bit disables the clocks for the EtherCAT core. R/W 0b Power Management Wakeup (PM_WAKE) When set, this bit enables automatic wake-up based on PME events. 0: Manual Wakeup only 1: Auto Wakeup enabled 26 LED Disable (LED_DIS) This bit disables LED outputs. Open-drain / open-source LEDs are un-driven. Push-pull LEDs are still driven but are set to their inactive state. 0: LEDs are enabled 1: LEDs are disabled 25:22 21 0: Clocks are enabled 1: Clocks are disabled In order for this bit to be set, it must be written as a 1 two consecutive times. A write of a 0 will reset the count. 20 RESERVED RO - 19:18 RESERVED RO - R/WC 0b R/WC 0b 17 Energy-Detect / WoL Status Port B (ED_WOL_STS_B) This bit indicates an energy detect or WoL event occurred on the Port B PHY. In order to clear this bit, it is required that the event in the PHY be cleared as well. The event sources are described in Section 6.3, "Power Management," on page 43. 16 Energy-Detect / WoL Status Port A (ED_WOL_STS_A) This bit indicates an energy detect or WoL event occurred on the Port A PHY. In order to clear this bit, it is required that the event in the PHY be cleared as well. The event sources are described in Section 6.3, "Power Management," on page 43. 15 Energy-Detect / WoL Enable Port B (ED_WOL_EN_B) When set, the PME_INT bit in the Interrupt Status Register (INT_STS) will be asserted upon an energy-detect or WoL event from Port B. R/W 0b 14 Energy-Detect / WoL Enable Port A (ED_WOL_EN_A) When set, the PME_INT bit in the Interrupt Status Register (INT_STS) will be asserted upon an energy-detect or WoL event from Port A. R/W 0b 13:10 RESERVED RO - 9 RESERVED RO - 8:7 RESERVED RO - 6:5 RESERVED RO - DS00001909A-page 48 2015 Microchip Technology Inc. LAN9252 Bits Description Type Default 4 RESERVED RO - 3:1 RESERVED RO - Device Ready (READY) When set, this bit indicates that the device is ready to be accessed. Upon power-up, RST# reset, return from power savings states, EtherCAT chip level or module level reset, or digital reset, the host processor may interrogate this field as an indication that the device has stabilized and is fully active. RO 0b 0 This rising edge of this bit will assert the Device Ready (READY) bit in INT_STS and can cause an interrupt if enabled. Note: With the exception of the HW_CFG, PMT_CTRL, BYTE_TEST, and RESET_CTL registers, read access to any internal resources is forbidden while the READY bit is cleared. Writes to any address are invalid until this bit is set. Note: This bit is identical to bit 27 of the Hardware Configuration Register (HW_CFG). 2015 Microchip Technology Inc. DS00001909A-page 49 LAN9252 6.4 Device Ready Operation The device supports a Ready status register bit that indicates to the Host software when the device is fully ready for operation. This bit may be read via the Power Management Control Register (PMT_CTRL) or the Hardware Configuration Register (HW_CFG). Following power-up reset, RST# reset, EtherCAT chip level reset or digital reset (see Section 6.2, "Resets"), the Device Ready (READY) bit indicates that the device has read, and is configured from, the contents of the EEPROM. An EtherCAT reset via the Reset Control Register (RESET_CTL) will cause the EtherCAT core to reload from the EEPROM, temporarily causing the Device Ready (READY) to be low. Entry into any power savings state (see Section 6.3.4, "Chip Level Power Management") other than D0 will cause Device Ready (READY) to be low. Upon wake-up, the Device Ready (READY) bit will go high once the device is returned to power savings state D0 and the PLL has re-stabilized. DS00001909A-page 50 2015 Microchip Technology Inc. LAN9252 7.0 CONFIGURATION STRAPS Configuration straps allow various features of the device to be automatically configured to user defined values. Hardstraps are latched upon Power-On Reset (POR), EtherCAT reset, or pin reset (RST#). Configuration straps include internal resistors in order to prevent the signal from floating when unconnected. If a particular configuration strap is connected to a load, an external pull-up or pull-down resistor should be used to augment the internal resistor to ensure that it reaches the required voltage level prior to latching. The internal resistor can also be overridden by the addition of an external resistor. Note: 7.1 The system designer must guarantee that configuration strap pins meet the timing requirements specified in Section 18.6.3, "Reset and Configuration Strap Timing". If configuration strap pins are not at the correct voltage level prior to being latched, the device may capture incorrect strap values. Hard-Straps Hard-straps are latched upon Power-On Reset (POR), EtherCAT reset, or pin reset (RST#) only. These straps are used as either direct configuration values or as register defaults. Table 7-1 provides a list of all hard-straps and their associated pin. These straps, along with their pin assignments are also fully defined in Section 3.0, "Pin Descriptions and Configuration," on page 11. TABLE 7-1: HARD-STRAP CONFIGURATION STRAP DEFINITIONS Strap Name eeprom_size_strap Description EEPROM Size Strap: Configures the EEPROM size range. Pins E2PSIZE A low selects 1K bits (128 x 8) through 16K bits (2K x 8). A high selects 32K bits (4K x 8) through 4Mbits (512K x 8). chip_mode_strap[1:0] EtherCAT Chip Mode Strap: This strap determines the number of active ports and port types. CHIP_MODE1, CHIP_MODE0 00 = 2 port mode. Ports 0 and 1 are connected to internal PHYs A and B. 01 = reserved 10 = 3 port downstream mode. Ports 0 and 1 are connected to internal PHYs A and B. Port 2 is connected to the external MII pins. 11 = 3 port upstream mode. Ports 2 and 1 are connected to internal PHYs A and B. Port 0 is connected to the external MII pins. link_pol_strap_mii EtherCAT MII Port Link Polarity Strap: This strap determines the polarity of the MII_LINK pin. MII_LINKPOL 0 = MII_LINK low means a 100 Mbit/s Full Duplex link is established 1= MII_LINK high means a 100 Mbit/s Full Duplex link is established 2015 Microchip Technology Inc. DS00001909A-page 51 LAN9252 TABLE 7-1: HARD-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED) Strap Name tx_shift_strap[1:0] Description Pins EtherCAT MII Port TX Timing Shift Strap: These straps determine the value of the MII TX Timing Shift for the MII port. TX_SHIFT[1:0] 00 = 0ns 01 = 10ns 10 = 20ns 11 = 30ns fx_mode_strap_1 PHY A FX Mode Strap: Selects FX mode for PHY A. FXLOSEN : FXSDENA This strap is set high when FXLOSEN is above 1 V (typ.) or FXSDENA is above 1 V (typ.). fx_mode_strap_2 PHY B FX Mode Strap: Selects FX mode for PHY B. FXLOSEN : FXSDENB This strap is set high when FXLOSEN is above 2 V (typ.) or FXSDENB is above 1 V (typ.). fx_los_strap_1 PHY A FX-LOS Select Strap: Selects Loss of Signal mode for PHY A. FXLOSEN This strap is set high when FXLOSEN is above 1 V (typ.). fx_los_strap_2 PHY B FX-LOS Select Strap: Selects Loss of Signal mode for PHY B. FXLOSEN This strap is set high when FXLOSEN is above 2 V (typ.). DS00001909A-page 52 2015 Microchip Technology Inc. LAN9252 8.0 SYSTEM INTERRUPTS 8.1 Functional Overview This chapter describes the system interrupt structure of the device. The device provides a multi-tier programmable interrupt structure which is controlled by the System Interrupt Controller. The programmable system interrupts are generated internally by the various device sub-modules and can be configured to generate a single external host interrupt via the IRQ interrupt output pin. The programmable nature of the host interrupt provides the user with the ability to optimize performance dependent upon the application requirements. The IRQ interrupt buffer type, polarity and de-assertion interval are modifiable. The IRQ interrupt can be configured as an open-drain output to facilitate the sharing of interrupts with other devices. All internal interrupts are maskable and capable of triggering the IRQ interrupt. 8.2 Interrupt Sources The device is capable of generating the following interrupt types: • • • • • • • Ethernet PHY Interrupts Power Management Interrupts General Purpose Timer Interrupt (GPT) EtherCAT Interrupt Software Interrupt (General Purpose) Device Ready Interrupt Clock Output Test Mode All interrupts are accessed and configured via registers arranged into a multi-tier, branch-like structure, as shown in Figure 8-1. At the top level of the device interrupt structure are the Interrupt Status Register (INT_STS), Interrupt Enable Register (INT_EN) and Interrupt Configuration Register (IRQ_CFG). The Interrupt Status Register (INT_STS) and Interrupt Enable Register (INT_EN) aggregate and enable/disable all interrupts from the various device sub-modules, combining them together to create the IRQ interrupt. These registers provide direct interrupt access/configuration to the General Purpose Timer, software and device ready interrupts. These interrupts can be monitored, enabled/disabled and cleared, directly within these two registers. In addition, event indications are provided for the EtherCAT Slave, Power Management, and Ethernet PHY interrupts. These interrupts differ in that the interrupt sources are generated and cleared in other sub-block registers. The INT_STS register does not provide details on what specific event within the sub-module caused the interrupt and requires the software to poll an additional sub-module interrupt register (as shown in Figure 8-1) to determine the exact interrupt source and clear it. For interrupts which involve multiple registers, only after the interrupt has been serviced and cleared at its source will it be cleared in the INT_STS register. The Interrupt Configuration Register (IRQ_CFG) is responsible for enabling/disabling the IRQ interrupt output pin as well as configuring its properties. The IRQ_CFG register allows the modification of the IRQ pin buffer type, polarity and de-assertion interval. The de-assertion timer guarantees a minimum interrupt de-assertion period for the IRQ output and is programmable via the Interrupt De-assertion Interval (INT_DEAS) field of the Interrupt Configuration Register 2015 Microchip Technology Inc. DS00001909A-page 53 LAN9252 (IRQ_CFG). A setting of all zeros disables the de-assertion timer. The de-assertion interval starts when the IRQ pin deasserts, regardless of the reason. FIGURE 8-1: FUNCTIONAL INTERRUPT HIERARCHY Top Level Interrupt Registers (System CSRs) INT_CFG INT_STS INT_EN PHY B Interrupt Registers Bit 27 (PHY_INT_B) of INT_STS register PHY_INTERRUPT_SOURCE_B PHY_INTERRUPT_MASK_B PHY A Interrupt Registers Bit 26 (PHY_INT_A) of INT_STS register PHY_INTERRUPT_SOURCE_A PHY_INTERRUPT_MASK_A Bit 17 (PME_INT) of INT_STS register Power Management Control Register PMT_CTRL EtherCAT Interrupt Registers Bit 0 (ECAT_INT) of INT_STS register ECAT_AL_EVENT_REQUEST ECAT_AL_EVENT_MASK The following sections detail each category of interrupts and their related registers. Refer to the corresponding function’s chapter for bit-level definitions of all interrupt registers. 8.2.1 ETHERNET PHY INTERRUPTS The Ethernet PHYs each provide a set of identical interrupt sources. The top-level PHY A Interrupt Event (PHY_INT_A) and PHY B Interrupt Event (PHY_INT_B) bits of the Interrupt Status Register (INT_STS) provide indication that a PHY interrupt event occurred in the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x). PHY interrupts are enabled/disabled via their respective PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x). The source of a PHY interrupt can be determined and cleared via the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x). Unique interrupts are generated based on the following events: • • • • • • • • • ENERGYON Activated Auto-Negotiation Complete Remote Fault Detected Link Down (Link Status Negated) Link Up (Link Status Asserted) Auto-Negotiation LP Acknowledge Parallel Detection Fault Auto-Negotiation Page Received Wake-on-LAN Event Detected DS00001909A-page 54 2015 Microchip Technology Inc. LAN9252 In order for an interrupt event to trigger the external IRQ interrupt pin, the desired PHY interrupt event must be enabled in the corresponding PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x), the PHY A Interrupt Event Enable (PHY_INT_A_EN) and/or PHY B Interrupt Event Enable (PHY_INT_B_EN) bits of the Interrupt Enable Register (INT_EN) must be set and the IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register (IRQ_CFG). For additional details on the Ethernet PHY interrupts, refer to Section 11.2.7, "PHY Interrupts," on page 128. 8.2.2 POWER MANAGEMENT INTERRUPTS Multiple Power Management Event interrupt sources are provided by the device. The top-level Power Management Interrupt Event (PME_INT) bit of the Interrupt Status Register (INT_STS) provides indication that a Power Management interrupt event occurred in the Power Management Control Register (PMT_CTRL). The Power Management Control Register (PMT_CTRL) provides enabling/disabling and status of all Power Management conditions. These include energy-detect on the PHYs and Wake-On-LAN (Perfect DA, Broadcast, Wake-up frame or Magic Packet) detection by PHYs A&B. In order for a Power Management interrupt event to trigger the external IRQ interrupt pin, the desired Power Management interrupt event must be enabled in the Power Management Control Register (PMT_CTRL), the Power Management Event Interrupt Enable (PME_INT_EN) bit of the Interrupt Enable Register (INT_EN) must be set and the IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit 8 of the Interrupt Configuration Register (IRQ_CFG). The power management interrupts are only a portion of the power management features of the device. For additional details on power management, refer to Section 6.3, "Power Management," on page 43. 8.2.3 GENERAL PURPOSE TIMER INTERRUPT A GP Timer (GPT_INT) interrupt is provided in the top-level Interrupt Status Register (INT_STS) and Interrupt Enable Register (INT_EN). This interrupt is issued when the General Purpose Timer Count Register (GPT_CNT) wraps past zero to FFFFh and is cleared when the GP Timer (GPT_INT) bit of the Interrupt Status Register (INT_STS) is written with 1. In order for a General Purpose Timer interrupt event to trigger the external IRQ interrupt pin, the GPT must be enabled via the General Purpose Timer Enable (TIMER_EN) bit in the General Purpose Timer Configuration Register (GPT_CFG), the GP Timer Interrupt Enable (GPT_INT_EN) bit of the Interrupt Enable Register (INT_EN) must be set and the IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register (IRQ_CFG). For additional details on the General Purpose Timer, refer to Section 15.1, "General Purpose Timer," on page 297. 8.2.4 ETHERCAT INTERRUPT The top-level EtherCAT Interrupt Event (ECAT_INT) of the Interrupt Status Register (INT_STS) provides indication that an EtherCAT interrupt event occurred in the AL Event Request Register. The AL Event Mask Register provides enabling/disabling of all EtherCAT interrupt conditions. The AL Event Request Register provides the status of all EtherCAT interrupts. In order for an EtherCAT interrupt event to trigger the external IRQ interrupt pin, the desired EtherCAT interrupt must be enabled in the AL Event Mask Register, the EtherCAT Interrupt Event Enable (ECAT_INT_EN) bit of the Interrupt Enable Register (INT_EN) must be set and the IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register (IRQ_CFG). For additional details on the EtherCAT interrupts, refer to Section 12.0, "EtherCAT," on page 196. 8.2.5 SOFTWARE INTERRUPT A general purpose software interrupt is provided in the top level Interrupt Status Register (INT_STS) and Interrupt Enable Register (INT_EN). The Software Interrupt (SW_INT) bit of the Interrupt Status Register (INT_STS) is generated when the Software Interrupt Enable (SW_INT_EN) bit of the Interrupt Enable Register (INT_EN) changes from cleared to set (i.e. on the rising edge of the enable). This interrupt provides an easy way for software to generate an interrupt and is designed for general software usage. In order for a Software interrupt event to trigger the external IRQ interrupt pin, the IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register (IRQ_CFG). 2015 Microchip Technology Inc. DS00001909A-page 55 LAN9252 8.2.6 DEVICE READY INTERRUPT A device ready interrupt is provided in the top-level Interrupt Status Register (INT_STS) and Interrupt Enable Register (INT_EN). The Device Ready (READY) bit of the Interrupt Status Register (INT_STS) indicates that the device is ready to be accessed after a power-up or reset condition. Writing a 1 to this bit in the Interrupt Status Register (INT_STS) will clear it. In order for a device ready interrupt event to trigger the external IRQ interrupt pin, the Device Ready Enable (READY_EN) bit of the Interrupt Enable Register (INT_EN) must be set and the IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register (IRQ_CFG). 8.2.7 CLOCK OUTPUT TEST MODE In order to facilitate system level debug, the crystal clock can be enabled onto the IRQ pin by setting the IRQ Clock Select (IRQ_CLK_SELECT) bit of the Interrupt Configuration Register (IRQ_CFG). The IRQ pin should be set to a push-pull driver by using the IRQ Buffer Type (IRQ_TYPE) bit for the best result. 8.3 Interrupt Registers This section details the directly addressable interrupt related System CSRs. These registers control, configure and monitor the IRQ interrupt output pin and the various device interrupt sources. For an overview of the entire directly addressable register map, refer to Section 5.0, "Register Map," on page 32. Table 0.1 Interrupt Registers ADDRESS REGISTER NAME (SYMBOL) 054h Interrupt Configuration Register (IRQ_CFG) 058h Interrupt Status Register (INT_STS) 05Ch Interrupt Enable Register (INT_EN) DS00001909A-page 56 2015 Microchip Technology Inc. LAN9252 8.3.1 INTERRUPT CONFIGURATION REGISTER (IRQ_CFG) Offset: 054h Size: 32 bits This read/write register configures and indicates the state of the IRQ signal. Bits Description Type Default 31:24 Interrupt De-assertion Interval (INT_DEAS) This field determines the Interrupt Request De-assertion Interval in multiples of 10 microseconds. R/W 00h RESERVED RO - Interrupt De-assertion Interval Clear (INT_DEAS_CLR) Writing a 1 to this register clears the de-assertion counter in the Interrupt Controller, thus causing a new de-assertion interval to begin (regardless of whether or not the Interrupt Controller is currently in an active de-assertion interval). R/W SC 0h RO 0b RO 0b RESERVED RO - IRQ Enable (IRQ_EN) This bit controls the final interrupt output to the IRQ pin. When clear, the IRQ output is disabled and permanently de-asserted. This bit has no effect on any internal interrupt status bits. R/W 0b RO - Setting this field to zero causes the device to disable the INT_DEAS Interval, reset the interval counter and issue any pending interrupts. If a new, non-zero value is written to this field, any subsequent interrupts will obey the new setting. 23:15 14 0: Normal operation 1: Clear de-assertion counter 13 Interrupt De-assertion Status (INT_DEAS_STS) When set, this bit indicates that the interrupt controller is currently in a deassertion interval and potential interrupts will not be sent to the IRQ pin. When this bit is clear, the interrupt controller is not currently in a de-assertion interval and interrupts will be sent to the IRQ pin. 0: Interrupt controller not in de-assertion interval 1: Interrupt controller in de-assertion interval 12 Master Interrupt (IRQ_INT) This read-only bit indicates the state of the internal IRQ line, regardless of the setting of the IRQ_EN bit, or the state of the interrupt de-assertion function. When this bit is set, one of the enabled interrupts is currently active. 0: No enabled interrupts active 1: One or more enabled interrupts active 11:9 8 0: Disable output on IRQ pin 1: Enable output on IRQ pin 7:5 RESERVED 2015 Microchip Technology Inc. DS00001909A-page 57 LAN9252 Bits Description Type Default 4 IRQ Polarity (IRQ_POL) When cleared, this bit enables the IRQ line to function as an active low output. When set, the IRQ output is active high. When the IRQ is configured as an open-drain output (via the IRQ_TYPE bit), this bit is ignored and the interrupt is always active low. R/W NASR Note 1 0b RESERVED RO - IRQ Clock Select (IRQ_CLK_SELECT) When this bit is set, the crystal clock may be output on the IRQ pin. This is intended to be used for system debug purposes in order to observe the clock and not for any functional purpose. R/W 0b R/W NASR Note 1 0b 0: IRQ active low output 1: IRQ active high output 3:2 1 Note: 0 When using this bit, the IRQ pin should be set to a push-pull driver. IRQ Buffer Type (IRQ_TYPE) When this bit is cleared, the IRQ pin functions as an open-drain output for use in a wired-or interrupt configuration. When set, the IRQ is a push-pull driver. When configured as an open-drain output, the IRQ_POL bit is ignored and the interrupt output is always active low. 0: IRQ pin open-drain output 1: IRQ pin push-pull driver Note: Note 1: Register bits designated as NASR are not reset when the DIGITAL_RST bit in the Reset Control Register (RESET_CTL) is set. DS00001909A-page 58 2015 Microchip Technology Inc. LAN9252 8.3.2 INTERRUPT STATUS REGISTER (INT_STS) Offset: 058h Size: 32 bits This register contains the current status of the generated interrupts. A value of 1 indicates the corresponding interrupt conditions have been met, while a value of 0 indicates the interrupt conditions have not been met. The bits of this register reflect the status of the interrupt source regardless of whether the source has been enabled as an interrupt in the Interrupt Enable Register (INT_EN). Where indicated as R/WC, writing a 1 to the corresponding bits acknowledges and clears the interrupt. Bits Description Type Default 31 Software Interrupt (SW_INT) This interrupt is generated when the Software Interrupt Enable (SW_INT_EN) bit of the Interrupt Enable Register (INT_EN) is set high. Writing a one clears this interrupt. R/WC 0b 30 Device Ready (READY) This interrupt indicates that the device is ready to be accessed after a power-up or reset condition. R/WC 0b 29 RESERVED RO - 28 RESERVED RO - 27 PHY B Interrupt Event (PHY_INT_B) This bit indicates an interrupt event from PHY B. The source of the interrupt can be determined by polling the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x). RO 0b 26 PHY A Interrupt Event (PHY_INT_A) This bit indicates an interrupt event from PHY A. The source of the interrupt can be determined by polling the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x). RO 0b 25:23 RESERVED RO - 22 RESERVED RO - 21:20 RESERVED RO - R/WC 0b RO - R/WC 0b 19 GP Timer (GPT_INT) This interrupt is issued when the General Purpose Timer Count Register (GPT_CNT) wraps past zero to FFFFh. 18 RESERVED 17 Power Management Interrupt Event (PME_INT) This interrupt is issued when a Power Management Event is detected as configured in the Power Management Control Register (PMT_CTRL). Writing a '1' clears this bit. In order to clear this bit, all unmasked bits in the Power Management Control Register (PMT_CTRL) must first be cleared. Note: The Interrupt De-assertion interval does not apply to the PME interrupt. 16:13 RESERVED RO - 12 RESERVED RO - 2015 Microchip Technology Inc. DS00001909A-page 59 LAN9252 Bits Description Type Default 11:3 RESERVED RO - 2:1 RESERVED RO - EtherCAT Interrupt Event (ECAT_INT) This bit indicates an EtherCAT interrupt event. The source of the interrupt can be determined by polling the AL Event Request Register. RO 0b 0 DS00001909A-page 60 2015 Microchip Technology Inc. LAN9252 8.3.3 INTERRUPT ENABLE REGISTER (INT_EN) Offset: 05Ch Size: 32 bits This register contains the interrupt enables for the IRQ output pin. Writing 1 to any of the bits enables the corresponding interrupt as a source for IRQ. Bits in the Interrupt Status Register (INT_STS) register will still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt in this register (with the exception of Software Interrupt Enable (SW_INT_EN). For descriptions of each interrupt, refer to the Interrupt Status Register (INT_STS) bits, which mimic the layout of this register. Bits Description Type Default 31 Software Interrupt Enable (SW_INT_EN) R/W 0b 30 Device Ready Enable (READY_EN) R/W 0b 29 RESERVED RO - 28 RESERVED RO - 27 PHY B Interrupt Event Enable (PHY_INT_B_EN) R/W 0b 26 PHY A Interrupt Event Enable (PHY_INT_A_EN) R/W 0b 25:23 RESERVED RO - 22 RESERVED RO - 21:20 RESERVED RO - 19 GP Timer Interrupt Enable (GPT_INT_EN) R/W 0b 18 RESERVED RO - 17 Power Management Event Interrupt Enable (PME_INT_EN) R/W 0b 16:13 RESERVED RO - 12 RESERVED RO - 11:3 RESERVED RO - 2:1 RESERVED RO - EtherCAT Interrupt Event Enable (ECAT_INT_EN) R/W 0b 0 2015 Microchip Technology Inc. DS00001909A-page 61 LAN9252 9.0 HOST BUS INTERFACE 9.1 Functional Overview The Host Bus Interface (HBI) module provides a high-speed asynchronous slave interface that facilitates communication between the device and a host system. The HBI allows access to the System CSRs and internal FIFOs and memories and handles byte swapping based on the endianness select. The following is an overview of the functions provided by the HBI: • Address bus input: Two addressing modes are supported. These are a multiplexed address / data bus and a demultiplexed address bus with address index register accesses. The mode selection is done through a configuration input. • Selectable data bus width: The host data bus width is selectable. 16 and 8-bit data modes are supported. This selection is done through a configuration input. The HBI performs BYTE and WORD to DWORD assembly on write data and keeps track of the BYTE / WORD count for reads. Individual BYTE access in 16-bit mode is not supported. • Selectable read / write control modes: Two control modes are available. Separate read and write pins or an enable and direction pin. The mode selection is done through a configuration input. • Selectable control line polarity: The polarity of the chip select, read / write and address latch signals is selectable through configuration inputs. • Dynamic Endianness control: The HBI supports the selection of big and little endian host byte ordering based on the endianness signal. This highly flexible interface provides mixed endian access for registers and memory. Depending on the addressing mode of the device, this signal is either configuration register controlled or as part of the strobed address input. • Direct FIFO access: A FIFO direct select signal directs all host write operations to the EtherCAT Process RAM Write Data FIFO (Multiplexed Address Mode only) and all host read operations from EtherCAT Process RAM Read Data FIFO (Multiplexed Address Mode only). This signal is strobed as part of the address input. 9.2 Read / Write Control Signals The device supports two distinct read / write signal methods: • read (RD) and write (WR) strobes are input on separate pins. • read and write signals are decoded from an enable input (ENB) and a direction input (RD_WR). 9.3 Control Line Polarity The device supports polarity control on the following: • • • • chip select input (CS) read strobe (RD) / direction input (RD_WR) write strobe (WR) / enable input (ENB) address latch control (ALELO and ALEHI) 9.4 Multiplexed Address / Data Mode In Multiplexed Address / Data mode, the address, FIFO Direct Select and endianness select inputs are shared with the data bus. Two methods are supported, a single phase address, utilizing up to 16 address / data pins and a dual phase address, utilizing only the lower 8 data bits. 9.4.1 9.4.1.1 ADDRESS LATCH CYCLES Single Phase Address Latching In Single Phase mode, all address bits, the FIFO Direct Select signal and the endianness select are strobed into the device using the trailing edge of the ALELO signal. The address latch is implemented on all 16 address / data pins. In 8-bit data mode, where pins AD[15:8] are used exclusively for addressing, it is not necessary to drive these upper address lines with a valid address continually through read and write operations. However, this operation, referred to as Partial Address Multiplexing, is acceptable since the device will never drive these pins. DS00001909A-page 62 2015 Microchip Technology Inc. LAN9252 Qualification of the ALELO signal with the CS signal is selectable. When qualification is enabled, CS must be active during ALELO in order to strobe the address inputs. When qualification is not enabled, CS is a don’t care during the address phase. The address is retained for all future read and write operations. It is retained until either a reset event occurs or a new address is loaded. This allows multiple read and write requests to take place to the same address, without requiring multiple address latching operations. 9.4.1.2 Dual Phase Address Latching In Dual Phase mode, the lower 8 address bits are strobed into the device using the inactive going edge of the ALELO signal and the remaining upper address bits, the FIFO Direct Select signals and the endianness select are strobed into the device using the trailing edge of the ALEHI signal. The strobes can be in either order. In 8-bit data mode, pins AD[15:8] are not used. In 16-bit data mode, pins D[15:8] are used only for data. Qualification of the ALELO and ALEHI signals with the CS signal is selectable. When qualification is enabled, CS must be active during ALELO and ALEHI in order to strobe the address inputs. When qualification is not enabled, CS is a don’t care during the address phase. The address is retained for all future read and write operations. It is retained until either a reset event occurs or a new address is loaded. This allows multiple read and write requests to take place to the same address, without requiring multiple address latching operations. 9.4.1.3 Address Bit to Address / Data Pin Mapping In 8-bit data mode, address bit 0 is multiplexed onto pin AD[0], address bit 1 onto pin AD[1], etc. The highest address bit is bit 9 and is multiplexed onto pin AD[9] (single phase) or AD[1] (dual phase). The address latched into the device is considered a BYTE address and covers 1K bytes (0 to 3FFh). In 16-bit data mode, address bit 1 is multiplexed onto pin AD[0], address bit 2 onto pin AD[1], etc. The highest address bit is bit 9 and is multiplexed onto pin AD[8] (single phase) or AD[0] (dual phase). The address latched into the device is considered a WORD address and covers 512 words (0 to 1FFh). When the address is sent to the rest of the device, it is converted to a BYTE address. 9.4.1.4 Endianness Select to Address / Data Pin Mapping The endianness select is included into the multiplexed address to allow the host system to dynamically select the endianness based on the memory address used. This allows for mixed endian access for registers and memory. The endianness selection is multiplexed to the data pin one bit above the last address bit. 9.4.1.5 FIFO Direct Select to Address / Data Pin Mapping The FIFO Direct Select signal is included into the multiplexed address to allow the host system to address the EtherCAT Process RAM Data FIFOs as if they were a large flat address space. The FIFO Direct Select signal is multiplexed to the data pin two bits above the last address bit. 9.4.2 DATA CYCLES The host data bus can be 16 or 8-bits wide while all internal registers are 32 bits wide. The Host Bus Interface performs the conversion from WORDs or BYTEs to DWORD, while in 8 or 16-bit data mode. Two or four contiguous accesses within the same DWORD are required in order to perform a write or read. 9.4.2.1 Write Cycles A write cycle occurs when CS and WR are active (or when ENB is active with RD_WR indicating write). The host address and endianness were already captured during the address latch cycle. On the trailing edge of the write cycle (either WR or CS or ENB going inactive), the host data is captured into registers in the HBI. Depending on the bus width, either a WORD or a BYTE is captured. For 8 or 16-bit data modes, this functions as the DWORD assembly with the affected WORD or BYTE determined by the lower address inputs. BYTE swapping is also done at this point based on the endianness. WRITES FOLLOWING INITIALIZATION Following device initialization, writes from the Host Bus are ignored until after a read cycle is performed. WRITES DURING AND FOLLOWING POWER MANAGEMENT 2015 Microchip Technology Inc. DS00001909A-page 63 LAN9252 During and following any power management mode other than D0, writes from the Host Bus are ignored until after a read cycle is performed. 8 AND 16-BIT ACCESS While in 8 or 16-bit data mode, the host is required to perform two or four, 16 or 8-bit writes to complete a single DWORD transfer. No ordering requirements exist. The host can access either the low or high WORD or BYTE first, as long as the other write(s) is(are) performed to the remaining WORD or BYTEs. Note: Writing the same WORD or BYTEs in the same DWORD assemble cycle may cause undefined or undesirable operation. The HBI hardware does not protect against this operation. A write BYTE / WORD counter keeps track of the number of writes. At the trailing edge of the write cycle, the counter is incremented. Once all writes occur, a 32-bit write is performed to the internal register. The write BYTE / WORD counter is reset if the power management mode is set to anything other than D0. 9.4.2.2 Read Cycles A read cycle occurs when CS and RD are active (or when ENB is active with RD_WR indicating read). The host address and endianness were already captured during the address latch cycle. At the beginning of the read cycle, the appropriate register is selected and its data is driven onto the data pins. Depending on the bus width, either a WORD or a BYTE is read. For 8 or 16-bit data modes, the returned BYTE or WORD is determined by the endianness and the lower address inputs. POLLING FOR INITIALIZATION COMPLETE Before device initialization, the HBI will not return valid data. To determine when the HBI is functional, the Byte Order Test Register (BYTE_TEST) should be polled. Each poll should consist of an address latch cycle(s) and a data cycle. Once the correct pattern is read, the interface can be considered functional. At this point, the Device Ready (READY) bit in the Hardware Configuration Register (HW_CFG) can be polled to determine when the device is fully configured. READS DURING AND FOLLOWING POWER MANAGEMENT During any power management mode other than D0, reads from the Host Bus are ignored. If the power management mode changes back to D0 during an active read cycle, the tail end of the read cycle is ignored. Internal registers are not affected and the state of the HBI does not change. 8 AND 16-BIT ACCESS For certain register accesses, the host is required to perform two or four consecutive 16 or 8-bit reads to complete a single DWORD transfer. No ordering requirements exist. The host can access either the low or high WORD or BYTE first, as long as the other read(s) is(are) performed from the remaining WORD or BYTEs. Note: Reading the same WORD or BYTEs from the same DWORD may cause undefined or undesirable operation. The HBI hardware does not protect against this operation. The HBI simply counts that four BYTEs have been read. A read BYTE / WORD counter keeps track of the number of reads. This counter is separate from the write counter above. At the trailing edge of the read cycle, the counter is incremented. On the last read for the DWORD, an internal read is performed to update any Change on Read CSRs. The read BYTE / WORD counter is reset if the power management mode is set to anything other than D0. SPECIAL CSR HANDLING Live Bits Any register bit that is updated by a H/W event is held at the beginning of the read cycle to prevent it from changing during the read cycle. Multiple BYTE / WORD Live Registers in 16 or 8-Bit Modes Some registers have “live” fields or related fields that span across multiple BYTEs or WORDs. For 16 and 8-bit data reads, it is possible for the value of these fields to change between host read cycles. In order to prevent reading intermediate values, these registers are locked when the first byte or word is read and unlocked when the last byte or word is read. The registers are unlocked if the power management mode is set to anything other than D0. DS00001909A-page 64 2015 Microchip Technology Inc. LAN9252 Change on Read Registers and FIFOs FIFOs or “Change on Read” registers, are updated at the end of the read cycle. For 16 and 8-bit modes, only one internal read cycle is indicated and occurs for the last byte or word. Change on Read Live Register Bits As described above, registers with live bits are held starting at the beginning of the read cycle and those that have multiple bits that span across BYTES or WORDS are also locked for 16 and 8-bit accesses. Although a H/W event that occurs during the hold or lock time would still update the live bit(s), the live bit(s) will be affected (cleared, etc.) at the end of the read cycle and the H/W event would be lost. In order to prevent this, the individual CSRs defer the H/W event update until after the read or multiple reads. Register Polling During Reset Or Initialization Some registers support polling during reset or device initialization to determine when the device is accessible. For these registers, only one read may be performed without the need to read the other WORD or BYTEs. The same BYTE or WORD of the register may be re-read repeatedly. A register that is 16 or 8-bit readable or readable during reset or device initialization, is noted in its register description. 9.4.2.3 Host Endianness The device supports big and little endian host byte ordering based upon the endianness select that is latched during the address latch cycle. When the endianness select is low, host access is little endian and when high, host access is big endian. In a typical application the endianness select is connected to a high-order address line, making endian selection address-based. This highly flexible interface provides mixed endian access for registers and memory for both PIO and host DMA access. All internal busses are 32-bit with little endian byte ordering. Logic within the Host Bus Interface re-orders bytes based on the appropriate endianness bit, and the state of the least significant address bits. Data path operations for the supported endian configurations and data bus sizes are illustrated in FIGURE 9-1: Little Endian Ordering on page 66 and FIGURE 9-2: Big Endian Ordering on page 67. 2015 Microchip Technology Inc. DS00001909A-page 65 LAN9252 FIGURE 9-1: LITTLE ENDIAN ORDERING 8-BIT LITTLE ENDIAN INTERNAL ORDER MSB 31 LSB 24 23 3 16 15 2 8 7 1 A=3 3 A=2 2 A=1 1 A=0 0 7 0 0 0 HOST DATA BUS 16-BIT LITTLE ENDIAN INTERNAL ORDER MSB 31 LSB 24 23 16 15 8 3 2 1 A=1 3 2 A=0 1 0 15 8 7 7 0 0 0 HOST DATA BUS DS00001909A-page 66 2015 Microchip Technology Inc. LAN9252 FIGURE 9-2: BIG ENDIAN ORDERING 8-BIT BIG ENDIAN INTERNAL ORDER MSB 31 LSB 24 23 3 16 15 2 8 7 1 A=3 0 A=2 1 A=1 2 A=0 3 7 0 0 0 HOST DATA BUS 16-BIT BIG ENDIAN INTERNAL ORDER MSB 31 LSB 24 23 16 15 8 3 2 1 A=1 0 1 A=0 2 3 15 8 7 7 0 0 0 HOST DATA BUS 2015 Microchip Technology Inc. DS00001909A-page 67 LAN9252 9.4.3 9.4.3.1 ETHERCAT PROCESS RAM DATA FIFO ACCESS FIFO Direct Select Access A FIFO Direct Select signal is provided allows the host system to address the EtherCAT Process RAM Data FIFOs as if they were a large flat address space. When the FIFO Direct Select signal, which was latched during the address latch cycle, is active all host write operations are to the EtherCAT Process RAM Write Data FIFO and all host read operations are from EtherCAT Process RAM Read Data FIFO. Only the lower latched address signals are decoded in order to select the proper BYTE or WORD. All other address inputs are ignored in this mode. All other operations are the same (DWORD assembly, FIFO popping, etc.). The endianness of FIFO Direct Select accesses is determined by the endianness select that was latched during the address latch cycle. Burst access when reading EtherCAT Process RAM Read Data FIFO is not supported. However, since the FIFO Direct Select signal is retained until either a reset event occurs or a new address is loaded, multiple read or write requests can occur without requiring multiple address latching operations. 9.4.4 MULTIPLEXED ADDRESSING MODE FUNCTIONAL TIMING DIAGRAMS The following timing diagrams illustrate example multiplexed addressing mode read and write cycles for various address/data configurations and bus sizes. These diagrams do not cover every supported host bus permutation, but are selected to detail the main configuration differences (bus size, dual/single phase address latching) within the multiplexed addressing mode of operation. The following should be noted for the timing diagrams in this section: • The diagrams in this section depict active-high ALEHI/ALELO, CS, RD, and WR signals. The polarities of these signals are selectable via the HBI ALE Polarity, HBI Chip Select Polarity, HBI Read, Read/Write Polarity, and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes), respectively. Refer to Section 9.3, "Control Line Polarity," on page 62 for additional details. • The diagrams in this section depict little endian byte ordering. However, dynamic big and little endianess are supported via the endianess signal. Endianess changes only the order of the bytes involved, and not the overall timing requirements. Refer to Section 9.4.1.4, "Endianness Select to Address / Data Pin Mapping," on page 63 for additional information. • The diagrams in Section 9.4.4.1, "Dual Phase Address Latching" and Section 9.4.4.2, "Single Phase Address Latching" utilize RD and WR signals. Alternative RD_WR and ENB signaling is also supported, as shown in Section 9.4.4.3, "RD_WR / ENB Control Mode Examples". The HBI read/write mode is selectable via the HBI Read/ Write Mode bit of the PDI Configuration Register (HBI Modes). The polarities of the RD_WR and ENB signals are selectable via the HBI Read, Read/Write Polarity and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes). • Qualification of the ALELO and/or ALEHI with the CS signal is selectable via the HBI ALE Qualification bit of the PDI Configuration Register (HBI Modes). Refer to Section 9.4.1.1, "Single Phase Address Latching," on page 62 and Section 9.4.1.2, "Dual Phase Address Latching," on page 63 for additional information. • In dual phase address latching mode, the ALEHI and ALELO cycles can be in any order. Either or both ALELO and ALEHI cycles maybe skipped and the device retains the last latched address. • In single phase address latching mode, the ALELO cycle maybe skipped and the device retains the last latched address. Note: In 8 and 16-bit modes, the ALELO cycle is normally not skipped since sequential BYTEs or WORDs are accessed in order to satisfy a complete DWORD cycle. However, there are registers for which a single BYTE or WORD access is allowed, in which case multiple accesses to these registers may be performed without the need to re-latch the repeated address. • For 16 and 8-bit modes, consecutive address cycles must be within the same DWORD until the DWORD is completely accessed (with the register exceptions noted above). Although BYTEs and WORDs can be accessed in any order, the diagrams in this section depict accessing the lower address BYTE or WORD first. DS00001909A-page 68 2015 Microchip Technology Inc. LAN9252 9.4.4.1 Dual Phase Address Latching The figures in this section detail read and write operations in multiplexed addressing mode with dual phase address latching for 16 and 8-bit modes. 16-BIT READ The address is latched sequentially from AD[7:0]. AD[15:8] is not used or driven for the address phase. A read on AD[15:0] follows. The cycle is repeated for the other 16-bits of the DWORD. FIGURE 9-3: MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 16-BIT READ ALELO ALEHI Optional CS Optional RD WR Data 15:8 AD[15:8] AD[7:0] Address Low Address High Data 7:0 Data 31:24 Address+1 Low Address High Data 23:16 16-BIT READ WITH SUPPRESSED ALEHI The address is latched sequentially from AD[7:0]. AD[15:8] is not used or driven for the address phase. A read on AD[15:0] follows. The lower address is then updated to access the opposite WORD. FIGURE 9-4: MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 16-BIT READ WITHOUT ALEHI ALELO ALEHI Optional CS Optional RD WR Data 15:8 AD[15:8] AD[7:0] Address Low 2015 Microchip Technology Inc. Address High Data 7:0 Data 31:24 Address+1 Low Data 23:16 DS00001909A-page 69 LAN9252 16-BIT WRITE The address is latched sequentially from AD[7:0]. AD[15:8] is not used or driven for the address phase. A write on AD[15:0] follows. The cycle is repeated for the other 16-bits of the DWORD. FIGURE 9-5: MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 16-BIT WRITE ALELO ALEHI Optional CS Optional RD WR Data 15:8 AD[15:8] AD[7:0] Address Low Address High Data 7:0 Data 31:24 Address+1 Low Address High Data 23:16 16-BIT WRITE WITH SUPPRESSED ALEHI The address is latched sequentially from AD[7:0]. AD[15:8] is not used or driven for the address phase. A write on AD[15:0] follows. The lower address is then updated to access the opposite WORD. FIGURE 9-6: MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 16-BIT WRITE WITHOUT ALEHI ALELO ALEHI Optional CS Optional RD WR Data 15:8 AD[15:8] AD[7:0] DS00001909A-page 70 Address Low Address High Data 7:0 Data 31:24 Address+1 Low Data 23:16 2015 Microchip Technology Inc. LAN9252 16-BIT READS AND WRITES TO CONSTANT ADDRESS The address is latched sequentially from AD[7:0]. AD[15:8] is not used or driven for the address phase. A mix of reads and writes on AD[15:0] follows. Note: Generally, two 16-bit reads to opposite WORDs of the same DWORD are required, with at least the lower address changing using ALELO. 16-bit reads and writes to the same WORD is a special case. FIGURE 9-7: MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 16-BIT READS AND WRITES CONSTANT ADDRESS ALELO ALEHI Optional CS RD WR AD[15:8] AD[7:0] Address Low Address High Data 15:8 Data 15:8 Data 15:8 Data 15:8 Data 15:8 Data 7:0 Data 7:0 Data 7:0 Data 7:0 Data 7:0 8-BIT READ The address is latched sequentially from AD[7:0]. A read on AD[7:0] follows. AD[15:8] pins are not used or driven. The cycle is repeated for the other BYTEs of the DWORD. FIGURE 9-8: MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 8-BIT READS ALELO ALEHI Optional CS Optional Optional Optional RD WR Hi-Z AD[15:8] AD[7:0] Address Low Address High Data 7:0 2015 Microchip Technology Inc. Address+1 Low Address High Data 15:8 Address+2 Low Address High Data 23:16 Address+3 Low Address High Data 31:24 DS00001909A-page 71 LAN9252 8-BIT READ WITH SUPPRESSED ALEHI The address is latched sequentially from AD[7:0]. A read on AD[7:0] follows. AD[15:8] pins are not used or driven. The lower address is then updated to access the other BYTEs. FIGURE 9-9: MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 8-BIT READS WITHOUT ALEHI ALELO ALEHI Optional CS Optional Optional Optional RD WR Hi-Z AD[15:8] AD[7:0] Address Low Address High Data 7:0 Address+1 Low Data 15:8 Address+2 Low Data 23:16 Address+3 Low Data 31:24 8-BIT WRITE The address is latched sequentially from AD[7:0]. A write on AD[7:0] follows. AD[15:8] pins are not used or driven. The cycle is repeated for the other BYTEs of the DWORD. FIGURE 9-10: MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 8-BIT WRITE ALELO ALEHI Optional CS Optional Optional Optional RD WR Hi-Z AD[15:8] AD[7:0] Address Low Address High DS00001909A-page 72 Data 7:0 Address+1 Low Address High Data 15:8 Address+2 Low Address High Data 23:16 Address+3 Low Address High Data 31:24 2015 Microchip Technology Inc. LAN9252 8-BIT WRITE WITH SUPPRESSED ALEHI The address is latched sequentially from AD[7:0]. A write on AD[7:0] follows. AD[15:8] pins are not used or driven. The lower address is then updated to access the other BYTEs. FIGURE 9-11: MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 8-BIT WRITE WITHOUT ALEHI ALELO ALEHI Optional CS Optional Optional Optional RD WR Hi-Z AD[15:8] AD[7:0] Address Low Address High Data 7:0 Address+1 Low Data 15:8 Address+2 Low Data 23:16 Address+3 Low Data 31:24 8-BIT READS AND WRITES TO CONSTANT ADDRESS The address is latched sequentially from AD[7:0]. A mix of reads and writes on AD[7:0] follows. AD[15:8] pins are not used or driven. Note: Generally, four 8-bit reads to opposite BYTEs of the same DWORD are required, with at least the lower address changing using ALELO. 8-bit reads and writes to the same BYTE is a special case. FIGURE 9-12: MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 8-BIT READS AND WRITES CONSTANT ADDRESS ALELO ALEHI Optional CS RD WR Hi-Z AD[15:8] AD[7:0] Address Low 2015 Microchip Technology Inc. Address High Data 7:0 Data 7:0 Data 7:0 Data 7:0 Data 7:0 DS00001909A-page 73 LAN9252 9.4.4.2 Single Phase Address Latching The figures in this section detail multiplexed addressing mode with single phase addressing for 16 and 8-bit modes of operation. 16-BIT READ The address is latched simultaneously from AD[7:0] and AD[15:8]. A read on AD[15:0] follows. The cycle is repeated for the other 16-bits of the DWORD. FIGURE 9-13: MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 16-BIT READ ALELO ALEHI CS Optional Optional RD WR AD[15:8] Address High Data 15:8 Address High Data 31:24 AD[7:0] Address Low Data 7:0 Address+1 Low Data 23:16 16-BIT WRITE The address is latched simultaneously from AD[7:0] and AD[15:8]. A write on AD[15:0] follows. The cycle is repeated for the other 16-bits of the DWORD. FIGURE 9-14: MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 16-BIT WRITE ALELO ALEHI CS Optional Optional RD WR DS00001909A-page 74 AD[15:8] Address High Data 15:8 Address High Data 31:24 AD[7:0] Address Low Data 7:0 Address+1 Low Data 23:16 2015 Microchip Technology Inc. LAN9252 16-BIT READS AND WRITES TO CONSTANT ADDRESS The address is latched simultaneously from AD[7:0] and AD[15:8]. A mix of reads and writes on AD[15:0] follows. Note: Generally, two 16-bit reads to opposite WORDs of the same DWORD are required. 16-bit reads and writes to the same WORD is a special case. FIGURE 9-15: MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 16-BIT READS AND WRITES CONSTANT ADDRESS ALELO ALEHI CS Optional RD WR AD[15:8] Address High Data 15:8 Data 15:8 Data 15:8 Data 15:8 Data 15:8 AD[7:0] Address Low Data 7:0 Data 7:0 Data 7:0 Data 7:0 Data 7:0 8-BIT READ The address is latched simultaneously from AD[7:0] and AD[15:8]. A read on AD[7:0] follows. AD[15:8] pins are not used or driven for the data phase as the host could potentially continue to drive the upper address on these signals. The cycle is repeated for the other BYTEs of the DWORD. FIGURE 9-16: MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 8-BIT READ ALELO ALEHI CS Optional Optional Optional Optional RD WR AD[15:8] Address High AD[7:0] Address Low Address High Data 7:0 2015 Microchip Technology Inc. Address+1 Low Address High Data 15:8 Address+2 Low Address High Data 23:16 Address+3 Low Data 31:24 DS00001909A-page 75 LAN9252 8-BIT WRITE The address is latched simultaneously from AD[7:0] and AD[15:8]. A write on AD[7:0] follows. AD[15:8] pins are not used or driven for the data phase as the host could potentially continue to drive the upper address on these signals. The cycle is repeated for the other BYTEs of the DWORD. FIGURE 9-17: MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 8-BIT WRITE ALELO ALEHI CS Optional Optional Optional Optional RD WR AD[15:8] Address High AD[7:0] Address Low Address High Data 7:0 Address+1 Low Address High Data 15:8 Address+2 Low Address High Data 23:16 Address+3 Low Data 31:24 8-BIT READS AND WRITES TO CONSTANT ADDRESS The address is latched simultaneously from AD[7:0] and AD[15:8]. A mix of reads and writes on AD[7:0] follows. AD[15:8] pins are not used or driven for the data phase as the host could potentially continue to drive the upper address on these signals. Note: Generally, four 8-bit reads to opposite BYTEs of the same DWORD are required. 8-bit reads and writes to the same BYTE is a special case. FIGURE 9-18: MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 8-BIT READS AND WRITES CONSTANT ADDRESS ALELO ALEHI CS Optional RD WR AD[15:8] Address High AD[7:0] Address Low DS00001909A-page 76 Data 7:0 Data 7:0 Data 7:0 Data 7:0 Data 7:0 2015 Microchip Technology Inc. LAN9252 9.4.4.3 RD_WR / ENB Control Mode Examples The figures in this section detail read and write operations utilizing the alternative RD_WR and ENB signaling. The HBI read/write mode is selectable via the HBI Read/Write Mode bit of the PDI Configuration Register (HBI Modes). Note: The examples in this section detail 16-bit mode with dual phase latching. However, the RD_WR and ENB signaling can be used identically in all other multiplexed addressing modes of operation. The examples in this section show the ENB signal active-high and the RD_WR signal low for read and high for write. The polarities of the RD_WR and ENB signals are selectable via the HBI Read, Read/Write Polarity and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes). 16-BIT FIGURE 9-19: MULTIPLEXED ADDRESSING RD_WR / ENB CONTROL MODE EXAMPLE - 16BIT READ ALELO ALEHI Optional CS Optional RD_WR ENB Data 15:8 AD[15:8] AD[7:0] FIGURE 9-20: Address Low Address High Data 7:0 Data 31:24 Address+1 Low Address High Data 23:16 MULTIPLEXED ADDRESSING RD_WR / ENB CONTROL MODE EXAMPLE - 16BIT WRITE ALELO ALEHI Optional CS Optional RD_WR ENB Data 15:8 AD[15:8] AD[7:0] Address Low 2015 Microchip Technology Inc. Address High Data 7:0 Data 31:24 Address+1 Low Address High Data 23:16 DS00001909A-page 77 LAN9252 9.4.5 MULTIPLEXED ADDRESSING MODE TIMING REQUIREMENTS The following figures and tables specify the timing requirements during Multiplexed Address / Data mode. Since timing requirements are similar across the multitude of operations (e.g. dual vs. single phase, 8 vs. 16-bit), many timing requirements are illustrated onto the same figures and do not necessarily represent any particular functional operation. The following should be noted for the timing specifications in this section: • The diagrams in this section depict active-high ALEHI/ALELO, CS, RD, WR, RD_WR and ENB signals. The polarities of these signals are selectable via the HBI ALE Polarity, HBI Chip Select Polarity, HBI Read, Read/Write Polarity, and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes), respectively. Refer to Section 9.3, "Control Line Polarity," on page 62 for additional details. • Qualification of the ALELO and/or ALEHI with the CS signal is selectable via the HBI ALE Qualification bit of the PDI Configuration Register (HBI Modes). This is shown as a dashed line. Timing requirements between ALELO / ALEHI and CS only apply when this mode is active. • In dual phase address latching mode, the ALEHI and ALELO cycles can be in any order. ALEHI first is depicted in solid line. ALELO first is depicted in dashed line. • A read cycle maybe followed by followed by an address cycle, a write cycle or another read cycle. A write cycle maybe followed by followed by a read cycle or another write cycle. These are shown in dashed line. 9.4.5.1 Read Timing Requirements If RD and WR signaling is used, a host read cycle begins when RD is asserted with CS active. The cycle ends when RD is de-asserted. CS maybe asserted and de-asserted along with RD but not during RD active. Alternatively, if RD_WR and ENB signaling is used, a host read cycle begins when ENB is asserted with CS active and RD_WR indicating a read. The cycle ends when ENB is de-asserted. CS maybe asserted and de-asserted along with ENB but not during ENB active. Please refer to Section 9.4.4, "Multiplexed Addressing Mode Functional Timing Diagrams," on page 68 for functional descriptions. FIGURE 9-21: MULTIPLEXED ADDRESSING READ CYCLE TIMING tcsale tcsrd trdcs CS twale trdale ALEHI taleale trdale ALELO tadrs tadrh AD[7:0] input AD[15:8] input RD_WR trdwrs talerd trdwrh trd trdcyc trdrd ENB, RD trdwr WR taledv trdon, tcson trddv, tcsdv trddh, tcsdh trddz, tcsdz AD[15:8] output AD[7:0] output DS00001909A-page 78 2015 Microchip Technology Inc. LAN9252 TABLE 9-1: MULTIPLEXED ADDRESSING READ CYCLE TIMING VALUES Symbol Description Min Typ max units tcsale CS Setup to ALELO, ALEHI Active Note 3, Note 2 0 ns tcsrd CS Setup to RD or ENB Active 0 ns trdcs CS Hold from RD or ENB Inactive 0 ns twale ALELO, ALEHI Pulse Width 10 ns tadrs Address Setup to ALELO, ALEHI Inactive 10 ns tadrh Address Hold from ALELO, ALEHI Inactive 5 ns taleale ALELO Inactive to ALEHI Active ALEHI Inactive to ALELO Active Note 1, Note 2 0 ns talerd ALELO, ALEHI Inactive to RD or ENB Active Note 2 5 ns trdwrs RD_WR Setup to ENB Active Note 4 5 ns trdwrh RD_WR Hold from ENB Inactive Note 4 5 ns trdon RD or ENB to Data Buffer Turn On 0 ns trddv RD or ENB Active to Data Valid trddh Data Output Hold Time from RD or ENB Inactive trddz Data Buffer Turn Off Time from RD or ENB Inactive tcson CS to Data Buffer Turn On tcsdv CS Active to Data Valid tcsdh Data Output Hold Time from CS Inactive tcsdz Data Buffer Turn Off Time from CS Inactive 9 ns taledv ALELO, ALEHI Inactive to Data Valid Note 2 35 ns 30 0 ns ns 9 0 ns ns 30 0 ns ns trd RD or ENB Active Time 32 ns trdcyc RD or ENB Cycle Time 45 ns trdale RD or ENB De-assertion Time before Address Phase 13 ns trdrd RD or ENB De-assertion Time before Next RD or ENB Note 5 13 ns trdwr RD De-assertion Time before Next WR Note 5, Note 6 13 ns Note 1: Dual Phase Addressing Note 2: Depends on ALEHI / ALELO order. 2015 Microchip Technology Inc. DS00001909A-page 79 LAN9252 Note 3: ALELO and/or ALEHI qualified with the CS. Note 4: RD_WR and ENB signaling. Note 5: No interposed address phase. Note 6: RD and WR signaling. Note: 9.4.5.2 Timing values are with respect to an equivalent test load of 25 pF. Write Timing Requirements If RD and WR signaling is used, a host write cycle begins when WR is asserted with CS active. The cycle ends when WR is de-asserted. CS maybe asserted and de-asserted along with WR but not during WR active. Alternatively, if RD_WR and ENB signaling is used, a host write cycle begins when ENB is asserted with CS active and RD_WR indicating a write. The cycle ends when ENB is de-asserted. CS maybe asserted and de-asserted along with ENB but not during ENB active. Please refer to Section 9.4.4, "Multiplexed Addressing Mode Functional Timing Diagrams," on page 68 for functional descriptions. FIGURE 9-22: MULTIPLEXED ADDRESSING WRITE CYCLE TIMING tcsale tcswr twrcs CS twale twrale ALEHI taleale twrale ALELO tadrs tadrh AD[7:0] input AD[15:8] input RD_WR tds tdh trdwrh trdwrs talewr twr twrcyc twrwr ENB, WR twrrd RD DS00001909A-page 80 2015 Microchip Technology Inc. LAN9252 TABLE 9-2: MULTIPLEXED ADDRESSING WRITE CYCLE TIMING VALUES Symbol Description Min Typ Max Units tcsale CS Setup to ALELO, ALEHI Active Note 9, Note 8 0 ns tcswr CS Setup to WR or ENB Active 0 ns twrcs CS Hold from WR or ENB Inactive 0 ns twale ALELO, ALEHI Pulse Width 10 ns tadrs Address Setup to ALELO, ALEHI Inactive 10 ns tadrh Address Hold from ALELO, ALEHI Inactive 5 ns taleale ALELO Inactive to ALEHI Active ALEHI Inactive to ALELO Active Note 7, Note 8 0 ns talewr ALELO, ALEHI Inactive to WR or ENB Active Note 8 5 ns trdwrs RD_WR Setup to ENB Active Note 10 5 ns trdwrh RD_WR Hold from ENB Inactive Note 10 5 ns tds Data Setup to WR or ENB Inactive 7 ns tdh Data Hold from WR or ENB Inactive 0 ns twr WR or ENB Active Time 32 ns twrcyc WR or ENB Cycle Time 45 ns twrale WR or ENB De-assertion Time before Address Phase 13 ns twrwr WR or ENB De-assertion Time before Next WR or ENB Note 11 13 ns twrrd WR De-assertion Time before Next RD Note 11, Note 12 13 ns Note 7: Dual Phase Addressing Note 8: Depends on ALEHI / ALELO order. Note 9: ALELO and/or ALEHI qualified with the CS. Note 10: RD_WR and ENB signaling. Note 11: No interposed address phase. Note 12: RD and WR signaling. 2015 Microchip Technology Inc. DS00001909A-page 81 LAN9252 9.5 Indexed Address Mode In Indexed Address mode, access to the internal registers and memory of the device are indirectly mapped using Index and Data registers. The desired internal address is written into the device at a particular offset. The value written is then used as the internal address when the associate Data register address is accessed. Three Index / Data register sets are provided allowing for multi-threaded operation without the concern of one thread corrupting the Index set by another thread. Endianness can be configured per Index / Data pair. Another Data register is provided for access to the FIFOs. The host address register map is given below. In 8-bit data mode, the host address input (ADDR[4:0]) is a BYTE address. In 16-bit data mode, ADDR0 is not provided and the host address input (ADDR[4:1]) is a WORD address. As discussed below in Section 9.5.5.1, "Index Register Bypass FIFO Access", the EtherCAT Process RAM Data FIFOs are accessed when reading or writing at address 18h-1Bh. TABLE 9-3: HOST BUS INTERFACE INDEXED ADDRESS MODE REGISTER MAP BYTE ADDRESS SYMBOL 00h-03h HBI_IDX_0 Host Bus Interface Index Register 0 04h-07h HBI_DATA_0 Host Bus Interface Data Register 0 08h-0Bh HBI_IDX_1 Host Bus Interface Index Register 1 0Ch-0Fh HBI_DATA_1 Host Bus Interface Data Register 1 10h-13h HBI_IDX_2 Host Bus Interface Index Register 2 14h-17h HBI_DATA_2 Host Bus Interface Data Register 2 18h-1Bh PROCESS_RAM_FIFO 1Ch-1Fh HBI_CFG DS00001909A-page 82 REGISTER NAME Process RAM Write Data FIFO Process RAM Read Data FIFO Host Bus Interface Configuration Register 2015 Microchip Technology Inc. LAN9252 9.5.1 HOST BUS INTERFACE INDEX REGISTER The Index registers are writable as WORDs or as BYTEs, depending upon the data mode. There is no concern about DWORD assembly rules when writing these registers. The Index registers are formatted as follows: Bits Description Type Default 31:16 RESERVED RO - 15:0 Internal Address The address used when the corresponding Data register is accessed. R/W 1234h Note 13 Note: The internal address provided by each Index register is always considered to be a BYTE address. Note 13: The default may be used to help determine the endianness of the register. 9.5.2 HOST BUS INTERFACE CONFIGURATION REGISTER The HBI Configuration register is used to specify the endianness of the interface. Endianess for each Index / Data pair and for FIFO accesses can be individually specified. The endianness of this register is irrelevant since each byte is shadowed into 4 positions. The HBI Configuration register is writable as WORDs or as BYTEs, depending upon the data mode. There is no concern about DWORD assembly rules when writing this register. The Configuration register is formatted as follows: Bits Type Default RESERVED RO - 27 FIFO Endianness Shadow 3 This bit is a shadow of bit 3. R/W 0b 26 Host Bus Interface Index / Data Register 2 Endianness Shadow 3 This bit is a shadow of bit 2. R/W 0b 25 Host Bus Interface Index / Data Register 1 Endianness Shadow 3 This bit is a shadow of bit 1. R/W 0b 24 Host Bus Interface Index / Data Register 0 Endianness Shadow 3 This bit is a shadow of bit 0. R/W 0b RESERVED RO - 19 FIFO Endianness Shadow 2 This bit is a shadow of bit 3. R/W 0b 18 Host Bus Interface Index / Data Register 2 Endianness Shadow 2 This bit is a shadow of bit 2. R/W 0b 17 Host Bus Interface Index / Data Register 1 Endianness Shadow 2 This bit is a shadow of bit 1. R/W 0b 16 Host Bus Interface Index / Data Register 0 Endianness Shadow 2 This bit is a shadow of bit 0. R/W 0b RESERVED RO - 11 FIFO Endianness Shadow 1 This bit is a shadow of bit 3. R/W 0b 10 Host Bus Interface Index / Data Register 2 Endianness Shadow 1 This bit is a shadow of bit 2. R/W 0b 31:28 23:20 15:12 Description 2015 Microchip Technology Inc. DS00001909A-page 83 LAN9252 Bits Description Type Default 9 Host Bus Interface Index / Data Register 1 Endianness Shadow 1 This bit is a shadow of bit 1. R/W 0b 8 Host Bus Interface Index / Data Register 0 Endianness Shadow 1 This bit is a shadow of bit 0. R/W 0b RESERVED RO - FIFO Endianness This bit specifies the endianness of FIFO accesses when they are accessed by means other than the Index / Data Register method. R/W 0b R/W 0b R/W 0b R/W 0b 7:4 3 0 = Little Endian 1 = Big Endian Note: 2 In order to avoid any ambiguity with the endianness of this register, bits 3, 11, 19 and 27 are shadowed. If any of these bits are set during a write, all of the bits will be set. Host Bus Interface Index / Data Register 2 Endianness This bit specifies the endianness of the Index and Data register set 2. 0 = Little Endian 1 = Big Endian Note: 1 In order to avoid any ambiguity with the endianness of this register, bits 2, 10, 18 and 26 are shadowed. If any of these bits are set during a write, all of the bits will be set. Host Bus Interface Index / Data Register 1 Endianness This bit specifies the endianness of the Index and Data register set 1. 0 = Little Endian 1 = Big Endian Note: 0 In order to avoid any ambiguity with the endianness of this register, bits 1, 9, 17 and 25 are shadowed. If any of these bits are set during a write, all of the bits will be set. Host Bus Interface Index / Data Register 0 Endianness This bit specifies the endianness of the Index and Data register set 0. 0 = Little Endian 1 = Big Endian Note: DS00001909A-page 84 In order to avoid any ambiguity with the endianness of this register, bits 0, 8, 16 and 24 are shadowed. If any of these bits are set during a write, all of the bits will be set. 2015 Microchip Technology Inc. LAN9252 9.5.3 INDEX AND CONFIGURATION REGISTER DATA ACCESS The host data bus can be 16 or 8-bits wide. The HBI Index registers and the HBI Configuration register are 32-bits wide and are writable as WORDs or as BYTEs, depending upon the data mode. They do not have nor do they require WORDs or BYTEs to DWORD conversion. 9.5.3.1 Write Cycles A write cycle occurs when CS and WR are active (or when ENB is active with RD_WR indicating write). On the trailing edge of the write cycle (either WR or CS or ENB going inactive), the host data is captured into the Configuration register or one for the Index registers. Depending on the bus width, either a WORD or a BYTE is written. The affected WORD or BYTE is determined by the endianness of the register (specified in the Host Bus Interface Configuration Register) and the lower address inputs. Individual BYTE (in 16-bit data mode) access is not supported. WRITES FOLLOWING INITIALIZATION Following device initialization, writes from the Host Bus are ignored until after a read cycle is performed. WRITES DURING AND FOLLOWING POWER MANAGEMENT During and following any power management mode other than D0, writes from the Host Bus are ignored until after a read cycle is performed. 9.5.3.2 Read Cycles A read cycle occurs when CS and RD are active (or when ENB is active with RD_WR indicating read). The host address is used directly from the Host Bus. At the beginning of the read cycle, the appropriate register is selected and its data is driven onto the data pins. Depending on the bus width, either a WORD or a BYTE is read. For 8 or 16-bit data modes, the returned BYTE or WORD is determined by the endianness of the register (specified in the Host Bus Interface Configuration Register) and the lower host address inputs. 9.5.4 INTERNAL REGISTER DATA ACCESS The host data bus can be 16 or 8-bits wide while all internal registers are 32 bits wide. The Host Bus Interface performs the conversion from WORDs or BYTEs to DWORD, while in 8 or 16-bit data mode. Two or four accesses within the same DWORD are required in order to perform a write or read. Each Data register, along with the FIFO direct address access, has a separate WORD or BYTE to DWORD conversion. Accesses may be mixed among these (and the HBI Index and Configuration registers) without concern of data corruption. 9.5.4.1 Write Cycles A write cycle occurs when CS and WR are active (or when ENB is active with RD_WR indicating write). The host address from the Host Bus selects the contents of one of the Index registers. The result of this operation is captured on the leading edge of the write cycle. The host address inputs from the Host Bus are also captured on the leading edge of the write cycle. These are used to increment the appropriate write BYTE / WORD counter (for 8 or 16-bit data mode described below) as well as to select the correct DWORD assembly register. On the trailing edge of the write cycle (either WR or CS or ENB going inactive), the host data is captured into one of the Data registers. Depending on the bus width, either a WORD or a BYTE is captured. For 8 or 16-bit data modes, this functions as the DWORD assembly with the affected WORD or BYTE determined by the lower host address inputs. BYTE swapping is also done at this point based on the endianness of the register (specified in the Host Bus Interface Configuration Register). Note: There are separate write BYTE / WORD counters and DWORD assembly registers for each of the three Data Registers as well as for FIFO access. WRITES FOLLOWING INITIALIZATION Following device initialization, writes from the Host Bus are ignored until after a read cycle is performed. 2015 Microchip Technology Inc. DS00001909A-page 85 LAN9252 WRITES DURING AND FOLLOWING POWER MANAGEMENT During and following any power management mode other than D0, writes from the Host Bus are ignored until after a read cycle is performed. 8 AND 16-BIT ACCESS While in 8 or 16-bit data mode, the host is required to perform two or four, 16 or 8-bit writes to complete a single DWORD transfer. No ordering requirements exist. The host can access either the low or high WORD or BYTE first, as long as the other write(s) is(are) performed to the remaining WORD or BYTEs. Note: Writing the same WORD or BYTEs into the same DWORD may cause undefined or undesirable operation. The HBI hardware does not protect against this operation. Accessing the same internal register using two Index / Data register pairs may cause undefined or undesirable operation. The HBI hardware does not protect against this operation. Mixing reads and writes into the same Data register may cause undefined or undesirable operation. The HBI hardware does not protect against this operation. A write BYTE / WORD counter keeps track of the number of writes. Each Data Register has its own BYTE / WORD counter. At the trailing edge of the write cycle, the appropriate counter (based on the captured host address from above) is incremented. Once all writes occur, a 32-bit write is performed to the internal register selected by the captured address from above. The data that is written is selected from one of the three DWORD assembly registers based on the captured host address from above. All of the write BYTE / WORD counters are reset if the power management mode is set to anything other than D0. 9.5.4.2 Read Cycles A read cycle occurs when CS and RD are active (or when ENB is active with RD_WR indicating read). The host address from the Host Bus selects the contents of one of the Index registers. The result of this operation is used to select the internal register to be read and also is captured on the leading edge of the read cycle. The host address inputs from the Host Bus are also captured on the leading edge of the read cycle. These are used to increment the appropriate read BYTE / WORD counter (for 8 or 16-bit data mode described below). At the beginning of the read cycle, the appropriate register is selected and its data is driven onto the data pins. Depending on the bus width, either a WORD or a BYTE is read. For 8 or 16-bit data modes, the returned BYTE or WORD is determined by the endianness of the Data register (specified in the Host Bus Interface Configuration Register) and the lower host address inputs. Note: There are separate read BYTE / WORD counters for each of the three Data Registers as well as for FIFO access. POLLING FOR INITIALIZATION COMPLETE Before device initialization, the HBI will not return valid data. To determine when the HBI is functional, first the Host Bus Interface Index Register 0 should be polled, then the Byte Order Test Register (BYTE_TEST) should be polled. Once the correct pattern is read, the interface can be considered functional. At this point, the Device Ready (READY) bit in the Hardware Configuration Register (HW_CFG) can be polled to determine when the device is fully configured. READS DURING AND FOLLOWING POWER MANAGEMENT During any power management mode other than D0, reads from the Host Bus are ignored. If the power management mode changes back to D0 during an active read cycle, the tail end of the read cycle is ignored. Internal registers are not affected and the state of the HBI does not change. DS00001909A-page 86 2015 Microchip Technology Inc. LAN9252 8 AND 16-BIT ACCESS For certain register accesses, the host is required to perform two or four consecutive 16 or 8-bit reads to complete a single DWORD transfer. No ordering requirements exist. The host can access either the low or high WORD or BYTE first, as long as the other read(s) is(are) performed from the remaining WORD or BYTEs. Note: Reading the same WORD or BYTEs from the same DWORD may cause undefined or undesirable operation. The HBI hardware does not protect against this operation. The HBI simply counts that four BYTEs have been read. Accessing the same internal register using two Index / Data register pairs may cause undefined or undesirable operation. The HBI hardware does not protect against this operation. Mixing reads and writes into the same Data register may cause undefined or undesirable operation. The HBI hardware does not protect against this operation. A read BYTE / WORD counter keeps track of the number of reads. Each Data Register has its own BYTE / WORD counter. These counters are separate from the write counters above. At the trailing edge of the read cycle, the appropriate counter (based on the captured host address from above) is incremented. On the last read for the DWORD, an internal read is performed to update any Change on Read CSRs. All of the read BYTE / WORD counters are reset if the power management mode is set to anything other than D0. SPECIAL CSR HANDLING Live Bits Any register bit that is updated by a H/W event is held at the beginning of the read cycle to prevent it from changing during the read cycle. Multiple BYTE / WORD Live Registers in 16 or 8-Bit Modes Some internal registers have fields or related fields that span across multiple BYTEs or WORDs. For 16 and 8-bit data reads, it is possible that the value of these fields change between host read cycles. In order to prevent reading intermediate values, these registers are locked when the first byte or word is read and unlocked when the last byte or word is read. The registers are unlocked if the power management mode is set to anything other than D0. Change on Read Registers and FIFOs FIFOs or “Change on Read” registers, are updated at the end of the read cycle. For 16 and 8-bit modes, only one internal read cycle is indicated and occurs for the last byte or word. Change on Read Live Register Bits As described above, registers with live bits are held starting at the beginning of the read cycle and those that have multiple bits that span across BYTES or WORDS are also locked for 16 and 8-bit accesses. Although a H/W event that occurs during the hold or lock time would still update the live bit(s), the live bit(s) will be affected (cleared, etc.) at the end of the read cycle and the H/W event would be lost. In order to prevent this, the individual CSRs defer the H/W event update until after the read or multiple reads. Registers Polling During Reset or Initialization Some registers support polling during reset or device initialization to determine when the device is accessible. For these registers, only one read may be performed without the need to read the other WORD or BYTEs. The same BYTE or WORD of the register may be re-read repeatedly. A register that is 16 or 8-bit readable or readable during reset or device initialization, is noted in its register description. 9.5.4.3 Host Endianness The device supports big and little endian host byte ordering based upon the endianness bits in the Host Bus Interface Configuration Register. When the appropriate endianness bit is low, host access is little endian and when high, host access is big endian. Endianness is specified for each Index / Data pair and for FIFO Direct Select accesses. All internal busses are 32-bit with little endian byte ordering. Logic within the Host Bus Interface re-orders bytes based on the appropriate endianness bit, and the state of the least significant address lines (ADDR[1:0]). 2015 Microchip Technology Inc. DS00001909A-page 87 LAN9252 Data path operations for the supported endian configurations and data bus sizes are illustrated in FIGURE 9-23: Little Endian Ordering on page 88 and FIGURE 9-24: Big Endian Ordering on page 89. FIGURE 9-23: LITTLE ENDIAN ORDERING 8-BIT LITTLE ENDIAN INTERNAL ORDER MSB 31 LSB 24 23 3 16 15 2 8 7 1 A=3 3 A=2 2 A=1 1 A=0 0 7 0 0 0 HOST DATA BUS 16-BIT LITTLE ENDIAN INTERNAL ORDER MSB 31 LSB 24 23 16 15 8 3 2 1 A=1 3 2 A=0 1 0 15 8 7 7 0 0 0 HOST DATA BUS DS00001909A-page 88 2015 Microchip Technology Inc. LAN9252 FIGURE 9-24: BIG ENDIAN ORDERING 8-BIT BIG ENDIAN INTERNAL ORDER MSB 31 LSB 24 23 3 16 15 2 8 7 1 A=3 0 A=2 1 A=1 2 A=0 3 7 0 0 0 HOST DATA BUS 16-BIT BIG ENDIAN INTERNAL ORDER MSB 31 LSB 24 23 16 15 8 3 2 1 A=1 0 1 A=0 2 3 15 8 7 7 0 0 0 HOST DATA BUS 2015 Microchip Technology Inc. DS00001909A-page 89 LAN9252 9.5.5 9.5.5.1 ETHERCAT PROCESS RAM DATA FIFO ACCESS Index Register Bypass FIFO Access In addition to the indexed access, the Index Registers can be bypassed and the FIFOs accessed at address 18h-1Bh. At this address, host write operations are to the EtherCAT Process RAM Write Data FIFO and host read operations are from EtherCAT Process RAM Read Data FIFO. There is no associated Index Register. The endianness of FIFO accesses using this method is specified by the FIFO Endianness bit in the Host Bus Interface Configuration Register. 9.5.6 INDEXED ADDRESS MODE FUNCTIONAL TIMING DIAGRAMS The following timing diagrams illustrate example indexed (non-multiplexed) addressing mode read and write cycles for various configurations and bus sizes. These diagrams do not cover every supported host bus permutation, but are selected to detail the main configuration differences (bus size, Configuration/Index/Data/FIFO-Direct cycles) within the indexed addressing mode of operation. The following should be noted for the timing diagrams in this section: • The diagrams in this section depict active-high CS, RD, and WR signals. The polarities of these signals are selectable via the HBI Chip Select Polarity, HBI Read, Read/Write Polarity, and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes), respectively. Refer to Section 9.3, "Control Line Polarity," on page 62 for additional details. • The diagrams in this section depict little endian byte ordering. However, configurable big and little endianess are supported via the endianness bits in the Host Bus Interface Configuration Register. Endianess changes only the order of the bytes involved, and not the overall timing requirements. Refer to Section 9.5.4.3, "Host Endianness," on page 87 for additional information. • The diagrams in this section utilize RD and WR signals. Alternative RD_WR and ENB signaling is also supported, similar to the multiplexed example in Section 9.4.4.3, "RD_WR / ENB Control Mode Examples". The HBI read/ write mode is selectable via the HBI Read/Write Mode bit of the PDI Configuration Register (HBI Modes). The polarities of the RD_WR and ENB signals are selectable via the HBI Read, Read/Write Polarity, and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes). • When accessing internal registers or FIFOs in 16 and 8-bit modes, consecutive address cycles must be within the same DWORD until the DWORD is completely accessed (some internal registers are excluded from this requirement). Although BYTEs and WORDs can be accessed in any order, the diagrams in this section depict accessing the lower address BYTE or WORD first. 9.5.6.1 Configuration Register Data Access The figures in this section detail configuration register read and write operations in indexed address mode for 16 and 8bit modes. DS00001909A-page 90 2015 Microchip Technology Inc. LAN9252 16-BIT READ AND WRITE For writes, the address is set to access the lower WORD of the Configuration Register. Data on D[15:0] is written on the trailing edge of WR. The cycle repeats for the upper WORD of the Configuration Register, if desired by the host. For reads, the address is set to access the lower WORD of the Configuration Register. Read data is driven on D[15:0] during RD active. The cycle repeats for the upper WORD of the Configuration Register, if desired by the host. FIGURE 9-25: INDEXED ADDRESSING CONFIGURATION REGISTER ACCESS - 16-BIT WRITE/ READ A[4:1] CONFIG,1'b0 CONFIG,1'b1 CONFIG,1'b0 CONFIG,1'b1 CS RD WR D[15:8] Data 15:8 Data 31:24 Data 15:8 Data 31:24 D[7:0] Data 7:0 Data 23:16 Data 7:0 Data 23:26 8-BIT READ AND WRITE For writes, the address is set to access the lower BYTE of the Configuration Register. Data on D[7:0] is written on the trailing edge of WR. D[15:8] pins are not used or driven. The cycle repeats for the remaining BYTEs of the Configuration Register, if desired by the host. For reads, the address is set to access the lower BYTE of the Configuration Register. Read data is driven on D[7:0] during RD active. D[15:8] pins are not used or driven. The cycle repeats for the remaining BYTEs of the Configuration Register, if desired by the host. FIGURE 9-26: A[4:0] CONFIG,2'b00 INDEXED ADDRESSING CONFIGURATION REGISTER ACCESS - 8-BIT WRITE/ READ CONFIG,2'b01 CONFIG,2'b10 CONFIG,2'b11 CONFIG,2'b00 CONFIG,2'b01 CONFIG,2'b10 CONFIG,2'b11 Data 7:0 Data 15:8 Data 23:16 Data 31:24 CS RD WR Hi-Z D[15:8] D[7:0] Data 7:0 Data 15:8 2015 Microchip Technology Inc. Data 23:16 Data 31:24 DS00001909A-page 91 LAN9252 9.5.6.2 Index Register Data Access The figures in this section detail index register read and write operations in indexed address mode for 16 and 8-bit modes. 16-BIT READ AND WRITE For writes, the address is set to access the lower WORD of one of the Index Registers. Data on D[15:0] is written on the trailing edge of WR. The cycle repeats for the upper WORD of the Index Register, if desired by the host. For reads, the address is set to access the lower WORD of one of the Index Registers. Read data is driven on D[15:0] during RD active. The cycle repeats for the upper WORD of the Index Register, if desired by the host. Note: The upper WORD of Index Registers is reserved and don’t care. Therefore reads and writes to that WORD are not useful. FIGURE 9-27: INDEXED ADDRESSING INDEX REGISTER ACCESS - 16-BIT WRITE/READ A[4:1] INDEX,1'b0 INDEX,1'b1 INDEX,1'b0 INDEX,1'b1 CS RD WR D[15:8] Index 15:8 8'hXX Index 15:8 8'hXX D[7:0] Index 7:0 8'hXX Index 7:0 8'hXX 8-BIT READ AND WRITE For writes, the address is set to access the lower BYTE of one of the Index Registers. Data on D[7:0] is written on the trailing edge of WR. D[15:8] pins are not used or driven. The cycle repeats for the remaining BYTEs of the Index Register, if desired by the host. For reads, the address is set to access the lower BYTE of one of the Index Registers. Read data is driven on D[7:0] during RD active. D[15:8] pins are not used or driven. The cycle repeats for the remaining BYTEs of the Index Register, if desired by the host. DS00001909A-page 92 2015 Microchip Technology Inc. LAN9252 Note: The upper WORD of Index Registers is reserved and don’t care. Therefore reads and writes to those BYTEs are not useful. FIGURE 9-28: A[4:0] INDEX,2'b00 INDEXED ADDRESSING INDEX REGISTER ACCESS - 8-BIT WRITE/READ INDEX,2'b01 INDEX,2'b10 INDEX,2'b11 INDEX,2'b00 INDEX,2'b01 INDEX,2'b10 INDEX,2'b11 Index 7:0 Index 15:8 8'hXX 8'hXX CS RD WR Hi-Z D[15:8] D[7:0] 9.5.6.3 Index 7:0 Index 15:8 8'hXX 8'hXX Internal Register Data Access The figures in this section detail typical internal register data read and write cycles in indexed address mode for 16 and 8-bit modes. This includes an index register write followed by either a data read or write. 16-BIT READ One of the Index Registers is set as described above. The address is then set to access the lower WORD of the corresponding Data Register. Read data is driven on D[15:0] during RD active. The cycle repeats for the upper WORD of the Data Register. FIGURE 9-29: INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 16-BIT READ A[4:1] INDEX,1'b0 INDEX,1'b1 DATA,1'b0 DATA,1'b1 CS RD WR D[15:8] Index 15:8 8'hXX Data 15:8 Data 31:24 D[7:0] Index 7:0 8'hXX Data 7:0 Data 23:16 2015 Microchip Technology Inc. DS00001909A-page 93 LAN9252 16-BIT WRITE One of the Index Registers is set as described above. The address is then set to access the corresponding Data Register. Data on D[15:0] is written on the trailing edge of WR. The cycle repeats for the upper WORD of the Data Register. FIGURE 9-30: INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 16-BIT WRITE A[4:1] INDEX,1'b0 INDEX,1'b1 DATA,1'b0 DATA,1'b1 CS RD WR D[15:8] Index 15:8 8'hXX Data 15:8 Data 31:24 D[7:0] Index 7:0 8'hXX Data 7:0 Data 23:16 16-BIT READS AND WRITES TO CONSTANT INTERNAL ADDRESS One of the Index Registers is set as described above. A mix of reads and writes on D[15:0] follows, with each read or write consisting of an access to both the lower and upper WORDs of the corresponding Data Register. FIGURE 9-31: A[4:1] INDEX,1'b0 INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 16-BIT READS/ WRITES CONSTANT ADDRESS INDEX,1'b1 DATA,1'b0 DATA,1'b1 DATA,1'b0 DATA,1'b1 DATA,1'b0 DATA,1'b1 DATA,1'b0 DATA,1'b1 DATA,1'b0 DATA,1'b1 CS RD WR D[15:8] Index 15:8 8'hXX Data 15:8 Data 31:24 Data 15:8 Data 31:24 Data 15:8 Data 31:24 Data 15:8 Data 31:24 Data 15:8 Data 31:24 D[7:0] Index 7:0 8'hXX Data 7:0 Data 23:16 Data 7:0 Data 23:16 Data 7:0 Data 23:16 Data 7:0 Data 23:16 Data 7:0 Data 23:16 DS00001909A-page 94 2015 Microchip Technology Inc. LAN9252 8-BIT READ One of the Index Registers is set as described above. The address is then set to access the lower BYTE of the corresponding Data Register. Read data is driven on D[7:0] during RD active. D[15:8] pins are not used or driven. The cycle repeats for the remaining BYTEs of the Data Register. FIGURE 9-32: A[4:0] INDEX,2'b00 INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 8-BIT READ INDEX,2'b01 INDEX,2'b10 INDEX,2'b11 DATA,2'b00 DATA,2'b01 DATA,2'b10 DATA,2'b11 Data 7:0 Data 15:8 Data 23:16 Data 31:24 CS RD WR Hi-Z D[15:8] D[7:0] Index 7:0 Index 15:8 8'hXX 8'hXX 8-BIT WRITE One of the Index Registers is set as described above. The address is then set to access the corresponding Data Register. Data on D[7:0] is written on the trailing edge of WR. D[15:8] pins are not used or driven. The cycle repeats for the remaining BYTEs of the Data Register. FIGURE 9-33: A[4:0] INDEX,2'b00 INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 8-BIT WRITE INDEX,2'b01 INDEX,2'b10 INDEX,2'b11 DATA,2'b00 DATA,2'b01 DATA,2'b10 DATA,2'b11 CS RD WR Hi-Z D[15:8] D[7:0] Index 7:0 Index 15:8 2015 Microchip Technology Inc. 8'hXX 8'hXX Data 7:0 Data 15:8 Data 23:16 Data 31:24 DS00001909A-page 95 LAN9252 8-BIT READS AND WRITES TO CONSTANT INTERNAL ADDRESS One of the Index Registers is set as described above. A mix of reads and writes on D[7:0] follows, with each read or write consisting of an access to all four BYTES of the corresponding Data Register. FIGURE 9-34: A[4:0] INDEX,2'b00 INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 8-BIT READS/ WRITES CONSTANT ADDRESS INDEX,2'b01 INDEX,2'b10 INDEX,2'b11 DATA,2'b00 DATA,2'b01 DATA,2'b10 DATA,2'b10 DATA,2'b11 Data 23:16 Data 31:24 DATA,2'b00 DATA,2'b01 DATA,2'b10 CS RD WR Hi-Z D[15:8] D[7:0] A[4:0] Index 7:0 Index 15:8 DATA,2'b10 8'hXX DATA,2'b11 8'hXX Data 7:0 Data 15:8 Data 23:16 DATA,2'b00 DATA,2'b01 DATA,2'b10 DATA,2'b10 DATA,2'b11 Data 7:0 Data 15:8 Data 23:16 Data 23:16 Data 31:24 Data 7:0 Data 15:8 Data 23:16 CS RD WR D[15:8] D[7:0] 9.5.6.4 Data 23:16 Data 31:24 RD_WR / ENB Control Mode Examples The figures in this section detail read and write operations utilizing the alternative RD_WR and ENB signaling. The HBI read/write mode is selectable via the HBI Read/Write Mode bit of the PDI Configuration Register (HBI Modes). Note: The examples in this section detail 16-bit mode with access to an Index Register. However, the RD_WR and ENB signaling can be used identically for all other accesses including FIFO Direct Select Access. The examples in this section show the ENB signal active-high and the RD_WR signal low for read and high for write. The polarities of the RD_WR and ENB signals are selectable via the HBI Read, Read/Write Polarity and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes). DS00001909A-page 96 2015 Microchip Technology Inc. LAN9252 16-BIT FIGURE 9-35: INDEXED ADDRESSING RD_WR / ENB CONTROL MODE EXAMPLE - 16-BIT WRITE/READ A[4:1] INDEX,1'b0 INDEX,1'b1 INDEX,1'b0 INDEX,1'b1 CS RD_WR ENB D[15:8] Index 15:8 8'hXX Index 15:8 8'hXX D[7:0] Index 7:0 8'hXX Index 7:0 8'hXX 2015 Microchip Technology Inc. DS00001909A-page 97 LAN9252 9.5.7 INDEXED ADDRESSING MODE TIMING REQUIREMENTS The following figures and tables specify the timing requirements during Indexed Address mode. Since timing requirements are similar across the multitude of operations (e.g. 8 vs. 16-bit, Index vs. Configuration vs. Data registers, FIFO Direct Select), many timing requirements are illustrated in the same figures and do not necessarily represent any particular functional operation. The following should be noted for the timing specifications in this section: • The diagrams in this section depict active-high CS, RD, WR, RD_WR and ENB signals. The polarities of these signals are selectable via the HBI Chip Select Polarity, HBI Read, Read/Write Polarity, and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes), respectively. Refer to Section 9.3, "Control Line Polarity," on page 62 for additional details. • A read cycle maybe followed by followed by a write cycle or another read cycle. A write cycle maybe followed by followed by a read cycle or another write cycle. These are shown in dashed line. 9.5.7.1 Read Timing Requirements If RD and WR signaling is used, a host read cycle begins when RD is asserted with CS active. The cycle ends when RD is de-asserted. CS maybe asserted and de-asserted along with RD but not during RD active. Alternatively, if RD_WR and ENB signaling is used, a host read cycle begins when ENB is asserted with CS active and RD_WR indicating a read. The cycle ends when ENB is de-asserted. CS maybe asserted and de-asserted along with ENB but not during ENB active. Please refer to Section 9.5.6, "Indexed Address Mode Functional Timing Diagrams," on page 90 for functional descriptions. FIGURE 9-36: INDEXED ADDRESSING READ CYCLE TIMING tcsrd trdcs tas tah CS A[4:0] RD_WR trdwrs trdwrh trd trdcyc trdrd ENB, RD trdwr WR tadv trdon, tcson trddv, tcsdv trddh, tcsdh trddz, tcsdz D[15:8] D[7:0] DS00001909A-page 98 2015 Microchip Technology Inc. LAN9252 TABLE 9-4: INDEXED ADDRESSING READ CYCLE TIMING VALUES Symbol Description Min Typ Max Units tcsrd CS Setup to RD or ENB Active 0 ns trdcs CS Hold from RD or ENB Inactive 0 ns tas Address Setup to RD or ENB Active 0 ns tah Address Hold from to RD or ENB Inactive 0 ns trdwrs RD_WR Setup to ENB Active Note 14 5 ns trdwrh RD_WR Hold from ENB Inactive Note 14 5 ns trdon RD or ENB to Data Buffer Turn On 0 ns trddv RD or ENB Active to Data Valid trddh Data Output Hold Time from RD or ENB Inactive trddz Data Buffer Turn Off Time from RD or ENB Inactive tcson CS to Data Buffer Turn On tcsdv CS Active to Data Valid tcsdh Data Output Hold Time from CS Inactive tcsdz Data Buffer Turn Off Time from CS Inactive 9 ns tadv Address to Data Valid 30 ns trd RD or ENB Active Time 32 ns trdcyc RD or ENB Cycle Time 45 ns trdrd RD or ENB De-assertion Time before Next RD or ENB 13 ns trdwr RD De-assertion Time before Next WR Note 15 13 ns 30 0 ns ns 9 0 ns ns 30 0 ns ns Note 14: RD_WR and ENB signaling. Note 15: RD and WR signaling. Note: Timing values are with respect to an equivalent test load of 25 pF. 2015 Microchip Technology Inc. DS00001909A-page 99 LAN9252 9.5.7.2 Write Timing Requirements If RD and WR signaling is used, a host write cycle begins when WR is asserted with CS active. The cycle ends when WR is de-asserted. CS maybe asserted and de-asserted along with WR but not during WR active. Alternatively, if RD_WR and ENB signaling is used, a host write cycle begins when ENB is asserted with CS active and RD_WR indicating a write. The cycle ends when ENB is de-asserted. CS maybe asserted and de-asserted along with ENB but not during ENB active. Please refer to Section 9.5.6, "Indexed Address Mode Functional Timing Diagrams," on page 90 for functional descriptions. FIGURE 9-37: INDEXED ADDRESSING WRITE CYCLE TIMING tcswr twrcs tas tah CS A[4:0] D[15:8] D[7:0] RD_WR tds trdwrs tdh trdwrh twr twrcyc twrwr ENB, WR twrrd RD TABLE 9-5: INDEXED ADDRESSING WRITE CYCLE TIMING VALUES Symbol Description Min Typ Max Units tcswr CS Setup to WR or ENB Active 0 ns twrcs CS Hold from WR or ENB Inactive 0 ns tas Address Setup to WR or ENB Active 0 ns tah Address Hold from to WR or ENB Inactive 0 ns trdwrs RD_WR Setup to ENB Active Note 16 5 ns trdwrh RD_WR Hold from ENB Inactive Note 16 5 ns tds Data Setup to WR or ENB Inactive 7 ns tdh Data Hold from WR or ENB Inactive 0 ns twr WR or ENB Active Time 32 ns DS00001909A-page 100 2015 Microchip Technology Inc. LAN9252 TABLE 9-5: INDEXED ADDRESSING WRITE CYCLE TIMING VALUES (CONTINUED) Symbol Description Min Typ Max Units twrcyc WR or ENB Cycle Time 45 ns twrwr WR or ENB De-assertion Time before Next WR or ENB 13 ns twrrd WR De-assertion Time before Next RD Note 17 13 ns Note 16: RD_WR and ENB signaling. Note 17: RD and WR signaling. 2015 Microchip Technology Inc. DS00001909A-page 101 LAN9252 10.0 SPI/SQI SLAVE 10.1 Functional Overview The SPI/SQI Slave module provides a low pin count synchronous slave interface that facilitates communication between the device and a host system. The SPI/SQI Slave allows access to the System CSRs and internal FIFOs and memories. It supports single and multiple register read and write commands with incrementing, decrementing and static addressing. Single, Dual and Quad bit lanes are supported in SPI mode with a clock rate of up to 80 MHz. SQI mode always uses four bit lanes and also operates at up to 80 MHz. The following is an overview of the functions provided by the SPI/SQI Slave: • Serial Read: 4-wire (clock, select, data in and data out) reads at up to 30 MHz. Serial command, address and data. Single and multiple register reads with incrementing, decrementing or static addressing. • Fast Read: 4-wire (clock, select, data in and data out) reads at up to 80 MHz. Serial command, address and data. Dummy byte(s) for first access. Single and multiple register reads with incrementing, decrementing or static addressing. • Dual / Quad Output Read: 4 or 6-wire (clock, select, data in / out) reads at up to 80 MHz. Serial command and address, parallel data. Dummy byte(s) for first access. Single and multiple register reads with incrementing, decrementing or static addressing. • Dual / Quad I/O Read: 4 or 6-wire (clock, select, data in / out) reads at up to 80 MHz. Serial command, parallel address and data. Dummy byte(s) for first access. Single and multiple register reads with incrementing, decrementing or static addressing. • SQI Read: 6-wire (clock, select, data in / out) writes at up to 80 MHz. Parallel command, address and data. Dummy byte(s) for first access. Single and multiple register reads with incrementing, decrementing or static addressing. • Write: 4-wire (clock, select, data in and data out) writes at up to 80 MHz. Serial command, address and data. Single and multiple register writes with incrementing, decrementing or static addressing. • Dual / Quad Data Write: 4 or 6-wire (clock, select, data in / out) writes at up to 80 MHz. Serial command and address, parallel data. Single and multiple register writes with incrementing, decrementing or static addressing. • Dual / Quad Address / Data Write: 4 or 6-wire (clock, select, data in / out) writes at up to 80 MHz. Serial command, parallel address and data. Single and multiple register writes with incrementing, decrementing or static addressing. • SQI Write: 6-wire (clock, select, data in / out) writes at up to 80 MHz. Parallel command, address and data. Single and multiple register writes with incrementing, decrementing or static addressing. 10.2 SPI/SQI Slave Operation Input data on the SIO[3:0] pins is sampled on the rising edge of the SCK input clock. Output data is sourced on the SIO[3:0] pins with the falling edge of the clock. The SCK input clock can be either an active high pulse or an active low pulse. When the SCS# chip select input is high, the SIO[3:0] inputs are ignored and the SIO[3:0] outputs are threestated. In SPI mode, the 8-bit instruction is started on the first rising edge of the input clock after SCS# goes active. The instruction is always input serially on SI/SIO0. For read and write instructions, two address bytes follow the instruction byte. Depending on the instruction, the address bytes are input either serially, or 2 or 4 bits per clock. Although all registers are accessed as DWORDs, the address field is considered a byte address. Fourteen address bits specify the address. Bits 15 and 14 of the address field specifies that the address is auto-decremented (10b) or auto-incremented (01b) for continuous accesses. For some read instructions, dummy byte cycles follow the address bytes. The device does not drive the outputs during the dummy byte cycles. The dummy byte(s) are input either serially, or 2 or 4 bits per clock. For read and write instructions, one or more 32-bit data fields follow the dummy bytes (if present, else they follow the address bytes). The data is input either serially, or 2 or 4 bits per clock. SQI mode is entered from SPI with the Enable Quad I/O (EQIO) instruction. Once in SQI mode, all further command, addresses, dummy bytes and data bytes are 4 bits per clock. SQI mode can be exited using the Reset Quad I/O (RSTQIO) instruction. DS00001909A-page 102 2015 Microchip Technology Inc. LAN9252 All instructions, addresses and data are transferred with the most-significant bit (msb) or di-bit (msd) or nibble (msn) first. Addresses are transferred with the most-significant byte (MSB) first. Data is transferred with the least-significant byte (LSB) first (little endian). The SPI interface supports up to a 80 MHz input clock. Normal (non-high speed) reads instructions are limited to 30 MHz. The SPI interface supports a minimum time of 50 ns between successive commands (a minimum SCS# inactive time of 50 ns). The instructions supported in SPI mode are listed in Table 10-1. SQI instructions are listed in Table 10-2. Unsupported instructions are must not be used. TABLE 10-1: SPI INSTRUCTIONS Description Bit width Note 1 Inst. code Addr. Bytes Dummy Bytes Data bytes Max Freq. EQIO Enable SQI 1-0-0 38h 0 0 0 80 MHz RSTQIO Reset SQI 1-0-0 FFh 0 0 0 80 MHz READ Read 1-1-1 03h 2 0 4 to 30 MHz FASTREAD Read at higher speed 1-1-1 0Bh 2 1 4 to 80 MHz SDOR SPI Dual Output Read 1-1-2 3Bh 2 1 4 to 80 MHz SDIOR SPI Dual I/O Read 1-2-2 BBh 2 2 4 to 80 MHz SQOR SPI Quad Output Read 1-1-4 6Bh 2 1 4 to 80 MHz SQIOR SPI Quad I/O Read 1-4-4 EBh 2 4 4 to 80 MHz WRITE Write 1-1-1 02h 2 0 4 to 80 MHz SDDW SPI Dual Data Write 1-1-2 32h 2 0 4 to 80 MHz SDADW SPI Dual Address / Data Write 1-2-2 B2h 2 0 4 to 80 MHz SQDW SPI Quad Data Write 1-1-4 62h 2 0 4 to 80 MHz SQADW SPI Quad Address / Data Write 1-4-4 E2h 2 0 4 to 80 MHz Instruction Configuration Read Write Note 1: The bit width format is: command bit width, address / dummy bit width, data bit width. 2015 Microchip Technology Inc. DS00001909A-page 103 LAN9252 TABLE 10-2: SQI INSTRUCTIONS Instruction Description Bit width Note 2 Inst. code Addr. Bytes Dummy Bytes Data bytes Max Freq. Reset SQI 4-0-0 FFh 0 0 0 80 MHz Read at higher speed 4-4-4 0Bh 2 3 4 to 80 MHz Write 4-4-4 02h 2 0 4 to 80 MHz Configuration RSTQIO Read FASTREAD Write WRITE Note 2: The bit width format is: command bit width, address / dummy bit width, data bit width. 10.2.1 DEVICE INITIALIZATION Until the device has been initialized to the point where the various configuration inputs are valid, the SPI/SQI interface does not respond to and is not affected by any external pin activity. Once device initialization completes, the SPI/SQI interface will ignore the pins until a rising edge of SCS# is detected. 10.2.1.1 SPI/SQI Slave Read Polling for Initialization Complete Before device initialization, the SPI/SQI interface will not return valid data. To determine when the SPI/SQI interface is functional, the Byte Order Test Register (BYTE_TEST) should be polled. Once the correct pattern is read, the interface can be considered functional. At this point, the Device Ready (READY) bit in the Hardware Configuration Register (HW_CFG) can be polled to determine when the device is fully configured. Note: 10.2.2 The Host should only use single register reads (one data cycle per SCS# low) while polling the BYTE_TEST register. ACCESS DURING AND FOLLOWING POWER MANAGEMENT During any power management mode other than D0, reads and writes are ignored and the SPI/SQI interface does not respond to and is not affected by any external pin activity. Once the power management mode changes back to D0, the SPI/SQI interface will ignore the pins until a rising edge of SCS# is detected. To determine when the SPI/SQI interface is functional, the Byte Order Test Register (BYTE_TEST) should be polled. Once the correct pattern is read, the interface can be considered functional. At this point, the Device Ready (READY) bit in the Hardware Configuration Register (HW_CFG) can be polled to determine when the device is fully configured. Note: 10.2.3 10.2.3.1 The Host should only use single register reads (one data cycle per SCS# low) while polling the BYTE_TEST register. SPI CONFIGURATION COMMANDS Enable SQI The Enable SQI instruction changes the mode of operation to SQI. This instruction is supported in SPI bus protocol only with clock frequencies up to 80 MHz. This instruction is not supported in SQI bus protocol. The SPI slave interface is selected by first bringing SCS# active. The 8-bit EQIO instruction, 38h, is input into the SI/ SIO[0] pin one bit per clock. The SCS# input is brought inactive to conclude the cycle. DS00001909A-page 104 2015 Microchip Technology Inc. LAN9252 Figure 10-1 illustrates the Enable SQI instruction. FIGURE 10-1: ENABLE SQI SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 X 8 X Instruction SI X 0 0 1 1 1 0 0 0 X Z SO SPI Enable SQI 10.2.3.2 Reset SQI The Reset SQI instruction changes the mode of operation to SPI. This instruction is supported in SPI and SQI bus protocols with clock frequencies up to 80 MHz. The SPI/SQI slave interface is selected by first bringing SCS# active. The 8-bit RSTQIO instruction, FFh, is input into the SI/SIO[0] pin, one bit per clock, in SPI mode and into the SIO[3:0] pins, four bits per clock, in SQI mode. The SCS# input is brought inactive to conclude the cycle. Figure 10-2 illustrates the Reset SQI instruction for SPI mode. Figure 10-3 illustrates the Reset SQI instruction for SQI mode. FIGURE 10-2: SPI MODE RESET SQI SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 X 8 X Instruction SI SO X 1 1 1 1 1 1 1 1 X Z SPI Mode Reset SQI 2015 Microchip Technology Inc. DS00001909A-page 105 LAN9252 FIGURE 10-3: SQI MODE RESET SQI SCS# SCK (active low) X SCK (active high) X 1 2 1 X 2 X Inst SIO[3:0] X F F X SQI Mode Reset SQI 10.2.4 SPI READ COMMANDS Various read commands are support by the SPI/SQI slave. The following applies to all read commands. MULTIPLE READS Additional reads, beyond the first, are performed by continuing the clock pulses while SCS# is active. The upper two bits of the address specify auto-incrementing (address[15:14]=01b) or auto-decrementing (address[15:14]=10b). The internal DWORD address is incremented, decremented, or maintained based on these bits. Maintaining a fixed internal address is useful for register polling. SPECIAL CSR HANDLING Live Bits Since data is read serially, the selected register’s value is saved at the beginning of each 32-bit read to prevent the host from reading an intermediate value. The saving occurs multiple times in a multiple read sequence. Change on Read Registers and FIFOs Any register that is affected by a read operation (e.g. a clear on read bit or FIFO) is updated once the current data output shift has started. In the event that 32-bits are not read when the SCS# is returned high, the register is still affected and any prior data is lost. Change on Read Live Register Bits As described above, the current value from a register with live bits (as is the case of any register) is saved before the data is shifted out. Although a H/W event that occurs following the data capture would still update the live bit(s), the live bit(s) will be affected (cleared, etc.) once the output shift has started and the H/W event would be lost. In order to prevent this, the individual CSRs defer the H/W event update until after the read indication. 10.2.4.1 Read The Read instruction inputs the instruction code and address bytes one bit per clock and outputs the data one bit per clock. This instruction is supported in SPI bus protocol only with clock frequencies up to 30 MHz. This instruction is not supported in SQI bus protocol. The SPI slave interface is selected by first bringing SCS# active. The 8-bit READ instruction, 03h, is input into the SI/ SIO[0] pin, followed by the two address bytes. The address bytes specify a BYTE address within the device. On the falling clock edge following the rising edge of the last address bit, the SO/SIO[1] pin is driven starting with the msb of the LSB of the selected register. The remaining register bits are shifted out on subsequent falling clock edges. The SCS# input is brought inactive to conclude the cycle. The SO/SIO[1] pin is three-stated at this time. DS00001909A-page 106 2015 Microchip Technology Inc. LAN9252 Figure 10-4 illustrates a typical single and multiple register read. FIGURE 10-4: SPI READ SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 1 1 1 0 9 1 2 1 3 1 1 1 2 1 4 1 3 1 5 1 4 1 5 Instruction SI X 0 0 0 0 0 0 1 6 1 7 1 6 1 8 1 7 1 9 1 8 2 0 1 9 2 1 2 0 2 2 2 1 2 3 2 2 2 4 2 3 2 5 2 4 2 6 2 5 2 7 2 6 ... 2 7 Address 1 1 d e c i n c A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 5 3 ... 5 4 5 3 5 5 5 4 5 6 5 5 ... X X 5 6 X X Data D 7 Z SO D 6 D 5 ... D 2 6 D 2 5 D 2 4 X Z SPI Read Single Register SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 9 1 1 1 0 1 2 1 3 1 1 1 2 1 4 1 3 X 0 0 0 0 0 0 1 6 1 4 Instruction SI 1 5 1 5 1 7 1 6 1 8 1 7 1 9 1 8 2 0 1 9 2 1 2 0 2 2 2 1 2 3 2 2 2 4 2 3 2 5 2 4 2 6 2 5 2 7 2 6 ... 2 7 Address 1 1 d e c i n c A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 ... Z D 7 D 6 D 5 ... X ... ... X Data 1... SO ... ... X Data m D 2 6 D 2 5 D 2 4 X X Data m+1... Data n D 7 D 6 D 5 ... D 2 6 D 2 5 D 2 4 X Z SPI Read Multiple Registers 10.2.4.2 Fast Read The Read at higher speed instruction inputs the instruction code and the address and dummy bytes one bit per clock and outputs the data one bit per clock. In SQI mode, the instruction code and the address and dummy bytes are input four bits per clock and the data is output four bits per clock. This instruction is supported in SPI and SQI bus protocols with clock frequencies up to 80 MHz. The SPI/SQI slave interface is selected by first bringing SCS# active. For SPI mode, the 8-bit FASTREAD instruction, 0Bh, is input into the SI/SIO[0] pin, followed by the two address bytes and 1 dummy byte. For SQI mode, the 8-bit FASTREAD instruction is input into the SIO[3:0] pins, followed by the two address bytes and 3 dummy bytes. The address bytes specify a BYTE address within the device. On the falling clock edge following the rising edge of the last dummy bit (or nibble), the SO/SIO[1] pin is driven starting with the msb of the LSB of the selected register. For SQI mode, SIO[3:0] are driven starting with the msn of the LSB of the selected register. The remaining register bits are shifted out on subsequent falling clock edges. The SCS# input is brought inactive to conclude the cycle. The SO/SIO[3:0] pins are three-stated at this time. 2015 Microchip Technology Inc. DS00001909A-page 107 LAN9252 Figure 10-5 illustrates a typical single and multiple register fast read for SPI mode. Figure 10-6 illustrates a typical single and multiple register fast read for SQI mode. FIGURE 10-5: SPI FAST READ SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 1 1 1 2 1 0 9 1 1 1 3 1 2 1 4 1 5 1 3 1 4 1 5 Instruction SI X 0 0 0 0 1 0 1 6 1 7 1 6 1 8 1 9 1 7 1 8 2 0 1 9 2 1 2 0 2 2 2 1 2 3 2 2 2 4 2 3 2 5 2 4 2 6 2 5 2 7 2 6 2 7 Address 1 1 d e c i n c A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 2 8 2 9 2 8 3 0 2 9 3 1 3 2 3 0 3 1 3 3 3 2 3 4 3 3 3 5 3 4 ... 3 5 Dummy A 6 A 5 A 4 A 3 A 2 A 1 A 0 x x x x x x x ... 6 2 6 1 6 3 6 2 6 4 6 3 ... X x 6 1 X 6 4 X X Data D 7 Z SO D 6 ... D 5 D 2 6 D 2 5 D 2 4 X Z SPI Fast Read Single Register SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 1 1 1 2 1 0 9 1 1 1 3 1 2 1 4 1 5 1 3 1 4 1 5 Instruction SI X 0 0 0 0 1 0 1 6 1 7 1 6 1 8 1 9 1 7 1 8 2 0 1 9 2 1 2 0 2 2 2 1 2 3 2 2 2 4 2 3 2 5 2 4 2 6 2 5 2 7 2 6 2 7 Address 1 1 d e c i n c A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 2 8 2 9 2 8 3 0 2 9 3 1 3 2 3 0 3 1 3 3 3 2 3 4 3 3 3 5 3 4 ... ... 3 5 Dummy A 6 A 5 A 4 A 3 A 2 A 1 A 0 x x x x x x x ... X x Data 1... D 7 Z SO D 6 ... ... D 5 ... D 2 6 D 2 5 D 2 4 X ... X Data m X X Data m+1... Data n D 7 D 6 D 5 ... D 2 6 D 2 5 D 2 4 X Z SPI Fast Read Multiple Registers FIGURE 10-6: SQI FAST READ SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 8 Inst Address SIO[3:0] X 0 B H 1 L 1 H 0 1 0 9 1 1 1 0 9 1 2 1 1 1 3 1 2 1 4 1 3 1 5 1 4 1 6 1 5 Dummy L 0 x x x x 1 7 1 6 1 8 1 7 1 9 1 8 2 0 1 9 X 2 0 X Data x H 0 x L 0 H 1 L 1 H 2 L 2 H 3 L 3 X SQI Fast Read Single Register SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 X 0 B H 1 L 1 H 0 L 0 1 0 9 7 Inst Address SIO[3:0] 8 8 1 1 1 0 9 1 2 1 1 1 2 Dummy x x x x x 1 3 1 4 1 3 1 5 1 4 ... 1 5 ... Data 1... x H 0 L 0 H 1 ... ... X ... Data m L 2 H 3 X Data m+1... Data n L 3 H 0 L 0 H 1 ... L 2 H 3 L 3 X SQI Fast Read Multiple Registers DS00001909A-page 108 2015 Microchip Technology Inc. LAN9252 10.2.4.3 Dual Output Read The SPI Dual Output Read instruction inputs the instruction code and the address and dummy bytes one bit per clock and outputs the data two bits per clock. This instruction is supported in SPI bus protocol only with clock frequencies up to 80 MHz. This instruction is not supported in SQI bus protocol. The SPI slave interface is selected by first bringing SCS# active. The 8-bit SDOR instruction, 3Bh, is input into the SIO[0] pin, followed by the two address bytes and 1 dummy byte. The address bytes specify a BYTE address within the device. On the falling clock edge following the rising edge of the last dummy di-bit, the SIO[1:0] pins are driven starting with the msbs of the LSB of the selected register. The remaining register di-bits are shifted out on subsequent falling clock edges. The SCS# input is brought inactive to conclude the cycle. The SIO[1:0] pins are three-stated at this time. Figure 10-7 illustrates a typical single and multiple register dual output read. FIGURE 10-7: SPI DUAL OUTPUT READ SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 1 1 1 0 9 1 2 1 1 1 3 1 2 1 4 1 3 1 5 1 4 1 5 Instruction SIO0 X 0 0 1 1 1 0 1 6 1 7 1 6 1 8 1 7 1 9 1 8 2 0 1 9 2 1 2 0 2 2 2 1 2 3 2 2 2 4 2 3 2 5 2 4 2 6 2 5 2 7 2 6 2 7 Address 1 1 d e c i n c A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 2 8 2 9 2 8 3 0 2 9 3 1 3 0 3 2 3 1 3 3 3 2 3 4 3 3 3 5 3 4 ... 3 5 Dummy A 6 A 5 A 4 A 3 A 2 A 1 A 0 x x x x x 4 5 ... 4 6 4 5 4 7 4 6 4 8 4 7 X 4 8 X Data x x D 6 x D 4 D 2 ... D 2 8 D 2 6 D 2 4 X D 2 9 D 2 7 D 2 5 X Z Data D 7 Z SIO1 D 5 D 3 ... SPI Dual Output Read Single Register SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 9 1 1 1 0 1 2 1 1 1 3 1 2 1 4 1 3 1 4 Instruction SIO0 X 0 0 1 1 1 0 1 5 1 6 1 5 1 7 1 6 1 8 1 7 1 9 1 8 2 0 1 9 2 1 2 0 2 2 2 1 2 3 2 2 2 4 2 3 2 5 2 4 2 6 2 5 1 d e c i n c A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 A 6 2 8 2 6 Address 1 2 7 2 7 2 9 2 8 3 0 2 9 3 1 3 0 3 2 3 1 3 2 Dummy A 5 A 4 A 3 A 2 A 1 A 0 x x x x x x 3 3 3 4 3 3 3 5 3 4 ... ... 3 5 Data 1... x x D 6 D 4 D 2 ... Data 1... SIO1 Z D 7 D 5 ... ... D 3 ... Data m D 2 8 D 2 6 D 2 4 Data m D 2 9 D 2 7 D 2 5 X X Data m+1... Data n D 6 D 4 D 2 ... D 2 8 D 2 6 D 2 4 X Data m+1... Data n D 7 D 5 D 3 ... D 2 9 D 2 7 D 2 5 X Z SPI Dual Output Read Multiple Registers 2015 Microchip Technology Inc. DS00001909A-page 109 LAN9252 10.2.5 QUAD OUTPUT READ The SPI Quad Output Read instruction inputs the instruction code and the address and dummy bytes one bit per clock and outputs the data four bits per clock. This instruction is supported in SPI bus protocol only with clock frequencies up to 80 MHz. This instruction is not supported in SQI bus protocol. The SPI slave interface is selected by first bringing SCS# active. The 8-bit SQOR instruction, 6Bh, is input into the SIO[0] pin, followed by the two address bytes and 1 dummy byte. The address bytes specify a BYTE address within the device. On the falling clock edge following the rising edge of the last dummy bit, the SIO[3:0] pins are driven starting with the msn of the LSB of the selected register. The remaining register nibbles are shifted out. The SCS# input is brought inactive to conclude the cycle. The SIO[3:0] pins are three-stated at this time. Figure 10-8 illustrates a typical single and multiple register quad output read. FIGURE 10-8: SPI QUAD OUTPUT READ SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 1 1 1 0 9 1 2 1 1 1 3 1 2 1 4 1 5 1 3 1 4 1 5 Instruction SIO0 X 0 1 1 0 1 0 1 6 1 7 1 6 1 8 1 7 1 9 1 8 2 0 1 9 2 1 2 0 2 2 2 1 2 3 2 2 2 4 2 3 2 5 2 4 2 6 2 5 2 7 2 6 2 7 Address 1 1 d e c i n c A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 2 8 2 9 2 8 3 0 2 9 3 1 3 0 3 2 3 1 3 3 3 2 3 4 3 3 3 5 3 4 3 6 3 5 Dummy A 6 A 5 A 4 A 3 A 2 A 1 A 0 x x x x x 3 7 3 6 3 8 3 7 3 9 3 8 4 0 3 9 X 4 0 X Data x x D 4 x D 0 D 1 2 D 8 D 2 0 D 1 6 D 2 8 D 2 4 X D 1 7 D 2 9 D 2 5 X Z D 1 8 D 3 0 D 2 6 X Z D 1 9 D 3 1 D 2 7 X Z Data D 5 Z SIO1 D 1 D 1 3 D 9 D 2 1 Data D 6 Z SIO2 D 2 D 1 4 D 1 0 D 2 2 Data D 7 Z SIO3 D 3 D 1 5 D 1 1 D 2 3 SPI Quad Output Read Single Register SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 9 1 1 1 0 1 2 1 1 1 3 1 2 1 4 1 3 1 4 Instruction SIO0 X 0 1 1 0 1 0 1 5 1 6 1 5 1 7 1 6 1 8 1 7 1 9 1 8 2 0 1 9 2 1 2 0 2 2 2 1 2 3 2 2 2 4 2 3 2 5 2 4 2 6 2 5 1 d e c i n c A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 A 6 2 8 2 6 Address 1 2 7 2 7 2 9 2 8 3 0 2 9 3 1 3 0 3 2 3 1 3 2 Dummy A 5 A 4 A 3 A 2 A 1 A 0 x x x x x x 3 3 3 4 3 3 3 5 3 4 ... ... 3 5 Data 1... x x D 4 D 0 D 1 2 ... Data 1... SIO1 Z D 5 D 1 D 1 3 ... Data 1... SIO2 Z D 6 D 2 D 1 4 ... Data 1... SIO3 Z D 7 D 3 ... ... D 1 5 ... Data m D 1 6 D 2 8 D 2 4 Data m D 1 7 D 2 9 D 2 5 Data m D 1 8 D 3 0 D 2 6 Data m D 1 9 D 3 1 D 2 7 X X Data m+1... Data n D 4 D 0 D 1 2 ... D 1 6 D 2 8 D 2 4 X Data m+1... Data n D 5 D 1 D 1 3 ... D 1 7 D 2 9 D 2 5 X Z Data m+1... Data n D 6 D 2 D 1 4 ... D 1 8 D 3 0 D 2 6 X Z Data m+1... Data n D 7 D 3 D 1 5 ... D 1 9 D 3 1 D 2 7 X Z SPI Quad Output Read Multiple Registers DS00001909A-page 110 2015 Microchip Technology Inc. LAN9252 10.2.5.1 Dual I/O Read The SPI Dual I/O Read instruction inputs the instruction code one bit per clock and the address and dummy bytes two bits per clock and outputs the data two bits per clock. This instruction is supported in SPI bus protocol only with clock frequencies up to 80 MHz. This instruction is not supported in SQI bus protocol. The SPI slave interface is selected by first bringing SCS# active. The 8-bit SDIOR instruction, BBh, is input into the SIO[0] pin, followed by the two address bytes and 2 dummy bytes into the SIO[1:0] pins. The address bytes specify a BYTE address within the device. On the falling clock edge following the rising edge of the last dummy di-bit, the SIO[1:0] pins are driven starting with the msbs of the LSB of the selected register. The remaining register di-bits are shifted out on subsequent falling clock edges. The SCS# input is brought inactive to conclude the cycle. The SIO[1:0] pins are three-stated at this time. Figure 10-9 illustrates a typical single and multiple register dual I/O read. FIGURE 10-9: SPI DUAL I/O READ SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 1 1 1 0 9 1 1 Instruction SIO0 X 1 0 1 1 1 0 1 2 1 3 1 2 1 4 1 3 1 5 1 4 1 6 1 5 1 7 1 6 1 8 1 7 1 9 1 8 1 9 Address 1 1 i n c A 1 2 A 1 0 d e c A 1 3 A 1 1 A 8 A 6 A 9 A 7 2 1 2 0 2 2 2 1 2 3 2 2 2 4 2 3 2 5 2 4 2 6 2 5 2 7 2 6 ... 2 7 Dummy A 4 A 2 A 0 x x x A 3 A 1 x x x Address Z SIO1 2 0 x x x x ... 3 8 3 7 3 9 3 8 4 0 3 9 X 4 0 X Data x x x D 6 D 4 D 2 x x D 7 D 5 D 3 Dummy A 5 3 7 ... D 2 8 D 2 6 D 2 4 X D 2 9 D 2 7 D 2 5 X Z Data x ... SPI Dual I/O Read Single Register SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 9 1 1 1 0 Instruction SIO0 X 1 0 1 1 1 0 1 2 1 1 1 3 1 2 1 4 1 3 1 5 1 4 1 6 1 5 1 7 1 6 1 8 1 7 1 i n c A 1 2 A 1 0 A 8 A 6 A 4 Z d e c A 1 3 A 1 1 A 9 A 7 A 5 1 9 2 1 2 0 2 2 2 1 2 3 2 2 2 4 2 3 2 5 2 4 Dummy A 2 A 0 x x Address SIO1 2 0 1 8 Address 1 1 9 x x x x A 1 x x x x x x 2 5 2 7 2 6 ... ... x x D 6 D 4 D 2 ... Data 1... x x D 7 D 5 ... ... 2 7 Data 1... Dummy A 3 2 6 D 3 ... Data m D 2 8 D 2 6 D 2 4 Data m D 2 9 D 2 7 D 2 5 X X Data m+1... Data n D 6 D 4 D 2 ... D 2 8 D 2 6 D 2 4 X Data m+1... Data n D 7 D 5 D 3 ... D 2 9 D 2 7 D 2 5 X Z SPI Dual I/O Read Multiple Registers 2015 Microchip Technology Inc. DS00001909A-page 111 LAN9252 10.2.5.2 Quad I/O Read The SPI Quad I/O Read instruction inputs the instruction code one bit per clock and the address and dummy bytes four bits per clock and outputs the data four bits per clock. This instruction is supported in SPI bus protocol only with clock frequencies up to 80 MHz. This instruction is not supported in SQI bus protocol. The SPI slave interface is selected by first bringing SCS# active. The 8-bit SQIOR instruction, EBh, is input into the SIO[0] pin, followed by the two address bytes and 4 dummy bytes into the SIO[3:0] pins. The address bytes specify a BYTE address within the device. On the falling clock edge following the rising edge of the last dummy nibble, the SIO[3:0] pins are driven starting with the msn of the LSB of the selected register. The remaining register nibbles are shifted out on subsequent falling clock edges. The SCS# input is brought inactive to conclude the cycle. The SIO[3:0] pins are three-stated at this time. Figure 10-10 illustrates a typical single and multiple register quad I/O read. FIGURE 10-10: SPI QUAD I/O READ SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 8 X 1 1 1 0 1 0 1 1 1 0 9 Instruction SIO0 1 0 9 1 2 1 1 1 3 1 2 1 4 1 3 1 5 1 4 1 5 Address 1 1 A 1 2 A 8 A 4 1 6 1 7 1 6 1 8 1 7 1 9 1 8 2 0 1 9 2 1 2 0 2 2 2 1 2 3 2 2 2 4 2 3 Dummy A 0 x x x x x A 1 3 Z A 9 A 5 A 1 x x x x x x 2 4 2 6 2 5 2 7 2 6 2 8 2 7 X 2 8 X Data x D 4 x D 0 D 1 2 D 8 D 2 0 D 1 6 D 2 8 D 2 4 X Data Dummy SIO1 2 5 x x x D 5 D 1 D 1 3 D 9 D 2 1 D 1 7 D 2 9 D 2 5 X Z x x D 6 D 2 D 1 4 D 1 0 D 2 2 D 1 8 D 3 0 D 2 6 X Z x x D 7 D 3 D 1 5 D 1 1 D 2 3 D 1 9 D 3 1 D 2 7 X Z Dummy i n c Z SIO2 A 1 0 A 6 A 2 x x x x x x Dummy d e c Z SIO3 A 1 1 A 7 A 3 x x x x x x SPI Quad I/O Read Single Register SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 8 Instruction SIO0 X 1 1 1 0 1 0 1 0 9 9 1 1 1 0 1 2 1 1 1 3 1 2 1 4 1 3 1 A 1 2 A 8 A 4 A 0 1 6 1 4 Address 1 1 5 1 5 1 7 1 6 1 8 1 7 1 9 1 8 2 0 1 9 2 0 Dummy x x x x x x Z A 1 3 A 9 A 5 A 1 x x x x x x x Z i n c A 1 0 A 6 A 2 x x x x x x x x Z d e c A 1 1 A 7 A 3 x x x x x x 2 2 ... ... D 4 D 0 D 5 D 1 x x D 6 D 2 D 1 2 ... D 1 3 ... D 1 4 ... Data 1... x x D 7 D 3 ... ... 2 3 Data 1... Dummy SIO3 2 1 2 3 Data 1... Dummy SIO2 2 2 Data 1... x Dummy SIO1 2 1 D 1 5 ... Data m D 1 6 D 2 8 D 2 4 Data m D 1 7 D 2 9 D 2 5 Data m D 1 8 D 3 0 D 2 6 Data m D 1 9 D 3 1 D 2 7 X X Data m+1... Data n D 4 D 0 D 1 2 ... D 1 6 D 2 8 D 2 4 X Data m+1... Data n D 5 D 1 D 1 3 ... D 1 7 D 2 9 D 2 5 X Z Data m+1... Data n D 6 D 2 D 1 4 ... D 1 8 D 3 0 D 2 6 X Z Data m+1... Data n D 7 D 3 D 1 5 ... D 1 9 D 3 1 D 2 7 X Z SPI Quad I/O Read Multiple Registers DS00001909A-page 112 2015 Microchip Technology Inc. LAN9252 10.2.6 SPI WRITE COMMANDS Multiple write commands are support by the SPI/SQI slave. The following applies to all write commands. MULTIPLE WRITES Multiple reads are performed by continuing the clock pulses and input data while SCS# is active. The upper two bits of the address specify auto-incrementing (address[15:14]=01b) or auto-decrementing (address[15:14]=10b). The internal DWORD address is incremented, decremented, or maintained based on these bits. Maintaining a fixed internal address may be useful for register “bit-banging” or other repeated writes. 10.2.6.1 Write The Write instruction inputs the instruction code and address and data bytes one bit per clock. In SQI mode, the instruction code and the address and data bytes are input four bits per clock. This instruction is supported in SPI and SQI bus protocols with clock frequencies up to 80 MHz. The SPI/SQI slave interface is selected by first bringing SCS# active. For SPI mode, the 8-bit WRITE instruction, 02h, is input into the SI/SIO[0] pin, followed by the two address bytes. For SQI mode, the 8-bit WRITE instruction, 02h, is input into the SIO[3:0] pins, followed by the two address bytes. The address bytes specify a BYTE address within the device. The data follows the address bytes. For SPI mode, the data is input into the SI/SIO[0] pin starting with the msb of the LSB. For SQI mode the data is input nibble wide using SIO[3:0] starting with the msn of the LSB. The remaining bits/ nibbles are shifted in on subsequent clock edges. The data write to the register occurs after the 32-bits are input. In the event that 32-bits are not written when the SCS# is returned high, the write is considered invalid and the register is not affected. The SCS# input is brought inactive to conclude the cycle. Figure 10-11 illustrates a typical single and multiple register write for SPI mode. Figure 10-12 illustrates a typical single and multiple register write for SQI mode. FIGURE 10-11: SPI WRITE SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 1 1 1 0 9 1 2 1 3 1 1 1 2 1 4 1 3 1 5 1 4 1 5 Instruction SI X 0 0 0 0 0 0 1 6 1 7 1 6 1 8 1 7 1 9 1 8 2 0 1 9 2 1 2 0 2 2 2 1 2 3 2 2 2 4 2 3 2 5 2 4 2 6 2 5 2 7 2 6 ... 2 7 Address 1 0 d e c i n c A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 5 3 ... 5 4 5 3 5 5 5 4 5 6 5 5 X 5 6 X Data A 6 A 5 A 4 A 3 A 2 A 1 A 0 D 7 D 6 D 5 ... D 2 6 D 2 5 D 2 4 X Z SO SPI Write Single Register SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 9 1 1 1 0 1 2 1 3 1 1 1 2 1 4 1 3 1 5 1 4 Instruction SI X 0 0 0 SO 0 0 0 1 6 1 5 1 7 1 6 1 8 1 7 1 9 1 8 2 0 1 9 2 1 2 0 2 2 2 1 2 3 2 2 2 4 2 3 2 4 Address 1 0 d e c i n c A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 A 6 2 5 2 6 2 5 2 7 2 6 ... ... 2 7 Data 1... A 5 A 4 A 3 A 2 A 1 A 0 D 7 D 6 ... ... D 5 ... Data m D 2 6 D 2 5 D 2 4 X X Data m+1... Data n D 7 D 6 D 5 ... D 2 6 D 2 5 D 2 4 X Z SPI Write Multiple Registers 2015 Microchip Technology Inc. DS00001909A-page 113 LAN9252 FIGURE 10-12: SQI WRITE SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 SIO[3:0] X 0 2 H 1 L 1 H 0 1 0 9 Inst Address 1 1 1 2 1 1 1 3 1 2 1 4 1 3 X 1 4 X Data L 0 H 0 L 0 H 1 L 1 H 2 L 2 H 3 L 3 X SQI Write Single Register SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 6 Inst Address SIO[3:0] X 0 2 H 1 L 1 H 0 7 L 0 8 7 9 8 ... 9 ... Data 1... H 0 L 0 H 1 ... ... X ... Data m L 2 H 3 X Data m+1... Data n L 3 H 0 L 0 H 1 ... L 2 H 3 L 3 X SQI Write Multiple Registers DS00001909A-page 114 2015 Microchip Technology Inc. LAN9252 10.2.6.2 Dual Data Write The SPI Dual Data Write instruction inputs the instruction code and address bytes one bit per clock and inputs the data two bits per clock. This instruction is supported in SPI bus protocol only with clock frequencies up to 80 MHz. This instruction is not supported in SQI bus protocol. The SPI slave interface is selected by first bringing SCS# active. The 8-bit SDDW instruction, 32h, is input into the SIO[0] pin, followed by the two address bytes. The address bytes specify a BYTE address within the device. The data follows the address bytes. The data is input into the SIO[1:0] pins starting with the msbs of the LSB. The remaining di-bits are shifted in on subsequent clock edges. The data write to the register occurs after the 32-bits are input. In the event that 32-bits are not written when the SCS# is returned high, the write is considered invalid and the register is not affected. The SCS# input is brought inactive to conclude the cycle. Figure 10-13 illustrates a typical single and multiple register dual data write. FIGURE 10-13: SPI DUAL DATA WRITE SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 1 1 1 0 9 1 2 1 3 1 1 1 2 1 4 1 3 1 5 1 4 1 5 Instruction SIO0 X 0 0 1 1 0 0 1 6 1 7 1 6 1 8 1 7 1 9 1 8 2 0 1 9 2 1 2 0 2 2 2 1 2 3 2 2 2 4 2 3 2 5 2 4 2 6 2 5 2 7 2 6 ... 2 7 Address 1 0 d e c i n c A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 3 7 ... 3 8 3 7 3 9 3 8 4 0 3 9 X 4 0 X Data A 6 A 5 A 4 A 3 A 2 A 1 A 0 D 6 D 4 D 2 ... D 2 8 D 2 6 D 2 4 X D 2 9 D 2 7 D 2 5 X Z Data D 7 Z SIO1 D 5 D 3 ... SPI Dual Data Write Single Register SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 9 1 1 1 0 1 2 1 3 1 1 1 2 1 4 1 3 1 5 1 4 Instruction SIO0 X 0 0 1 1 0 0 1 6 1 5 1 7 1 6 1 8 1 7 1 9 1 8 2 0 1 9 2 1 2 0 2 2 2 1 2 3 2 2 2 4 2 3 2 5 2 4 Address 1 0 d e c i n c A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 A 6 2 6 2 5 2 7 2 6 ... ... 2 7 Data 1... A 5 A 4 A 3 A 2 A 1 A 0 D 6 D 4 D 2 ... Data 1... SIO1 Z D 7 D 5 ... ... D 3 ... Data m D 2 8 D 2 6 D 2 4 Data m D 2 9 D 2 7 D 2 5 X X Data m+1... Data n D 6 D 4 D 2 ... D 2 8 D 2 6 D 2 4 X Data m+1... Data n D 7 D 5 D 3 ... D 2 9 D 2 7 D 2 5 X Z SPI Dual Data Write Multiple Registers 2015 Microchip Technology Inc. DS00001909A-page 115 LAN9252 10.2.6.3 Quad Data Write The SPI Quad Data Write instruction inputs the instruction code and address bytes one bit per clock and inputs the data four bits per clock. This instruction is supported in SPI bus protocol only with clock frequencies up to 80 MHz. This instruction is not supported in SQI bus protocol. The SPI slave interface is selected by first bringing SCS# active. The 8-bit SQDW instruction, 62h, is input into the SIO[0] pin, followed by the two address bytes. The address bytes specify a BYTE address within the device. The data follows the address bytes. The data is input into the SIO[3:0] pins starting with the msn of the LSB. The remaining nibbles are shifted in on subsequent clock edges. The data write to the register occurs after the 32-bits are input. In the event that 32-bits are not written when the SCS# is returned high, the write is considered invalid and the register is not affected. The SCS# input is brought inactive to conclude the cycle. Figure 10-14 illustrates a typical single and multiple register quad data write. FIGURE 10-14: SPI QUAD DATA WRITE SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 1 1 1 0 9 1 2 1 3 1 1 1 2 1 4 1 3 1 5 1 4 1 5 Instruction SIO0 X 0 1 1 0 0 0 1 6 1 7 1 6 1 8 1 7 1 9 1 8 2 0 1 9 2 1 2 0 2 2 2 1 2 3 2 2 2 4 2 3 2 5 2 4 2 6 2 5 2 7 2 6 2 8 2 7 Address 1 0 d e c i n c A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 2 9 2 8 3 0 2 9 3 1 3 0 3 2 3 1 X 3 2 X Data A 6 A 5 A 4 A 3 A 2 A 1 A 0 D 4 D 0 D 1 2 D 8 D 2 0 D 1 6 D 2 8 D 2 4 X D 1 7 D 2 9 D 2 5 X Z D 1 8 D 3 0 D 2 6 X Z D 1 9 D 3 1 D 2 7 X Z Data D 5 Z SIO1 D 1 D 1 3 D 9 D 2 1 Data D 6 Z SIO2 D 2 D 1 4 D 1 0 D 2 2 Data D 7 Z SIO3 D 3 D 1 5 D 1 1 D 2 3 SPI Quad Data Write Single Register SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 9 1 1 1 0 1 2 1 3 1 1 1 2 1 4 1 3 1 5 1 4 Instruction SIO0 X 0 1 1 0 0 0 1 6 1 5 1 7 1 6 1 8 1 7 1 9 1 8 2 0 1 9 2 1 2 0 2 2 2 1 2 3 2 2 2 4 2 3 2 5 2 4 Address 1 0 d e c i n c A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 A 6 2 6 2 5 2 7 2 6 ... ... 2 7 Data 1... A 5 A 4 A 3 A 2 A 1 A 0 D 4 D 0 D 1 2 ... Data 1... SIO1 Z D 5 D 1 D 1 3 ... Data 1... SIO2 Z D 6 D 2 D 1 4 ... Data 1... SIO3 Z D 7 D 3 ... ... D 1 5 ... Data m D 1 6 D 2 8 D 2 4 Data m D 1 7 D 2 9 D 2 5 Data m D 1 8 D 3 0 D 2 6 Data m D 1 9 D 3 1 D 2 7 X X Data m+1... Data n D 4 D 0 D 1 2 ... D 1 6 D 2 8 D 2 4 X Data m+1... Data n D 5 D 1 D 1 3 ... D 1 7 D 2 9 D 2 5 X Z Data m+1... Data n D 6 D 2 D 1 4 ... D 1 8 D 3 0 D 2 6 X Z Data m+1... Data n D 7 D 3 D 1 5 ... D 1 9 D 3 1 D 2 7 X Z SPI Quad Data Write Multiple Registers DS00001909A-page 116 2015 Microchip Technology Inc. LAN9252 10.2.6.4 Dual Address / Data Write The SPI Dual Address / Data Write instruction inputs the instruction code one bit per clock and the address and data bytes two bits per clock. This instruction is supported in SPI bus protocol only with clock frequencies up to 80 MHz. This instruction is not supported in SQI bus protocol. The SPI slave interface is selected by first bringing SCS# active. The 8-bit SDADW instruction, B2h, is input into the SIO[0] pin, followed by the two address bytes into the SIO[1:0] pins. The address bytes specify a BYTE address within the device. The data follows the address bytes. The data is input into the SIO[1:0] pins starting with the msbs of the LSB. The remaining di-bits are shifted in on subsequent clock edges. The data write to the register occurs after the 32-bits are input. In the event that 32-bits are not written when the SCS# is returned high, the write is considered invalid and the register is not affected. The SCS# input is brought inactive to conclude the cycle. Figure 10-15 illustrates a typical single and multiple register dual address / data write. FIGURE 10-15: SPI DUAL ADDRESS / DATA WRITE SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 1 1 1 0 9 1 1 Instruction SIO0 X 1 0 1 1 0 0 1 2 1 3 1 2 1 4 1 3 1 5 1 4 1 6 1 5 1 7 1 6 1 8 1 7 1 9 1 8 ... 1 9 0 i n c A 1 2 A 1 0 A 8 A 6 A 4 A 2 A 0 D 6 D 4 D 2 Address d e c Z SIO1 A 1 3 A 1 1 A 9 A 7 ... 3 0 2 9 3 1 3 0 3 2 3 1 X 3 2 X Data Address 1 2 9 ... D 2 8 D 2 6 D 2 4 X D 2 9 D 2 7 D 2 5 X Z Data A 5 A 3 A 1 D 7 D 5 D 3 ... SPI Dual Address / Data Write Single Register SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 1 0 9 8 1 0 9 Instruction SIO0 X 1 0 1 1 0 0 1 1 1 2 1 1 1 3 1 2 1 4 1 3 1 5 1 4 1 6 1 5 1 7 1 6 Address 1 0 i n c A 1 2 A 1 0 A 8 A 6 A 4 Z d e c A 1 3 A 1 1 A 9 A 7 A 5 1 7 1 9 1 8 ... ... A 2 A 0 D 6 D 4 D 2 ... Data 1... A 3 A 1 D 7 D 5 ... ... 1 9 Data 1... Address SIO1 1 8 D 3 ... Data m D 2 8 D 2 6 D 2 4 Data m D 2 9 D 2 7 D 2 5 X X Data m+1... Data n D 6 D 4 D 2 ... D 2 8 D 2 6 D 2 4 X Data m+1... Data n D 7 D 5 D 3 ... D 2 9 D 2 7 D 2 5 X Z SPI Dual Address / Data Write Multiple Registers 2015 Microchip Technology Inc. DS00001909A-page 117 LAN9252 10.2.6.5 Quad Address / Data Write The SPI Quad Address / Data Write instruction inputs the instruction code one bit per clock and the address and data bytes four bits per clock. This instruction is supported in SPI bus protocol only with clock frequencies up to 80 MHz. This instruction is not supported in SQI bus protocol. The SPI slave interface is selected by first bringing SCS# active. The 8-bit SQADW instruction, E2h, is input into the SIO[0] pin, followed by the two address bytes into the SIO[3:0] pins. The address bytes specify a BYTE address within the device. The data follows the address bytes. The data is input into the SIO[3:0] pins starting with the msn of the LSB. The remaining nibbles are shifted in on subsequent clock edges. The data write to the register occurs after the 32-bits are input. In the event that 32-bits are not written when the SCS# is returned high, the write is considered invalid and the register is not affected. The SCS# input is brought inactive to conclude the cycle. Figure 10-16 illustrates a typical single and multiple register dual address / data write. FIGURE 10-16: SPI QUAD ADDRESS / DATA WRITE SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 8 X 1 1 1 0 0 0 1 1 1 0 9 Instruction SIO0 1 0 9 1 2 1 1 1 3 1 2 1 4 1 3 1 5 1 4 1 6 1 5 Address 1 0 A 1 2 A 8 A 4 1 7 1 6 1 8 1 7 1 9 1 8 2 0 1 9 X 2 0 X Data A 0 D 4 D 0 D 1 2 D 8 D 2 0 D 1 6 D 2 8 D 2 4 X D 1 7 D 2 9 D 2 5 X Z D 1 8 D 3 0 D 2 6 X Z D 1 9 D 3 1 D 2 7 X Z Data A 1 3 Z SIO1 A 9 A 5 A 1 D 5 D 1 D 1 3 D 9 D 2 1 Data i n c Z SIO2 A 1 0 A 6 A 2 D 6 D 2 D 1 4 D 1 0 D 2 2 Data d e c Z SIO3 A 1 1 A 7 A 3 D 7 D 3 D 1 5 D 1 1 D 2 3 SPI Quad Address / Data Write Single Register SCS# SCK (active low) X SCK (active high) X 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 8 Instruction SIO0 X 1 1 1 0 0 0 1 0 9 9 1 1 1 0 1 2 1 1 1 3 1 2 Address 1 0 A 1 2 A 8 A 4 A 0 1 4 1 3 1 5 1 4 ... ... 1 5 Data 1... D 4 D 0 D 1 2 ... Data 1... SIO1 Z A 1 3 A 9 A 5 A 1 D 5 SIO2 Z i n c A 1 0 A 6 A 2 D 6 SIO3 Z d e c A 1 1 A 7 A 3 D 7 D 1 D 1 3 ... Data 1... D 2 D 1 4 ... Data 1... D 3 ... ... D 1 5 ... Data m D 1 6 D 2 8 D 2 4 Data m D 1 7 D 2 9 D 2 5 Data m D 1 8 D 3 0 D 2 6 Data m D 1 9 D 3 1 D 2 7 X X Data m+1... Data n D 4 D 0 D 1 2 ... D 1 6 D 2 8 D 2 4 X Data m+1... Data n D 5 D 1 D 1 3 ... D 1 7 D 2 9 D 2 5 X Z Data m+1... Data n D 6 D 2 D 1 4 ... D 1 8 D 3 0 D 2 6 X Z Data m+1... Data n D 7 D 3 D 1 5 ... D 1 9 D 3 1 D 2 7 X Z SPI Quad Address / Data Write Multiple Registers DS00001909A-page 118 2015 Microchip Technology Inc. LAN9252 10.3 SPI/SQI Timing Requirements FIGURE 10-17: SPI/SQI INPUT TIMING tscshl SCS# tscss tscsh thigh tlow SCK tsu thd SI/SIO[3:0] FIGURE 10-18: SPI/SQI OUTPUT TIMING SCS# thigh tlow SCK ton tv tho tdis SO/SIO[3:0] TABLE 10-3: SPI/SQI TIMING VALUES Symbol Description Min Typ Max Units 30 / 80 MHz fsck SCK clock frequency Note 3 thigh SCK high time 5.5 ns tlow SCK low time 5.5 ns tscss SCS# setup time to SCK 5 ns tscsh SCS# hold time from SCK 5 ns tscshl SCS# inactive time 50 ns tsu Data input setup time to SCK 3 ns thd Data input hold time from SCK 4 ns ton Data output turn on time from SCK 0 ns tv Data output valid time from SCK Note 4, Note 5 tho Data output hold time from SCK tdis Data output disable time from SCS# inactive 11.0/9.0 0 ns ns 20 ns Note 3: The Read instruction is limited to 30 MHz maximum Note 4: Depends on loading of 30 pF or 10 pF Note 5: Depending on the clock frequency and pulse width, data may not be valid until following the next rising edge of SCK. The host SPI controller may need to delay the sampling of the data by either a fixed time or by using the falling edge of SCK. 2015 Microchip Technology Inc. DS00001909A-page 119 LAN9252 11.0 ETHERNET PHYS 11.1 Functional Overview The device contains PHYs A and B. The A and B PHYs are identical in functionality. PHY A connects to the EtherCAT Core port 0 or 2. PHY B connects to EtherCAT core port 1. These PHYs interface with their respective MAC via an internal MII interface. The PHYs comply with the IEEE 802.3 Physical Layer for Twisted Pair Ethernet and can be configured for full duplex 100 Mbps (100BASE-TX / 100BASE-FX) Ethernet operation. All PHY registers follow the IEEE 802.3 (clause 22.2.4) specified MII management register set and are fully configurable. 11.1.1 PHY ADDRESSING The address for PHY A is set to 0 or 2, based on the device mode, and the address for PHY B is fixed to 1. In addition, the addresses for PHY A and B can be changed via the PHY Address (PHYADD) field in the PHY x Special Modes Register (PHY_SPECIAL_MODES_x). For proper operation, the addresses for PHYs A and B must be unique. No check is performed to assure each PHY is set to a different address. 11.2 PHYs A & B The device integrates two IEEE 802.3 PHY functions. The PHYs can be configured for either 100 Mbps copper (100BASE-TX) or 100 Mbps fiber (100BASE-FX) Ethernet operation and include Auto-Negotiation and HP Auto-MDIX. Note: 11.2.1 Because PHYs A and B are functionally identical, this section will describe them as the “PHY x”, or simply “PHY”. Wherever a lowercase “x” has been appended to a port or signal name, it can be replaced with “A” or “B” to indicate the PHY A or PHY B respectively. In some instances, a “1” or a “2” may be appropriate instead. All references to “PHY” in this section can be used interchangeably for both the PHYs A and B. FUNCTIONAL DESCRIPTION Functionally, each PHY can be divided into the following sections: • • • • • • • • • • • 100BASE-TX Transmit and 100BASE-TX Receive Auto-Negotiation HP Auto-MDIX PHY Management Control and PHY Interrupts PHY Power-Down Modes Wake on LAN (WoL) Resets Link Integrity Test Cable Diagnostics Loopback Operation 100BASE-FX Far End Fault Indication DS00001909A-page 120 2015 Microchip Technology Inc. LAN9252 A block diagram of the main components of each PHY can be seen in Figure 11-1. FIGURE 11-1: PHY BLOCK DIAGRAM AutoNegotiation 100 Transmitter MII To Port x EtherCAT MAC TXPx/TXNx MII MAC Interface HP Auto-MDIX RXPx/RXNx To External Port x Ethernet Pins 100 Reciever To EtherCAT core MDIO PHY Management Control Registers PLL Interrupts To System Interrupt Controller 11.2.2 From System Clocks Controller 100BASE-TX TRANSMIT The 100BASE-TX transmit data path is shown in Figure 11-2. Shaded blocks are those which are internal to the PHY. Each major block is explained in the following sections. FIGURE 11-2: 100BASE-TX TRANSMIT DATA PATH Internal MII Transmit Clock 100M PLL Internal MII 25 MHz by 4 bits MII MAC Interface Port x MAC 25MHz by 4 bits 4B/5B Encoder 25MHz by 5 bits Scrambler and PISO 125 Mbps Serial NRZI Converter MLT-3 Converter NRZI MLT-3 100M TX Driver MLT-3 Magnetics MLT-3 RJ45 11.2.2.1 MLT-3 CAT-5 100BASE-TX Transmit Data Across the Internal MII Interface For a transmission, the EtherCAT Core MAC drives the transmit data onto the internal MII TXD bus and asserts the internal MII TXEN to indicate valid data. The data is in the form of 4-bit wide 25 MHz data. 2015 Microchip Technology Inc. DS00001909A-page 121 LAN9252 11.2.2.2 4B/5B Encoder The transmit data passes from the MII block to the 4B/5B Encoder. This block encodes the data from 4-bit nibbles to 5bit symbols (known as “code-groups”) according to Table 11-1. Each 4-bit data-nibble is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for control information or are not valid. The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through F. The remaining code-groups are given letter designations with slashes on either side. For example, an IDLE code-group is / I/, a transmit error code-group is /H/, etc. TABLE 11-1: 4B/5B CODE TABLE Code Group Sym Receiver Interpretation 11110 0 0 0000 01001 1 1 10100 2 10101 0 0000 0001 1 0001 2 0010 2 0010 3 3 0011 3 0011 01010 4 4 0100 4 0100 01011 5 5 0101 5 0101 01110 6 6 0110 6 0110 01111 7 7 0111 7 0111 10010 8 8 1000 8 1000 10011 9 9 1001 9 1001 10110 A A 1010 A 1010 10111 B B 1011 B 1011 11010 C C 1100 C 1100 11011 D D 1101 D 1101 11100 E E 1110 E 1110 11101 F F 1111 F 1111 11111 /I/ IDLE Sent after /T/R/ until the MII Transmitter Enable signal (TXEN) is received 11000 /J/ First nibble of SSD, translated to “0101” following IDLE, else MII Receive Error (RXER) Sent for rising MII Transmitter Enable signal (TXEN) 10001 /K/ Second nibble of SSD, translated to “0101” following J, else MII Receive Error (RXER) Sent for rising MII Transmitter Enable signal (TXEN) 01101 /T/ First nibble of ESD, causes de-assertion of CRS if followed by /R/, else assertion of MII Receive Error (RXER) Sent for falling MII Transmitter Enable signal (TXEN) 00111 /R/ Second nibble of ESD, causes de-assertion of CRS if following /T/, else assertion of MII Receive Error (RXER) Sent for falling MII Transmitter Enable signal (TXEN) 00100 /H/ Transmit Error Symbol Sent for rising MII Transmit Error (TXER) DS00001909A-page 122 DATA Transmitter Interpretation DATA 2015 Microchip Technology Inc. LAN9252 TABLE 11-1: 4B/5B CODE TABLE (CONTINUED) Code Group Sym 00110 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) INVALID 11001 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) INVALID 00000 /P/ INVALID INVALID 00001 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) INVALID 00010 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) INVALID 00011 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) INVALID 00101 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) INVALID 01000 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) INVALID 01100 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) INVALID 10000 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) INVALID 11.2.2.3 Receiver Interpretation Transmitter Interpretation Scrambler and PISO Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large narrow-band peaks. Scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire channel bandwidth. This uniform spectral density is required by FCC regulations to prevent excessive EMI from being radiated by the physical wiring. The seed for the scrambler is generated from the PHY address, ensuring that each PHY will have its own scrambler sequence. For more information on PHY addressing, refer to Section 11.1.1, "PHY Addressing". The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data. 11.2.2.4 NRZI and MLT-3 Encoding The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a serial 125MHz NRZI data stream. The NRZI is then encoded to MLT-3. MLT-3 is a tri-level code where a change in the logic level represents a code bit “1” and the logic output remaining at the same level represents a code bit “0”. 11.2.2.5 100M Transmit Driver The MLT-3 data is then passed to the analog transmitter, which drives the differential MLT-3 signal on output pins TXPx and TXNx, to the twisted pair media across a 1:1 ratio isolation transformer. The transmitter drives into the 100 impedance of the CAT-5 cable. Cable termination and impedance matching require external components. 11.2.2.6 100M Phase Lock Loop (PLL) The 100M PLL locks onto the reference clock and generates the 125 MHz clock used to drive the 125 MHz logic and the 100BASE-TX Transmitter. 2015 Microchip Technology Inc. DS00001909A-page 123 LAN9252 11.2.3 100BASE-TX RECEIVE The 100BASE-TX receive data path is shown in Figure 11-3. Shaded blocks are those which are internal to the PHY. Each major block is explained in the following sections. FIGURE 11-3: 100BASE-TX RECEIVE DATA PATH 100M PLL Internal MII Receive Clock Port x MAC MII MAC Interface Internal MII 25MHz by 4 bits 25MHz by 4 bits 4B/5B Decoder 25MHz by 5 bits Descrambler and SIPO 125 Mbps Serial NRZI Converter A/D Converter MLT-3 Converter NRZI MLT-3 Magnetics MLT-3 MLT-3 RJ45 DSP: Timing recovery, Equalizer and BLW Correction MLT-3 CAT-5 6 bit Data 11.2.3.1 100M Receive Input The MLT-3 data from the cable is fed into the PHY on inputs RXPx and RXNx via a 1:1 ratio transformer. The ADC samples the incoming differential signal at a rate of 125M samples per second. Using a 64-level quantizer, 6 digital bits are generated to represent each sample. The DSP adjusts the gain of the ADC according to the observed signal levels such that the full dynamic range of the ADC can be used. 11.2.3.2 Equalizer, BLW Correction and Clock/Data Recovery The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors, and CAT- 5 cable. The equalizer can restore the signal for any good-quality CAT-5 cable between 1m and 100m. If the DC content of the signal is such that the low-frequency components fall below the low frequency pole of the isolation transformer, then the droop characteristics of the transformer will become significant and Baseline Wander (BLW) on the received signal will result. To prevent corruption of the received data, the PHY corrects for BLW and can receive the ANSI X3.263-1995 FDDI TP-PMD defined “killer packet” with no bit errors. The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP, selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to extract the serial data from the received signal. 11.2.3.3 NRZI and MLT-3 Decoding The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an NRZI data stream. 11.2.3.4 Descrambler The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel Out (SIPO) conversion of the data. DS00001909A-page 124 2015 Microchip Technology Inc. LAN9252 During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the incoming stream. Once synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data. Special logic in the descrambler ensures synchronization with the remote transceiver by searching for IDLE symbols within a window of 4000 bytes (40 us). This window ensures that a maximum packet size of 1514 bytes, allowed by the IEEE 802.3 standard, can be received with no interference. If no IDLE-symbols are detected within this time-period, receive operation is aborted and the descrambler re-starts the synchronization process. The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream Delimiter (SSD) pair at the start of a packet. Once the code-word alignment is determined, it is stored and utilized until the next start of frame. 11.2.3.5 5B/4B Decoding The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The translated data is presented on the internal MII RXD[3:0] signal lines. The SSD, /J/K/, is translated to “0101 0101” as the first 2 nibbles of the MAC preamble. Reception of the SSD causes the transceiver to assert the receive data valid signal, indicating that valid data is available on the RXD bus. Successive valid code-groups are translated to data nibbles. Reception of either the End of Stream Delimiter (ESD) consisting of the /T/R/ symbols, or at least two /I/ symbols causes the transceiver to deassert carrier sense and receive data valid signal. Note: 11.2.3.6 These symbols are not translated into data. Receive Data Valid Signal The internal MII’s Receive Data Valid signal (RXDV) indicates that recovered and decoded nibbles are being presented on the RXD[3:0] outputs synchronous to RXCLK. RXDV becomes active after the /J/K/ delimiter has been recognized and RXD is aligned to nibble boundaries. It remains active until either the /T/R/ delimiter is recognized or link test indicates failure or SIGDET becomes false. RXDV is asserted when the first nibble of translated /J/K/ is ready for transfer over the Media Independent Interface. 11.2.3.7 Receiver Errors During a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0 through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the internal MII’s RXER signal is asserted and arbitrary data is driven onto the internal MII’s RXD[3:0] lines. Should an error be detected during the time that the / J/K/ delimiter is being decoded (bad SSD error), RXER is asserted true and the value 1110b is driven onto the RXD[3:0] lines. Note that the internal MII’s data valid signal (RXDV) is not yet asserted when the bad SSD occurs. 11.2.3.8 100M Receive Data Across the Internal MII Interface For reception, the 4-bit data nibbles are sent to the MII MAC Interface block. These data nibbles are clocked to the controller at a rate of 25 MHz. RXCLK is the output clock for the internal MII bus. It is recovered from the received data to clock the RXD bus. If there is no received signal, it is derived from the system reference clock. 11.2.4 AUTO-NEGOTIATION The purpose of the Auto-Negotiation function is to automatically configure the transceiver to the optimum link parameters based on the capabilities of its link partner. Auto-Negotiation is a mechanism for exchanging configuration information between two link-partners and automatically selecting the highest performance mode of operation supported by both sides. Auto-Negotiation is fully defined in clause 28 of the IEEE 802.3 specification and is enabled by setting the Auto-Negotiation Enable (PHY_AN) of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x). Note: Auto-Negotiation is not used for 100BASE-FX mode. The advertised capabilities of the PHY are stored in the PHY x Auto-Negotiation Advertisement Register (PHY_AN_ADV_x). The PHY contains the ability to advertise 100BASE-TX and 10BASE-T in both full or half-duplex modes. Besides the connection speed, the PHY can advertise remote fault indication and symmetric or asymmetric pause flow control as defined in the IEEE 802.3 specification. The transceiver supports “Next Page” capability which is used to negotiate Energy Efficient Ethernet functionality as well as to support software controlled pages. Many of the default advertised capabilities of the PHY are determined via configuration straps as shown in Section 11.2.16.5, "PHY x Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)," on page 150. Refer to Section 7.0, "Configuration Straps," on page 51 for additional details on how to use the device configuration straps. 2015 Microchip Technology Inc. DS00001909A-page 125 LAN9252 Once Auto-Negotiation has completed, information about the resolved link and the results of the negotiation process are reflected in the Speed Indication bits in the PHY x Special Control/Status Register (PHY_SPECIAL_CONTROL_STATUS_x), as well as the PHY x Auto-Negotiation Link Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x). The Auto-Negotiation protocol is a purely physical layer activity and proceeds independently of the MAC controller. The following blocks are activated during an Auto-Negotiation session: • • • • • • • Auto-Negotiation (digital) 100M ADC (analog) 100M PLL (analog) 100M equalizer/BLW/clock recovery (DSP) 10M SQUELCH (analog) 10M PLL (analog) 10M Transmitter (analog) When enabled, Auto-Negotiation is started by the occurrence of any of the following events: • Power-On Reset (POR) • Hardware reset (RST#) • PHY Software reset (via Reset Control Register (RESET_CTL), or bit 15 of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x)) • PHY Power-down reset (Section 11.2.8, "PHY Power-Down Modes," on page 131) • PHY Link status down (bit 2 of the PHY x Basic Status Register (PHY_BASIC_STATUS_x) is cleared) • Setting the PHY x Basic Control Register (PHY_BASIC_CONTROL_x), bit 9 high (auto-neg restart) • EtherCAT System Reset Note: Refer to Section 6.2, "Resets," on page 38 for information on these and other system resets. On detection of one of these events, the transceiver begins Auto-Negotiation by transmitting bursts of Fast Link Pulses (FLP). These are bursts of link pulses from the 10M TX Driver. They are shaped as Normal Link Pulses and can pass uncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst consists of up to 33 pulses. The 17 odd-numbered pulses, which are always present, frame the FLP burst. The 16 even-numbered pulses, which may be present or absent, contain the data word being transmitted. Presence of a data pulse represents a “1”, while absence represents a “0”. The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE 802.3 clause 28. In summary, the transceiver advertises 802.3 compliance in its selector field (the first 5 bits of the Link Code Word). It advertises its technology ability according to the bits set in the PHY x Auto-Negotiation Advertisement Register (PHY_AN_ADV_x). There are 4 possible matches of the technology abilities. In the order of priority these are: • • • • 100M Full Duplex (Highest priority) 100M Half Duplex 10M Full Duplex 10M Half Duplex (Lowest priority) If the full capabilities of the transceiver are advertised (100M, full-duplex), and if the link partner is capable of 10M and 100M, then Auto-Negotiation selects 100M as the highest performance mode. If the link partner is capable of half and full-duplex modes, then Auto-Negotiation selects full-duplex as the highest performance mode. Once a capability match has been determined, the link code words are repeated with the acknowledge bit set. Any difference in the main content of the link code words at this time will cause Auto-Negotiation to re-start. Auto-Negotiation will also re-start if not all of the required FLP bursts are received. Writing the PHY x Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) bits [8:5] allows software control of the capabilities advertised by the transceiver. Writing the PHY x Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) does not automatically re-start Auto-Negotiation. The Restart Auto-Negotiation (PHY_RST_AN) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) must be set before the new abilities will be advertised. Auto-Negotiation can also be disabled via software by clearing the Auto-Negotiation Enable (PHY_AN) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x). DS00001909A-page 126 2015 Microchip Technology Inc. LAN9252 11.2.4.1 Parallel Detection If the device is connected to a device lacking the ability to Auto-Negotiate (i.e. no FLPs are detected), it is able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE 802.3 standard. This ability is known as “Parallel Detection.” This feature ensures interoperability with legacy link partners. If a link is formed via parallel detection, then the Link Partner AutoNegotiation Able bit of the PHY x Auto-Negotiation Expansion Register (PHY_AN_EXP_x) is cleared to indicate that the link partner is not capable of Auto-Negotiation. If a fault occurs during parallel detection, the Parallel Detection Fault bit of the PHY x Auto-Negotiation Expansion Register (PHY_AN_EXP_x) is set. The PHY x Auto-Negotiation Link Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x) is used to store the Link Partner Ability information, which is coded in the received FLPs. If the link partner is not Auto-Negotiation capable, then this register is updated after completion of parallel detection to reflect the speed capability of the link partner. 11.2.4.2 Restarting Auto-Negotiation Auto-Negotiation can be re-started at any time by setting the Restart Auto-Negotiation (PHY_RST_AN) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x). Auto-Negotiation will also re-start if the link is broken at any time. A broken link is caused by signal loss. This may occur because of a cable break, or because of an interruption in the signal transmitted by the Link Partner. Auto-Negotiation resumes in an attempt to determine the new link configuration. If the management entity re-starts Auto-Negotiation by setting the Restart Auto-Negotiation (PHY_RST_AN) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x), the device will respond by stopping all transmission/receiving operations. Once the internal break_link_time is completed in the Auto-Negotiation state-machine (approximately 1200ms), Auto-Negotiation will re-start. In this case, the link partner will have also dropped the link due to lack of a received signal, so it too will resume Auto-Negotiation. 11.2.4.3 Disabling Auto-Negotiation Auto-Negotiation can be disabled by clearing the Auto-Negotiation Enable (PHY_AN) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x). The transceiver will then force its speed of operation to reflect the information in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) (Speed Select LSB (PHY_SPEED_SEL_LSB) and Duplex Mode (PHY_DUPLEX)). These bits are ignored when Auto-Negotiation is enabled. 11.2.4.4 Half Vs. Full-Duplex Half-duplex operation relies on the CSMA/CD (Carrier Sense Multiple Access / Collision Detect) protocol to handle network traffic and collisions. In this mode, the carrier sense signal, CRS, responds to both transmit and receive activity. If data is received while the transceiver is transmitting, a collision results. In full-duplex mode, the transceiver is able to transmit and receive data simultaneously. In this mode, CRS responds only to receive activity. The CSMA/CD protocol does not apply and collision detection is disabled. 11.2.5 HP AUTO-MDIX HP Auto-MDIX facilitates the use of CAT-3 (10 BASE-T) or CAT-5 (100 BASE-T) media UTP interconnect cable without consideration of interface wiring scheme. If a user plugs in either a direct connect LAN cable or a cross-over patch cable, as shown in Figure 11-4, the transceiver is capable of configuring the TXPx/TXNx and RXPx/RXNx twisted pair pins for correct transceiver operation. Note: Auto-MDIX is not used for 100BASE-FX mode. The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX and TX line pairs are interchangeable, special PCB design considerations are needed to accommodate the symmetrical magnetics and termination of an Auto-MDIX design. Software based control of the Auto-MDIX function may be performed using the Auto-MDIX Control (AMDIXCTRL) bit of the PHY x Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x). When AMDIXCTRL is set to 1, the Auto-MDIX capability is determined by the Auto-MDIX Enable (AMDIXEN) and Auto-MDIX State (AMDIXSTATE) bits of the PHY x Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x). 2015 Microchip Technology Inc. DS00001909A-page 127 LAN9252 Note: When operating in 10BASE-T or 100BASE-TX manual modes, the Auto-MDIX crossover time can be extended via the Extend Manual 10/100 Auto-MDIX Crossover Time bit of the PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG_x). Refer to Section 11.2.16.12, on page 159 for additional information. When Energy Detect Power-Down is enabled, the Auto-MDIX crossover time can be extended via the EDPD Extend Crossover bit of the PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG_x). Refer to Section 11.2.16.12, on page 159 for additional information FIGURE 11-4: DIRECT CABLE CONNECTION VS. CROSS-OVER CABLE CONNECTION RJ-45 8-pin straight-through for 10BASE-T/100BASE-TX signaling TXPx RJ-45 8-pin cross-over for 10BASE-T/100BASE-TX signaling 1 TXPx TXPx 1 1 TXPx 2 2 TXNx TXNx 2 2 TXNx RXPx 3 3 RXPx RXPx 3 3 RXPx Not Used 4 4 Not Used Not Used 4 4 Not Used Not Used 5 5 Not Used Not Used 5 5 Not Used RXNx 6 6 RXNx RXNx 6 6 RXNx Not Used 7 7 Not Used Not Used 8 8 Not Used TXNx 1 Not Used 7 7 Not Used Not Used 8 8 Not Used Direct Connect Cable 11.2.6 Cross-Over Cable PHY MANAGEMENT CONTROL The PHY Management Control block is responsible for the management functions of the PHY, including register access and interrupt generation. A Serial Management Interface (SMI) is used to support registers as required by the IEEE 802.3 (Clause 22), as well as the vendor specific registers allowed by the specification. The SMI interface consists of the MII Management Data (MDIO) signal and the MII Management Clock (MDC) signal. These signals allow access to all PHY registers. Refer to Section 11.2.16, "PHY Registers," on page 142 for a list of all supported registers and register descriptions. Non-supported registers will be read as FFFFh. 11.2.7 PHY INTERRUPTS The PHY contains the ability to generate various interrupt events. Reading the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) shows the source of the interrupt. The PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) enables or disables each PHY interrupt. The PHY Management Control block aggregates the enabled interrupts status into an internal signal which is sent to the System Interrupt Controller and is reflected via the PHY A Interrupt Event (PHY_INT_A) and PHY B Interrupt Event (PHY_INT_B) bits of the Interrupt Status Register (INT_STS). For more information on the device interrupts, refer to Section 8.0, "System Interrupts," on page 53. The PHY interrupt system provides two modes, a Primary interrupt mode and an Alternative interrupt mode. Both modes will assert the internal interrupt signal sent to the System Interrupt Controller when the corresponding mask bit is set. These modes differ only in how they de-assert the internal interrupt signal. These modes are detailed in the following subsections. Note: The Primary interrupt mode is the default interrupt mode after a power-up or hard reset. The Alternative interrupt mode requires setup after a power-up or hard reset. DS00001909A-page 128 2015 Microchip Technology Inc. LAN9252 11.2.7.1 Primary Interrupt Mode The Primary interrupt mode is the default interrupt mode. The Primary interrupt mode is always selected after power-up or hard reset. In this mode, to enable an interrupt, set the corresponding mask bit in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) (see Table 11-2). When the event to assert an interrupt is true, the internal interrupt signal will be asserted. When the corresponding event to de-assert the interrupt is true, the internal interrupt signal will be de-asserted. TABLE 11-2: Mask INTERRUPT MANAGEMENT TABLE Interrupt Source Flag Interrupt Source Event to Assert interrupt Event to De-assert interrupt 30.9 29.9 Link Up LINKSTAT See Note 1 Link Status Rising LINKSTAT Falling LINKSAT or Reading register 29 30.8 29.8 Wake on LAN WOL_INT See Note 2 Enabled WOL event Rising WOL_INT Falling WOL_INT or Reading register 29 30.7 29.7 ENERGYON 17.1 ENERGYON Rising 17.1 (Note 3) Falling 17.1 or Reading register 29 30.6 29.6 Auto-Negotiation complete 1.5 Auto-Negotiate Complete Rising 1.5 Falling 1.5 or Reading register 29 30.5 29.5 Remote Fault Detected 1.4 Remote Fault Rising 1.4 Falling 1.4, or Reading register 1 or Reading register 29 30.4 29.4 Link Down 1.2 Link Status Falling 1.2 Reading register 1 or Reading register 29 30.3 29.3 Auto-Negotiation LP Acknowledge 5.14 Acknowledge Rising 5.14 Falling 5.14 or Reading register 29 30.2 29.2 Parallel Detection Fault 6.4 Parallel Detection Fault Rising 6.4 Falling 6.4 or Reading register 6, or Reading register 29, or Re-Auto Negotiate or Link down 30.1 29.1 Auto-Negotiation Page Received 6.1 Page Received Rising 6.1 Falling 6.1 or Reading register 6, or Reading register 29, or Re-Auto Negotiate, or Link down. Note 1: LINKSTAT is the internal link status and is not directly available in any register bit. Note 2: WOL_INT is defined as bits 7:4 in the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) ANDed with bits 3:0 of the same register, with the resultant 4 bits OR’ed together. 2015 Microchip Technology Inc. DS00001909A-page 129 LAN9252 Note 3: If the mask bit is enabled and the internal interrupt signal has been de-asserted while ENERGYON is still high, the internal interrupt signal will assert for 256 ms, approximately one second after ENERGYON goes low when the Cable is unplugged. To prevent an unexpected assertion of the internal interrupt signal, the ENERGYON interrupt mask should always be cleared as part of the ENERGYON interrupt service routine. Note: 11.2.7.2 The Energy On (ENERGYON) bit in the PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) is defaulted to a ‘1’ at the start of the signal acquisition process, therefore the INT7 bit in the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) will also read as a ‘1’ at power-up. If no signal is present, then both Energy On (ENERGYON) and INT7 will clear within a few milliseconds. Alternate Interrupt Mode The Alternate interrupt mode is enabled by setting the ALTINT bit of the PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) to “1”. In this mode, to enable an interrupt, set the corresponding bit of the in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) (see Table 11-3). To clear an interrupt, clear the interrupt source and write a ‘1’ to the corresponding Interrupt Source Flag. Writing a ‘1’ to the Interrupt Source Flag will cause the state machine to check the Interrupt Source to determine if the Interrupt Source Flag should clear or stay as a ‘1’. If the condition to de-assert is true, then the Interrupt Source Flag is cleared and the internal interrupt signal is also deasserted. If the condition to de-assert is false, then the Interrupt Source Flag remains set, and the internal interrupt signal remains asserted. TABLE 11-3: Mask ALTERNATIVE INTERRUPT MODE MANAGEMENT TABLE Interrupt Source Flag Interrupt Source Event to Assert interrupt Condition to De-assert Bit to Clear interrupt 30.9 29.9 Link Up LINKSTAT See Note 4 Link Status Rising LINKSTAT LINKSTAT low 29.9 30.8 29.8 Wake on LAN WOL_INT See Note 5 Enabled WOL event Rising WOL_INT WOL_INT low 29.8 30.7 29.7 ENERGYON 17.1 ENERGYON Rising 17.1 17.1 low 29.7 30.6 29.6 Auto-Negotiation complete 1.5 Auto-Negotiate Complete Rising 1.5 1.5 low 29.6 30.5 29.5 Remote Fault Detected 1.4 Remote Fault Rising 1.4 1.4 low 29.5 30.4 29.4 Link Down 1.2 Link Status Falling 1.2 1.2 high 29.4 30.3 29.3 Auto-Negotiation LP Acknowledge 5.14 Acknowledge Rising 5.14 5.14 low 29.3 30.2 29.2 Parallel Detection Fault 6.4 Parallel Detection Fault Rising 6.4 6.4 low 29.2 30.1 29.1 Auto-Negotiation Page Received 6.1 Page Received Rising 6.1 6.1 low 29.1 Note 4: LINKSTAT is the internal link status and is not directly available in any register bit. DS00001909A-page 130 2015 Microchip Technology Inc. LAN9252 Note 5: WOL_INT is defined as bits 7:4 in the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) ANDed with bits 3:0 of the same register, with the resultant 4 bits OR’ed together. Note: 11.2.8 The Energy On (ENERGYON) bit in the PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) is defaulted to a ‘1’ at the start of the signal acquisition process, therefore the INT7 bit in the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) will also read as a ‘1’ at power-up. If no signal is present, then both Energy On (ENERGYON) and INT7 will clear within a few milliseconds. PHY POWER-DOWN MODES There are two PHY power-down modes: General Power-Down Mode and Energy Detect Power-Down Mode. These modes are described in the following subsections. Note: For more information on the various power management features of the device, refer to Section 6.3, "Power Management," on page 43. The power-down modes of each PHY are controlled independently. The PHY power-down modes do not reload or reset the PHY registers. 11.2.8.1 General Power-Down This power-down mode is controlled by the Power Down (PHY_PWR_DWN) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x). In this mode the entire transceiver, except the PHY management control interface, is powered down. The transceiver will remain in this power-down state as long as the Power Down (PHY_PWR_DWN) bit is set. When the Power Down (PHY_PWR_DWN) bit is cleared, the transceiver powers up and is automatically reset. 11.2.8.2 Energy Detect Power-Down This power-down mode is enabled by setting the Energy Detect Power-Down (EDPWRDOWN) bit of the PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x). In this mode, when no energy is present on the line, the entire transceiver is powered down (except for the PHY management control interface, the SQUELCH circuit and the ENERGYON logic). The ENERGYON logic is used to detect the presence of valid energy from 100BASE-TX, 10BASET, or Auto-Negotiation signals. In this mode, when the Energy On (ENERGYON) bit in the PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) signal is low, the transceiver is powered down and nothing is transmitted. When energy is received, via link pulses or packets, the Energy On (ENERGYON) bit goes high, and the transceiver powers up. The transceiver automatically resets itself into the state prior to power-down, and asserts the INT7 bit of the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x). The first and possibly second packet to activate ENERGYON may be lost. When the Energy Detect Power-Down (EDPWRDOWN) bit of the PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) is low, energy detect power-down is disabled. When in EDPD mode, the device’s NLP characteristics may be modified. The device can be configured to transmit NLPs in EDPD via the EDPD TX NLP Enable bit of the PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG_x). When enabled, the TX NLP time interval is configurable via the EDPD TX NLP Interval Timer Select field of the PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG_x). When in EDPD mode, the device can also be configured to wake on the reception of one or two NLPs. Setting the EDPD RX Single NLP Wake Enable bit of the PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG_x) will enable the device to wake on reception of a single NLP. If the EDPD RX Single NLP Wake Enable bit is cleared, the maximum interval for detecting reception of two NLPs to wake from EDPD is configurable via the EDPD RX NLP Max Interval Detect Select field of the PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG_x). The energy detect power down feature is part of the broader power management features of the device and can be used to trigger the power management event or general interrupt request pin (IRQ). This is accomplished by enabling the energy detect power-down feature of the PHY as described above, and setting the corresponding energy detect enable (bit 14 for PHY A, bit 15 for PHY B) of the Power Management Control Register (PMT_CTRL). Refer to Power Management for additional information. 2015 Microchip Technology Inc. DS00001909A-page 131 LAN9252 11.2.9 WAKE ON LAN (WOL) The PHY supports layer WoL event detection of Perfect DA, Broadcast, Magic Packet, and Wakeup frames. Each type of supported wake event (Perfect DA, Broadcast, Magic Packet, or Wakeup frames) may be individually enabled via Perfect DA Wakeup Enable (PFDA_EN), Broadcast Wakeup Enable (BCST_EN), Magic Packet Enable (MPEN), and Wakeup Frame Enable (WUEN) bits of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x), respectively. The WoL event is indicated via the INT8 bit of the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x). The WoL feature is part of the broader power management features of the device and can be used to trigger the power management event or general interrupt request pin (IRQ). This is accomplished by enabling the WoL feature of the PHY as described above, and setting the corresponding WoL enable (bit 14 for PHY A, bit 15 for PHY B) of the Power Management Control Register (PMT_CTRL). Refer to Section 6.3, "Power Management," on page 43 for additional information. The PHY x Wakeup Control and Status Register (PHY_WUCSR_x) also provides a WoL Configured bit, which may be set by software after all WoL registers are configured. Because all WoL related registers are not affected by software resets, software can poll the WoL Configured bit to ensure all WoL registers are fully configured. This allows the software to skip reprogramming of the WoL registers after reboot due to a WoL event. The following subsections detail each type of WoL event. For additional information on the main system interrupts, refer to Section 8.0, "System Interrupts," on page 53. 11.2.9.1 Perfect DA (Destination Address) Detection When enabled, the Perfect DA detection mode allows the detection of a frame with the destination address matching the address stored in the PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x), PHY x MAC Receive Address B Register (PHY_RX_ADDRB_x), and PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x). The frame must also pass the FCS and packet length check. As an example, the Host system must perform the following steps to enable the device to detect a Perfect DA WoL event: 1. 2. 3. Set the desired MAC address to cause the wake event in the PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x), PHY x MAC Receive Address B Register (PHY_RX_ADDRB_x), and PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x). Set the Perfect DA Wakeup Enable (PFDA_EN) bit of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) to enable Perfect DA detection. Set bit 8 (WoL event indicator) in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) to enable WoL events. When a match is triggered, bit 8 of the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) will be set, and the Perfect DA Frame Received (PFDA_FR) bit of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) will be set. 11.2.9.2 Broadcast Detection When enabled, the Broadcast detection mode allows the detection of a frame with the destination address value of FF FF FF FF FF FF. The frame must also pass the FCS and packet length check. As an example, the Host system must perform the following steps to enable the device to detect a Broadcast WoL event: 1. 2. Set the Broadcast Wakeup Enable (BCST_EN) bit of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) to enable Broadcast detection. Set bit 8 (WoL event indicator) in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) to enable WoL events. When a match is triggered, bit 8 of the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) will be set, and the Broadcast Frame Received (BCAST_FR) bit of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) will be set. 11.2.9.3 Magic Packet Detection When enabled, the Magic Packet detection mode allows the detection of a Magic Packet frame. A Magic Packet is a frame addressed to the device - either a unicast to the programmed address, or a broadcast - which contains the pattern 48’h FF_FF_FF_FF_FF_FF after the destination and source address field, followed by 16 repetitions of the desired MAC address (loaded into the PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x), PHY x MAC Receive Address DS00001909A-page 132 2015 Microchip Technology Inc. LAN9252 B Register (PHY_RX_ADDRB_x), and PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x)) without any breaks or interruptions. In case of a break in the 16 address repetitions, the logic scans for the 48’h FF_FF_FF_FF_FF_FF pattern again in the incoming frame. The 16 repetitions may be anywhere in the frame but must be preceded by the synchronization stream. The frame must also pass the FCS check and packet length checking. As an example, if the desired address is 00h 11h 22h 33h 44h 55h, then the logic scans for the following data sequence in an Ethernet frame: Destination Address Source Address ……………FF FF FF FF FF FF 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 …FCS As an example, the Host system must perform the following steps to enable the device to detect a Magic Packet WoL event: Set the desired MAC address to cause the wake event in the PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x), PHY x MAC Receive Address B Register (PHY_RX_ADDRB_x), and PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x). Set the Magic Packet Enable (MPEN) bit of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) to enable Magic Packet detection. Set bit 8 (WoL event indicator) in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) to enable WoL events. When a match is triggered, bit 8 of the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) will be set, and the Magic Packet Received (MPR) bit of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) will be set. 11.2.9.4 Wakeup Frame Detection When enabled, the Wakeup Frame detection mode allows the detection of a pre-programmed Wakeup Frame. Wakeup Frame detection provides a way for system designers to detect a customized pattern within a packet via a programmable wake-up frame filter. The filter has a 128-bit byte mask that indicates which bytes of the frame should be compared by the detection logic. A CRC-16 is calculated over these bytes. The result is then compared with the filter’s respective CRC-16 to determine if a match exists. When a wake-up pattern is received, the Remote Wakeup Frame Received (WUFR) bit of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) is set. If enabled, the filter can also include a comparison between the frame’s destination address and the address specified in the PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x), PHY x MAC Receive Address B Register (PHY_RX_ADDRB_x), and PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x). The specified address can be a unicast or a multicast. If address matching is enabled, only the programmed unicast or multicast address will be considered a match. Non-specific multicast addresses and the broadcast address can be separately enabled. The address matching results are logically OR’d (i.e., specific address match result OR any multicast result OR broadcast result). Whether or not the filter is enabled and whether the destination address is checked is determined by configuring the PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x). Before enabling the filter, the application program must provide the detection logic with the sample frame and corresponding byte mask. This information is provided by writing the PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x), PHY x Wakeup Filter Configuration Register B (PHY_WUF_CFGB_x), and PHY x Wakeup Filter Byte Mask Registers (PHY_WUF_MASK_x). The starting offset within the frame and the expected CRC-16 for the filter is determined by the Filter Pattern Offset and Filter CRC16 fields, respectively. If remote wakeup mode is enabled, the remote wakeup function checks each frame against the filter and recognizes the frame as a remote wakeup frame if it passes the filter’s address filtering and CRC value match. The pattern offset defines the location of the first byte that should be checked in the frame. The byte mask is a 128-bit field that specifies whether or not each of the 128 contiguous bytes within the frame, beginning with the pattern offset, should be checked. If bit j in the byte mask is set, the detection logic checks the byte (pattern offset + j) in the frame, otherwise byte (pattern offset + j) is ignored. 2015 Microchip Technology Inc. DS00001909A-page 133 LAN9252 At the completion of the CRC-16 checking process, the CRC-16 calculated using the pattern offset and byte mask is compared to the expected CRC-16 value associated with the filter. If a match occurs, a remote wake-up event is signaled. The frame must also pass the FCS check and packet length checking. Table 11-4 indicates the cases that produce a wake-up event. All other cases do not generate a wake-up event. TABLE 11-4: WAKEUP GENERATION CASES Filter Enabled Frame Type CRC Matches Address Match Enabled Any Mcast Enabled Bcast Enabled Frame Address Matches Yes Unicast Yes No X X X Yes Unicast Yes Yes X X Yes Yes Multicast Yes X Yes X X Yes Multicast Yes Yes No X Yes Yes Broadcast Yes X X Yes X As an example, the Host system must perform the following steps to enable the device to detect a Wakeup Frame WoL event: Declare Pattern: 1. 2. Update the PHY x Wakeup Filter Byte Mask Registers (PHY_WUF_MASK_x) to indicate the valid bytes to match. Calculate the CRC-16 value of valid bytes offline and update the PHY x Wakeup Filter Configuration Register B (PHY_WUF_CFGB_x). CRC-16 is calculated as follows: At the start of a frame, CRC-16 is initialized with the value FFFFh. CRC-16 is updated when the pattern offset and mask indicate the received byte is part of the checksum calculation. The following algorithm is used to update the CRC-16 at that time: Let: ^ denote the exclusive or operator. Data [7:0] be the received data byte to be included in the checksum. CRC[15:0] contain the calculated CRC-16 checksum. F0 … F7 be intermediate results, calculated when a data byte is determined to be part of the CRC-16. Calculate: F0 = CRC[15] ^ Data[0] F1 = CRC[14] ^ F0 ^ Data[1] F2 = CRC[13] ^ F1 ^ Data[2] F3 = CRC[12] ^ F2 ^ Data[3] F4 = CRC[11] ^ F3 ^ Data[4] F5 = CRC[10] ^ F4 ^ Data[5] F6 = CRC[09] ^ F5 ^ Data[6] F7 = CRC[08] ^ F6 ^ Data[7] The CRC-32 is updated as follows: CRC[15] = CRC[7] ^ F7 CRC[14] = CRC[6] CRC[13] = CRC[5] CRC[12] = CRC[4] CRC[11] = CRC[3] DS00001909A-page 134 2015 Microchip Technology Inc. LAN9252 CRC[10] = CRC[2] CRC[9] = CRC[1] ^ F0 CRC[8] = CRC[0] ^ F1 CRC[7] = F0 ^ F2 CRC[6] = F1 ^ F3 CRC[5] = F2 ^ F4 CRC[4] = F3 ^ F5 CRC[3] = F4 ^ F6 CRC[2] = F5 ^ F7 CRC[1] = F6 CRC[0] = F7 3. Determine the offset pattern with offset 0 being the first byte of the destination address. Update the offset in the Filter Pattern Offset field of the PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x). Determine Address Matching Conditions: 4. 5. 6. Determine the address matching scheme based on Table 11-4 and update the Filter Broadcast Enable, Filter Any Multicast Enable, and Address Match Enable bits of the PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x) accordingly. If necessary (see step 4), set the desired MAC address to cause the wake event in the PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x), PHY x MAC Receive Address B Register (PHY_RX_ADDRB_x), and PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x). Set the Filter Enable bit of the PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x) to enable the filter. Enable Wakeup Frame Detection: 7. 8. Set the Wakeup Frame Enable (WUEN) bit of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) to enable Wakeup Frame detection. Set bit 8 (WoL event indicator) in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) to enable WoL events. When a match is triggered, the Remote Wakeup Frame Received (WUFR) bit of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) will be set. To provide additional visibility to software, the Filter Triggered bit of the PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x) will be set. 11.2.10 RESETS In addition to the chip-level hardware reset (RST#), EtherCAT system reset, and Power-On Reset (POR), the PHY supports three block specific resets. These are discussed in the following sections. For detailed information on all device resets and the reset sequence refer to Section 6.2, "Resets," on page 38. Note: Only a hardware reset (RST#), Power-On Reset (POR) or EtherCAT system reset will automatically reload the configuration strap values into the PHY registers. The Digital Reset (DIGITAL_RST) bit in the Reset Control Register (RESET_CTL) does not reset the PHYs. For all other PHY resets, PHY registers will need to be manually configured via software. 11.2.10.1 PHY Software Reset via RESET_CTL The PHYs can be reset via the Reset Control Register (RESET_CTL). These bits are self clearing after approximately 102 us. This reset does not reload the configuration strap values into the PHY registers. 11.2.10.2 PHY Software Reset via PHY_BASIC_CTRL_x The PHY can also be reset by setting the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x). This bit is self clearing and will return to 0 after the reset is complete. This reset does not reload the configuration strap values into the PHY registers. 2015 Microchip Technology Inc. DS00001909A-page 135 LAN9252 11.2.10.3 PHY Power-Down Reset After the PHY has returned from a power-down state, a reset of the PHY is automatically generated. The PHY powerdown modes do not reload or reset the PHY registers. Refer to Section 11.2.8, "PHY Power-Down Modes," on page 131 for additional information. 11.2.11 LINK INTEGRITY TEST The device performs the link integrity test as outlined in the IEEE 802.3u (clause 24-15) Link Monitor state diagram. The link status is multiplexed with the 10 Mbps link status to form the Link Status bit in the PHY x Basic Status Register (PHY_BASIC_STATUS_x) and to drive the LINK LED functions. The DSP indicates a valid MLT-3 waveform present on the RXPx and RXNx signals as defined by the ANSI X3.263 TPPMD standard, to the Link Monitor state-machine, using the internal DATA_VALID signal. When DATA_VALID is asserted, the control logic moves into a Link-Ready state and waits for an enable from the auto-negotiation block. When received, the Link-Up state is entered, and the Transmit and Receive logic blocks become active. Should auto-negotiation be disabled, the link integrity logic moves immediately to the Link-Up state when the DATA_VALID is asserted. To allow the line to stabilize, the link integrity logic will wait a minimum of 330 ms from the time DATA_VALID is asserted until the Link-Ready state is entered. Should the DATA_VALID input be negated at any time, this logic will immediately negate the Link signal and enter the Link-Down state. 11.2.12 CABLE DIAGNOSTICS The PHYs provide cable diagnostics which allow for open/short and length detection of the Ethernet cable. The cable diagnostics consist of two primary modes of operation: • Time Domain Reflectometry (TDR) Cable Diagnostics TDR cable diagnostics enable the detection of open or shorted cabling on the TX or RX pair, as well as cable length estimation to the open/short fault. • Matched Cable Diagnostics Matched cable diagnostics enable cable length estimation on 100 Mbps-linked cables. Refer to the following sub-sections for details on proper operation of each cable diagnostics mode. Note: 11.2.12.1 Cable diagnostics are not used for 100BASE-FX mode. Time Domain Reflectometry (TDR) Cable Diagnostics The PHYs provide TDR cable diagnostics which enable the detection of open or shorted cabling on the TX or RX pair, as well as cable length estimation to the open/short fault. To utilize the TDR cable diagnostics, Auto-MDIX and Auto Negotiation must be disabled, and the PHY must be forced to 100 Mbps full-duplex mode. These actions must be performed before setting the TDR Enable bit in the PHY x TDR Control/Status Register (PHY_TDR_CONTROL_STAT_x). With Auto-MDIX disabled, the TDR will test the TX or RX pair selected by register bit 27.13 (Auto-MDIX State (AMDIXSTATE)). Proper cable testing should include a test of each pair. TDR cable diagnostics is not appropriate for 100BASEFX mode. When TDR testing is complete, prior register settings may be restored. Figure 11-5 provides a flow diagram of proper TDR usage. DS00001909A-page 136 2015 Microchip Technology Inc. LAN9252 FIGURE 11-5: TDR USAGE FLOW DIAGRAM Start Disable ANEG and Force 100Mb FullDuplex Write PHY Reg 0: 0x2100 Disable AMDIX and Force MDI (or MDIX) Write PHY Reg 27: 0x8000 (MDI) - OR Write PHY Reg 27: 0xA000 (MDIX) Enable TDR Write PHY Reg 25: 0x8000 Check TDR Control/Status Register Read PHY Reg 25 NO Reg 25.8 == 0 TDR Channel Status Complete? YES Reg 25.8 == 1 Save: TDR Channel Type (Reg 25.10:9) TDR Channel Length (Reg 25.7:0) Repeat Testing in MDIX Mode MDIX Case Tested? YES Done The TDR operates by transmitting pulses on the selected twisted pair within the Ethernet cable (TX in MDI mode, RX in MDIX mode). If the pair being tested is open or shorted, the resulting impedance discontinuity results in a reflected signal that can be detected by the PHY. The PHY measures the time between the transmitted signal and received reflection and indicates the results in the TDR Channel Length field of the PHY x TDR Control/Status Register (PHY_TDR_CONTROL_STAT_x). The TDR Channel Length field indicates the “electrical” length of the cable, and can be multiplied by the appropriate propagation constant in Table 11-5 to determine the approximate physical distance to the fault. Note: The TDR function is typically used when the link is inoperable. However, an active link will drop when operating the TDR. 2015 Microchip Technology Inc. DS00001909A-page 137 LAN9252 Since the TDR relies on the reflected signal of an improperly terminated cable, there are several factors that can affect the accuracy of the physical length estimate. These include: 1. 2. 3. 4. Cable Type (CAT 5, CAT5e, CAT6): The electrical length of each cable type is slightly different due to the twistsper-meter of the internal signal pairs and differences in signal propagation speeds. If the cable type is known, the length estimate can be calculated more accurately by using the propagation constant appropriate for the cable type (see Table 11-5). In many real-world applications the cable type is unknown, or may be a mix of different cable types and lengths. In this case, use the propagation constant for the “unknown” cable type. TX and RX Pair: For each cable type, the EIA standards specify different twist rates (twists-per-meter) for each signal pair within the Ethernet cable. This results in different measurements for the RX and TX pair. Actual Cable Length: The difference between the estimated cable length and actual cable length grows as the physical cable length increases, with the most accurate results at less than approximately 100 m. Open/Short Case: The Open and Shorted cases will return different TDR Channel Length values (electrical lengths) for the same physical distance to the fault. Compensation for this is achieved by using different propagation constants to calculate the physical length of the cable. For the Open case, the estimated distance to the fault can be calculated as follows: Distance to Open fault in meters TDR Channel Length * POPEN Where: POPEN is the propagation constant selected from Table 11-5 For the Shorted case, the estimated distance to the fault can be calculated as follows: Distance to Open fault in meters TDR Channel Length * PSHORT Where: PSHORT is the propagation constant selected from Table 11-5 TABLE 11-5: TDR PROPAGATION CONSTANTS TDR Propagation Constant Cable Type Unknown CAT 6 CAT 5E CAT 5 POPEN 0.769 0.745 0.76 0.85 PSHORT 0.793 0.759 0.788 0.873 The typical cable length measurement margin of error for Open and Shorted cases is dependent on the selected cable type and the distance of the open/short from the device. Table 11-6 and Table 11-7 detail the typical measurement error for Open and Shorted cases, respectively. TABLE 11-6: TYPICAL MEASUREMENT ERROR FOR OPEN CABLE (+/- METERS) Selected Propagation Constant Physical Distance to Fault POPEN = Unknown POPEN = CAT 6 CAT 6 Cable, 0-100 m 9 6 CAT 5E Cable, 0-100 m 5 CAT 5 Cable, 0-100 m 13 CAT 6 Cable, 101-160 m 14 CAT 5E Cable, 101-160 m 8 CAT 5 Cable, 101-160 m 20 DS00001909A-page 138 POPEN = CAT 5E POPEN = CAT 5 5 3 6 6 6 2015 Microchip Technology Inc. LAN9252 TABLE 11-7: TYPICAL MEASUREMENT ERROR FOR SHORTED CABLE (+/- METERS) SELECTED PROPAGATION CONSTANT PHYSICAL DISTANCE TO FAULT 11.2.12.2 PSHORT = Unknown PSHORT = CAT 6 CAT 6 Cable, 0-100 m 8 5 CAT 5E Cable, 0-100 m 5 CAT 5 Cable, 0-100 m 11 CAT 6 Cable, 101-160 m 14 CAT 5E Cable, 101-160 m 7 CAT 5 Cable, 101-160 m 11 PSHORT = CAT 5E PSHORT = CAT 5 5 2 6 6 3 Matched Cable Diagnostics Matched cable diagnostics enable cable length estimation on 100 Mbps-linked cables of up to 120 meters. If there is an active 100 Mb link, the approximate distance to the link partner can be estimated using the PHY x Cable Length Register (PHY_CABLE_LEN_x). If the cable is properly terminated, but there is no active 100 Mb link (the link partner is disabled, nonfunctional, the link is at 10 Mb, etc.), the cable length cannot be estimated and the PHY x Cable Length Register (PHY_CABLE_LEN_x) should be ignored. The estimated distance to the link partner can be determined via the Cable Length (CBLN) field of the PHY x Cable Length Register (PHY_CABLE_LEN_x) using the lookup table provided in Table 11-8. The typical cable length measurement margin of error for a matched cable case is +/- 20 m. The matched cable length margin of error is consistent for all cable types from 0 to 120 m. TABLE 11-8: MATCH CASE ESTIMATED CABLE LENGTH (CBLN) LOOKUP CBLN Field Value Estimated Cable Length 0-3 0 4 6 5 17 6 27 7 38 8 49 9 59 10 70 11 81 12 91 13 102 14 113 15 123 2015 Microchip Technology Inc. DS00001909A-page 139 LAN9252 Note: 11.2.13 For a properly terminated cable (Match case), there is no reflected signal. In this case, the TDR Channel Length field is invalid and should be ignored. LOOPBACK OPERATION The PHYs may be configured for near-end loopback and connector loopback. These loopback modes are detailed in the following subsections. 11.2.13.1 Near-end Loopback Near-end loopback mode sends the digital transmit data back out the receive data signals for testing purposes, as indicated by the blue arrows in Figure 11-6. The near-end loopback mode is enabled by setting the Loopback (PHY_LOOPBACK) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) to “1”. A large percentage of the digital circuitry is operational in near-end loopback mode because data is routed through the PCS and PMA layers into the PMD sublayer before it is looped back. The COL signal will be inactive in this mode, unless Collision Test Mode (PHY_COL_TEST) is enabled in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x). The transmitters are powered down regardless of the state of the internal MII TXEN signal. FIGURE 11-6: NEAR-END LOOPBACK BLOCK DIAGRAM 10/100 Ethernet MAC TXD X RXD Digital 11.2.13.2 Analog X TX RX XFMR CAT-5 Connector Loopback The device maintains reliable transmission over very short cables and can be tested in a connector loopback as shown in Figure 11-7. An RJ45 loopback cable can be used to route the transmit signals from the output of the transformer back to the receiver inputs. The loopback works at both 10 and 100 Mbps. FIGURE 11-7: 10/100 Ethernet MAC CONNECTION LOOPBACK BLOCK DIAGRAM TXD TX RXD RX Digital Analog XFMR 1 2 3 4 5 6 7 8 RJ45 Loopback Cable. Created by connecting pin 1 to pin 3 and connecting pin 2 to pin 6. DS00001909A-page 140 2015 Microchip Technology Inc. LAN9252 11.2.14 100BASE-FX OPERATION When set for 100BASE-FX operation, the scrambler and MTL-3 blocks are disable and the analog RX and TX pins are changed to differential LVPECL pins and connect through external terminations to the external Fiber transceiver. The differential LVPECL pins support a signal voltage range compatible with SFF (LVPECL) and SFP (reduced LVPECL) type transceivers. While in 100BASE-FX operation, the quality of the receive signal is provided by the external transceiver as either an open-drain, CMOS level, Loss of Signal (SFP) or a LVPECL Signal Detect (SFF). 11.2.14.1 100BASE-FX Far End Fault Indication Since Auto-Negotiation is not specified for 100BASE-FX, its Remote Fault capability is unavailable. Instead, 100BASEFX provides an optional Far-End Fault function. When no signal is being received, the Far-End Fault feature transmits a special Far-End Fault Indication to its far-end peer. The Far-End Fault Indication is sent only when a physical error condition is sensed on the receive channel. The Far-End Fault Indication is comprised of three or more repeating cycles, each of 84 ONEs followed by a single ZERO. This signal is sent in-band and is readily detectable but is constructed so as to not satisfy the 100BASE-X carrier sense criterion. Far-End Fault is implemented through the Far-End Fault Generate, Far-End Fault Detect, and the Link Monitor processes. The Far-End Fault Generate process is responsible for sensing a receive channel failure (signal_status=OFF) and transmitting the Far-End Fault Indication in response. The transmission of the Far-End Fault Indication may start or stop at any time depending only on signal_status. The Far-End Fault Detect process continuously monitors the RX process for the Far-End Fault Indication. Detection of the Far-End Fault Indication disables the station by causing the Link Monitor process to de-assert link_status, which in turn causes the station to source IDLEs. Far-End Fault is enabled by default while in 100BASE-FX mode via the Far End Fault Indication Enable (FEFI_EN) of the PHY x Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x). 11.2.14.2 100BASE-FX Enable and LOS/SD Selection 100BASE-FX operation is enabled by the use of the FX mode straps (fx_mode_strap_1 and fx_mode_strap_2) and is reflected in the 100BASE-FX Mode (FX_MODE) bit in the PHY x Special Modes Register (PHY_SPECIAL_MODES_x). Loss of Signal mode is selected for both PHYs by the three level FXLOSEN strap input pin. The three levels correspond to Loss of Signal mode for a) neither PHY (less than 1 V (typ.)), b) PHY A (greater than 1 V (typ.) but less than 2 V (typ.)) or c) both PHYs (greater than 2 V (typ.)). It is not possible to select Loss of Signal mode for only PHY B. If Loss of Signal mode is not selected, then Signal Detect mode is selected, independently, by the FXSDENA or FXSDENB strap input pin. When greater than 1 V (typ.), Signal Detect mode is enabled, when less than 1 V (typ.), copper twisted pair is enabled. Note: The FXSDENA strap input pin is shared with the FXSDA pin and the FXSDENB strap input pin is shared with the FXSDB pin. As such, the LVPECL levels ensure that the input is greater than 1 V (typ.) and that Signal Detect mode is selected. When TP copper is desired, the Signal Detect input function is not required and the pin should be set to 0 V. Care must be taken such that an non-powered or disabled transceiver does not load the Signal Detect input below the valid LVPECL level. Table 11-9 and Table 11-10 summarize the selections. TABLE 11-9: 100BASE-FX LOS, SD AND TP COPPER SELECTION PHY A FXLOSEN FXSDENA PHY Mode <1 V (typ.) <1 V (typ.) TP copper >1 V (typ.) 100BASE-FX Signal Detect n/a 100BASE-FX LOS >1 V (typ.) 2015 Microchip Technology Inc. DS00001909A-page 141 LAN9252 TABLE 11-10: 100BASE-FX LOS, SD AND TP COPPER SELECTION PHY B FXLOSEN FXSDENB PHY Mode <1 V (typ.) <1 V (typ.) TP copper >1 V (typ.) 100BASE-FX Signal Detect n/a 100BASE-FX LOS >2 V (typ.) 11.2.15 REQUIRED ETHERNET MAGNETICS (100BASE-TX) The magnetics selected for use with the device should be an Auto-MDIX style magnetic, which is widely available from several vendors. Please review the SMSC/Microchip Application note 8.13 “Suggested Magnetics” for the latest qualified and suggested magnetics. A list of vendors and part numbers are provided within the application note. 11.2.16 PHY REGISTERS PHYs A and B are comparable in functionality and have an identical set of non-memory mapped registers. These registers are indirectly accessed through the MII Management Control/Status Register, PHY Address Register, PHY Register Address Register, PHY DATA Register, MII Management ECAT Access State Register, and MII Management ECAT Access State Register. Because PHY A and B registers are functionally identical, their register descriptions have been consolidated. A lowercase “x” has been appended to the end of each PHY register name in this section, where “x” hold be replaced with “A” or “B” for the PHY A or PHY B registers respectively. In some instances, a “1” or a “2” may be appropriate instead. A list of the MII serial accessible Control and Status registers and their corresponding register index numbers is included in Table 11-11. Each individual PHY is assigned a unique PHY address as detailed in Section 11.1.1, "PHY Addressing," on page 120. In addition to the MII serial accessible Control and Status registers, a set of indirectly accessible registers provides support for the IEEE 802.3 Section 45.2 MDIO Manageable Device (MMD) Registers. A list of these registers and their corresponding register index numbers is included in Table 11-14. Control and Status Registers Table 11-11 provides a list of supported registers. Register details, including bit definitions, are provided in the following subsections. Unless otherwise specified, reserved fields must be written with zeros if the register is written. TABLE 11-11: PHY A AND B MII SERIALLY ACCESSIBLE CONTROL AND STATUS REGISTERS Index Register Name (SYMBOL) Group 0 PHY x Basic Control Register (PHY_BASIC_CONTROL_x) Basic 1 PHY x Basic Status Register (PHY_BASIC_STATUS_x) Basic 2 PHY x Identification MSB Register (PHY_ID_MSB_x) Extended 3 PHY x Identification LSB Register (PHY_ID_LSB_x) Extended 4 PHY x Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) Extended 5 PHY x Auto-Negotiation Link Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x) Extended 6 PHY x Auto-Negotiation Expansion Register (PHY_AN_EXP_x) Extended 7 PHY x Auto Negotiation Next Page TX Register (PHY_AN_NP_TX_x) Extended 8 PHY x Auto Negotiation Next Page RX Register (PHY_AN_NP_RX_x) Extended DS00001909A-page 142 2015 Microchip Technology Inc. LAN9252 TABLE 11-11: PHY A AND B MII SERIALLY ACCESSIBLE CONTROL AND STATUS REGISTERS Index Register Name (SYMBOL) Group 13 PHY x MMD Access Control Register (PHY_MMD_ACCESS) Extended 14 PHY x MMD Access Address/Data Register (PHY_MMD_ADDR_DATA) Extended 16 PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG_x) Vendorspecific 17 PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) Vendorspecific 18 PHY x Special Modes Register (PHY_SPECIAL_MODES_x) Vendorspecific 24 PHY x TDR Patterns/Delay Control Register (PHY_TDR_PAT_DELAY_x) Vendorspecific 25 PHY x TDR Control/Status Register (PHY_TDR_CONTROL_STAT_x) Vendorspecific 26 PHY x Symbol Error Counter Register Vendorspecific 27 PHY x Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x) Vendorspecific 28 PHY x Cable Length Register (PHY_CABLE_LEN_x) Vendorspecific 29 PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) Vendorspecific 30 PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) Vendorspecific 31 PHY x Special Control/Status Register (PHY_SPECIAL_CONTROL_STATUS_x) Vendorspecific 2015 Microchip Technology Inc. DS00001909A-page 143 LAN9252 11.2.16.1 PHY x Basic Control Register (PHY_BASIC_CONTROL_x) Index (decimal): 0 Size: 16 bits This read/write register is used to configure the PHY. Bits 15 Description Soft Reset (PHY_SRST) When set, this bit resets all the PHY registers to their default state, except those marked as NASR type. This bit is self clearing. Type Default R/W SC 0b R/W 0b R/W 1b R/W Note 6 R/W 0b 0: Normal operation 1: Reset 14 Loopback (PHY_LOOPBACK) This bit enables/disables the loopback mode. When enabled, transmissions are not sent to network. Instead, they are looped back into the PHY. 0: Loopback mode disabled (normal operation) 1: Loopback mode enabled 13 Speed Select LSB (PHY_SPEED_SEL_LSB) This bit is used to set the speed of the PHY when the Auto-Negotiation Enable (PHY_AN) bit is disabled. 0: 10 Mbps 1: 100 Mbps 12 Auto-Negotiation Enable (PHY_AN) This bit enables/disables Auto-Negotiation. When enabled, the Speed Select LSB (PHY_SPEED_SEL_LSB) and Duplex Mode (PHY_DUPLEX) bits are overridden. This bit is forced to a 0 if the 100BASE-FX Mode (FX_MODE) bit of the PHY x Special Modes Register (PHY_SPECIAL_MODES_x) is a high. 0: Auto-Negotiation disabled 1: Auto-Negotiation enabled 11 Power Down (PHY_PWR_DWN) This bit controls the power down mode of the PHY. 0: Normal operation 1: General power down mode 10 RESERVED RO - 9 Restart Auto-Negotiation (PHY_RST_AN) When set, this bit restarts the Auto-Negotiation process. R/W SC 0b 0: Normal operation 1: Auto-Negotiation restarted DS00001909A-page 144 2015 Microchip Technology Inc. LAN9252 Bits 8 Description Duplex Mode (PHY_DUPLEX) This bit is used to set the duplex when the Auto-Negotiation Enable (PHY_AN) bit is disabled. Type Default R/W 1b R/W 0b RO - 0: Half Duplex 1: Full Duplex 7 Collision Test Mode (PHY_COL_TEST) This bit enables/disables the collision test mode of the PHY. When set, the collision signal is active during transmission. It is recommended that this feature be used only in loopback mode. 0: Collision test mode disabled 1: Collision test mode enabled 6:0 RESERVED Note 6: This field defaults to a 0 if in 100BASE-FX mode or to a 1 otherwise. EtherCAT always uses Auto-Negotiate, 100 Mbps, Full-Duplex. 2015 Microchip Technology Inc. DS00001909A-page 145 LAN9252 11.2.16.2 PHY x Basic Status Register (PHY_BASIC_STATUS_x) Index (decimal): 1 Size: 16 bits This register is used to monitor the status of the PHY. Bits 15 Description 100BASE-T4 This bit displays the status of 100BASE-T4 compatibility. Type Default RO 0b RO 1b RO 1b RO 1b RO 1b RO 0b RO 0b RO 0b 0: PHY not able to perform 100BASE-T4 1: PHY able to perform 100BASE-T4 14 100BASE-X Full Duplex This bit displays the status of 100BASE-X full duplex compatibility. 0: PHY not able to perform 100BASE-X full duplex 1: PHY able to perform 100BASE-X full duplex 13 100BASE-X Half Duplex This bit displays the status of 100BASE-X half duplex compatibility. 0: PHY not able to perform 100BASE-X half duplex 1: PHY able to perform 100BASE-X half duplex 12 10BASE-T Full Duplex This bit displays the status of 10BASE-T full duplex compatibility. 0: PHY not able to perform 10BASE-T full duplex 1: PHY able to perform 10BASE-T full duplex 11 10BASE-T Half Duplex (typ.) This bit displays the status of 10BASE-T half duplex compatibility. 0: PHY not able to perform 10BASE-T half duplex 1: PHY able to perform 10BASE-T half duplex 10 100BASE-T2 Full Duplex This bit displays the status of 100BASE-T2 full duplex compatibility. 0: PHY not able to perform 100BASE-T2 full duplex 1: PHY able to perform 100BASE-T2 full duplex 9 100BASE-T2 Half Duplex This bit displays the status of 100BASE-T2 half duplex compatibility. 0: PHY not able to perform 100BASE-T2 half duplex 1: PHY able to perform 100BASE-T2 half duplex 8 Extended Status This bit displays whether extended status information is in register 15 (per IEEE 802.3 clause 22.2.4). 0: No extended status information in Register 15 1: Extended status information in Register 15 DS00001909A-page 146 2015 Microchip Technology Inc. LAN9252 Bits 7 Description Unidirectional Ability This bit indicates whether the PHY is able to transmit regardless of whether the PHY has determined that a valid link has been established. Type Default RO 0b RO 0b RO 0b RO/LH 0b RO 1b RO/LL 0b RO/LH 0b RO 1b 0: Can only transmit when a valid link has been established 1: Can transmit regardless 6 MF Preamble Suppression This bit indicates whether the PHY accepts management frames with the preamble suppressed. 0: Management frames with preamble suppressed not accepted 1: Management frames with preamble suppressed accepted 5 Auto-Negotiation Complete This bit indicates the status of the Auto-Negotiation process. 0: Auto-Negotiation process not completed 1: Auto-Negotiation process completed 4 Remote Fault This bit indicates if a remote fault condition has been detected. 0: No remote fault condition detected 1: Remote fault condition detected 3 Auto-Negotiation Ability This bit indicates the PHY’s Auto-Negotiation ability. 0: PHY is unable to perform Auto-Negotiation 1: PHY is able to perform Auto-Negotiation 2 Link Status This bit indicates the status of the link. 0: Link is down 1: Link is up 1 Jabber Detect This bit indicates the status of the jabber condition. 0: No jabber condition detected 1: Jabber condition detected 0 Extended Capability This bit indicates whether extended register capability is supported. 0: Basic register set capabilities only 1: Extended register set capabilities 2015 Microchip Technology Inc. DS00001909A-page 147 LAN9252 11.2.16.3 PHY x Identification MSB Register (PHY_ID_MSB_x) Index (decimal): 2 Size: 16 bits This read/write register contains the MSB of the Organizationally Unique Identifier (OUI) for the PHY. The LSB of the PHY OUI is contained in the PHY x Identification LSB Register (PHY_ID_LSB_x). Bits 15:0 Description PHY ID This field is assigned to the 3rd through 18th bits of the OUI, respectively (OUI = 00800Fh). DS00001909A-page 148 Type Default R/W 0007h 2015 Microchip Technology Inc. LAN9252 11.2.16.4 PHY x Identification LSB Register (PHY_ID_LSB_x) Index (decimal): 3 Size: 16 bits This read/write register contains the LSB of the Organizationally Unique Identifier (OUI) for the PHY. The MSB of the PHY OUI is contained in the PHY x Identification MSB Register (PHY_ID_MSB_x). Bits 15:10 Description Type PHY ID This field is assigned to the 19th through 24th bits of the PHY OUI, respectively. (OUI = 00800Fh). R/W 9:4 Model Number This field contains the 6-bit manufacturer’s model number of the PHY. R/W 3:0 Revision Number This field contain the 4-bit manufacturer’s revision number of the PHY. R/W Note: Default C140h The default value of the Revision Number field may vary dependent on the silicon revision number. 2015 Microchip Technology Inc. DS00001909A-page 149 LAN9252 11.2.16.5 PHY x Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) Index (decimal): 4 Size: 16 bits This read/write register contains the advertised ability of the PHY and is used in the Auto-Negotiation process with the link partner. Bits 15 Description Next Page Type Default R/W 0b 0 = No next page ability 1 = Next page capable 14 RESERVED RO - 13 Remote Fault This bit determines if remote fault indication will be advertised to the link partner. R/W 0b R/W 0b R/W 0b R/W 0b 0: Remote fault indication not advertised 1: Remote fault indication advertised 12 Extended Next Page Note: 11 This bit should be written as 0. Asymmetric Pause This bit determines the advertised asymmetric pause capability. 0: No Asymmetric PAUSE toward link partner advertised 1: Asymmetric PAUSE toward link partner advertised 10 Symmetric Pause This bit determines the advertised symmetric pause capability. 0: No Symmetric PAUSE toward link partner advertised 1: Symmetric PAUSE toward link partner advertised 9 RESERVED RO - 8 100BASE-X Full Duplex This bit determines the advertised 100BASE-X full duplex capability. R/W 1b R/W 0b R/W 0b 0: 100BASE-X full duplex ability not advertised 1: 100BASE-X full duplex ability advertised 7 100BASE-X Half Duplex This bit determines the advertised 100BASE-X half duplex capability. 0: 100BASE-X half duplex ability not advertised 1: 100BASE-X half duplex ability advertised 6 10BASE-T Full Duplex This bit determines the advertised 10BASE-T full duplex capability. 0: 10BASE-T full duplex ability not advertised 1: 10BASE-T full duplex ability advertised DS00001909A-page 150 2015 Microchip Technology Inc. LAN9252 Bits 5 Description 10BASE-T Half Duplex This bit determines the advertised 10BASE-T half duplex capability. Type Default R/W 0b R/W 00001b 0: 10BASE-T half duplex ability not advertised 1: 10BASE-T half duplex ability advertised 4:0 Selector Field This field identifies the type of message being sent by Auto-Negotiation. 00001: IEEE 802.3 2015 Microchip Technology Inc. DS00001909A-page 151 LAN9252 11.2.16.6 PHY x Auto-Negotiation Link Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x) Index (decimal): 5 Size: 16 bits This read-only register contains the advertised ability of the link partner’s PHY and is used in the Auto-Negotiation process between the link partner and the PHY. Bits 15 Description Next Page This bit indicates the link partner PHY page capability. Type Default RO 0b RO 0b RO 0b RO 0b RO 0b RO 0b RO 0b RO 0b 0: Link partner PHY does not advertise next page capability 1: Link partner PHY advertises next page capability 14 Acknowledge This bit indicates whether the link code word has been received from the partner. 0: Link code word not yet received from partner 1: Link code word received from partner 13 Remote Fault This bit indicates whether a remote fault has been detected. 0: No remote fault 1: Remote fault detected 12 Extended Next Page 0: Link partner PHY does not advertise extended next page capability 1: Link partner PHY advertises extended next page capability 11 Asymmetric Pause This bit indicates the link partner PHY asymmetric pause capability. 0: No Asymmetric PAUSE toward link partner 1: Asymmetric PAUSE toward link partner 10 Pause This bit indicates the link partner PHY symmetric pause capability. 0: No Symmetric PAUSE toward link partner 1: Symmetric PAUSE toward link partner 9 100BASE-T4 This bit indicates the link partner PHY 100BASE-T4 capability. 0: 100BASE-T4 ability not supported 1: 100BASE-T4 ability supported 8 100BASE-X Full Duplex This bit indicates the link partner PHY 100BASE-X full duplex capability. 0: 100BASE-X full duplex ability not supported 1: 100BASE-X full duplex ability supported DS00001909A-page 152 2015 Microchip Technology Inc. LAN9252 Bits 7 Description 100BASE-X Half Duplex This bit indicates the link partner PHY 100BASE-X half duplex capability. Type Default RO 0b RO 0b RO 0b RO 00001b 0: 100BASE-X half duplex ability not supported 1: 100BASE-X half duplex ability supported 6 10BASE-T Full Duplex This bit indicates the link partner PHY 10BASE-T full duplex capability. 0: 10BASE-T full duplex ability not supported 1: 10BASE-T full duplex ability supported 5 10BASE-T Half Duplex This bit indicates the link partner PHY 10BASE-T half duplex capability. 0: 10BASE-T half duplex ability not supported 1: 10BASE-T half duplex ability supported 4:0 Selector Field This field identifies the type of message being sent by Auto-Negotiation. 00001: IEEE 802.3 2015 Microchip Technology Inc. DS00001909A-page 153 LAN9252 11.2.16.7 PHY x Auto-Negotiation Expansion Register (PHY_AN_EXP_x) Index (decimal): 6 Size: 16 bits This read/write register is used in the Auto-Negotiation process between the link partner and the PHY. Bits 15:7 6 Description Type Default RESERVED RO - Receive Next Page Location Able RO 1b RO 1b RO/LH 0b RO 0b RO 1b RO/LH 0b RO 0b 0 = Received next page storage location is not specified by bit 6.5 1 = Received next page storage location is specified by bit 6.5 5 Received Next Page Storage Location 0 = Link partner next pages are stored in the PHY x Auto-Negotiation Link Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x) (PHY register 5) 1 = Link partner next pages are stored in the PHY x Auto Negotiation Next Page RX Register (PHY_AN_NP_RX_x) (PHY register 8) 4 Parallel Detection Fault This bit indicates whether a Parallel Detection Fault has been detected. 0: A fault hasn’t been detected via the Parallel Detection function 1: A fault has been detected via the Parallel Detection function 3 Link Partner Next Page Able This bit indicates whether the link partner has next page ability. 0: Link partner does not contain next page capability 1: Link partner contains next page capability 2 Next Page Able This bit indicates whether the local device has next page ability. 0: Local device does not contain next page capability 1: Local device contains next page capability 1 Page Received This bit indicates the reception of a new page. 0: A new page has not been received 1: A new page has been received 0 Link Partner Auto-Negotiation Able This bit indicates the Auto-Negotiation ability of the link partner. 0: Link partner is not Auto-Negotiation able 1: Link partner is Auto-Negotiation able DS00001909A-page 154 2015 Microchip Technology Inc. LAN9252 11.2.16.8 PHY x Auto Negotiation Next Page TX Register (PHY_AN_NP_TX_x) Index (In Decimal): Bits 7 Description Size: 16 bits Type Default 15 Next Page 0 = No next page ability 1 = Next page capable R/W 0b 14 RESERVED RO - 13 Message Page 0 = Unformatted page 1 = Message page R/W 1b 12 Acknowledge 2 0 = Device cannot comply with message. 1 = Device will comply with message. R/W 0b 11 Toggle 0 = Previous value was HIGH. 1 = Previous value was LOW. RO 0b Message Code Message/Unformatted Code Field R/W 000 0000 0001b 10:0 2015 Microchip Technology Inc. DS00001909A-page 155 LAN9252 11.2.16.9 PHY x Auto Negotiation Next Page RX Register (PHY_AN_NP_RX_x) Index (In Decimal): BITS 15 8 Size: DESCRIPTION Next Page 16 bits TYPE DEFAULT RO 0b RO 0b RO 0b RO 0b RO 0b RO 000 0000 0000b 0 = No next page ability 1 = Next page capable 14 Acknowledge 0 = Link code word not yet received from partner 1 = Link code word received from partner 13 Message Page 0 = Unformatted page 1 = Message page 12 Acknowledge 2 0 = Device cannot comply with message. 1 = Device will comply with message. 11 Toggle 0 = Previous value was HIGH. 1 = Previous value was LOW. 10:0 Message Code Message/Unformatted Code Field DS00001909A-page 156 2015 Microchip Technology Inc. LAN9252 11.2.16.10 PHY x MMD Access Control Register (PHY_MMD_ACCESS) Index (In Decimal): 13 Size: 16 bits This register in conjunction with the PHY x MMD Access Address/Data Register (PHY_MMD_ADDR_DATA) provides indirect access to the MDIO Manageable Device (MMD) registers. Refer to the MDIO Manageable Device (MMD) Registers on page 175 for additional details. Bits 15:14 Description MMD Function This field is used to select the desired MMD function: Type Default R/W 00b 00 = Address 01 = Data, no post increment 10 = RESERVED 11 = RESERVED 13:5 RESERVED RO - 4:0 MMD Device Address (DEVAD) This field is used to select the desired MMD device address. (3 = PCS, 7 = auto-negotiation) R/W 0h 2015 Microchip Technology Inc. DS00001909A-page 157 LAN9252 11.2.16.11 PHY x MMD Access Address/Data Register (PHY_MMD_ADDR_DATA) Index (In Decimal): 14 Size: 16 bits This register in conjunction with the PHY x MMD Access Control Register (PHY_MMD_ACCESS) provides indirect access to the MDIO Manageable Device (MMD) registers. Refer to the MDIO Manageable Device (MMD) Registers on page 175 for additional details. Bits Description Type Default 15:0 MMD Register Address/Data If the MMD Function field of the PHY x MMD Access Control Register (PHY_MMD_ACCESS) is “00”, this field is used to indicate the MMD register address to read/write of the device specified in the MMD Device Address (DEVAD) field. Otherwise, this register is used to read/write data from/to the previously specified MMD address. R/W 0000h DS00001909A-page 158 2015 Microchip Technology Inc. LAN9252 11.2.16.12 PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG_x) Index (decimal): 16 Size: 16 bits This register is used to Enable EEE functionality and control NLP pulse generation and the Auto-MDIX Crossover Time of the PHY. Bits Description Type Default 15 EDPD TX NLP Enable Enables the generation of a Normal Link Pulse (NLP) with a selectable interval while in Energy Detect Power-Down. 0=disabled, 1=enabled. R/W NASR Note 7 0b R/W NASR Note 7 00b R/W NASR Note 7 0b R/W NASR Note 7 00b RO - R/W NASR Note 7 0b The Energy Detect Power-Down (EDPWRDOWN) bit in the PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) needs to be set in order to enter Energy Detect Power-Down mode and the PHY needs to be in the Energy Detect Power-Down state in order for this bit to generate the NLP. The EDPD TX NLP Independent Mode bit of this register also needs to be set when setting this bit. 14:13 EDPD TX NLP Interval Timer Select Specifies how often a NLP is transmitted while in the Energy Detect PowerDown state. 00b: 1 s 01b: 768 ms 10b: 512 ms 11b: 256 ms 12 EDPD RX Single NLP Wake Enable When set, the PHY will wake upon the reception of a single Normal Link Pulse. When clear, the PHY requires two link pluses, within the interval specified below, in order to wake up. Single NLP Wake Mode is recommended when connecting to “Green” network devices. 11:10 EDPD RX NLP Max Interval Detect Select These bits specify the maximum time between two consecutive Normal Link Pulses in order for them to be considered a valid wake up signal. 00b: 64 ms 01b: 256 ms 10b: 512 ms 11b: 1 s 9:4 3 RESERVED EDPD TX NLP Independent Mode When set, each PHY port independently detects power down for purposes of the EDPD TX NLP function (via the EDPD TX NLP Enable bit of this register). When cleared, both ports need to be in a power-down state in order to generate TX NLPs during energy detect power-down. Normally set this bit when setting EDPD TX NLP Enable. 2015 Microchip Technology Inc. DS00001909A-page 159 LAN9252 Bits Description 2 RESERVED 1 EDPD Extend Crossover When in Energy Detect Power-Down (EDPD) mode (Energy Detect PowerDown (EDPWRDOWN) = 1), setting this bit to 1 extends the crossover time by 2976 ms. Type Default RO - R/W NASR Note 7 0b R/W NASR Note 7 1b 0 = Crossover time extension disabled 1 = Crossover time extension enabled (2976 ms) 0 Extend Manual 10/100 Auto-MDIX Crossover Time When Auto-Negotiation is disabled, setting this bit extends the Auto-MDIX crossover time by 32 sample times (32 * 62 ms = 1984 ms). This allows the link to be established with a partner PHY that has Auto-Negotiation enabled. When Auto-Negotiation is enabled, this bit has no affect. It is recommended that this bit is set when disabling AN with Auto-MDIX enabled. Note 7: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Register (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set. DS00001909A-page 160 2015 Microchip Technology Inc. LAN9252 11.2.16.13 PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) Index (decimal): 17 Size: 16 bits This read/write register is used to control and monitor various PHY configuration options. Bits Type Default RESERVED RO - Energy Detect Power-Down (EDPWRDOWN) This bit controls the Energy Detect Power-Down mode. R/W 0b RO - R/W NASR Note 8 0b RESERVED RO - 1 Energy On (ENERGYON) Indicates whether energy is detected. This bit transitions to “0” if no valid energy is detected within 256 ms (1500 ms if auto-negotiation is enabled). It is reset to “1” by a hardware reset and by a software reset if auto-negotiation was enabled or will be enabled via strapping. Refer to Section 11.2.8.2, "Energy Detect Power-Down," on page 131 for additional information. RO 1b 0 RESERVED RO - 15:14 13 Description 0: Energy Detect Power-Down is disabled 1: Energy Detect Power-Down is enabled Note: 12:7 6 5:2 When in EDPD mode, the device’s NLP characteristics can be modified via the PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG_x). RESERVED ALTINT Alternate Interrupt Mode: 0 = Primary interrupt system enabled (Default) 1 = Alternate interrupt system enabled Refer to Section 11.2.7, "PHY Interrupts," on page 128 for additional information. Note 8: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Register (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set. 2015 Microchip Technology Inc. DS00001909A-page 161 LAN9252 11.2.16.14 PHY x Special Modes Register (PHY_SPECIAL_MODES_x) Index (decimal): 18 Size: 16 bits This read/write register is used to control the special modes of the PHY. Bits Description 15:11 10 RESERVED 100BASE-FX Mode (FX_MODE) This bit enables 100BASE-FX Mode Note: FX_MODE cannot properly be changed with this bit. This bit must always be written with its current value. Device strapping must be used to set the desired mode. 9:8 RESERVED 7:5 PHY Mode (MODE[2:0]) This field controls the PHY mode of operation. Refer to Table 11-12 for a definition of each mode. Note: 4:0 Default RO - R/W NASR Note 9 Note 10 RO - R/W NASR Note 9 Note 11 R/W NASR Note 9 Note 12 This field should be written with its read value. PHY Address (PHYADD) The PHY Address field determines the MMI address to which the PHY will respond and is also used for initialization of the cipher (scrambler) key. Each PHY must have a unique address. Refer to Section 11.1.1, "PHY Addressing," on page 120 for additional information. Note: Type No check is performed to ensure that this address is unique from the other PHY addresses (PHY A, PHY B). Note 9: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Register (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set. Note 10: The default value of this bit is determined by the Fiber Enable strap (fx_mode_strap_1 for PHY A, fx_mode_strap_2 for PHY B). Note 11: This field defaults to 100b when in 100BASE-TX mode (since EtherCAT only uses Auto-Negotiate, 100 Mbps, Full-Duplex) or to 011b when in 100BASE-FX mode (since EtherCAT only uses 100 Mbps, FullDuplex). Note 12: The default value of this field is determined per Section 11.1.1, "PHY Addressing," on page 120. TABLE 11-12: MODE[2:0] DEFINITIONS MODE[2:0] Mode Definitions 000 10BASE-T Half Duplex. Auto-Negotiation disabled. 001 10BASE-T Full Duplex. Auto-Negotiation disabled. 010 100BASE-TX or 100BASE-FX Half Duplex. Auto-Negotiation disabled. CRS is active during Transmit & Receive. 011 100BASE-TX or 100BASE-FX Full Duplex. Auto-Negotiation disabled. CRS is active during Receive. DS00001909A-page 162 2015 Microchip Technology Inc. LAN9252 TABLE 11-12: MODE[2:0] DEFINITIONS (CONTINUED) MODE[2:0] Mode Definitions 100 100BASE-TX Full Duplex is advertised. Auto-Negotiation enabled. CRS is active during Receive. 101 RESERVED 110 Power Down mode. 111 All capable. Auto-Negotiation enabled. 2015 Microchip Technology Inc. DS00001909A-page 163 LAN9252 11.2.16.15 PHY x TDR Patterns/Delay Control Register (PHY_TDR_PAT_DELAY_x) Index (In Decimal): Bits 24 Size: 16 bits Type Default R/W NASR Note 13 1b TDR Line Break Counter When TDR Delay In is 1, this field specifies the increase in line break time in increments of 256 ms, up to 2 seconds. R/W NASR Note 13 001b 11:6 TDR Pattern High This field specifies the data pattern sent in TDR mode for the high cycle. R/W NASR Note 13 101110b 5:0 TDR Pattern Low This field specifies the data pattern sent in TDR mode for the low cycle. R/W NASR Note 13 011101b 15 Description TDR Delay In 0 = Line break time is 2 ms. 1 = The device uses TDR Line Break Counter to increase the line break time before starting TDR. 14:12 Note 13: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Register (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set. DS00001909A-page 164 2015 Microchip Technology Inc. LAN9252 11.2.16.16 PHY x TDR Control/Status Register (PHY_TDR_CONTROL_STAT_x) Index (In Decimal): Bits 15 25 Size: 16 bits Description TDR Enable 0 = TDR mode disabled 1 = TDR mode enabled Note: 14 Type Default R/W NASR SC Note 14 0b R/W NASR Note 14 0b RO - This bit self clears when TDR completes (TDR Channel Status goes high) TDR Analog to Digital Filter Enable 0 = TDR analog to digital filter disabled 1 = TDR analog to digital filter enabled (reduces noise spikes during TDR pulses) 13:11 RESERVED 10:9 TDR Channel Cable Type Indicates the cable type determined by the TDR test. 00 = Default 01 = Shorted cable condition 10 = Open cable condition 11 = Match cable condition R/W NASR Note 14 00b 8 TDR Channel Status When high, this bit indicates that the TDR operation has completed. This bit will stay high until reset or the TDR operation is restarted (TDR Enable = 1) R/W NASR Note 14 0b 7:0 TDR Channel Length This eight bit value indicates the TDR channel length during a short or open cable condition. Refer to Section 11.2.12.1, "Time Domain Reflectometry (TDR) Cable Diagnostics," on page 136 for additional information on the usage of this field. R/W NASR Note 14 00h Note: This field is not valid during a match cable condition. The PHY x Cable Length Register (PHY_CABLE_LEN_x) must be used to determine cable length during a non-open/short (match) condition. Refer to Section 11.2.12, "Cable Diagnostics," on page 136 for additional information. Note 14: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Register (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set. 2015 Microchip Technology Inc. DS00001909A-page 165 LAN9252 11.2.16.17 PHY x Symbol Error Counter Register Index (In Decimal): 26 Size: 16 bits Bits Description Type Default 15:0 Symbol Error Counter (SYM_ERR_CNT) This 100BASE-TX receiver-based error counter increments when an invalid code symbol is received, including IDLE symbols. The counter is incremented only once per packet, even when the received packet contains more than one symbol error. This field counts up to 65,536 and rolls over to 0 if incremented beyond its maximum value. RO 0000h Note: This register is cleared on reset, but is not cleared by reading the register. It does not increment in 10BASE-T mode. DS00001909A-page 166 2015 Microchip Technology Inc. LAN9252 11.2.16.18 PHY x Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x) Index (decimal): 27 Size: 16 bits This read/write register is used to control various options of the PHY. Bits Type Default R/W NASR Note 15 0b R/W NASR Note 15 0b R/W NASR Note 15 0b RO - R/W NASR Note 15 0b RESERVED RO - 5 Far End Fault Indication Enable (FEFI_EN) This bit enables Far End Fault Generation and Detection. See Section 11.2.14.1, "100BASE-FX Far End Fault Indication," on page 141 for more information. R/W Note 16 4 10Base-T Polarity State (XPOL) This bit shows the polarity state of the 10Base-T. RO 0b RO - 15 Description Auto-MDIX Control (AMDIXCTRL) This bit is responsible for determining the source of Auto-MDIX control for Port x. 0: Port x Auto-MDIX enabled 1: Port x Auto-MDIX determined by bits 14 and 13 14 Auto-MDIX Enable (AMDIXEN) When the AMDIXCTRL bit of this register is set, this bit is used in conjunction with the AMDIXSTATE bit to control the Port Auto-MDIX functionality as shown in Table 11-13. Auto-MDIX is not appropriate and should not be enabled for 100BASE-FX mode. 13 Auto-MDIX State (AMDIXSTATE) When the AMDIXCTRL bit of this register is set, this bit is used in conjunction with the AMDIXEN bit to control the Port Auto-MDIX functionality as shown in Table 11-13. 12 RESERVED 11 SQE Test Disable (SQEOFF) This bit controls the disabling of the SQE test (Heartbeat). SQE test is enabled by default. 0: SQE test enabled 1: SQE test disabled 10:6 0: Normal Polarity 1: Reversed Polarity 3:0 RESERVED Note 15: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Register (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set. Note 16: The default value of this bit is a 1 if in 100BASE-FX mode, otherwise the default is a 0. 2015 Microchip Technology Inc. DS00001909A-page 167 LAN9252 TABLE 11-13: AUTO-MDIX ENABLE AND AUTO-MDIX STATE BIT FUNCTIONALITY Auto-MDIX Enable Auto-MDIX State Mode 0 0 Manual mode, no crossover 0 1 Manual mode, crossover 1 0 Auto-MDIX mode 1 1 RESERVED (do not use this state) DS00001909A-page 168 2015 Microchip Technology Inc. LAN9252 11.2.16.19 PHY x Cable Length Register (PHY_CABLE_LEN_x) Index (In Decimal): Bits 15:12 Size: 16 bits Description Cable Length (CBLN) This four bit value indicates the cable length. Refer to Section 11.2.12.2, "Matched Cable Diagnostics," on page 139 for additional information on the usage of this field. Note: 11:0 28 Type Default RO 0000b R/W - This field indicates cable length for 100BASE-TX linked devices that do not have an open/short on the cable. To determine the open/short status of the cable, the PHY x TDR Patterns/Delay Control Register (PHY_TDR_PAT_DELAY_x) and PHY x TDR Control/Status Register (PHY_TDR_CONTROL_STAT_x) must be used. Cable length is not supported for 10BASE-T links. Refer to Section 11.2.12, "Cable Diagnostics," on page 136 for additional information. RESERVED - Write as 100000000000b, ignore on read 2015 Microchip Technology Inc. DS00001909A-page 169 LAN9252 11.2.16.20 PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) Index (decimal): 29 Size: 16 bits This read-only register is used to determine to source of various PHY interrupts. All interrupt source bits in this register are read-only and latch high upon detection of the corresponding interrupt (if enabled). A read of this register clears the interrupts. These interrupts are enabled or masked via the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x). Bits 15:9 9 Description RESERVED INT9 This interrupt source bit indicates a Link Up (link status asserted). Type Default RO - RO/LH 0b RO/LH 0b RO/LH 0b RO/LH 0b RO/LH 0b RO/LH 0b RO/LH 0b 0: Not source of interrupt 1: Link Up (link status asserted) 8 INT8 0: Not source of interrupt 1: Wake on LAN (WoL) event detected 7 INT7 This interrupt source bit indicates when the Energy On (ENERGYON) bit of the PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) has been set. 0: Not source of interrupt 1: ENERGYON generated 6 INT6 This interrupt source bit indicates Auto-Negotiation is complete. 0: Not source of interrupt 1: Auto-Negotiation complete 5 INT5 This interrupt source bit indicates a remote fault has been detected. 0: Not source of interrupt 1: Remote fault detected 4 INT4 This interrupt source bit indicates a Link Down (link status negated). 0: Not source of interrupt 1: Link Down (link status negated) 3 INT3 This interrupt source bit indicates an Auto-Negotiation LP acknowledge. 0: Not source of interrupt 1: Auto-Negotiation LP acknowledge DS00001909A-page 170 2015 Microchip Technology Inc. LAN9252 Bits 2 Description INT2 This interrupt source bit indicates a Parallel Detection fault. Type Default RO/LH 0b RO/LH 0b RO - 0: Not source of interrupt 1: Parallel Detection fault 1 INT1 This interrupt source bit indicates an Auto-Negotiation page received. 0: Not source of interrupt 1: Auto-Negotiation page received 0 RESERVED 2015 Microchip Technology Inc. DS00001909A-page 171 LAN9252 11.2.16.21 PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) Index (decimal): 30 Size: 16 bits This read/write register is used to enable or mask the various PHY interrupts and is used in conjunction with the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x). Bits 15:10 9 Description Type Default RESERVED RO - INT9_MASK This interrupt mask bit enables/masks the Link Up (link status asserted) interrupt. R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b 0: Interrupt source is masked 1: Interrupt source is enabled 8 INT8_MASK This interrupt mask bit enables/masks the WoL interrupt. 0: Interrupt source is masked 1: Interrupt source is enabled 7 INT7_MASK This interrupt mask bit enables/masks the ENERGYON interrupt. 0: Interrupt source is masked 1: Interrupt source is enabled 6 INT6_MASK This interrupt mask bit enables/masks the Auto-Negotiation interrupt. 0: Interrupt source is masked 1: Interrupt source is enabled 5 INT5_MASK This interrupt mask bit enables/masks the remote fault interrupt. 0: Interrupt source is masked 1: Interrupt source is enabled 4 INT4_MASK This interrupt mask bit enables/masks the Link Down (link status negated) interrupt. 0: Interrupt source is masked 1: Interrupt source is enabled 3 INT3_MASK This interrupt mask bit enables/masks the Auto-Negotiation LP acknowledge interrupt. 0: Interrupt source is masked 1: Interrupt source is enabled DS00001909A-page 172 2015 Microchip Technology Inc. LAN9252 Bits 2 Description INT2_MASK This interrupt mask bit enables/masks the Parallel Detection fault interrupt. Type Default R/W 0b R/W 0b RO - 0: Interrupt source is masked 1: Interrupt source is enabled 1 INT1_MASK This interrupt mask bit enables/masks the Auto-Negotiation page received interrupt. 0: Interrupt source is masked 1: Interrupt source is enabled 0 RESERVED 2015 Microchip Technology Inc. DS00001909A-page 173 LAN9252 11.2.16.22 PHY x Special Control/Status Register (PHY_SPECIAL_CONTROL_STATUS_x) Index (decimal): 31 Size: 16 bits This read/write register is used to control and monitor various options of the PHY. Bits 15:13 12 Description Type Default RESERVED RO - Autodone This bit indicates the status of the Auto-Negotiation on the PHY. RO 0b 0: Auto-Negotiation is not completed, is disabled, or is not active 1: Auto-Negotiation is completed 11:5 RESERVED - Write as 0000010b, ignore on read R/W 0000010b 4:2 Speed Indication This field indicates the current PHY speed configuration. RO XXXb RO 0b STATE 1:0 DESCRIPTION 000 RESERVED 001 10BASE-T Half-duplex 010 100BASE-TX Half-duplex 011 RESERVED 100 RESERVED 101 10BASE-T Full-duplex 110 100BASE-TX Full-duplex 111 RESERVED RESERVED DS00001909A-page 174 2015 Microchip Technology Inc. LAN9252 MDIO Manageable Device (MMD) Registers The device MMD registers adhere to the IEEE 802.3-2008 45.2 MDIO Interface Registers specification. The MMD registers are not memory mapped. These registers are accessed indirectly via the PHY x MMD Access Control Register (PHY_MMD_ACCESS) and PHY x MMD Access Address/Data Register (PHY_MMD_ADDR_DATA). The supported MMD device addresses are 3 (PCS), 7 (Auto-Negotiation), and 30 (Vendor Specific). Table 11-14, "MMD Registers" details the supported registers within each MMD device. TABLE 11-14: MMD REGISTERS MMD DEVICE ADDRESS (IN DECIMAL) INDEX (IN DECIMAL) REGISTER NAME 5 PHY x PCS MMD Devices Present 1 Register (PHY_PCS_MMD_PRESENT1_x) 6 PHY x PCS MMD Devices Present 2 Register (PHY_PCS_MMD_PRESENT2_x) 32784 PHY x Wakeup Control and Status Register (PHY_WUCSR_x) 32785 PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x) 32786 PHY x Wakeup Filter Configuration Register B (PHY_WUF_CFGB_x) 32801 32802 3 (PCS) 32803 32804 32805 PHY x Wakeup Filter Byte Mask Registers (PHY_WUF_MASK_x) 32806 32807 32808 32865 PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x) 32866 PHY x MAC Receive Address B Register (PHY_RX_ADDRB_x) 32867 PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x) 7 (Auto-Negotiation) 2015 Microchip Technology Inc. 5 PHY x Auto-Negotiation MMD Devices Present 1 Register (PHY_AN_MMD_PRESENT1_x) 6 PHY x Auto-Negotiation MMD Devices Present 2 Register (PHY_AN_MMD_PRESENT2_x) DS00001909A-page 175 LAN9252 TABLE 11-14: MMD REGISTERS (CONTINUED) MMD DEVICE ADDRESS (IN DECIMAL) 30 (Vendor Specific) INDEX (IN DECIMAL) REGISTER NAME 2 PHY x Vendor Specific MMD 1 Device ID 1 Register (PHY_VEND_SPEC_MMD1_DEVID1_x) 3 PHY x Vendor Specific MMD 1 Device ID 2 Register (PHY_VEND_SPEC_MMD1_DEVID2_x) 5 PHY x Vendor Specific MMD 1 Devices Present 1 Register (PHY_VEND_SPEC_MMD1_PRESENT1_x) 6 PHY x Vendor Specific MMD 1 Devices Present 2 Register (PHY_VEND_SPEC_MMD1_PRESENT2_x) 8 PHY x Vendor Specific MMD 1 Status Register (PHY_VEND_SPEC_MMD1_STAT_x) 14 PHY x Vendor Specific MMD 1 Package ID 1 Register (PHY_VEND_SPEC_MMD1_PKG_ID1_x) 15 PHY x Vendor Specific MMD 1 package ID 2 Register (PHY_VEND_SPEC_MMD1_PKG_ID2_x) To read or write an MMD register, the following procedure must be observed: 1. 2. 3. 4. Write the PHY x MMD Access Control Register (PHY_MMD_ACCESS) with 00b (address) for the MMD Function field and the desired MMD device (3 for PCS, 7 for Auto-Negotiation) for the MMD Device Address (DEVAD) field. Write the PHY x MMD Access Address/Data Register (PHY_MMD_ADDR_DATA) with the 16-bit address of the desired MMD register to read/write within the previously selected MMD device (PCS or Auto-Negotiation). Write the PHY x MMD Access Control Register (PHY_MMD_ACCESS) with 01b (data) for the MMD Function field and choose the previously selected MMD device (3 for PCS, 7 for Auto-Negotiation) for the MMD Device Address (DEVAD) field. If reading, read the PHY x MMD Access Address/Data Register (PHY_MMD_ADDR_DATA), which contains the selected MMD register contents. If writing, write the PHY x MMD Access Address/Data Register (PHY_MMD_ADDR_DATA) with the register contents intended for the previously selected MMD register. Unless otherwise specified, reserved fields must be written with zeros if the register is written. DS00001909A-page 176 2015 Microchip Technology Inc. LAN9252 11.2.16.23 PHY x PCS MMD Devices Present 1 Register (PHY_PCS_MMD_PRESENT1_x) Index (In Decimal): 3.5 Bits 15:8 7 Description Size: 16 bits Type Default RESERVED RO - Auto-Negotiation Present RO 1b RO 0b RO 0b RO 0b RO 1b RO 0b RO 0b RO 0b 0 = Auto-negotiation not present in package 1 = Auto-negotiation present in package 6 TC Present 0 = TC not present in package 1 = TC present in package 5 DTE XS Present 0 = DTE XS not present in package 1 = DTE XS present in package 4 PHY XS Present 0 = PHY XS not present in package 1 = PHY XS present in package 3 PCS Present 0 = PCS not present in package 1 = PCS present in package 2 WIS Present 0 = WIS not present in package 1 = WIS present in package 1 PMD/PMA Present 0 = PMD/PMA not present in package 1 = PMD/PMA present in package 0 Clause 22 Registers Present 0 = Clause 22 registers not present in package 1 = Clause 22 registers present in package 2015 Microchip Technology Inc. DS00001909A-page 177 LAN9252 11.2.16.24 PHY x PCS MMD Devices Present 2 Register (PHY_PCS_MMD_PRESENT2_x) Index (In Decimal): 3.6 Bits 15 Size: Description Vendor Specific Device 2 Present 16 bits Type Default RO 0b RO 1b RO 0b RO - 0 = Vendor specific device 2 not present in package 1 = Vendor specific device 2 present in package 14 Vendor Specific Device 1 Present 0 = Vendor specific device 1 not present in package 1 = Vendor specific device 1 present in package 13 Clause 22 Extension Present 0 = Clause 22 extension not present in package 1 = Clause 22 extension present in package 12:0 RESERVED DS00001909A-page 178 2015 Microchip Technology Inc. LAN9252 11.2.16.25 PHY x Wakeup Control and Status Register (PHY_WUCSR_x) Index (In Decimal): Bits 15:9 8 3.32784 Size: 16 bits Description RESERVED WoL Configured This bit may be set by software after the WoL registers are configured. This sticky bit (and all other WoL related register bits) is reset only via a power cycle or a pin reset, allowing software to skip programming of the WoL registers in response to a WoL event. Note: Type Default RO - R/W/ NASR Note 17 0b Refer to Section 11.2.9, "Wake on LAN (WoL)," on page 132 for additional information. 7 Perfect DA Frame Received (PFDA_FR) The MAC sets this bit upon receiving a valid frame with a destination address that matches the physical address. R/WC/ NASR Note 17 0b 6 Remote Wakeup Frame Received (WUFR) The MAC sets this bit upon receiving a valid remote Wakeup Frame. R/WC/ NASR Note 17 0b 5 Magic Packet Received (MPR) The MAC sets this bit upon receiving a valid Magic Packet. R/WC/ NASR Note 17 0b 4 Broadcast Frame Received (BCAST_FR) The MAC Sets this bit upon receiving a valid broadcast frame. R/WC/ NASR Note 17 0b 3 Perfect DA Wakeup Enable (PFDA_EN) When set, remote wakeup mode is enabled and the MAC is capable of waking up on receipt of a frame with a destination address that matches the physical address of the device. The physical address is stored in the PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x), PHY x MAC Receive Address B Register (PHY_RX_ADDRB_x) and PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x). R/W/ NASR Note 17 0b 2 Wakeup Frame Enable (WUEN) When set, remote wakeup mode is enabled and the MAC is capable of detecting Wakeup Frames as programmed in the Wakeup Filter. R/W/ NASR Note 17 0b 1 Magic Packet Enable (MPEN) When set, Magic Packet wakeup mode is enabled. R/W/ NASR Note 17 0b 0 Broadcast Wakeup Enable (BCST_EN) When set, remote wakeup mode is enabled and the MAC is capable of waking up from a broadcast frame. R/W/ NASR Note 17 0b Note 17: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Register (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set. 2015 Microchip Technology Inc. DS00001909A-page 179 LAN9252 11.2.16.26 PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x) Index (In Decimal): Bits 15 3.32785 Size: 16 bits Description Filter Enable 0 = Filter disabled 1 = Filter enabled 14 Filter Triggered 0 = Filter not triggered 1 = Filter triggered 13:11 RESERVED Type Default R/W/ NASR Note 18 0b R/WC/ NASR Note 18 0b RO - 10 Address Match Enable When set, the destination address must match the programmed address. When cleared, any unicast packet is accepted. Refer to Section 11.2.9.4, "Wakeup Frame Detection," on page 133 for additional information. R/W/ NASR Note 18 0b 9 Filter Any Multicast Enable When set, any multicast packet other than a broadcast will cause an address match. Refer to Section 11.2.9.4, "Wakeup Frame Detection," on page 133 for additional information. R/W/ NASR Note 18 0b R/W/ NASR Note 18 0b R/W/ NASR Note 18 00h Note: 8 Filter Broadcast Enable When set, any broadcast frame will cause an address match. Refer to Section 11.2.9.4, "Wakeup Frame Detection," on page 133 for additional information. Note: 7:0 This bit has priority over bit 10 of this register. This bit has priority over bit 10 of this register. Filter Pattern Offset Specifies the offset of the first byte in the frame on which CRC checking begins for Wakeup Frame recognition. Offset 0 is the first byte of the incoming frame’s destination address. Note 18: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Register (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set. DS00001909A-page 180 2015 Microchip Technology Inc. LAN9252 11.2.16.27 PHY x Wakeup Filter Configuration Register B (PHY_WUF_CFGB_x) Index (In Decimal): 3.32786 Size: 16 bits Bits Description Type Default 15:0 Filter CRC-16 This field specifies the expected 16-bit CRC value for the filter that should be obtained by using the pattern offset and the byte mask programmed for the filter. This value is compared against the CRC calculated on the incoming frame, and a match indicates the reception of a Wakeup Frame. R/W/ NASR Note 19 0000h Note 19: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Register (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set. 2015 Microchip Technology Inc. DS00001909A-page 181 LAN9252 11.2.16.28 PHY x Wakeup Filter Byte Mask Registers (PHY_WUF_MASK_x) Index (In Decimal): Bits 15:0 3.32802 Size: Wakeup Filter Byte Mask [111:96] Bits 3.32803 Size: Wakeup Filter Byte Mask [95:80] Bits 3.32804 Description Wakeup Filter Byte Mask [79:64] DS00001909A-page 182 Size: Default R/W/ NASR Note 20 0000h Type Default R/W/ NASR Note 20 0000h Type Default R/W/ NASR Note 20 0000h Type Default R/W/ NASR Note 20 0000h 16 bits Description Index (In Decimal): Type 16 bits Description Index (In Decimal): 15:0 16 bits Wakeup Filter Byte Mask [127:112] Bits 15:0 Size: Description Index (In Decimal): 15:0 3.32801 16 bits 2015 Microchip Technology Inc. LAN9252 Index (In Decimal): Bits 15:0 3.32806 Size: Wakeup Filter Byte Mask [47:32] Bits 3.32807 Size: Wakeup Filter Byte Mask [31:16] Bits 3.32808 Description Wakeup Filter Byte Mask [15:0] Size: Default R/W/ NASR Note 20 0000h Type Default R/W/ NASR Note 20 0000h Type Default R/W/ NASR Note 20 0000h Type Default R/W/ NASR Note 20 0000h 16 bits Description Index (In Decimal): Type 16 bits Description Index (In Decimal): 15:0 16 bits Wakeup Filter Byte Mask [63:48] Bits 15:0 Size: Description Index (In Decimal): 15:0 3.32805 16 bits Note 20: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Register (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set. 2015 Microchip Technology Inc. DS00001909A-page 183 LAN9252 11.2.16.29 PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x) Index (In Decimal): Bits 15:0 3.32865 Description Physical Address [47:32] Size: 16 bits Type Default R/W/ NASR Note 21 FFFFh Note 21: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Register (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set. DS00001909A-page 184 2015 Microchip Technology Inc. LAN9252 11.2.16.30 PHY x MAC Receive Address B Register (PHY_RX_ADDRB_x) Index (In Decimal): Bits 15:0 3.32866 Description Physical Address [31:16] Size: 16 bits Type Default R/W/ NASR Note 22 FFFFh Note 22: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Register (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set. 2015 Microchip Technology Inc. DS00001909A-page 185 LAN9252 11.2.16.31 PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x) Index (In Decimal): Bits 15:0 3.32867 Description Physical Address [15:0] Size: 16 bits Type Default R/W/ NASR Note 23 FFFFh Note 23: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Register (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set. DS00001909A-page 186 2015 Microchip Technology Inc. LAN9252 11.2.16.32 PHY x Auto-Negotiation MMD Devices Present 1 Register (PHY_AN_MMD_PRESENT1_x) Index (In Decimal): 7.5 Bits 15:8 7 Description Size: 16 bits Type Default RESERVED RO - Auto-Negotiation Present RO 1b RO 0b RO 0b RO 0b RO 1b RO 0b RO 0b RO 0b 0 = Auto-negotiation not present in package 1 = Auto-negotiation present in package 6 TC Present 0 = TC not present in package 1 = TC present in package 5 DTE XS Present 0 = DTE XS not present in package 1 = DTE XS present in package 4 PHY XS Present 0 = PHY XS not present in package 1 = PHY XS present in package 3 PCS Present 0 = PCS not present in package 1 = PCS present in package 2 WIS Present 0 = WIS not present in package 1 = WIS present in package 1 PMD/PMA Present 0 = PMD/PMA not present in package 1 = PMD/PMA present in package 0 Clause 22 Registers Present 0 = Clause 22 registers not present in package 1 = Clause 22 registers present in package 2015 Microchip Technology Inc. DS00001909A-page 187 LAN9252 11.2.16.33 PHY x Auto-Negotiation MMD Devices Present 2 Register (PHY_AN_MMD_PRESENT2_x) Index (In Decimal): 7.6 Bits 15 Size: Description Vendor Specific Device 2 Present 16 bits Type Default RO 0b RO 1b RO 0b RO - 0 = Vendor specific device 2 not present in package 1 = Vendor specific device 2 present in package 14 Vendor Specific Device 1 Present 0 = Vendor specific device 1 not present in package 1 = Vendor specific device 1 present in package 13 Clause 22 Extension Present 0 = Clause 22 extension not present in package 1 = Clause 22 extension present in package 12:0 RESERVED DS00001909A-page 188 2015 Microchip Technology Inc. LAN9252 11.2.16.34 PHY x Vendor Specific MMD 1 Device ID 1 Register (PHY_VEND_SPEC_MMD1_DEVID1_x) Index (In Decimal): Bits 15:0 30.2 Description RESERVED 2015 Microchip Technology Inc. Size: 16 bits Type Default RO 0000h DS00001909A-page 189 LAN9252 11.2.16.35 PHY x Vendor Specific MMD 1 Device ID 2 Register (PHY_VEND_SPEC_MMD1_DEVID2_x) Index (In Decimal): Bits 15:0 30.3 Description RESERVED DS00001909A-page 190 Size: 16 bits Type Default RO 0000h 2015 Microchip Technology Inc. LAN9252 11.2.16.36 PHY x Vendor Specific MMD 1 Devices Present 1 Register (PHY_VEND_SPEC_MMD1_PRESENT1_x) Index (In Decimal): 30.5 Bits 15:8 7 Description Size: 16 bits Type Default RESERVED RO - Auto-Negotiation Present RO 1b RO 0b RO 0b RO 0b RO 1b RO 0b RO 0b RO 0b 0 = Auto-negotiation not present in package 1 = Auto-negotiation present in package 6 TC Present 0 = TC not present in package 1 = TC present in package 5 DTE XS Present 0 = DTE XS not present in package 1 = DTE XS present in package 4 PHY XS Present 0 = PHY XS not present in package 1 = PHY XS present in package 3 PCS Present 0 = PCS not present in package 1 = PCS present in package 2 WIS Present 0 = WIS not present in package 1 = WIS present in package 1 PMD/PMA Present 0 = PMD/PMA not present in package 1 = PMD/PMA present in package 0 Clause 22 Registers Present 0 = Clause 22 registers not present in package 1 = Clause 22 registers present in package 2015 Microchip Technology Inc. DS00001909A-page 191 LAN9252 11.2.16.37 PHY x Vendor Specific MMD 1 Devices Present 2 Register (PHY_VEND_SPEC_MMD1_PRESENT2_x) Index (In Decimal): 30.6 Bits 15 Size: Description Vendor Specific Device 2 Present 16 bits Type Default RO 0b RO 1b RO 0b RO - 0 = Vendor specific device 2 not present in package 1 = Vendor specific device 2 present in package 14 Vendor Specific Device 1 Present 0 = Vendor specific device 1 not present in package 1 = Vendor specific device 1 present in package 13 Clause 22 Extension Present 0 = Clause 22 extension not present in package 1 = Clause 22 extension present in package 12:0 RESERVED DS00001909A-page 192 2015 Microchip Technology Inc. LAN9252 11.2.16.38 PHY x Vendor Specific MMD 1 Status Register (PHY_VEND_SPEC_MMD1_STAT_x) Index (In Decimal): Bits 15:14 30.8 Description Device Present Size: 16 bits Type Default RO 10b RO - 00 = No device responding at this address 01 = No device responding at this address 10 = Device responding at this address 11 = No device responding at this address 13:0 RESERVED 2015 Microchip Technology Inc. DS00001909A-page 193 LAN9252 11.2.16.39 PHY x Vendor Specific MMD 1 Package ID 1 Register (PHY_VEND_SPEC_MMD1_PKG_ID1_x) Index (In Decimal): Bits 15:0 30.14 Description RESERVED DS00001909A-page 194 Size: 16 bits Type Default RO 0000h 2015 Microchip Technology Inc. LAN9252 11.2.16.40 PHY x Vendor Specific MMD 1 package ID 2 Register (PHY_VEND_SPEC_MMD1_PKG_ID2_x) Index (In Decimal): Bits 15:0 30.15 Description RESERVED Size: 16 bits Type Default RO 0000h . 2015 Microchip Technology Inc. DS00001909A-page 195 LAN9252 12.0 ETHERCAT 12.1 EtherCAT Functional Overview The EtherCAT module implements a 3 port EtherCAT slave controller with 4K bytes of Dual Port memory (DPRAM), 4 SyncManagers, 3 Fieldbus Memory Management Units (FMMUs) and a 64-bit Distributed Clock. Each port receives an Ethernet frame, performs frame checking and forwards it to the next port. Time stamps of received frames are generated when they are received. The Loop-back function of each port forwards Ethernet frames to the next logical port if there is either no link at a port, or if the port is not available, or if the loop is closed for that port. The Loop-back function of port 0 forwards the frames to the EtherCAT Processing Unit. The loop settings can be controlled by the EtherCAT master. Packets are forwarded in the following order: Port 0->EtherCAT Processing Unit->Port 1->Port 2. The EtherCAT Processing Unit (EPU) receives, analyses and processes the EtherCAT data stream. The main purpose of the EtherCAT Processing unit is to enable and coordinate access to the internal registers and the memory space of the ESC, which can be addressed both from the EtherCAT master and from the local application. Data exchange between master and slave application is comparable to a dual-ported memory (process memory), enhanced by special functions e.g. for consistency checking (SyncManager) and data mapping (FMMU). Each FMMU performs the task of bitwise mapping of logical EtherCAT system addresses to physical addresses of the device. SyncManagers are responsible for consistent data exchange and mailbox communication between EtherCAT master and slaves. Each SyncManager's direction and mode of operation is configured by the EtherCAT master. Two modes of operation are available: buffered mode or mailbox mode. In the buffered mode, both the local microcontroller and EtherCAT master can write to the device concurrently. The buffer within the LAN9252 will always contain the latest data. If newer data arrives before the old data can be read out, the old data will be dropped. In mailbox mode, access to the buffer by the local microcontroller and the EtherCAT master is performed using handshakes, guaranteeing that no data will be dropped. Distributed Clocks (DC) allow for precisely synchronized generation of output signals and input sampling, as well as time stamp generation of events. The EtherCAT chapter consists of the following main sections: • • • • • • • • • • • • • Section 12.2, "Distributed Clocks," on page 197 Section 12.3, "PDI Selection and Configuration," on page 198 Section 12.4, "Digital I/O PDI," on page 198 Section 12.5, "Host Interface PDI," on page 200 Section 12.6, "GPIOs," on page 201 Section 12.7, "User RAM," on page 201 Section 12.8, "EEPROM Configurable Registers," on page 201 Section 12.9, "Port Interfaces," on page 202 Section 12.10, "LEDs," on page 208 Section 12.11, "EtherCAT CSR and Process Data RAM Access," on page 208 Section 12.12, "EtherCAT Reset," on page 213 Section 12.13, "EtherCAT CSR and Process Data RAM Access Registers (Directly Addressable)," on page 214 Section 12.14, "EtherCAT Core CSR Registers (Indirectly Addressable)," on page 223 Refer to FIGURE 2-2: Internal Block Diagram on page 9 for an overview of the interconnection of the EtherCAT module within the device. DS00001909A-page 196 2015 Microchip Technology Inc. LAN9252 12.2 Distributed Clocks The device supports 64-bit distributed clocks as detailed in the following sub-sections. 12.2.1 SYNC/LATCH PIN MULTIPLEXING The EtherCAT Core provides two input pins (LATCH0 and LATCH1) which are used for time stamping of external events. Both rising edge and falling edge time stamps are recorded. These pins are shared with the SYNC0 and SYNC1 output pins, respectively, which are used to indicate the occurrence of time events. The functions of the SYNC0/LATCH0 and SYNC1/LATCH1 pins are determined by the SYNC0/LATCH0 Configuration and SYNC1/LATCH1 Configuration bits of the Sync/Latch PDI Configuration Register, respectively. When set for SYNC0/SYNC1 functionality, the output type (Push-Pull vs. Open Drain/Source) and output polarity are determined by the SYNC0 Output Driver/Polarity and SYNC1 Output Driver/Polarity bits of the Sync/Latch PDI Configuration Register. Note: 12.2.2 The Sync/Latch PDI Configuration Register is initialized from the contents of EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. SYNC IRQ MAPPING The SYNC0 and SYNC1 states can be mapped into the State of DC SYNC0 and State of DC SYNC1 bits of the AL Event Request Register, respectively. The mapping of the SYNC0 and SYNC1 states is enabled by the SYNC0 Map and SYNC1 Map bits of the Sync/Latch PDI Configuration Register, respectively. Note: 12.2.3 The Sync/Latch PDI Configuration Register is initialized from the contents of EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. SYNC PULSE LENGTH The SYNC0 and SYNC1 pulse length is controlled via the Pulse Length of SyncSignals Register. The Pulse Length of SyncSignals Register is initialized from the contents of EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. 12.2.4 SYNC/LATCH I/O TIMING REQUIREMENTS This section specifies the SYNC0/LATCH0 and SYNC1/LATCH1 input and output timings. FIGURE 12-1: ETHERCAT SYNC/LATCH TIMING DIAGRAM tdc_latch tdc_latch LATCH0/1 tdc_sync_jitter tdc_sync_jitter SYNC0/1 output event time TABLE 12-1: ETHERCAT SYNC/LATCH TIMING VALUES Symbol tdc_latch Description Time between LATCH0 or LATCH1 events tdc_sync_jitter SYNC0 or SYNC1 output jitter 2015 Microchip Technology Inc. Min Typ Max Units 15 - - ns - - 15 ns DS00001909A-page 197 LAN9252 12.3 PDI Selection and Configuration The Process Data Interface (PDI) used by the device is indicated via the PDI Control Register. The available PDIs are: • 04h: Digital I/O PDI • 80h-8Dh: Host Interface PDI (SPI, HBI Multiplexed/Indexed 1/2 Phase 8/16-bit) Note: The PDI Control Register can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. The Host Interface PDI is used to support HBI and SPI modes, as described in Section 14.0, "Chip Mode Configuration," on page 296. The configuration of the enabled PDI is controlled via the PDI Configuration Register and Extended PDI Configuration Register. The definition of these registers depends on the selected mode of operation. However, only one register set exists. 12.4 Digital I/O PDI The Digital I/O PDI provides 16 configurable digital I/Os (DIGIO[15:0]) to be used for simple systems without a host controller. The Digital I/O Output Data Register is used to control the output values, while the Digital I/O Input Data Register is used to read the input values. Each 2-bit pair of the digital I/Os is configurable as an input or output. The direction is selected by the Extended PDI Configuration Register, which is configured via EEPROM (Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information). The Digital I/Os can also be configured to bi-directional mode, where the outputs are driven and latched externally and then released so that the input data can be sampled. Bi-directional operation is selected via the Unidirectional/Bidirectional Mode bit of the PDI Configuration Register. The PDI Configuration Register is initialized from the contents of EEPROM. 12.4.1 OUTPUT WATCHDOG BEHAVIOR The watchdog control of the digital outputs can be configured to specify if the expiration of the SyncManager Watchdog will have an immediate effect on the I/O signals (output reset immediately after watchdog timeout) or if the effect is delayed until the next output event (output reset with next output event). The choice is determined by the Watchdog Behavior bit of the PDI Configuration Register. The PDI Configuration Register is initialized from the contents of EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. 12.4.2 OE_EXT OUTPUT WATCHDOG BEHAVIOR For external watchdog implementations, the WD_TRIG (watchdog trigger) pin can be used. A pulse is generated if the SyncManager Watchdog is triggered. In this case, the internal SyncManager Watchdog should be disabled, and the external watchdog may use the OE_EXT pin to reset the I/O signals if the watchdog is expired. The OUTVALID Mode bit of the PDI Configuration Register controls if WD_TRIG is mapped onto the OUTVALID pin. The PDI Configuration Register is initialized from the contents of EEPROM. Since there is a dedicated WD_TRIG pin, this bit is normally set to 0 in the EEPROM. 12.4.3 INPUT DATA SAMPLING Digital inputs can be configured to be sampled in four ways, at the start of each Ethernet frame, at the rising edge of the LATCH_IN pin, at Distributed Clocks SYNC0 events or at Distributed Clocks SYNC1 events. The choice of sampling mode is determined by the Input Data Sample Selection bits of the PDI Configuration Register. The PDI Configuration Register is initialized from the contents of EEPROM. 12.4.4 OUTPUT DATA UPDATING Digital outputs can be configured to be update four ways, at the end of each Ethernet frame, with Distributed Clocks SYNC0 events, with Distributed Clocks SYNC1 events or at the end of an EtherCAT frame which triggered the Process Data Watchdog. The choice of sampling mode is determined by the Output Data Sample Selection bits of the PDI Configuration Register. The PDI Configuration Register is initialized from the contents of EEPROM. 12.4.5 OUTVALID POLARITY The output polarity of the OUTVALID pin is determined by the OUTVALID Polarity bit of the PDI Configuration Register. The PDI Configuration Register is initialized from the contents of EEPROM. DS00001909A-page 198 2015 Microchip Technology Inc. LAN9252 12.4.6 DIGITAL I/O TIMING REQUIREMENTS This section specifies the DIGIO[15:0], LATCH_IN and SOF input and output timings. FIGURE 12-2: ETHERCAT DIGITAL I/O INPUT TIMING DIAGRAM SYNC0/1 tlatchindelay tlatchin LATCH_IN tsof SOF tsofdatah tindatalatchs tsofdatav tindatasyncs tindatalatchh tindatasynch DIGIO[15:0] FIGURE 12-3: ETHERCAT DIGITAL I/O OUTPUT TIMING DIAGRAM toutvaliddelay toutvalid OUTVALID toutdatas DIGIO[15:0] twd_trigdata toe_extdata teofdata tsyncdata twd_trig WD_TRIG teof EOF SYNC0/1 OE_EXT 2015 Microchip Technology Inc. DS00001909A-page 199 LAN9252 FIGURE 12-4: ETHERCAT DIGITAL I/O BI-DIRECTIONAL TIMING DIAGRAM toutvalid OUTVALID toutdatas DIGIO[15:0] Input Data input events input events allowed toutdatah Output Data Input Data tbidirdelay TABLE 12-2: tbidirdelay no input events allowed input events allowed ETHERCAT DIGITAL I/O TIMING VALUES Symbol Description Min Typ Max Units tindatasyncs Input data setup to SYNC0/1 rising 10 - - ns tindatasynch Input data hold from SYNC0/1 rising 0 - - ns tindatalatchs Input data setup to LATCH_IN rising 8 - - ns tindatalatchh Input data hold from LATCH_IN rising 4 - - ns tlatchin tlatchindelay LATCH_IN high time 8 - - ns time between consecutive input events 440 - - ns SOF high time 35 - 45 ns tsofdatav Input data valid after SOF active, so that input data can be read in the same frame - - 1.2 s tsofdatah Input data hold after SOF active, so that input data can be read in the same frame 1.6 - - s tsof toutdatas Output data setup to OUTVALID rising 65 - - ns toutdatah Output data hold from OUTVALID falling 65 - - ns toutvalid OUTVALID high time 75 - 85 ns 320 - - ns toutvaliddelay time between consecutive output events teof EOF high time teofdata Output data valid after EOF twd_trig WD_TRIG high time twd_trigdata tsyncdata Output data valid after WD_TRIG 35 - 45 ns - - 35 ns 35 - 45 ns - - 35 ns Output data valid after SYNC0/1 - - 25 ns toe_extdata OE_EXT to data low 0 - 15 ns tbidirdelay time between consecutive input or output events 440 - - ns 12.5 Host Interface PDI The Host Interface PDI is used for systems with a host controller that use either a HBI or SPI chip-level host interface. The values in the PDI Configuration Register and the Extended PDI Configuration Register reflect the value from EEPROM. The value in the PDI Configuration Register is used for Host Interface modes to configure the HBI. The value in the Extended PDI Configuration Register is used if GPIOs are enabled (SPI w/GPIO). The PDI Configuration Register and Extended PDI Configuration Register are initialized from the contents of the EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. DS00001909A-page 200 2015 Microchip Technology Inc. LAN9252 12.6 GPIOs The EtherCAT Core provides 16 General Purpose Inputs (GPI[15:0]) and 16 General Purpose Outputs (GPO[15:0]) The General Purpose Output Register is used to control the output value. The General Purpose Input Register is used to read the input value. Note: When GPIOs are not available due to chip configuration, the General Purpose Output Register remains R/ W, but has no effect. When GPIOs are not available due to chip configuration, the General Purpose Input Register will return zeros. Each 2-bit pair is configurable as input, push-pull output or open-drain output. The direction and buffer type are determined by the Extended PDI Configuration Register. Bits 7:0 control the direction of the pairs (bit 0 for GPIO[1:0], bit 1 for GPIO[3:2], etc.). A value of 1 selects the output direction. Bits 15:8 control the output type (bit 8 for GPIO[1:0], bit 9 for GPIO[3:2], etc.). A value of 1 selects the open-drain. The Extended PDI Configuration Register is initialized from the contents of the EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. Note: 12.7 The Extended PDI Configuration Register is also used for the Digital I/O PDI direction. However, GPIOs are not used during Digital I/O mode. User RAM A 128 byte user RAM is located at 0F80h-0FFFh. The default values within this RAM are undefined for all addresses. 12.8 EEPROM Configurable Registers The following registers are configurable via EEPROM. Refer to the corresponding register definition for details on each bit function. Note: Reserved bits must be written as 0 unless otherwise noted. TABLE 12-3: ETHERCAT CORE EEPROM CONFIGURABLE REGISTERS Register PDI Control Register (0140h) ESC Configuration Register (0141h) Bits [7:0] Process Data Interface 0 / [7:0] [7] (unused) 0 / [15] [6] Enhanced Link Port 2 0 / [14] [5] Enhanced Link Port 1 0 / [13] [4] Enhanced Link Port 0 0 / [12] [3] Distributed Clocks Latch In Unit Note: Bit 3 is NOT set by EEPROM [2] Distributed Clocks SYNC Out Unit Note: 2015 Microchip Technology Inc. EEPROM Word / [Bits] Bit 2 is NOT set by EEPROM - [1] Enhanced Link Detection All Ports 0 / [9] [0] Device Emulation (control of AL Status Register) 0 / [8] DS00001909A-page 201 LAN9252 TABLE 12-3: ETHERCAT CORE EEPROM CONFIGURABLE REGISTERS Register PDI Configuration Register (0150h) Digital I/O Mode PDI Configuration Register (0150h) HBI Mode EEPROM Word / [Bits] Bits [7:6] Output Data Sample Selection 1 / [7:6] [5:4] Input Data Sample Selection 1 / [5:4] [3] Watchdog Behavior 1 / [3] [2] Unidirectional/Bidirectional Mode 1 / [2] [1] OUTVALID Mode 1 / [1] [0] OUTVALID Polarity 1 / [0] [7] HBI ALE Qualification 1 / [7] [6] HBI Read/Write Mode 1 / [6] [5] HBI Chip Select Polarity 1 / [5] [4] HBI Read, Read/Write Polarity 1 / [4] [3] HBI Write, Enable Polarity 1 / [3] [2] HBI ALE Polarity Sync/Latch PDI Configuration Register (0151h) Pulse Length of SyncSignals Register (0982h-0983h) Extended PDI Configuration Register (0152h-0153h) Digital I/O Mode Extended PDI Configuration Register (0152h-0153h) SPI Mode Configured Station Alias Register (0012h-0013h) MII Management Control/Status Register (0510h-0511h) 1 / [2] [1:0] RESERVED (unused) 1 / [1:0] [7] SYNC1 Map 1 / [15] [6] SYNC1/LATCH1 Configuration 1 / [14] [5:4] SYNC1 Output Driver/Polarity 1 / [13:12] [3] SYNC0 Map 1 / [11] [2] SYNC0/LATCH0 Configuration 1 / [10] [1:0] SYNC0 Output Driver/Polarity 1 / [9:8] [15:0] Pulse length of SyncSignals 2 / [15:0] [15:8] RESERVED 3 / [15:8] [7:0] I/O 15-0 Direction 3 / [7:0] [15:8] I/O 15-0 Buffer Type 3 / [15:8] [7:0] I/O 15-0 Direction 3 / [7:0] [15:0] Configured Station Alias Address 4 / [15:0] [2] MI Link Detection 5 / [15] [15] MI Link Detection ASIC Configuration Register (0142h-0143h) RESERVED Register (0144h-0145h) 12.9 12.9.1 [14:8] RESERVED 5 / [14:8] [7] MI Write Gigabit Register 9 Enable 5 / [7] [6:0] RESERVED 5 / [6:0] [15:0] RESERVED 6 / [15:0] Port Interfaces PORTS 0 AND 2 (INTERNAL PHY A OR EXTERNAL MII) Port 0 of the EtherCAT Slave is connected to internal PHY A when chip_mode_strap[1:0] is not equal to 11b (2 port mode or 3 port downstream mode). Port 0 is connected to the MII pins when chip_mode_strap[1:0] is equal to 11b (3 port upstream mode). Port 2 of the EtherCAT Slave is connected to internal PHY A when chip_mode_strap[1:0] is equal to 11b (3 port upstream mode). Port 2 is connected to the MII pins when chip_mode_strap[1:0] is equal to 10b (3 port downstream mode). DS00001909A-page 202 2015 Microchip Technology Inc. LAN9252 12.9.1.1 EXTERNAL MII PHY CONNECTION An external PHY is connected to the MII port as shown in Figure 12-5. The clock source for the Ethernet PHY and the EtherCAT Slave must be the same. A 25 MHz output (MII_CLK25) is provided to be used as the reference clock for the PHY. TX_CLK from the PHY is not connected since the EtherCAT Slave does not incorporate a TX FIFO. The TX signals from the EtherCAT Slave may be delayed with respect to the CLK25 output by using TX shift compensation so that they align properly as if they were driven by the PHY’s TX_CLK. MII timing is described in Section 12.9.7, "External PHY Timing". The Ethernet PHY should be connected to the EtherCAT Slave RST# pin so that the PHY is held in reset until the EtherCAT Slave is ready. Otherwise, the far end Link Partner would detect valid link signals from the PHY and would “open” its port assuming that the local EtherCAT Slave was ready. The MII_MDC and MII_MDIO signals are connected between the EtherCAT slave and the PHY. MII_MDIO requires an external pull-up. The management address of the external PHY must be set to 0 when chip_mode_strap[1:0] is equal to 11b (3 port upstream mode) and to 2 when chip_mode_strap[1:0] is equal to 10b (3 port downstream mode). LINK_STATUS from the PHY is an LED output which indicates that a 100 Mbit/s, Full Duplex link is active. The polarity of the MII_LINK input of the EtherCAT slave is configurable. The COL and CRS outputs from the PHY are not connected since EtherCAT operates in full-duplex mode. The TX_ER input to the PHY is tied to system ground since the EtherCAT Slave never generates transmit errors. FIGURE 12-5: ETHERCAT EXTERNAL PHY CONNECTION 25 MHz LAN9252 OSCI OSCO PHY CLK25 MII_CLK25 LINK_STATUS MII_LINK RX_CLK RX_DV RX_D[3:0] RX_ER MII_RXCLK MII_RXDV MII_RXD[3:0] MII_RXER MII_TXEN MII_TXD[3:0] 0 ns 10 ns 20 ns 30 ns VDDIO TX shift configuration MII_MDIO MII_MDC RST# 12.9.1.2 TX_CLK TX_EN TX_D[3:0] COL CRS TX_ER MDIO MDC PHY_ADDR 0 or 2 RESET# BACK-TO-BACK CONNECTION Two EtherCAT Slave devices can be connected using a back-to-back MII connection as shown in Figure 12-6. One device is placed in 3 port upstream mode and the other in 3 port downstream mode. The clock sources of each EtherCAT Slave may be different. The 25 MHz output (MII_CLK25) is provided to be used as the RX_CLK input to the other device. The TX signals from each EtherCAT Slave may be delayed with respect to the CLK25 output by using TX shift compensation so that they align properly to meet the RX timing requirement of the other device. Back-to-back MII timing is described in Section 12.9.7, "External PHY Timing". The MII_RXER signals are not used since the EtherCAT Slaves never generate errors. The MII_MDIO and MII_MDC signals are not used since neither device contains a PHY register set. The MII_MDIO pins require (separate) pull-ups so that a high value is returned when PHY register reads are attempted. 2015 Microchip Technology Inc. DS00001909A-page 203 LAN9252 MII_LINK may be tied active, if the two EtherCAT slaves are released from reset at about the same time. Otherwise, MII_LINK can be used to indicate to the partner that the device is not ready. FIGURE 12-6: ETHERCAT BACK-TO-BACK MII CONNECTION VDDIO OSCI OSCO MII_CLK25 MII_LINK MII_LINK MII_RXCLK MII_RXDV MII_RXD[3:0] MII_RXER towards Master (downstream mode) MII_MDIO MII_MDC RST# 12.9.1.3 OSCO towards other salves (upstream mode) VDDIO TX shift configuration OSCI MII_CLK25 MII_TXEN MII_TXD[3:0] MII_TXEN MII_TXD[3:0] 10 ns 20 ns LAN9252 MII_RXCLK 25 MHz 25 MHz LAN9252 MII_RXDV MII_RXD[3:0] MII_RXER TX shift configuration 10 ns 20 ns MII_MDIO MII_MDC RST# 2 PORT OPERATION When configured for two port mode (chip_mode_strap[1:0] equal to 00b), port 2 is disabled. The port status is also shown in the Port 2 Configuration bits of the Port Descriptor Register and is set to a 01b (Not configured) when the device is configured for two port operation. 12.9.2 PORT 1 (INTERNAL PHY B) Port 1 of the EtherCAT core is always connected to internal PHY B. 12.9.3 PHY CONFIGURATION By default, the internal PHYs are configured for 100Mbps, full-duplex operation. Auto-Negotiation is enable for 100BASE-TX mode and disable for 100BASE-FX mode. The EtherCAT Core will also check and update the configuration if necessary. By default, the external PHY is configured for 100Mbps, full-duplex operation with Auto-Negotiation enabled. The EtherCAT Core will check and update the configuration if necessary. 12.9.4 PHY LINK STATUS The link status originates from the PHY’s link signal (internal or external). The EtherCAT Core also checks the PHY status to determine a proper link. By cyclically polling the PHYs, it checks that Auto-negotiation registers are configure properly, if a link is established, if Auto-Negotiation has finished successfully and if the link partner also used Auto-Negotiation. Link checking through the MII Management Interface (MI) is enabled via EEPROM and reflected in the MII Management Control/Status Register. Note: MI link detection is disabled until the device is successfully configured from the EEPROM. The EEPROM setting for MI link detection is only taken at the first EEPROM loading after power-on or reset. Changing the EEPROM and manually reloading it will not affect the MI link detection enable status, even if the EEPROM could not be read initially. DS00001909A-page 204 2015 Microchip Technology Inc. LAN9252 As shown in Table 12-3, "EtherCAT Core EEPROM Configurable Registers", bit 7 of the ASIC Configuration Register is used to enable writes to PHY register 9 for PHYs which use this register per IEEE 802.3. 12.9.4.1 MI LINK DETECTION AND CONFIGURATION STATE MACHINE The MI Link Detection and Configuration state machine operates as follows: • • • • • • Check that auto-negotiation is enabled Check that only 100BASE-X full-duplex is advertised Check that 1000BASE-T is not advertised Check that auto-negotiation is completed Check that link partner is 100BASE-X full-duplex Otherwise, set the registers as needed and restart auto-negotiation 12.9.5 ENHANCED LINK DETECTION The EtherCAT Core supports the enhanced link detection feature with the enable is controlled by the EEPROM. With this, the EtherCAT Core will disconnect a link if at least 32 RX errors (RX_ER) occur in a fixed interval of time (~10 us). Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. 12.9.6 100BASE-FX SUPPORT Since 100BASE-FX operation does not provide support for Auto-Negotiation, special consideration is required for MI and Enhanced link detection operation. MII LINK DETECTION When any port is set for 100BASE-FX operation, MI link detection must be disabled by maintaining bit 2 of the MII Management Control/Status Register low. ENHANCED LINK DETECTION Enhanced link detection may still be enabled. If enhanced link detection detects an error condition, it will still attempt to restart Auto-Negotiation. Since this would have no effect, the internal PHY is also reset. A system that uses an external 100BASE-FX PHY must implement the logic described in the Enhanced FX Link Detection section of the Beckhoff PHY Selection guide to detect the restart Auto-Negotiation command and reset the external PHY and reset / disable the external transceiver. 2015 Microchip Technology Inc. DS00001909A-page 205 LAN9252 12.9.7 EXTERNAL PHY TIMING Since the EtherCAT Core does not use the PHY transmit clock, proper timing must be ensured based on the common 25 MHz reference clock (which is output to the external PHY via the MII_CLK25 pin). To aid in this, the EtherCAT Core has the TX shift feature enabled. This feature can delay the generation of the transmit signals from the EtherCAT Core by 0ns, 10ns, 20ns or 30ns. This value is manually set using tx_shift_strap[1:0]. 12.9.7.1 MII Connection Timing The MII interface TX and RX timing is as follows: FIGURE 12-7: MII TX TIMING tclkp tclkh MII_CLK25 tval (output) tclkl tval thold MII_TXD[3:0] thold tval MII_TXEN TABLE 12-4: MII TX TIMING VALUES Symbol Description Min Max Units 40 - ns Notes tclkp MII_CLK25 period tclkh MII_CLK25 high time tclkp * 0.45 tclkp * 0.55 ns tclkl MII_CLK25 low time tclkp * 0.45 tclkp * 0.55 ns tval MII_TXD[3:0], MII_TXEN output valid from rising edge of MII_CLK25 Note 2 - 10.0 ns Note 1 thold MII_TXD[3:0], MII_TXEN output hold from rising edge of MII_CLK25 Note 2 0 - ns Note 1 Note 1: Timing is designed for a system load between 10 pF and 25 pF. Note 2: Assumes TX shift value of 2, add 10 ns for each increment of TX shift (shift values of 3, 0, and 1 in order). DS00001909A-page 206 2015 Microchip Technology Inc. LAN9252 FIGURE 12-8: MII RX TIMING tclkp tclkh tclkl MII_RXCLK (input) tsu thold MII_RXD[3:0], MII_RXER tsu thold thold thold tsu MII_RXDV TABLE 12-5: MII RX TIMING VALUES Symbol Description Min Max Units Notes tclkp MII_RXCLK period 40 - ns tclkh MII_RXCLK high time tclkp * 0.4 tclkp * 0.6 ns tclkl MII_RXCLK low time tclkp * 0.4 tclkp * 0.6 ns tsu MII_RXD[3:0], MII_RXER, MII_RXDV setup time to rising edge of MII_RXCLK 5.0 - ns Note 3 thold MII_RXD[3:0], MII_RXER, MII_RXDV hold time after rising edge of MII_RXCLK 6.0 - ns Note 3 Note 3: Timing is designed for a system load between 10 pF and 25 pF. 12.9.7.2 Back-to-Back MII Connection Timing With the previously listed MII TX and RX timings, back-to-back connections should use a TX shift value of 3 or 0. 2015 Microchip Technology Inc. DS00001909A-page 207 LAN9252 12.9.7.3 Management Interface Timing The MII_MDIO and MII_MDC timing is follows: FIGURE 12-9: MANAGEMENT ACCESS TIMING tclkp tclkh tclkl MII_MDC tval tohold tohold MII_MDIO (Data-Out) tsu tihold MII_MDIO (Data-In) TABLE 12-6: MANAGEMENT ACCESS TIMING VALUES Symbol Description Min Max Units 400 - ns tclkp MII_MDC period tclkh MII_MDC high time 180 (90%) - ns tclkl MII_MDC low time 180 (90%) - ns tval MII_MDIO output valid from rising edge of MII_MDC - 250 ns tohold MII_MDIO output hold from rising edge of MII_MDC 150 - ns tsu MII_MDIO input setup time to rising edge of MII_MDC 70 - ns tihold MII_MDIO input hold time after rising edge of MII_MDC 0 - ns Notes 12.10 LEDs The device includes one run LED (RUNLED) and a link / activity LED per port (LINKACTLED[0:2]). The LED pin polarity is determined based on the corresponding LED polarity strap. The pin outputs are open drain or open source. Note: The LED pins for Port 0 and Port 2 are not swapped based on the chip mode. The EtherCAT Core configuration provides for direct control of the RUN LED via the RUN LED Override Register. All LED outputs may be disabled (un-driven) by setting the LED_DIS bit in the Power Management Control Register (PMT_CTRL). 12.11 EtherCAT CSR and Process Data RAM Access The EtherCAT CSRs provide register level access to the various parameters of the EtherCAT Core. EtherCAT related registers can be classified into two main categories based upon their method of access: direct and indirect. The directly accessible EtherCAT registers are part of the main system CSRs and are detailed in Section 12.13, "EtherCAT CSR and Process Data RAM Access Registers (Directly Addressable)," on page 214. These registers provide data/command registers (for access to the indirect EtherCAT Core registers). The indirectly accessible EtherCAT Core registers reside within the EtherCAT Core and must be accessed indirectly via the EtherCAT CSR Interface Data Register (ECAT_CSR_DATA) and EtherCAT CSR Interface Command Register (ECAT_CSR_CMD). The indirectly accessible EtherCAT Core CSRs provide full access to the many configurable parameters of the EtherCAT Core. The indirectly accessible EtherCAT Core CSRs are accessed at address 0h through 0FFFh and are detailed in Section 12.14, "EtherCAT Core CSR Registers (Indirectly Addressable)," on page 223. DS00001909A-page 208 2015 Microchip Technology Inc. LAN9252 The EtherCAT Core Process Data RAM can be accessed indirectly via the EtherCAT CSR Interface Data Register (ECAT_CSR_DATA) and EtherCAT CSR Interface Command Register (ECAT_CSR_CMD), starting at 1000h. The EtherCAT Core Process Data RAM can also be accessed more efficiently using the EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA) and EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA). This method provides for multiple DWORDS to be transferred via a FIFO mechanism using a single command and fewer status reads. 12.11.1 ETHERCAT CSR READS To perform a read of an individual EtherCAT Core register, the read cycle must be initiated by performing a single write to the EtherCAT CSR Interface Command Register (ECAT_CSR_CMD) with the CSR Busy (CSR_BUSY) bit set, the CSR Address (CSR_ADDR) field set to the desired register address, the Read/Write (R_nW) bit set and the CSR Size (CSR_SIZE) field set to the desired size. Valid data is available for reading when the CSR Busy (CSR_BUSY) bit is cleared, indicating that the data can be read from the EtherCAT CSR Interface Data Register (ECAT_CSR_DATA). Valid data is always aligned into the lowest bits of the EtherCAT CSR Interface Data Register (ECAT_CSR_DATA). Note: All bytes of the EtherCAT CSR Interface Data Register (ECAT_CSR_DATA) are updated regardless of the value of CSR Size (CSR_SIZE). Figure 12-10 illustrates the process required to perform a EtherCAT Core CSR read. Minimum wait periods are required where noted. The minimum wait periods as specified in Table 5-2, “Read After Write Timing Rules,” on page 35 are required where noted. FIGURE 12-10: ETHERCAT CSR READ ACCESS FLOW DIAGRAM CSR Read Idle Write Command Register min wait period CSR_ BUSY = 1 Read Command Register CSR_ BUSY = 0 Read Data Register 2015 Microchip Technology Inc. DS00001909A-page 209 LAN9252 12.11.2 ETHERCAT CSR WRITES To perform a write to an individual EtherCAT Core register, the desired data must first be written into the EtherCAT CSR Interface Data Register (ECAT_CSR_DATA). Valid data is always aligned into the lowest bits of the EtherCAT CSR Interface Data Register (ECAT_CSR_DATA). The write cycle is initiated by performing a single write to the EtherCAT CSR Interface Command Register (ECAT_CSR_CMD) with the CSR Busy (CSR_BUSY) bit set, the CSR Address (CSR_ADDR) field set to the desired register address, the Read/Write (R_nW) bit cleared and the CSR Size (CSR_SIZE) field set to the desired size. The completion of the write cycle is indicated by the clearing of the CSR Busy (CSR_BUSY) bit. Figure 12-11 illustrates the process required to perform a EtherCAT Core CSR write. Minimum wait periods are required where noted. Minimum wait periods are required where noted. The minimum wait periods as specified in Table 5-2, “Read After Write Timing Rules,” on page 35 are required where noted. FIGURE 12-11: ETHERCAT CSR WRITE ACCESS FLOW DIAGRAM CSR Write Idle Write Data Register Write Command Register min wait period Read Command CSR_ BUSY = 0 Register 12.11.3 CSR_ BUSY = 1 ETHERCAT PROCESS RAM READS Process data is transferred from the EtherCAT Core through a 16 deep 32-bit wide FIFO. The FIFO has the base address of 00h, however, it is also accessible at seven additional contiguous memory locations. The Host may access the FIFO at any of these alias port locations, as they all function identically and contain the same data. This alias port addressing is implemented to allow hosts to burst through sequential addresses. For HBI access, the Process RAM Read Data FIFO may also be accessed using FIFO Direct Selection mode. In this mode, the address input is ignored and all read accesses are directed to the Process RAM Read Data FIFO. See Section 9.4.3.1, "FIFO Direct Select Access," on page 68. DS00001909A-page 210 2015 Microchip Technology Inc. LAN9252 To perform a read of the EtherCAT Process RAM, the read cycle is initiated by first writing the EtherCAT Process RAM Read Address and Length Register (ECAT_PRAM_RD_ADDR_LEN) with the starting byte address and length (in bytes) of the desired transfer followed by a write to the EtherCAT Process RAM Read Command Register (ECAT_PRAM_RD_CMD) with the PRAM Read Busy (PRAM_READ_BUSY) bit set. Note: The starting byte address and length must be programmed with valid values such that all transfers are within the bounds of the Process RAM address range of 1000h to 1FFFh. Valid data, as indicated by the PRAM Read Data Available (PRAM_READ_AVAIL) bit in the EtherCAT Process RAM Read Command Register (ECAT_PRAM_RD_CMD) is read from the FIFO through the EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA). The PRAM Read Data Available Count (PRAM_READ_AVAIL_CNT) field indicates how many reads can be performed without needing to check the status again. Following the final read of the EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA), the PRAM Read Busy (PRAM_READ_BUSY) selfclears. Note: The final read of the EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA) implies that all four bytes have been read, even if not all bytes are required. As the data is transferred from the EtherCAT Core into the FIFO the PRAM Read Length (PRAM_READ_LEN) and PRAM Read Address (PRAM_READ_ADDR) are updated to show the progress. Based on the starting address, the valid bytes in the first FIFO read are as follows: TABLE 12-7: ETHERCAT PROCESS RAM VALID FIRST READ BYTES Starting Address[1:0] 00b bytes 3, 2, 1 and 0 01b bytes 3, 2 and 1 10b bytes 3 and 2 11b byte 3 Based on the starting address and length, the valid bytes in the last FIFO read are as follows: TABLE 12-8: ETHERCAT PROCESS RAM VALID LAST READ BYTES Starting Length[1:0] Starting Address[1:0] 01b (e.g. 5, 9, etc.) 10b (e.g. 6, 10, etc.) 11b (e.g. 7, 11, etc.) 00b (e.g. 8, 12, etc.) 00b byte 0 bytes 1 and 0 bytes 2, 1 and 0 bytes 3, 2, 1 and 0 01b bytes 1 and 0 bytes 2, 1 and 0 bytes 3, 2, 1 and 0 byte 0 10b bytes 2, 1 and 0 bytes 3, 2, 1 and 0 byte 0 bytes 1 and 0 11b bytes 3, 2, 1 and 0 byte 0 bytes 1 and 0 bytes 2, 1 and 0 2015 Microchip Technology Inc. DS00001909A-page 211 LAN9252 If the initial length is 4 bytes of less and all bytes fit into one read, the valid bytes in the only FIFO read are as follows: TABLE 12-9: ETHERCAT PROCESS RAM VALID BYTES ONE READ Starting Length Starting Address[1:0] 4 1 2 3 00b bytes 3, 2, 1 and 0 byte 0 bytes 1 and 0 bytes 2, 1 and 0 01b na byte 1 bytes 2 and 1 bytes 3, 2 and 1 10b na byte 2 bytes 3 and 2 na 11b na byte 3 na na 12.11.3.1 Aborting a Read If necessary, a read command can be aborted by setting the PRAM Read Abort (PRAM_READ_ABORT) bit in the EtherCAT Process RAM Read Command Register (ECAT_PRAM_RD_CMD). 12.11.4 ETHERCAT PROCESS RAM WRITES Process data is transferred to the EtherCAT Core through a 16 deep 32-bit wide FIFO. The FIFO has the base address of 20h, however, it is also accessible at seven additional contiguous memory locations. The Host may access the FIFO at any of these alias port locations, as they all function identically and contain the same data. This alias port addressing is implemented to allow hosts to burst through sequential addresses. For HBI access, the Process RAM Write Data FIFO may also be accessed using FIFO Direct Selection mode. In this mode, the address input is ignored and all write accesses are directed to the Process RAM Write Data FIFO. See Section 9.4.3.1, "FIFO Direct Select Access," on page 68. To perform a write to the EtherCAT Process RAM, the write cycle is initiated by first writing the EtherCAT Process RAM Write Address and Length Register (ECAT_PRAM_WR_ADDR_LEN) with the starting byte address and length (in bytes) of the desired transfer followed by a write to the EtherCAT Process RAM Write Command Register (ECAT_PRAM_WR_CMD) with the PRAM Write Busy (PRAM_WRITE_BUSY) bit set. . Note: The starting byte address and length must be programmed with valid values such that all transfers are within the bounds of the Process RAM address range of 1000h to 1FFFh. Data is transferred into the EtherCAT Core through a 16 deep 32-bit wide FIFO. The host may write data to the FIFO through the EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA) when space is available as indicated by the PRAM Write Space Available (PRAM_WRITE_AVAIL) bit in the EtherCAT Process RAM Write Command Register (ECAT_PRAM_WR_CMD). The PRAM Write Space Available Count (PRAM_WRITE_AVAIL_CNT) field indicates how many writes can be performed without needing to check the status again. Following the final write of the data into the EtherCAT Core, the PRAM Write Busy (PRAM_WRITE_BUSY) self-clears. Note: The final write of the EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA) implies that all four bytes have been written, even if not all bytes are required. As the data is transferred to the EtherCAT Core from the FIFO the PRAM Write Length (PRAM_WRITE_LEN) and PRAM Write Address (PRAM_WRITE_ADDR) are updated to show the progress. Based on the starting address, the valid bytes in the first FIFO write are as follows: DS00001909A-page 212 2015 Microchip Technology Inc. LAN9252 TABLE 12-10: ETHERCAT PROCESS RAM VALID FIRST WRITE BYTES Starting Address[1:0] 00b bytes 3, 2, 1 and 0 01b bytes 3, 2 and 1 10b bytes 3 and 2 11b byte 3 Based on the starting address and length, the valid bytes in the last FIFO write are as follows: TABLE 12-11: ETHERCAT PROCESS RAM VALID LAST WRITE BYTES Starting Length[1:0] Starting address[1:0] 01b (e.g. 5, 9, etc.) 10b (e.g. 6, 10, etc.) 11b (e.g. 7, 11, etc.) 00b (e.g. 8, 12, etc.) 00b byte 0 bytes 1 and 0 bytes 2, 1 and 0 bytes 3, 2, 1 and 0 01b bytes 1 and 0 bytes 2, 1 and 0 bytes 3, 2, 1 and 0 byte 0 10b bytes 2, 1 and 0 bytes 3, 2, 1 and 0 byte 0 bytes 1 and 0 11b bytes 3, 2, 1 and 0 byte 0 bytes 1 and 0 bytes 2, 1 and 0 If the initial length is 4 bytes of less and all bytes fit into one write, the valid bytes in the only FIFO write are as follows: TABLE 12-12: ETHERCAT PROCESS RAM VALID BYTES ONE WRITE Starting Length starting address[1:0] 4 1 2 3 00b bytes 3, 2, 1 and 0 byte 0 bytes 1 and 0 bytes 2, 1 and 0 01b na byte 1 bytes 2 and 1 bytes 3, 2 and 1 10b na byte 2 bytes 3 and 2 na 11b na byte 3 na na 12.11.4.1 Aborting a Write If necessary, a write command can be aborted by setting the PRAM Write Abort (PRAM_WRITE_ABORT) bit in the EtherCAT Process RAM Write Command Register (ECAT_PRAM_WR_CMD). 12.12 EtherCAT Reset After writing 0x52 (R), 0x45 (E) and 0x53 (S) into the ESC Reset ECAT Register with 3 consecutive frames or after writing 0x52 (R), 0x45 (E) and 0x53 (S) into the ESC Reset PDI Register with 3 consecutive writes, a device reset (and optional system reset) will occur, as defined in Section 6.2.1.3, "EtherCAT System Reset," on page 40. Note: It is likely that the last frame of the sequence will not return to the master (depending on the topology), because the links to and from the slave which is reset will go down. 2015 Microchip Technology Inc. DS00001909A-page 213 LAN9252 12.13 EtherCAT CSR and Process Data RAM Access Registers (Directly Addressable) This section details the directly addressable System CSRs, outside of the EtherCAT Core, which are related to the EtherCAT Core. For information on how to access EtherCAT registers, refer to Section 12.11, "EtherCAT CSR and Process Data RAM Access," on page 208. The EtherCAT Core registers are detailed in Section 12.14, "EtherCAT Core CSR Registers (Indirectly Addressable)," on page 223. TABLE 12-13: ETHERCAT PROCESS RAM AND CSR ACCESS REGISTERS Address Register Name (Symbol) 000h-01Ch EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA) 020h-03Ch EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA) 300h EtherCAT CSR Interface Data Register (ECAT_CSR_DATA) 304h EtherCAT CSR Interface Command Register (ECAT_CSR_CMD) 308h EtherCAT Process RAM Read Address and Length Register (ECAT_PRAM_RD_ADDR_LEN) 30Ch EtherCAT Process RAM Read Command Register (ECAT_PRAM_RD_CMD) 310h EtherCAT Process RAM Write Address and Length Register (ECAT_PRAM_WR_ADDR_LEN) 314h EtherCAT Process RAM Write Command Register (ECAT_PRAM_WR_CMD) DS00001909A-page 214 2015 Microchip Technology Inc. LAN9252 12.13.1 ETHERCAT PROCESS RAM READ DATA FIFO (ECAT_PRAM_RD_DATA) Offset: 000h-01Ch Size: 32 bits This read only register is used in conjunction with the EtherCAT Process RAM Read Command Register (ECAT_PRAM_RD_CMD) and the EtherCAT Process RAM Read Address and Length Register (ECAT_PRAM_RD_ADDR_LEN) to perform read operations of the EtherCAT Core Process RAM. Data read from this register is only valid if the PRAM Read Data Available (PRAM_READ_AVAIL) bit in the EtherCAT Process RAM Read Command Register (ECAT_PRAM_RD_CMD) is a 1. The host should not read this register unless there is valid data available. Bits 31:0 Description EtherCAT Process RAM Read Data (PRAM_RD_DATA) This field contains the value read from the EtherCAT Core Process RAM. Note: Type Default RO - Some bytes maybe invalid based on the starting address and transfer length. 2015 Microchip Technology Inc. DS00001909A-page 215 LAN9252 12.13.2 ETHERCAT PROCESS RAM WRITE DATA FIFO (ECAT_PRAM_WR_DATA) Offset: 020h-03Ch Size: 32 bits This write only register is used in conjunction with the EtherCAT Process RAM Write Command Register (ECAT_PRAM_WR_CMD) and the EtherCAT Process RAM Write Address and Length Register (ECAT_PRAM_WR_ADDR_LEN) to perform write operations to the EtherCAT Core Process RAM. The host should not write this register unless there is available space as indicated by the PRAM Write Space Available (PRAM_WRITE_AVAIL) bit in the EtherCAT Process RAM Write Command Register (ECAT_PRAM_WR_CMD). Bits 31:0 Description EtherCAT Process RAM Write Data (PRAM_WR_DATA) This field contains the value written to the EtherCAT Core Process RAM. Note: DS00001909A-page 216 Type Default WO - Some bytes maybe invalid based on the starting address and transfer length. 2015 Microchip Technology Inc. LAN9252 12.13.3 ETHERCAT CSR INTERFACE DATA REGISTER (ECAT_CSR_DATA) Offset: 300h Size: 32 bits This read/write register is used in conjunction with the EtherCAT CSR Interface Command Register (ECAT_CSR_CMD) to perform read and write operations with the EtherCAT Core CSRs. Bits Description Type Default 31:0 EtherCAT CSR Data (CSR_DATA) This field contains the value read from or written to the EtherCAT Core CSR. The EtherCAT Core CSR is selected via the CSR Address (CSR_ADDR) bits of the EtherCAT CSR Interface Command Register (ECAT_CSR_CMD). R/W 00000000h Valid data is always written to or read from the lower bits of this field. The H/ W handles any required byte alignment. Upon a read, the value returned depends on the Read/Write (R_nW) bit in the EtherCAT CSR Interface Command Register (ECAT_CSR_CMD). If Read/Write (R_nW) is set, the data is from the EtherCAT Core. If Read/Write (R_nW) is cleared, the data is the value that was last written into this register. 2015 Microchip Technology Inc. DS00001909A-page 217 LAN9252 12.13.4 ETHERCAT CSR INTERFACE COMMAND REGISTER (ECAT_CSR_CMD) Offset: 304h Size: 32 bits This read/write register is used in conjunction with the EtherCAT CSR Interface Data Register (ECAT_CSR_DATA) to perform read and write operations with the EtherCAT Core CSRs. Bits 31 Description Type Default R/W SC 0b R/W 0b CSR Busy (CSR_BUSY) When a 1 is written to this bit, the read or write operation (as determined by the R_nW bit) is performed to the specified EtherCAT Core CSR in CSR Address (CSR_ADDR). This bit will remain set until the operation is complete, at which time the bit will self-clear. In the case of a read, the clearing of this bit indicates to the Host that valid data can be read from the EtherCAT CSR Interface Data Register (ECAT_CSR_DATA). Writing a 0 to this bit has no affect. The host should not modify the ETHERCAT_CSR_CMD and ETHERCAT_CSR_DATA registers unless this bit is a 0. 30 Read/Write (R_nW) This bit determines whether a read or write operation is performed by the Host to the specified EtherCAT Core CSR. 0: Write 1: Read 29:19 RESERVED RO - 18:16 CSR Size (CSR_SIZE) This field specifies the size of the EtherCAT Core CSR in bytes. R/W 0h R/W 00h Valid values are 1, 2 and 4. The host should not use invalid values. Note 4. 15:0 CSR Address (CSR_ADDR) This field selects the EtherCAT Core CSR that will be accessed with a read or write operation. This is a byte address which is the format used to specify the offsets of the EtherCAT Core CSRs. Note 4. Note 4: WORD and DWORD accesses must be aligned on the proper address boundary according to the following table. TABLE 12-14: ETHERCAT CSR ADDRESS VS. SIZE DS00001909A-page 218 CSR_SIZE[2:0] CSR_ADDR[1:0] 1 00b, 01b, 10b, 11b 2 00b, 10b 4 00b 2015 Microchip Technology Inc. LAN9252 12.13.5 ETHERCAT PROCESS RAM READ ADDRESS AND LENGTH REGISTER (ECAT_PRAM_RD_ADDR_LEN) Offset: 308h Size: 32 bits This read/write register is used in conjunction with the EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA) and the EtherCAT Process RAM Read Command Register (ECAT_PRAM_RD_CMD) to perform read operations from the EtherCAT Core Process RAM. Note: The starting byte address and length must be programmed with valid values such that all transfers are within the bounds of the Process RAM address range of 1000h to 1FFFh. Bits Description Type Default 31:16 PRAM Read Length (PRAM_READ_LEN) This field indicates the number of bytes to be read from the EtherCAT Core Process RAM. It is decremented as data is read from the EtherCAT Core and placed into the FIFO. R/W 0000h R/W 0000h The host should not modify this field unless the PRAM Read Busy (PRAM_READ_BUSY) bit is a low. 15:0 PRAM Read Address (PRAM_READ_ADDR) This field indicates the EtherCAT Core byte address to be read. It is incremented as data is read from the EtherCAT Core and placed into the FIFO. Note: The Process RAM starts at address 1000h. The host should not modify this field unless the PRAM Read Busy (PRAM_READ_BUSY) bit is a 0. 2015 Microchip Technology Inc. DS00001909A-page 219 LAN9252 12.13.6 ETHERCAT PROCESS RAM READ COMMAND REGISTER (ECAT_PRAM_RD_CMD) Offset: 30Ch Size: 32 bits This read/write register is used in conjunction with the EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA) and the EtherCAT Process RAM Read Address and Length Register (ECAT_PRAM_RD_ADDR_LEN) to perform read operations from the EtherCAT Core Process RAM. Bits Description Type Default 31 PRAM Read Busy (PRAM_READ_BUSY) When a 1 is written to this bit, the read operation is started beginning at the EtherCAT Core Process RAM location specified in PRAM Read Address (PRAM_READ_ADDR) for the length specified in PRAM Read Length (PRAM_READ_LEN). This bit will remain set until the entire read operation is complete, at which time the bit will self-clear. R/W SC 0b R/W SC 0b Writing a 0 to this bit has no affect. 30 PRAM Read Abort (PRAM_READ_ABORT) Writing a 1 to this bit will cause the read operation in process to be canceled. The PRAM Read Busy (PRAM_READ_BUSY) will be cleared and the Read Data FIFO, along with the status bits, will be reset. This bit will self-clear. Writing a 0 to this bit has no affect. 29:13 RESERVED RO - 12:8 PRAM Read Data Available Count (PRAM_READ_AVAIL_CNT) This field indicates the number of times that the EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA) can be read without further need to check the status. RO 00000b RESERVED RO - PRAM Read Data Available (PRAM_READ_AVAIL) This field indicates that the EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA) has valid data to be read. RO 0b This field increments as data is read from the EtherCAT Core and placed into the FIFO. This field is decremented when the a entire DWORD of data is read from the EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA). 7:1 0 DS00001909A-page 220 2015 Microchip Technology Inc. LAN9252 12.13.7 ETHERCAT PROCESS RAM WRITE ADDRESS AND LENGTH REGISTER (ECAT_PRAM_WR_ADDR_LEN) Offset: 310h Size: 32 bits This read/write register is used in conjunction with the EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA) and the EtherCAT Process RAM Write Command Register (ECAT_PRAM_WR_CMD) to perform write operations to the EtherCAT Core Process RAM. Note: The starting byte address and length must be programmed with valid values such that all transfers are within the bounds of the Process RAM address range of 1000h to 1FFFh. Bits Description Type Default 31:16 PRAM Write Length (PRAM_WRITE_LEN) This field indicates the number of bytes to be written to the EtherCAT Core Process RAM. It is decremented as data is written to the EtherCAT Core from the FIFO. R/W 0000h R/W 0000h The host should not modify this field unless the PRAM Write Busy (PRAM_WRITE_BUSY) bit is a low. 15:0 PRAM Write Address (PRAM_WRITE_ADDR) This field indicates the EtherCAT Core byte address to be written. It is incremented as data is written to the EtherCAT Core from the FIFO. Note: The Process RAM starts at address 1000h. The host should not modify this field unless the PRAM Write Busy (PRAM_WRITE_BUSY) bit is a 0. 2015 Microchip Technology Inc. DS00001909A-page 221 LAN9252 12.13.8 ETHERCAT PROCESS RAM WRITE COMMAND REGISTER (ECAT_PRAM_WR_CMD) Offset: 314h Size: 32 bits This read/write register is used in conjunction with the EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA) and the EtherCAT Process RAM Write Address and Length Register (ECAT_PRAM_WR_ADDR_LEN) to perform write operations to the EtherCAT Core Process RAM. Bits Description Type Default 31 PRAM Write Busy (PRAM_WRITE_BUSY) When a 1 is written to this bit, the write operation is started beginning at the EtherCAT Core Process RAM location specified in PRAM Write Address (PRAM_WRITE_ADDR) for the length specified in PRAM Write Length (PRAM_WRITE_LEN). This bit will remain set until the entire write operation is complete, at which time the bit will self-clear. R/W SC 0b R/W SC 0b Writing a 0 to this bit has no affect. 30 PRAM Write Abort (PRAM_WRITE_ABORT) Writing a 1 to this bit will cause the write operation in process to be canceled. The PRAM Write Busy (PRAM_WRITE_BUSY) will be cleared and the Write Data FIFO, along with the status bits, will be reset. This bit will self-clear. Writing a 0 to this bit has no affect. 29:13 RESERVED RO - 12:8 PRAM Write Space Available Count (PRAM_WRITE_AVAIL_CNT) This field indicates the number of times that the EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA) can be written without further need to check the status. RO 10000b RESERVED RO - PRAM Write Space Available (PRAM_WRITE_AVAIL) This field indicates that the EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA) has available space for data to be written. RO 1b This field is decremented when the a entire DWORD of data is written into the EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA). This field increments as data is read from the FIFO and placed into the EtherCAT Core. 7:1 0 DS00001909A-page 222 2015 Microchip Technology Inc. LAN9252 12.14 EtherCAT Core CSR Registers (Indirectly Addressable) This section details the indirectly addressable EtherCAT Core CSRs, which are accessed via the directly addressable EtherCAT CSR Interface Data Register (ECAT_CSR_DATA) and EtherCAT CSR Interface Command Register (ECAT_CSR_CMD). For information on how to access EtherCAT registers, refer to Section 12.11, "EtherCAT CSR and Process Data RAM Access," on page 208. The directly addressable EtherCAT registers are detailed in Section 12.13, "EtherCAT CSR and Process Data RAM Access Registers (Directly Addressable)," on page 214. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. The read/write behavior of specific EtherCAT Core register bits may differ depending on how the register is accessed. Each EtherCAT Core register includes “ECAT Type” and “PDI Type” columns, which provide the bit/field type for register accesses via an EtherCAT Master Node or Process Data Interface (SPI / Host Bus), respectively. TABLE 12-15: ETHERCAT CORE CSR REGISTERS Address Register Name (Symbol) ESC Information 0000h Type Register 0001h Revision Register 0002h-0003h Build Register 0004h FMMUs Supported Register 0005h SyncManagers Supported Register 0006h RAM Size Register 0007h Port Descriptor Register 0008h-0009h ESC Features Supported Register Station Address 0010h-0011h Configured Station Register 0012h-0013h Configured Station Alias Register Write Protection 0020h Write Register Enable Register 0021h Write Register Protection Register 0030h ESC Write Register Enable Register 0031h ESC Write Register Protection Register Data Link Layer 0040h ESC Reset ECAT Register 0041h ESC Reset PDI Register 0100h-0103h ESC DL Control Register 0108h-0109h Physical Read/Write Offset Register 0110h-0111h ESC DL Status Register Application Layer 0120h-0121h AL Control Register 0130h-0131h AL Status Register 0134h-0135h AL Status Code Register 0138h RUN LED Override Register 0139h Reserved PDI (Process Data Interface) 0140h PDI Control Register 2015 Microchip Technology Inc. DS00001909A-page 223 LAN9252 TABLE 12-15: ETHERCAT CORE CSR REGISTERS Address 0141h Register Name (Symbol) ESC Configuration Register 0142h-0143h ASIC Configuration Register 0144h-0145h RESERVED Register 0150h PDI Configuration Register 0151h Sync/Latch PDI Configuration Register 0152h-0153h Extended PDI Configuration Register Interrupts 0200h-0201h ECAT Event Mask Register 0204h-0207h AL Event Mask Register 0210h-0211h ECAT Event Request Register 0220h-0223h AL Event Request Register Error Counters 0300h-0307h RX Error Counter Registers 0308h-030Bh Forwarded RX Error Counter Registers 030Ch ECAT Processing Unit Error Counter Register 030Dh PDI Error Counter Register 030Eh PDI Error Code Register 0310h-0313h Lost Link Counter Registers Watchdogs 0400h-0401h Watchdog Divider Register 0410h-0411h Watchdog Time PDI Register 0420h-0421h Watchdog Time Process Data Register 0440h-0441h Watchdog Status Process Data Register 0442h Watchdog Counter Process Data Register 0443h Watchdog Counter PDI Register 0500h EEPROM Configuration Register 0501h EEPROM PDI Access State Register EEPROM Interface 0502h-0503h EEPROM Control/Status Register 0504h-0507h EEPROM Address Register 0508h-050Bh EEPROM Data Register MII Management Interface 0510h-0511h MII Management Control/Status Register 0512h PHY Address Register 0513h PHY Register Address Register 0514h-0515h PHY DATA Register 0516h MII Management ECAT Access State Register 0517h MII Management PDI Access State Register 0518h-051Bh PHY Port Status Registers 0600h-062Fh FMMU[2:0] Registers (3x16 bytes) +0h-3h FMMUx Logical Start Address Register +4h-5h FMMUx Length Register +6h FMMUx Logical Start Bit Register +7h FMMUx Logical Stop Bit Register DS00001909A-page 224 2015 Microchip Technology Inc. LAN9252 TABLE 12-15: ETHERCAT CORE CSR REGISTERS Address +8h-9h Register Name (Symbol) FMMUx Physical Start Address Register +Ah FMMUx Physical Start Bit Register +Bh FMMUx Type Register +Ch FMMUx Activate Register +Dh-Fh FMMUx Reserved Register 0630h-06FFh Reserved 0800h-081Fh SyncManager[3:0] Registers (4x8 bytes) +0h-1h SyncManager x Physical Start Address Register +2h-3h SyncManager x Length Register +4h SyncManager x Control Register +5h SyncManager x Status Register +6h SyncManager x Activate Register +7h SyncManager x PDI Control Register 0820h-087Fh Reserved 0900h-09FFh Distributed Clocks (DC) Distributed Clocks - Receive Times 0900h-0903h Receive Time Port 0 Register 0904h-0907h Receive Time Port 1 Register 0908h-090Bh Receive Time Port 2 Register 090Ch-090Fh Reserved Distributed Clocks - Time Loop Control Unit 0910h-0917h System Time Register 0918h-091Fh Receive Time ECAT Processing Unit Register 0920h-0927h System Time Offset Register 0928h-092Bh System Time Delay Register 092Ch-092Fh System Time Difference Register 0930h-0931h Speed Counter Start Register 0932h-0933h Speed Counter Diff Register 0934h System Time Difference Filter Depth Register 0935h Speed Counter Filter Depth Register Distributed Clocks - Cyclic Unit Control 0980h Cyclic Unit Control Register Distributed Clocks - SYNC Out Unit 0981h Activation Register 0982h-0983h Pulse Length of SyncSignals Register 0984h Activation Status Register 098Eh SYNC0 Status Register 098Fh SYNC1 Status Register 0990h-0997h Start Time Cyclic Operation Register 0998h-099Fh Next SYNC1 Pulse Register 09A0h-09A3h SYNC0 Cycle Time Register 09A4h-09A7h SYNC1 Cycle Time Register Distributed Clocks - Latch In Unit 09A8h LATCH0 Control Register 2015 Microchip Technology Inc. DS00001909A-page 225 LAN9252 TABLE 12-15: ETHERCAT CORE CSR REGISTERS Address Register Name (Symbol) 09A9h LATCH1 Control Register 09AEh LATCH0 Status Register 09AFh LATCH1 Status Register 09B0h-09B7h LATCH0 Time Positive Edge Register 09B8h-09BFh LATCH0 Time Negative Edge Register 09C0h-09C7h LATCH1 Time Positive Edge Register 09C8h-09CFh LATCH1 Time Negative Edge Register Distributed Clocks - SyncManager Event Times 09F0h-09F3h EtherCAT Buffer Change Event Time Register 09F8h-09FBh PDI Buffer Start Time Event Register 09FCh-09FFh PDI Buffer Change Event Time Register ESC Specific 0E00h-0E07h Product ID Register 0E08h-0E0Fh Vendor ID Register Digital Input/Output 0F00h-0F01h Digital I/O Output Data Register 0F10h-0F11h General Purpose Output Register 0F18h-0F19h General Purpose Input Register User RAM 0F80h-0FFFh User RAM Process Data RAM 1000h-1001h Digital I/O Input Data Register 1000h-1FFFh Process Data RAM DS00001909A-page 226 2015 Microchip Technology Inc. LAN9252 12.14.1 TYPE REGISTER Offset: Bits 7:0 12.14.2 0000h Description EtherCAT Controller Type C0h = Microchip. Bits 12.14.3 0001h EtherCAT Controller Revision ECAT Type PDI Type Default RO RO C0h ECAT Type PDI Type Default RO RO 02h ECAT Type PDI Type Default RO RO 0000h 8 bits BUILD REGISTER Bits Note: Size: Description Offset: 15:0 8 bits REVISION REGISTER Offset: 7:0 Size: 0002h-0003h Description EtherCAT Controller Build [7:4] = minor version [3:0] = Maintenance version Size: 16 bits For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 2015 Microchip Technology Inc. DS00001909A-page 227 LAN9252 12.14.4 FMMUS SUPPORTED REGISTER Offset: 0004h Size: Bits Description 7:0 Supported FMMUs This field details the number of supported FMMU channels (or entities) of the EtherCAT slave controller. The device provides 3. 12.14.5 Bits 12.14.6 ECAT Type PDI Type Default RO RO 03h ECAT Type PDI Type Default RO RO 04h ECAT Type PDI Type Default RO RO 04h SYNCMANAGERS SUPPORTED REGISTER Offset: 7:0 8 bits 0005h Size: Description Supported SyncManagers This field details the number of supported SyncManager channels (or entities) of the EtherCAT slave controller. The device provides 4. 8 bits RAM SIZE REGISTER Offset: 0006h Size: Bits Description 7:0 Process Data RAM Size This field details the process data RAM size included in the EtherCAT slave controller. The device provides 4KB. DS00001909A-page 228 8 bits 2015 Microchip Technology Inc. LAN9252 12.14.7 PORT DESCRIPTOR REGISTER Offset: Bits 0007h Description Size: 8 bits ECAT Type PDI Type Default 00b 7:6 Port 3 Configuration This field details the Port 3 configuration. 00: Not implemented 01: Not configured 10: EBUS 11: MII/RMII RO RO 5:4 Port 2 Configuration This field details the Port 2 configuration. 00: Not implemented 01: Not configured 10: EBUS 11: MII/RMII RO RO 3:2 Port 1 Configuration This field details the Port 1 configuration. 00: Not implemented 01: Not configured 10: EBUS 11: MII/RMII RO RO 11b 1:0 Port 0 Configuration This field details the Port 0 configuration. 00: Not implemented 01: Not configured 10: EBUS 11: MII/RMII RO RO 11b 2015 Microchip Technology Inc. 11b (3-port operation) 01b (2-port operation) See Section 14.0 “Chip Mode Configuration” DS00001909A-page 229 LAN9252 12.14.8 ESC FEATURES SUPPORTED REGISTER Offset: 0008h-0009h Size: 16 bits ECAT Type PDI Type Default RESERVED RO RO 0h 11 Fixed FMMU/SyncManager Configuration 0: Variable configuration 1: Fixed configuration RO RO 0b 10 EtherCAT Read/Write Command Support 0: Supported 1: Not supported RO RO 0b 9 EtherCAT LRW Command Support 0: Supported 1: Not supported RO RO 0b 8 Enhanced DC SYNC Activation 0: Not available 1: Available RO RO 1b Bits 15:12 Description Note: This feature refers to the Activation Register and Activation Status Register 7 Separate Handling of FCS Errors 0: Not supported 1: Supported, frame with wrong FCS and additional nibble will be counted separately in Forwarded RX Counter RO RO 1b 6 Enhanced Link Detection MII 0: Not available 1: Available RO RO 1b 5 Enhanced Link Detection EBUS 0: Not available 1: Available RO RO 0b 4 Low Jitter EBUS 0: Not available, standard jitter 1: Available, jitter minimized RO RO 0b 3 Distributed Clocks (width) 0: 32-bit 1: 64-bit RO RO 1b 2 Distributed Clock 0: Not available 1: Available RO RO 1b 1 RESERVED RO RO 0b 0 FMMU Operation 0: Bit oriented 1: Byte oriented RO RO 0b DS00001909A-page 230 2015 Microchip Technology Inc. LAN9252 Note: 12.14.9 For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. CONFIGURED STATION REGISTER Offset: 0010h-0011h Size: Bits Description 15:0 Configured Station Address This field contains the address used for node addressing (FPxx commands) Note: 16 bits ECAT Type PDI Type Default R/W RO 0000h For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.10 CONFIGURED STATION ALIAS REGISTER Offset: Bits 15:0 0012h-0013h Size: Description Configured Station Alias Address This field contains the alias address used for node addressing (FPxx commands). The use of this alias is activated by the Station Alias bit of the ESC DL Control Register. Note: 16 bits ECAT Type PDI Type RO R/W Default 0000h Note 5 EEPROM value is only taken over at first EEPROM load after lower-on reset. Note 5: The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.11 WRITE REGISTER ENABLE REGISTER Offset: 2015 Microchip Technology Inc. 0020h Size: 8 bits DS00001909A-page 231 LAN9252 ECAT Type PDI Type Default RESERVED Write 0. RO RO 0000000b Write Register Enable If write protection is enabled, this register must be written in the same Ethernet frame (value is a don’t care) before other writes to this station are allowed. Write protection is still active after this frame (if the Write Register Protection Register is not changed) R/W RO 0b Bits 7:1 0 Description DS00001909A-page 232 2015 Microchip Technology Inc. LAN9252 12.14.12 WRITE REGISTER PROTECTION REGISTER Offset: 0 Size: 8 bits ECAT Type PDI Type Default RESERVED Write 0. RO RO 0000000b Write Register Protection 0: Protection disabled 1: Protection enabled R/W RO 0b ECAT Type PDI Type Default RESERVED Write 0. RO RO 0000000b ESC Write Register Enable If ESC write protection is enabled, this register must be written in the same Ethernet frame (value is a don’t care) before other writes to this station are allowed. ESC write protection is still active after this frame (if the ESC Write Register Protection Register is not changed) R/W RO 0b Bits 7:1 0021h Description Note: Registers 0000h-0F0Fh are write protected, except for 0030h. 12.14.13 ESC WRITE REGISTER ENABLE REGISTER Offset: Bits 7:1 0 0030h Size: Description 2015 Microchip Technology Inc. 8 bits DS00001909A-page 233 LAN9252 12.14.14 ESC WRITE REGISTER PROTECTION REGISTER Offset: 0031h Size: 8 bits ECAT Type PDI Type Default RESERVED Write 0. RO RO 0000000b ESC Write Register Protection 0: Protection disabled 1: Protection enabled R/W RO 0b ECAT Type PDI Type Default ESC Reset ECAT A reset is asserted after writing 52h (”R”), 45h (“E”), and 53h (“S”) in this register with 3 consecutive commands. R/W RO 00h 7:2 RESERVED RO RO 000000b 1:0 Reset Procedure Progress 01: After writing 52h 10: After writing 45h (if 52h previously written) 00: Else R/W RO 00b Bits 7:1 0 Description Note: All areas are write protected, except for 0030h. 12.14.15 ESC RESET ECAT REGISTER Offset: Bits 0040h Size: Description 8 bits Write 7:0 Read DS00001909A-page 234 2015 Microchip Technology Inc. LAN9252 12.14.16 ESC RESET PDI REGISTER Offset: 0041h Size: 8 bits ECAT Type PDI Type Default ESC Reset PDI A reset is asserted after writing 52h (”R”), 45h (“E”), and 53h (“S”) in this register with 3 consecutive commands. RO R/W 00h 7:2 RESERVED RO RO 000000b 1:0 Reset Procedure Progress 01: After writing 52h 10: After writing 45h (if 52h previously written) 00: Else RO R/W 00b Bits Description Write 7:0 Read 2015 Microchip Technology Inc. DS00001909A-page 235 LAN9252 12.14.17 ESC DL CONTROL REGISTER Offset: 24 23:20 19 18:16 Size: 32 bits ECAT Type PDI Type Default RESERVED Write 0. RO RO 0000000b Station Alias 0: Ignore station alias 1: Alias can be used for all configured address command types (FPRD, FPWR, etc.) R/W RO 0b RESERVED Write 0. RO RO 0000b EBUS Low Jitter 0: Normal jitter 1: Reduced jitter R/W RO 0b RX FIFO Size/RX Delay Reduction (ESC delays start of forwarding until FIFO is at least half full) See Note 6. R/W RO 111b RO RO 00b Bits 31:25 0100h-0103h Description 000: 001: 010: 011: 100: 101: 110: 111: EBUS -50 ns -40 ns -30 ns -20 ns -10 ns No change No change Default MII -40 ns -40 ns -40 ns -40 ns No change No change No change Default 15:14 RESERVED Write 0. 13:12 Loop Port 2 00: Auto. 01: Auto Close. 10: Open. 11: Closed. R/W Note 7 RO 00b 11:10 Loop Port 1 00: Auto. 01: Auto Close. 10: Open. 11: Closed. R/W Note 7 RO 00b 9:8 Loop Port 0 00: Auto. 01: Auto Close. 10: Open. 11: Closed. R/W Note 7 RO 00b 7:2 RESERVED Write 0. RO RO 000000b DS00001909A-page 236 2015 Microchip Technology Inc. LAN9252 Bits Description ECAT Type PDI Type Default 1 Temporary Use of Register 0101h Settings 0: Permanent Use 1: Temporarily use for ~1 s, then revert to previous settings. R/W RO 0b 0 Forwarding Rule 0: EtherCAT frames are processed, Non-EtherCAT frames are forwarded without processing 1: EtherCAT frame are processed, Non-EtherCAT frames are destroyed. R/W RO 1b The source MAC address is changed for every frame (SOURCE_MAC[1] is set to 1 - locally administered address) regardless of the forwarding rule. Note 6: The possibility of RX FIFO Size reduction depends on the clock source accuracy of the ESC and of every connected EtherCAT/Ethernet device (master, slave, etc.). RX FIFO Size of 111b is sufficient for 100ppm accuracy, RX FIFO Size 000b is possible with 25ppm accuracy (frame size of 1518/1522 Byte). Note 7: Loop configuration changes are delayed until the end of a currently received or transmitted frame at the port. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.18 PHYSICAL READ/WRITE OFFSET REGISTER Offset: Bits 15:0 Note: 0108h-0109h Size: Description Physical Read/Write Offset Offset of R/W commands (FPRW, APRW) between Read address and Write address. RD_ADR - ADR and WR_ADR = ADR + R/W-offset. 16 bits ECAT Type PDI Type Default R/W RO 0b For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 2015 Microchip Technology Inc. DS00001909A-page 237 LAN9252 12.14.19 ESC DL STATUS REGISTER Offset: 0110h-0111h Size: 16 bits ECAT Type PDI Type Default RESERVED RO RO 00b 13 Communication on Port 2 0: No stable communication 1: Communication established RO RO 0b 12 Loop Port 2 0: Open. 1: Closed. RO RO 0b 11 Communication on Port 1 0: No stable communication 1: Communication established RO RO 0b 10 Loop Port 1 0: Open. 1: Closed. RO RO 0b 9 Communication on Port 0 0: No stable communication 1: Communication established RO RO 0b 8 Loop Port 0 0: Open. 1: Closed. RO RO 0b 7 RESERVED RO RO 0b 6 Physical Link on Port 2 0: No link 1: Link detected RO RO 0b 5 Physical Link on Port 1 0: No link 1: Link detected RO RO 0b 4 Physical Link on Port 0 0: No link 1: Link detected RO RO 0b 3 RESERVED RO RO 0b 2 Enhanced Link Detection 0: Deactivated for all ports 1: Activated for at least one port RO RO Bits 15:14 Description Note: 1 EEPROM value is only taken over at first EEPROM load after power-on reset. PDI Watchdog Status 0: Watchdog expired 1: Watchdog reloaded DS00001909A-page 238 0b (until first EEPROM load, then EEPROM ADR 0000h bit 9 or 0000h[15:12]) RO RO 0b 2015 Microchip Technology Inc. LAN9252 Bits Description 0 PDI Operational/EEPROM Loaded Correctly 0: EEPROM not loaded, PDI not operational (no access to Process Data RAM) 1: EEPROM loaded correctly, PDI operational (access to Process Data RAM) Note: ECAT Type PDI Type Default RO RO 0b Reading this register from ECAT clears the DL Status Event bit in the ECAT Event Request Register. For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.20 AL CONTROL REGISTER Offset: 4 3:0 Size: 16 bits ECAT Type PDI Type Default RESERVED Write as 0. R/W Note 8 R/WC 000h Error Ind Ack 0: No Ack of Error Ind in AL status register 1: Ack of Error Ind in AL status register R/W Note 8 R/WC 0b Initiate State Transition of Device State Machine 1h: Request Init State 2h: Request Pre-Operational State 3h: Request Bootstrap State 4h: Request Safe-Operational State 8h: Request Operational State R/W Note 8 R/WC 1h Bits 15:5 0120h-0121h Description Note 8: This register behaves like a mailbox if Device Emulation is off (Device Emulation bit of ESC Configuration Register is 0). The PDI must read this register after ECAT has written it. Otherwise, ECAT can not write again to this register. After rest, this register can be written by ECAT. Regarding mailbox functionality, both registers 0120h and 0121h are equivalent, e.g., reading 0121h is sufficient to make this register writable again. If Device Emulation is on, this register can always be written and it contents are copied to the AL Status Register. Reading this register from PDI clears all Event Requests (register 0220h bit 0). Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 2015 Microchip Technology Inc. DS00001909A-page 239 LAN9252 12.14.21 AL STATUS REGISTER Offset: 4 3:0 Size: 16 bits ECAT Type PDI Type RESERVED Write as 0. RO R/W Note 9 000h Error Ind 0: Device is in state as requested or Flag cleared by command 1: Device has not entered requested state or changed state as a result of a local action RO R/W Note 9 0b Actual State of the Device State Machine 1h: Init State 2h: Pre-Operational State 3h: Bootstrap State 4h: Safe-Operational State 8h: Operational State RO R/W Note 9 1h Bits 15:5 0130h-0131h Description Default Note 9: This register is only writable if Device Emulation is off (Device Emulation bit of ESC Configuration Register is 0). Otherwise, this register will reflect the AL Control Register values. Reading this register from ECAT clears the AL Status Event bit in the ECAT Event Request Register. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.22 AL STATUS CODE REGISTER Offset: Bits 15:0 Note: 0134h-0135h Description AL Status Code Size: 16 bits ECAT Type PDI Type Default RO R/W 0000h For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. DS00001909A-page 240 2015 Microchip Technology Inc. LAN9252 12.14.23 RUN LED OVERRIDE REGISTER Offset: 4 3:0 8 bits PDI Type Default RESERVED Write 0. R/W R/W 000b RUN Override 0: Override disabled 1: Override enabled R/W R/W 0b RUN LED Code R/W R/W 0h Description 0h: 1h-Ch: Dh: Eh: Fh: Note: Size: ECAT Type Bits 7:5 0138h Code Off Flash 1x-12x Blinking Flickering On FSM State 1 - Init 4 - SafeOp 1x 2 - PreOp 3 - Bootstrap 8 - Op Changes to AL Status Register with valid values will disable RUN Override (bit 4 = 0). The value read in this register always reflects the current LED output. 2015 Microchip Technology Inc. DS00001909A-page 241 LAN9252 12.14.24 PDI CONTROL REGISTER Offset: Bits 7:0 0140h Description Process Data Interface 04h: Digital I/O 80h: SPI 88h: HBI Multiplexed 1 Phase 8-bit 89h: HBI Multiplexed 1 Phase 16-bit 8Ah: HBI Multiplexed 2 Phase 8-bit 8Bh: HBI Multiplexed 2 Phase 16-bit 8Ch: HBI Indexed 8-bit 8Dh: HBI Indexed 16-bit Others: RESERVED Size: 8 bits ECAT Type PDI Type RO RO Default 00h Note 10 Note 10: The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. DS00001909A-page 242 2015 Microchip Technology Inc. LAN9252 12.14.25 ESC CONFIGURATION REGISTER Offset: Bits 0141h Size: Description 8 bits ECAT Type PDI Type Default 7 RESERVED RO RO 0b 6 Enhanced Link Port 2 0: Disabled (if bit 1 = 0) 1: Enabled RO RO 0b Note 11 5 Enhanced Link Port 1 0: Disabled (if bit 1 = 0) 1: Enabled RO RO 0b Note 11 4 Enhanced Link Port 0 0: Disabled (if bit 1 = 0) 1: Enabled RO RO 0b Note 11 3 Distributed Clocks Latch In Unit 0: Disabled (power saving) 1: Enabled RO RO 0b RO RO 0b Note: 2 This bit has no affect. Distributed Clocks SYNC Out Unit 0: Disabled (power saving) 1: Enabled Note: This bit has no affect. 1 Enhanced Link Detection All Ports 0: Disabled (if bits [7:4] = 0) 1: Enabled all ports RO RO 0b Note 11 0 Device Emulation (control of AL Status Register) 0: AL Status Register must be set by PDI 1: AL Status Register set to value written to AL Control Register RO RO 0b Note 11 Note: The value programmed should be 1 for Digital I/O mode and 0 for applications with a host controller. Note 11: The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. Note: This register is initialized from the contents of the EEPROM. The EEPROM settings for Enhanced Link detection (bits 6,5,4,1) are only taken at the first EEPROM loading after power-on reset. Changing the EEPROM and manually reloading it will not affect the Enhanced link detection enable status, even if the EEPROM could not be read initially. 2015 Microchip Technology Inc. DS00001909A-page 243 LAN9252 12.14.26 ASIC CONFIGURATION REGISTER Offset: 14:6 7 6:0 Size: 16 bits ECAT Type PDI Type MI Link Detection (Link configuration, link detection, registers PHY Port Status Registers) 0: Not available 1: MI Link Detection Active RO RO 0b Note 12 RESERVED RO RO 0000000b Note 12 MI Write Gigabit Register 9 Enable Enables writes to PHY register 9 for PHYs which use this register per IEEE 802.3 0: MI writes to Gigabit register 9 disabled 1: MI writes to Gigabit register 9 enabled RO RO 0b Note 12 RESERVED RO RO 0000000b Note 12 Bits 15 0142h-0143h Description Default Note 12: The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.27 RESERVED REGISTER Offset: Bits 15:0 0144h-0145h Description RESERVED Size: 16 bits ECAT Type PDI Type RO RO Default 0000h Note 13 Note 13: The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. DS00001909A-page 244 2015 Microchip Technology Inc. LAN9252 12.14.28 PDI CONFIGURATION REGISTER Offset: 0150h Size: 8 bits The bit definitions of this register are dependent on the selected PDI mode (Process Data Interface field in the PDI Control Register): Digital I/O Mode or HBI Modes. PDI Configuration Register: Digital I/O Mode ECAT Type PDI Type RO RO 00b Note 14 Input Data Sample Selection 00: End of Frame 01: Rising edge of LATCH_IN 10: DC SYNC0 event 11: DC SYNC1 event RO RO 00b Note 14 3 Watchdog Behavior 0: Outputs are reset immediately after watchdog expires 1: Outputs are reset with next output event that follows watchdog expiration RO RO 0b Note 14 2 Unidirectional/Bidirectional Mode 0: Unidirectional Mode: input/output direction of pins configured individually 1: Bidirectional Mode: all I/O pins are bidirectional, direction configuration is ignored RO RO 0b Note 14 1 OUTVALID Mode 0: Output event signaling 1: Process Data Watchdog trigger (WD_TRIG) signaling on OUTVALID. Output data is updated if watchdog is triggered. Overrides Output Data Sample Selection bit. RO RO 0b Note 14 0 OUTVALID Polarity 0: Active high 1: Active low RO RO 0b Note 14 Bits 7:6 Description Output Data Sample Selection 00: End of Frame 01: RESERVED 10: DC SYNC0 event 11: DC SYNC1 event Note: 5:4 Default If OUTVALID Mode = 1, output DATA is updated at Process Data Watchdog trigger event (Output Data Sample Selection bit ignored) Note 14: The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. 2015 Microchip Technology Inc. DS00001909A-page 245 LAN9252 PDI Configuration Register: HBI Modes Bits Description ECAT Type PDI Type Default 7 HBI ALE Qualification Configures the HBI interface to qualify the ALEHI and ALELO signals with the CS signal. 0: Address input is latched with ALEHI and ALELO 1: Address input is latched with ALEHI and ALELO only when CS is active. RO RO 0b Note 15 6 HBI Read/Write Mode Configures the HBI interface for separate read and write signals or direction and enable signals. 0: Read and Write 1: Direction and Enable RO RO 0b Note 15 5 HBI Chip Select Polarity Configures the polarity of the HBI interface chip select signal. 0: Active Low 1: Active High RO RO 0b Note 15 4 HBI Read, Read/Write Polarity Configures the polarity of the HBI interface read signal. 0: Active Low Read 1: Active High Read RO RO 0b Note 15 RO RO 0b Note 15 HBI ALE Polarity Configures the polarity of the HBI interface ALEHI and ALELO signals. 0: Active Low Strobe (Address saved on rising edge) 1: Active High Strobe (Address saved on falling edge) RO RO 0b Note 15 RESERVED RO RO 00b Note 15 Configures the polarity of the HBI interface read/write signal. 0: Read when 1, write when 0 (R/nW) 1: Write when 1, read when 0 (W/nR) 3 HBI Write, Enable Polarity Configures the polarity of the HBI interface write signal. 0: Active Low Write 1: Active High Write Configures the polarity of the HBI interface read/write signal. 0: Active Low Enable 1: Active High Enable 2 1:0 Note 15: The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. DS00001909A-page 246 2015 Microchip Technology Inc. LAN9252 12.14.29 SYNC/LATCH PDI CONFIGURATION REGISTER Offset: Bits 0151h Size: Description 8 bits ECAT Type PDI Type Default 7 SYNC1 Map SYNC1 mapped to AL Event Request Register (0220h bit 3) 0: Disabled 1: Enabled RO RO 0b Note 16 6 SYNC1/LATCH1 Configuration 0: LATCH1 Input 1: SYNC1 Output RO RO 0b Note 16 5:4 SYNC1 Output Driver/Polarity 00: Push-Pull Active Low 01: Open Drain (Active Low) 10: Push-Pull Active High 11: Open Source (Active High) RO RO 00b Note 16 3 SYNC0 Map SYNC0 mapped to AL Event Request Register (0220h bit 2) 0: Disabled 1: Enabled RO RO 0b Note 16 2 SYNC0/LATCH0 Configuration 0: LATCH0 Input 1: SYNC0 Output RO RO 0b Note 16 1:0 SYNC0 Output Driver/Polarity 00: Push-Pull Active Low 01: Open Drain (Active Low) 10: Push-Pull Active High 11: Open Source (Active High) RO RO 00b Note 16 Note 16: The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. 2015 Microchip Technology Inc. DS00001909A-page 247 LAN9252 12.14.30 EXTENDED PDI CONFIGURATION REGISTER Offset: 0152h-0153h Size: 16 bits The bit definitions of this register are dependent on the selected PDI mode (Process Data Interface field in the PDI Control Register): Digital I/O Mode or SPI Mode. Extended PDI Configuration Register: Digital I/O Mode ECAT Type PDI Type Default RESERVED RO RO 0000h I/O[15:14] Direction 0: Input 1: Output RO RO 0b Note 17 RO RO 0b Note 17 RO RO 0b Note 17 RO RO 0b Note 17 RO RO 0b Note 17 RO RO 0b Note 17 RO RO 0b Note 17 RO RO 0b Note 17 Bits 15:8 7 Description Note: 6 I/O[13:12] Direction 0: Input 1: Output Note: 5 Reserved in bidirectional mode (0b). I/O[3:2] Direction 0: Input 1: Output Note: 0 Reserved in bidirectional mode (0b). I/O[5:4] Direction 0: Input 1: Output Note: 1 Reserved in bidirectional mode (0b). I/O[7:6] Direction 0: Input 1: Output Note: 2 Reserved in bidirectional mode (0b). I/O[9:8] Direction 0: Input 1: Output Note: 3 Reserved in bidirectional mode (0b). I/O[11:10] Direction 0: Input 1: Output Note: 4 Reserved in bidirectional mode (0b). Reserved in bidirectional mode (0b). I/O[1:0] Direction 0: Input 1: Output Note: Reserved in bidirectional mode (0b). Note 17: The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. DS00001909A-page 248 2015 Microchip Technology Inc. LAN9252 PDI Configuration Register: SPI Mode Bits Description ECAT Type PDI Type Default 15 I/O[15:14] Buffer Type 0: Push-Pull 1: Open Drain RO RO 0b Note 18 14 I/O[13:12] Buffer Type 0: Push-Pull 1: Open Drain RO RO 0b Note 18 13 I/O[11:10] Buffer Type 0: Push-Pull 1: Open Drain RO RO 0b Note 18 12 I/O[9:8] Buffer Type 0: Push-Pull 1: Open Drain RO RO 0b Note 18 11 I/O[7:6] Buffer Type 0: Push-Pull 1: Open Drain RO RO 0b Note 18 10 I/O[5:4] Buffer Type 0: Push-Pull 1: Open Drain RO RO 0b Note 18 9 I/O[3:2] Buffer Type 0: Push-Pull 1: Open Drain RO RO 0b Note 18 8 I/O[1:0] Buffer Type 0: Push-Pull 1: Open Drain RO RO 0b Note 18 7 I/O[15:14] Direction 0: Input 1: Output RO RO 0b Note 18 6 I/O[13:12] Direction 0: Input 1: Output RO RO 0b Note 18 5 I/O[11:10] Direction 0: Input 1: Output RO RO 0b Note 18 4 I/O[9:8] Direction 0: Input 1: Output RO RO 0b Note 18 3 I/O[7:6] Direction 0: Input 1: Output RO RO 0b Note 18 2 I/O[5:4] Direction 0: Input 1: Output RO RO 0b Note 18 1 I/O[3:2] Direction 0: Input 1: Output RO RO 0b Note 18 2015 Microchip Technology Inc. DS00001909A-page 249 LAN9252 Bits 0 Description I/O[1:0] Direction 0: Input 1: Output ECAT Type PDI Type RO RO Default 0b Note 18 Note 18: The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.31 ECAT EVENT MASK REGISTER Offset: 0200h-0201h Size: Bits Description 15:0 ECAT Event Mask ECAT event masking of the ECAT Event Request register Events for mapping into the ECAT event fields of EtherCAT frames. 0: Corresponding ECAT Event Request register bit is not mapped 1: Corresponding ECAT Event Request register bit is mapped Note: 16 bits ECAT Type PDI Type Default R/W RO 0000h For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.32 AL EVENT MASK REGISTER Offset: Bits 31:0 Note: 0204h-0207h Size: Description AL Event Mask AL event masking of the AL Event Request register Events for mapping to the PDI IRQ signal. 0: Corresponding AL Event Request register bit is not mapped 1: Corresponding AL Event Request register bit is mapped 32 bits ECAT Type PDI Type Default RO R/W 00FFFF0Fh For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. DS00001909A-page 250 2015 Microchip Technology Inc. LAN9252 12.14.33 ECAT EVENT REQUEST REGISTER Offset: 0210h-0211h Size: 16 bits ECAT Type PDI Type Default RESERVED RO RO 00h 7 SyncManager Status Mirror This bit mirrors the value of the SyncManager Channel 3 Status. 0: No Sync Channel 3 Event 1: Sync Channel 3 Event Pending RO RO 0b 6 SyncManager Status Mirror This bit mirrors the value of the SyncManager Channel 2 Status. 0: No Sync Channel 2 Event 1: Sync Channel 2 Event Pending RO RO 0b 5 SyncManager Status Mirror This bit mirrors the value of the SyncManager Channel 1 Status. 0: No Sync Channel 1 Event 1: Sync Channel 1 Event Pending RO RO 0b 4 SyncManager Status Mirror This bit mirrors the value of the SyncManager Channel 0 Status. 0: No Sync Channel 0 Event 1: Sync Channel 0 Event Pending RO RO 0b 3 AL Status Event 0: No change in AL Status 1: AL Status Change RO RO 0b RO RO 0b Bits 15:8 Description Note: 2 This bit is cleared by reading the AL Status Register from ECAT. DL Status Event 0: No change in DL Status 1: DL Status Change Note: This bit is cleared by reading the ESC DL Status Register from ECAT. 1 RESERVED RO RO 0b 0 DC Latch Event 0: No change on DC Latch Inputs 1: At least one change on DC Latch Inputs RO RO 0b Note: Note: This bit is cleared by reading the DC Latch event times from ECAT for ECAT controlled Latch Units, so that the LATCH0 Status Register/LATCH1 Status Register indicates no event. For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 2015 Microchip Technology Inc. DS00001909A-page 251 LAN9252 12.14.34 AL EVENT REQUEST REGISTER Offset: 0220h-0223h Size: 32 bits ECAT Type PDI Type Default RESERVED RO RO 000h 11 SyncManager 3 Interrupts (SyncManager register offset 5h, bit 0 or 1) 0: No SyncManager 3 Interrupt 1: SyncManager 3 Interrupt pending RO RO 0b 10 SyncManager 2 Interrupts (SyncManager register offset 5h, bit 0 or 1) 0: No SyncManager 2 Interrupt 1: SyncManager 2 Interrupt pending RO RO 0b 9 SyncManager 1 Interrupts (SyncManager register offset 5h, bit 0 or 1) 0: No SyncManager 1 Interrupt 1: SyncManager 1 Interrupt RO RO 0b 8 SyncManager 0 Interrupts (SyncManager register offset 5h, bit 0 or 1) 0: No SyncManager 0 Interrupt 1: SyncManager 0 Interrupt pending RO RO 0b 7 RESERVED RO RO 0b 6 Watchdog Process Data 0: Has not expired 1: Has expired RO RO 0b RO RO 0b Bits 31:12 Description Note: 5 This bit is cleared by reading the Watchdog Status Process Data Register. EEPROM Emulation 0: No command pending 1: EEPROM command pending Note: This bit is cleared by acknowledging the command in EEPROM Control/Status Register from PDI. 4 SyncManager x Activation Register Changed (SyncManager x Activate Register) 0: No change in any SyncManager 1: At least one SyncManager changed Note: This bit is cleared by reading the corresponding SyncManager x Activate Register from PDI. RO RO 0b 3 State of DC SYNC1 (If Sync/Latch PDI Configuration Register bit 7 = 1) RO RO 0b RO RO 0b Note: 2 Bit is cleared by reading SYNC1 status 0x098F. State of DC SYNC0 (If Sync/Latch PDI Configuration Register bit 3 = 1) Note: DS00001909A-page 252 Bit is cleared by reading SYNC0 status 0x098E. 2015 Microchip Technology Inc. LAN9252 ECAT Type PDI Type Default DC Latch Event 0: No change on DC Latch Inputs 1: At least one change on DC Latch Inputs Note: This bit is cleared by reading the DC Latch event times from PDI for PDI controlled Latch Units, so that the LATCH0 Status Register/LATCH1 Status Register indicates no event. RO RO 0b AL Control Event 0: No AL Control Register change 1: AL Control Register has been written (AL control event is only generated if PDI emulation is turned off (ESC Configuration Register bit 8 = 0). Note: This bit is cleared by reading the AL Control Register from PDI. RO RO 0b Bits Description 1 0 Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 2015 Microchip Technology Inc. DS00001909A-page 253 LAN9252 12.14.35 RX ERROR COUNTER REGISTERS Offset: 0300h-0307h Size: Port 0: 0300h-0301h Port 1: 0302h-0303h Port 2: 0304h-0305h Port 3: 0306h-0307h 16 bits There are 4 16-bit RX Error Counter registers, each with unique address offsets as shown above. The variable “x” is used in the following bit descriptions to represent ports 0-3. Bits Description ECAT Type PDI Type Default 00h 15:8 Port x RX Error Counter Counting is stopped when FFh is reached. This is coupled directly to RX ERR of the MII/EBUS interfaces. R/WC RO 7:0 Port x Invalid Frame Counter Counting is stopped when FFh is reached. R/WC RO Note: This register is cleared if any one of the RX Error Counter Registers is written. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. Note: Port 3 is not used. DS00001909A-page 254 2015 Microchip Technology Inc. LAN9252 12.14.36 FORWARDED RX ERROR COUNTER REGISTERS Offset: 0308h-030Bh Port 0: 0308h Port 1: 0309h Port 2: 030Ah Port 3: 030Bh Size: 8 bits There are 4 8-bit Forwarded RX Error Counter registers, each with unique address offsets as shown above. The variable “x” is used in the following bit descriptions to represent ports 0-3. Bits 7:0 Description Port x Forwarded RX Error Counter Counting is stopped when FFh is reached. This is coupled directly to RX ERR of the MII/EBUS interfaces. ECAT Type PDI Type Default R/WC RO 00h ECAT Type PDI Type Default R/WC RO 00h ECAT Type PDI Type Default R/WC RO 00h Note: This register is cleared if any one of the RX Error Counter Registers is written. Note: Port 3 is not used. 12.14.37 ECAT PROCESSING UNIT ERROR COUNTER REGISTER Offset: 030Ch Size: Bits Description 7:0 ECAT Processing Unit Error Counter Counting is stopped when FFh is reached. This field counts the errors of frames passing the Processing Unit (e.g., FCS error or datagram structure error). 8 bits 12.14.38 PDI ERROR COUNTER REGISTER Offset: Bits 7:0 030Dh Size: Description PDI Error Counter Counting is stopped when FFh is reached. This field counts if a PDI access has an interface error. 2015 Microchip Technology Inc. 8 bits DS00001909A-page 255 LAN9252 12.14.39 PDI ERROR CODE REGISTER Offset: 030Eh Size: 8 bits The bit definitions of this register are dependent on the selected PDI mode (Process Data Interface field in the PDI Control Register): SPI Mode or HBI Modes. Note: This register is cleared when the PDI Error Counter Register is written. PDI Error Codes: SPI Mode Bits 7:0 Description RESERVED ECAT Type PDI Type Default RO RO 00h ECAT Type PDI Type Default RO RO 00h PDI Error Codes: HBI Modes Bits 7:0 Description RESERVED DS00001909A-page 256 2015 Microchip Technology Inc. LAN9252 12.14.40 LOST LINK COUNTER REGISTERS Offset: 0310h-0313h Port 0: 0310h Port 1: 0311h Port 2: 0312h Port 3: 0313h Size: 8 bits There are 4 8-bit Lost Link Counter registers, each with unique address offsets as shown above. The variable “x” is used in the following bit descriptions to represent ports 0-3. Bits 7:0 Description Port x Lost Link Counter Counting is stopped when FFh is reached. This counter only counts if port loop is Auto or Auto-Close. Note: ECAT Type PDI Type Default R/WC RO 00h ECAT Type PDI Type Default R/W RO 09C2h Only lost links at open ports are counted. Note: This register is cleared if any one of the Lost Link Counter Registers is written. Note: Port 3 is not used. 12.14.41 WATCHDOG DIVIDER REGISTER Offset: Bits 15:0 Note: 0400h-0401h Size: Description Watchdog Divider Number of 25MHz ticks (minus 2) that represents the basic watchdog increment. (default value is 100 us = 2498) 16 bits For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 2015 Microchip Technology Inc. DS00001909A-page 257 LAN9252 12.14.42 WATCHDOG TIME PDI REGISTER Offset: 0410h-0411h Size: Bits Description 15:0 Watchdog Time PDI Number of basic watchdog increments. (default value with Watchdog Divider of 100 us results in 100 ms watchdog.) 16 bits ECAT Type PDI Type Default R/W RO 03E8h Note: The watchdog is disabled if Watchdog Time PDI is set to 0000h. Watchdog is restarted with every PDI access. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.43 WATCHDOG TIME PROCESS DATA REGISTER Offset: 0420h-0421h Size: Bits Description 15:0 Watchdog Time Process Data Number of basic watchdog increments. (default value with Watchdog Divider of 100 us results in 100 ms watchdog.) 16 bits ECAT Type PDI Type Default R/W RO 03E8h Note: There is one watchdog for all SyncManagers. The watchdog is disabled if Watchdog Time PDI is set to 0000h. The watchdog is restarted with every write access to the SyncManagers with the Watchdog Trigger Enable bit set. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. DS00001909A-page 258 2015 Microchip Technology Inc. LAN9252 12.14.44 WATCHDOG STATUS PROCESS DATA REGISTER Offset: 0 Size: 16 bits ECAT Type PDI Type Default RESERVED RO RO 0000h Watchdog Status of Process Data (triggered by SyncManagers) 0: Watchdog Process Data expired 1: Watchdog Process Data is active or disabled RO RO 0b Bits 15:1 0440h-0441h Description Note: Reading this register clears the Watchdog Process Data bit of the AL Event Request Register. Note: The Watchdog Status for the PDI can be read in the PDI Watchdog Status bit of the ESC DL Status Register. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.45 WATCHDOG COUNTER PROCESS DATA REGISTER Offset: 0442h Size: Bits Description 7:0 Watchdog Counter Process Data Counting is stopped when FFh is reached. Counts if Process Data Watchdog expires. This field is cleared if one of the Watchdog counters (0442h-0443h) is written. 8 bits ECAT Type PDI Type Default R/WC RO 00h ECAT Type PDI Type Default R/WC RO 00h 12.14.46 WATCHDOG COUNTER PDI REGISTER Offset: 0443h Size: Bits Description 7:0 Watchdog PDI Counter Counting is stopped when FFh is reached. Counts if PDI Watchdog expires. This field is cleared if one of the Watchdog counters (0442h-0443h) is written. 2015 Microchip Technology Inc. 8 bits DS00001909A-page 259 LAN9252 12.14.47 EEPROM CONFIGURATION REGISTER Offset: 0500h Size: 8 bits ECAT Type PDI Type Default RESERVED Write 0. RO RO 000000b 1 Force ECAT Access 0: Do not change 1: Reset R/W RO 0b 0 PDI EEPROM Control 0: No 1: Yes (PDI has EEPROM control) R/W RO 0b Bits 7:2 Note: Description EtherCAT controls the SII EEPROM interface if the PDI EEPROM Control bit of the EEPROM Configuration Register is 0 and the Access to EEPROM bit of the EEPROM PDI Access State Register is 0. Otherwise, PDI controls the EEPROM interface. DS00001909A-page 260 2015 Microchip Technology Inc. LAN9252 12.14.48 EEPROM PDI ACCESS STATE REGISTER Offset: 0 Size: 8 bits ECAT Type PDI Type Default RESERVED Write 0. RO RO 0000000b Access to EEPROM 0: Do not change 1: Reset RO R/W Note 19 0b Bits 7:1 0501h Description Note 19: Write access only possible if the PDI EEPROM Control bit of the EEPROM Configuration Register is 1 and Force ECAT Access bit is 0. Note: EtherCAT controls the SII EEPROM interface if the PDI EEPROM Control bit of the EEPROM Configuration Register is 0 and the Access to EEPROM bit of the EEPROM PDI Access State Register is 0. Otherwise, PDI controls the EEPROM interface. 12.14.49 EEPROM CONTROL/STATUS REGISTER Offset: Bits 0502h-0503h Size: Description 16 bits ECAT Type PDI Type Default 15 Busy 0: EEPROM interface is idle 1: EEPROM interface is busy RO RO 0b 14 Error Write Enable 0: No error 1: Write Command without Write enable (See Note 20) RO RO 0b 13 Error Acknowledge/Command 0: No error 1: Missing EEPROM acknowledge or invalid command (See Note 20) RO R/[W] Note 21 0b Note: EEPROM emulation only: PDI writes 1 if a temporary failure has occurred. 12 EEPROM Loading Status 0: EEPROM loaded, device information okay 1: EEPROM not loaded, device information not available (EEPROM loading in-progress or finished with a failure) RO RO 0b 11 Checksum Error in ESC Configuration Area 0: Checksum okay 1: Checksum error RO R/[W] Note 21 0b 2015 Microchip Technology Inc. DS00001909A-page 261 LAN9252 ECAT Type PDI Type Command Register Write: Initiate command Read: Currently executed command 000: No command/EEPROM idle (clear error bits) 001: Read 010: Write 100: Reload Others: RESERVED / invalid commands (no not issue) (See Note 22) R/W R/[W] Note 21 000b 7 Selected EEPROM Algorithm 0: 1 address byte (1Kbit - 16Kbit EEPROMs) 1: 2 address bytes (32Kbit - 4Mbit EEPROMs) RO RO Note 23 6 Supported Number of EEPROM Bytes 0: 4 Bytes 1: 8 Bytes RO RO 0b 5 EEPROM Emulation 0: Normal operation (I2C interface used) 1: PDI emulates EEPROM (I2C not used) RO RO 0b RESERVED RO RO 0b ECAT Write Enable 0: Write requests are disabled 1: Write requests are enabled (See Note 24) R/W RO 0b Bits 10:8 Description Note: 4:1 0 Default Must be written as 0. Note 20: Error bits are cleared by writing “000” (or any valid command) to Command Register bits. Note 21: Write access is possible if EEPROM interface is busy (Busy bit = 1). PDI acknowledges pending commands by writing a 1 into the corresponding command register bits 10:8. Errors can be indicated by writing a 1 into the error bits (11 and 13). Acknowledging clears bit 5 of the AL Event Request Register. Note 22: The Command Register bits are self clearing after the command is executed (EEPROM Busy ends). Writing “000” to the Command Register bits will also clear the error bits 14:13. The Command Register bits are ignored if the Error Acknowledge/Command is pending. Note 23: The default of this bit is dependent on the eeprom_size_strap. Note 24: The ECAT Write Enable bit is self clearing at the SOF of the next frame. Note: EtherCAT controls the SII EEPROM interface if the PDI EEPROM Control bit of the EEPROM Configuration Register is 0 and the Access to EEPROM bit of the EEPROM PDI Access State Register is 0. Otherwise, PDI controls the EEPROM interface. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. DS00001909A-page 262 2015 Microchip Technology Inc. LAN9252 12.14.50 EEPROM ADDRESS REGISTER Offset: Bits 31:0 0504h-0507h Size: Description EEPROM Address Bit 0: First word (16-bit) Bit 1: Second word ..... Note: 32 bits ECAT Type PDI Type Default R/W R/W 00000000h Actually used EEPROM address bits: [9:0]: EEPROM size up to 16Kbit [17:0]: EEPROM size 32Kbit - 4Mbit [31:0]: EEPROM Emulation Note: Write access depends upon the assignment of the EEPROM interface (ECAT/PDI). Write access is generally blocked if the EEPROM interface is busy (Busy bit of EEPROM Control/Status Register = 1) Note: EtherCAT controls the SII EEPROM interface if the PDI EEPROM Control bit of the EEPROM Configuration Register is 0 and the Access to EEPROM bit of the EEPROM PDI Access State Register is 0. Otherwise, PDI controls the EEPROM interface. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.51 EEPROM DATA REGISTER Offset: Bits 0508h-050Bh Size: Description 32 bits ECAT Type PDI Type Default 31:16 EEPROM Read Data Data to be read from EEPROM, higher bytes RO RO 0000h 15:0 EEPROM Read/Write Data Data to be read from EEPROM, lower bytes or data to be written to EEPROM. R/W R/W 0000h Note: Write access depends upon the assignment of the EEPROM interface (ECAT/PDI). Write access is generally blocked if the EEPROM interface is busy (Busy bit of EEPROM Control/Status Register = 1) Note: EtherCAT controls the SII EEPROM interface if the PDI EEPROM Control bit of the EEPROM Configuration Register is 0 and the Access to EEPROM bit of the EEPROM PDI Access State Register is 0. Otherwise, PDI controls the EEPROM interface. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 2015 Microchip Technology Inc. DS00001909A-page 263 LAN9252 12.14.52 MII MANAGEMENT CONTROL/STATUS REGISTER Offset: Bits 0510h-0511h Size: Description 16 bits ECAT Type PDI Type Default 15 Busy 0: MI control state machine is idle 1: MI control state machine is active RO RO 0b 14 Command Error 0: Last command was successful 1: Invalid command or write command without write enable RO RO 0b R/W Note 25 R/W Note 25 0b RO RO 0b R/W Note 25 R/W Note 25 00b PHY Address Offset RO RO 00000b 2 MI Link Detection (Link configuration, link detection, registers PHY Port Status Registers) 0: Not available 1: MI Link Detection Active RO RO 0b Note 27 1 Management Interface Control 0: ECAT control only 1: MPDI control possible (MII Management ECAT Access State Register and MII Management PDI Access State Register) RO RO 1b 0 Write Enable 0: Write Disabled 1: Write Enabled R/W Note 25 RO 0b Note: 13 Read Error 0: No read error 1: Read error occurred (PHY or register bi available) Note: 12:10 9:8 Cleared with a valid command or by writing “00” to Command Register. Cleared by writing this register. RESERVED Command Register Write: Initiate command. Read: Currently executed command See Note 26. Commands: 00: No command / MI Idle (clear error bits) 01: Read 10: Write 11: RESERVED (do not issue) 7:3 Note: This bit is always 1 if PDI has MI control. (See Note 28) Note 25: Write access depends upon the assignment of the MI interface (ECAT/PDI). Write access is generally blocked if the MII interface is busy (Busy bit of MII Management Control/Status Register = 1) DS00001909A-page 264 2015 Microchip Technology Inc. LAN9252 Note 26: Command Register bits (9:8) are self-clearing after the command is executed (Busy ends). Writing “00” to the Command Register bits will also clear the error bits 14:13 of this register. The Command Register bits (9:8) are cleared after the command is executed. Note 27: The default value of this field can be configured via EEPROM. This bit will be 0 and MI link detection disabled until the device is successfully configured from EEPROM. The EEPROM setting for MI link detection is only taken at the first EEPROM loading after power-on reset. Changing the EEPROM and manually reloading it will not affect the MI link detection enable status, even if the EEPROM could not be read initially. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. Note 28: Write enable bit 0 is self-clearing at the SOF of the next frame (or end of the PDI access). Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.53 PHY ADDRESS REGISTER Offset: Bits 0512h Size: Description 7:5 RESERVED Write 0. 4:0 PHY Address 8 bits ECAT Type PDI Type Default RO RO 000b R/W Note 29 R/W Note 29 00000b Note 29: Write access depends upon the assignment of the MI interface (ECAT/PDI). Write access is generally blocked if the MII interface is busy (Busy bit of MII Management Control/Status Register = 1) 12.14.54 PHY REGISTER ADDRESS REGISTER Offset: Bits 0513h Description 7:5 RESERVED Write 0. 4:0 Address of PHY Register to be Read/Written Size: 8 bits ECAT Type PDI Type Default RO RO 000b R/W Note 30 R/W Note 30 00000b Note 30: Write access depends upon the assignment of the MI interface (ECAT/PDI). Write access is generally blocked if the MII interface is busy (Busy bit of MII Management Control/Status Register = 1) 2015 Microchip Technology Inc. DS00001909A-page 265 LAN9252 12.14.55 PHY DATA REGISTER Offset: Bits 15:0 0514h-0515h Size: Description PHY Read/Write Data 16 bits ECAT Type PDI Type R/W Note 31 R/W Note 31 Default 0000h Note 31: Write access depends upon the assignment of the MI interface (ECAT/PDI). Write access is generally blocked if the MII interface is busy (Busy bit of MII Management Control/Status Register = 1) Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.56 MII MANAGEMENT ECAT ACCESS STATE REGISTER Offset: Bits 7:1 0 0516h Size: Description RESERVED Write 0. Access to MII Management (ECAT) 0: ECAT enables PDI takeover of MII management control 1: ECAT claims exclusive access to MII management 8 bits ECAT Type PDI Type Default RO RO 0000000b R/W Note 32 RO 0b Note 32: Write access only possible if the Access to MII Management (PDI) bit of the MII Management PDI Access State Register is 0. DS00001909A-page 266 2015 Microchip Technology Inc. LAN9252 12.14.57 MII MANAGEMENT PDI ACCESS STATE REGISTER Offset: 0517h Size: 8 bits ECAT Type PDI Type Default RESERVED Write 0. RO RO 000000b 1 Force PDI Access State 0: Do not change Access to MII Management (PDI) bit 1: Reset Access to MII Management (PDI) bit R/W RO 0b 0 Access to MII Management (PDI) 0: ECAT has access to MII management 1: PDI has access to MII management RO R/W Note 33 0b Bits 7:2 Description Note 33: Write access to the Access to MII Management (PDI) bit of this register is only possible if the Force PDI Access State bit of this register is 0 and the Access to MII Management (ECAT) bit of the MII Management ECAT Access State Register is 0. 12.14.58 PHY PORT STATUS REGISTERS Offset: 0518h-051Bh Port 0: 0518h Port 1: 0519h Port 2: 051Ah Port 3: 051Bh Size: 8 bits There are 4 8-bit PHY Port Status registers, each with unique address offsets as shown above. The variable “x” is used in the following bit descriptions to represent ports 0-3. Bits 7:6 5 Description RESERVED Write as 0. Port x Lost Link Counter 0: No Update 1: PHY Configuration was Updated Note: ECAT Type PDI Type Default RO RO 00b R/WC Note 34 R/WC Note 34 0b Cleared by writing any value to at least one of the PHY Port Status Registers. 4 Port x Link Partner Error 0: No Error Detected 1: Link Partner Error RO RO 0b 3 Port x Read Error 0: No Read Error Detected 1: Read Error has Occurred R/WC Note 34 R/WC Note 34 0b Note: Cleared by writing any value to at least one of the PHY Port Status Registers. 2015 Microchip Technology Inc. DS00001909A-page 267 LAN9252 Bits Description ECAT Type PDI Type Default 2 Port x Link Status Error 0: No Error 1: Link Error, Link Inhibited RO RO 0b 1 Port x Link Status (100 Mbit/s, Full-Duplex, Auto-negotiation) 0: No Link 1: Link Detected RO RO 0b 0 Port x Physical Link (PHY Status Register 1.2) 0: No Physical Link 1: Physical Link Detected RO RO 0b Note 34: Write access depends upon the assignment of the MI interface (ECAT/PDI). Port 3 is not used. Note: 12.14.59 FMMU[2:0] REGISTERS The device includes 3 FMMUs. Each FMMU is described in 16 Bytes, starting at 0600h. Table 12-16 details the base address for each FMMU. The subsequent FMMU registers will be referenced as an offset from these various base addresses. The variable “x” is used in the following descriptions to represent FMMUs 0 through 2. TABLE 12-16: FMMU X BASE ADDRESSES FMMU Base Address 0 0600h 1 0610h 2 0620h 12.14.59.1 FMMUx Logical Start Address Register Offset: Bits 31:0 Note: FMMUx Base Address +0h-3h Description Logical Start Address Logical start address within the EtherCAT address space. Size: 32 bits ECAT Type PDI Type Default R/W RO 00000000h For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. DS00001909A-page 268 2015 Microchip Technology Inc. LAN9252 12.14.59.2 FMMUx Length Register Offset: FMMUx Base Address +4h-5h Size: Bits Description 15:0 Length Offset from the first logical FMMU byte to the last FMMU Byte + 1 (e.g., if two bytes are used, then this parameter shall contain 2). Note: 16 bits ECAT Type PDI Type Default R/W RO 0000h For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.59.3 FMMUx Logical Start Bit Register Offset: Bits FMMUx Base Address +6h Size: Description 8 bits ECAT Type PDI Type Default 7:3 RESERVED Write as 0. RO RO 00000b 2:0 Logical Start Bit Logical starting bit that shall be mapped (bits are counted from least significant bit (0) to most significant bit (7)). R/W RO 000b 12.14.59.4 FMMUx Logical Stop Bit Register Offset: Bits FMMUx Base Address +7h Size: Description 8 bits ECAT Type PDI Type Default 7:3 RESERVED Write as 0. RO RO 00000b 2:0 Logical Stop Bit Last logical bit that shall be mapped (bits are counted from least significant bit (0) to most significant bit (7)). R/W RO 000b 2015 Microchip Technology Inc. DS00001909A-page 269 LAN9252 12.14.59.5 FMMUx Physical Start Address Register Offset: Bits 15:0 Note: FMMUx Base Address +8h-9h Size: Description Physical Start Address (Mapped to logical start address) 16 bits ECAT Type PDI Type Default R/W RO 0000h For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.59.6 FMMUx Physical Start Bit Register Offset: Bits FMMUx Base Address +Ah Size: Description 8 bits ECAT Type PDI Type Default 7:3 RESERVED Write as 0. RO RO 00000b 2:0 Physical Start Bit Physical starting bit as target of logical start bit mapping (bits are counted from least significant bit (0) to most significant bit (7)). R/W RO 000b 12.14.59.7 FMMUx Type Register Offset: FMMUx Base Address +Bh Size: 8 bits ECAT Type PDI Type Default RESERVED Write as 0. RO RO 000000b 1 Write Access Mapping 0: Ignore mapping for write accesses 1: Use mapping for write accesses R/W RO 0b 0 Read Access Mapping 0: Ignore mapping for read accesses 1: Use mapping for read accesses R/W RO 0b Bits 7:2 Description DS00001909A-page 270 2015 Microchip Technology Inc. LAN9252 12.14.59.8 FMMUx Activate Register Offset: 0 Size: 8 bits ECAT Type PDI Type Default RESERVED Write as 0. RO RO 0000000b FMMU Activation 0: FMMUx Deactivated 1: FMMUx Activated. FMMUx checks logical addressed blocks to be mapped according to the configured mapping. R/W RO 0b Bits 7:1 FMMUx Base Address +Ch Description 12.14.59.9 FMMUx Reserved Register Offset: Bits 23:0 Note: FMMUx Base Address +Dh-Fh Description RESERVED Write as 0. Size: 24 bits ECAT Type PDI Type Default RO RO 000000h For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 2015 Microchip Technology Inc. DS00001909A-page 271 LAN9252 12.14.60 SYNCMANAGER[3:0] REGISTERS The device includes 4 SyncManagers. Each SyncManager is described in 8 Bytes, starting at 0800h. Table 12-17 details the base address for each SyncManager. The subsequent SyncManager registers will be referenced as an offset from these various base addresses. The variable “x” is used in the following descriptions to represent SyncManagers 0 through 3. TABLE 12-17: SYNCMANAGER X BASE ADDRESSES SyncManager Base Address 0 0800h 1 0808h 2 0810h 3 0818h 12.14.60.1 SyncManager x Physical Start Address Register Offset: Bits 15:0 SyncManager x Base Address +0h-1h Size: Description Physical Start Address Specifies the first byte that will be handled by SyncManager x. 16 bits ECAT Type PDI Type Default R/W Note 35 RO 0000h Note 35: This register can only be written if the corresponding SyncManager is disabled via the SyncManager Enable/Disable bit of the SyncManager x Activate Register. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.60.2 SyncManager x Length Register Offset: SyncManager x Base Address +2h-3h Size: Bits Description 15:0 Length Number of bytes assigned to SyncManager x. (This field shall be greater than 1, otherwise the SyncManager is not activated. If set to 1, only Watchdog Trigger is generated, if configured.) 16 bits ECAT Type PDI Type Default R/W Note 36 RO 0000h Note 36: This register can only be written if SyncManager x is disabled via the SyncManager Enable/Disable bit of the SyncManager x Activate Register. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. DS00001909A-page 272 2015 Microchip Technology Inc. LAN9252 12.14.60.3 SyncManager x Control Register Offset: Bits SyncManager x Base Address +4h Description Size: 8 bits ECAT Type PDI Type Default RO RO 0b 7 RESERVED Write as 0. 6 Watchdog Trigger Enable 0: Disabled 1: Enabled R/W Note 37 RO 0b 5 Interrupt in PDI Event Request Register 0: Disabled 1: Enabled R/W Note 37 RO 0b 4 Interrupt in ECAT Event Request Register 0: Disabled 1: Enabled R/W Note 37 RO 0b 3:2 Direction 00: Read: ECAT read access, PDI write access 01: Write: ECAT write access, PDI read access 10: RESERVED 11: RESERVED R/W Note 37 RO 00b 1:0 Operation Mode 00: Buffered (3 buffer mode) 01: RESERVED 10: Mailbox (single buffer mode) 11: RESERVED R/W Note 37 RO 00b Note 37: This register can only be written if SyncManager x is disabled via the SyncManager Enable/Disable bit of the SyncManager x Activate Register. 2015 Microchip Technology Inc. DS00001909A-page 273 LAN9252 12.14.60.4 SyncManager x Status Register Offset: SyncManager x Base Address +5h Bits Size: Description 8 bits ECAT Type PDI Type Default 7 Write Buffer in Use (opened) RO RO 0b 6 Read Buffer in Use (opened) RO RO 0b Buffer Status (Last Written Buffer) RO RO 11b RO RO 0b 5:4 Buffered Mode: 00: 1. buffer 01: 2. buffer 10: 3. buffer 11: No buffer written Mailbox Mode: RESERVED 3 Mailbox Status Mailbox Mode: 0: Mailbox Empty 1: Mailbox Full Buffered Mode: RESERVED 2 RESERVED Write as 0. RO RO 0b 1 Interrupt Read 0: Interrupt cleared after first byte of buffer was written 1: Interrupt after buffer was completely and successfully read RO RO 0b 0 Interrupt Write 0: Interrupt cleared after first byte of buffer was read 1: Interrupt after buffer was completely and successfully written RO RO 0b DS00001909A-page 274 2015 Microchip Technology Inc. LAN9252 12.14.60.5 SyncManager x Activate Register Offset: Bits SyncManager x Base Address +6h Size: Description 8 bits ECAT Type PDI Type Default 7 Latch Event PDI 0: No 1: Generate latch events if PDI issues a buffer exchange or if PDI accesses buffer start address. R/W RO 0b 6 Latch Event ECAT 0: No 1: Generate latch event if EtherCAT master issues a buffer exchange. R/W RO 0b RESERVED Write as 0. RO RO 0000b 1 Repeat Request A toggle of Repeat Request indicates that a mailbox retry is needed (primarily used in conjunction with ECAT Read Mailbox) R/W RO 0b 0 SyncManager Enable/Disable 0: Disable: Access to memory without SyncManager control 1: Enable: SyncManager is active and controls memory area set in configuration. R/W RO 0b 5:2 Note: Reading this register from PDI in all SyncManagers which have changed activation clears the “SyncManager x Activation Register Changed” bit in the AL Event Request Register. 2015 Microchip Technology Inc. DS00001909A-page 275 LAN9252 12.14.60.6 SyncManager x PDI Control Register Offset: SyncManager x Base Address +7h Size: 8 bits ECAT Type PDI Type Default RESERVED Write as 0. RO RO 000000b 1 Repeat Ack If this is set to the same value as Repeat Request, the PDI acknowledges the execution of a previous set repeat request. RO R/W 0b 0 Deactivate SyncManager x RO R/W 0b ECAT Type PDI Type Default R/W RO Undefined Bits 7:2 Description Read: 0: Normal operation, SyncManager x activated 1: SyncManager x deactivated and reset SyncManager x locks access to memory area Write: 0: Activate SyncManager 1: Request SyncManager Deactivation 12.14.61 RECEIVE TIME PORT 0 REGISTER Offset: 0900h-0903h Size: Bits Description 31:0 Write: A write access to register 0900h with BWR, APWR (any address) or FPWR (configured address) latches the local time of the beginning of the receive frame (start first bit of preamble) at each port. Read: Local time of the beginning of the last receive frame containing a write access to this register. Note: Note: 32 bits The time stamps cannot be read in the same frame in which this register was written. For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. DS00001909A-page 276 2015 Microchip Technology Inc. LAN9252 12.14.62 RECEIVE TIME PORT 1 REGISTER Offset: 0904h-0907h Size: Bits Description 31:0 Local time of the beginning of a frame (start first bit of preamble) received at port 1 containing a BWR/APWR or FPWR to the Receive Time Port 0 Register. Note: 32 bits ECAT Type PDI Type Default RO RO Undefined For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.63 RECEIVE TIME PORT 2 REGISTER Offset: 0908h-090Bh Size: Bits Description 31:0 Local time of the beginning of a frame (start first bit of preamble) received at port 2 containing a BWR/APWR or FPWR to the Receive Time Port 0 Register. Note: 32 bits ECAT Type PDI Type Default RO RO Undefined For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 2015 Microchip Technology Inc. DS00001909A-page 277 LAN9252 12.14.64 SYSTEM TIME REGISTER Offset: 0910h-0917h Size: 64 bits ECAT Type PDI Type ECAT Read Access: Local copy of the System Time when the frame passed the reference clock (i.e., including System Time Delay). Time latched at beginning of the frame (Ethernet SOF delimiter). PDI Read Access: Local copy of the System Time. Time latched when reading first byte (0910h). RO RO 00000000h 00000000h Write Access: Written value will be compared with the local copy of the system time. The result is an input to the time control loop. W Note 38 RO 00000000h Bits Description 63:0 31:0 Note: Default Written value will be compared at the end of the frame with the latched (SOF) local copy of the system time if at least the first byte (0910h) was written. Note 38: When writing via ECAT, the control loop is triggered to process the new value. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.65 RECEIVE TIME ECAT PROCESSING UNIT REGISTER Offset: 0918h-091Fh Size: Bits Description 63:0 Local time of the beginning of a frame (start first bit of preamble) received at the ECAT Processing Unit containing a write access to Receive Time Port 0 Register (0900h). Note: Note: 64 bits ECAT Type PDI Type RO RO Default 00000000h 00000000h If port 0 is open, this register reflects the Receive Time Port 0 Register as a 64-bit value. For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. DS00001909A-page 278 2015 Microchip Technology Inc. LAN9252 12.14.66 SYSTEM TIME OFFSET REGISTER Offset: 0920h-0927h Size: Bits Description 63:0 Difference between local time and System Time. Offset is added to local time. Local time of the beginning of a frame (start first bit of preamble) received at the ECAT Processing Unit containing a write access to Receive Time Port 0 Register (0900h). Note: Note: 64 bits ECAT Type PDI Type R/W RO Default 00000000h 00000000h If port 0 is open, this register reflects the Receive Time Port 0 Register as a 64-bit value. For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.67 SYSTEM TIME DELAY REGISTER Offset: Bits 31:0 Note: 0928h-092Bh Size: Description Delay between Reference Clock and the ESC. 32 bits ECAT Type PDI Type Default R/W RO 00000000h For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.68 SYSTEM TIME DIFFERENCE REGISTER Offset: 30:0 Note: Size: 32 bits ECAT Type PDI Type Default 0: Local copy of System Time greater than or equal to received System Time 1: Local copy of System Time smaller than received System Time RO RO 0b Mean difference between local copy of System Time and received System Time values. RO RO 00000000h Bits 31 092Ch-092Fh Description For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 2015 Microchip Technology Inc. DS00001909A-page 279 LAN9252 12.14.69 SPEED COUNTER START REGISTER Offset: 14:0 Note: Size: 16 bits ECAT Type PDI Type Default RESERVED Write as 0. RO RO 0b Bandwidth for adjustment of local copy of System Time (larger values -> smaller bandwidth and smoother adjustment). A write access resets the System Time Difference Register and Speed Counter Diff Register. Valid range: 0080h-3FFFh. R/W RO 1000h Bits 15 0930h-0931h Description For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.70 SPEED COUNTER DIFF REGISTER Offset: Bits 15:0 0932h-0933h Size: Description Representation of the deviation between local clock period and Reference Clock’s clock period (representation: two’s compliment). Valid Range: +/-(Speed Counter Start Register-7Fh). 16 bits ECAT Type PDI Type Default RO RO 0000h Note: The clock deviation after System Time Difference has settled at a low value can be calculated as follows: Deviation = Speed Counter Diff / 5(Speed Counter Start + Speed Counter Diff + 2)(Speed Counter Start Speed Counter Diff + 2) Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. DS00001909A-page 280 2015 Microchip Technology Inc. LAN9252 12.14.71 SYSTEM TIME DIFFERENCE FILTER DEPTH REGISTER Offset: Bits 0934h Size: Description 8 bits ECAT Type PDI Type Default 7:4 RESERVED RO RO 0h 3:0 Filter depth for averaging the received System Time deviation. R/W RO 4h ECAT Type PDI Type Default Note: A write access resets the System Time Difference Register. 12.14.72 SPEED COUNTER FILTER DEPTH REGISTER Offset: Bits 0935h Size: Description 8 bits 7:4 RESERVED RO RO 0h 3:0 Filter depth for averaging the clock period deviation. R/W RO Ch Note: A write access resets the internal speed counter filter. 2015 Microchip Technology Inc. DS00001909A-page 281 LAN9252 12.14.73 CYCLIC UNIT CONTROL REGISTER Offset: 5 Default RESERVED Write as 0. RO RO 00b Latch In Unit 1 0: ECAT Controlled 1: PDI Controlled R/W RO 0b R/W RO 0b RESERVED Write as 0. RO RO 000b 0 Sync Out Unit Control 0: ECAT Controlled 1: PDI Controlled R/W RO 0b Latch interrupt is routed to ECAT/PDI depending on this setting. Latch In Unit 0 0: ECAT Controlled 1: PDI Controlled Note: 3:1 8 bits PDI Type Description Note: 4 Size: ECAT Type Bits 7:6 0980h DS00001909A-page 282 Always 1 (PDI controlled) is System Time is PDI controlled. Latch interrupt is routed to ECAT/PDI depending on this setting. 2015 Microchip Technology Inc. LAN9252 12.14.74 ACTIVATION REGISTER Offset: Bits 0981h Size: Description 8 bits ECAT Type PDI Type Default 7 SyncSignal Debug Pulse (Vasili Bit) 0: Deactivated 1: Immediately generate a single debug ping on SYNC0 and SYNC1 according to bits 2 and 1 of this register. R/W R/W 0b 6 Near Future Configuration (approx.) 0: 1/2 DC width future (231 ns or 263 ns) 1: 2.1 sec future (231 ns) R/W R/W 0b 5 Start Time Plausibility Check 0: Disabled. SyncSignal generation if Start Time is reached. 1: Immediate SyncSignal generation if Start Time is outside Near Future Configuration (approx.). R/W R/W 0b 4 Extension of Start Time Cyclic Operation (Start Time Cyclic Operation Register) 0: No extension 1: Extend 32-bit written Start Time to 64-bit R/W R/W 0b 3 Auto-activation (By writing Start Time Cyclic Operation Register) 0: Disabled 1: Auto-activation enabled. Sync Out Unit Activation is set automatically after Start Time is written. R/W R/W 0b 2 SYNC1 Generation 0: Deactivated 1: SYNC1 pulse is generated R/W R/W 0b 1 SYNC0 Generation 0: Deactivated 1: SYNC0 pulse is generated R/W R/W 0b 0 Sync Out Unit Activation 0: Deactivated 1: Activated R/W R/W 0b Note: Note: Write 1 after Start Time is written Writes to this register depend on the Sync Out Unit Control bit of the Cyclic Unit Control Register. 2015 Microchip Technology Inc. DS00001909A-page 283 LAN9252 12.14.75 PULSE LENGTH OF SYNCSIGNALS REGISTER Offset: Bits 15:0 0982h-0983h Size: Description Pulse length of SyncSignals (in units of 10ns) A value of 0 is used for Acknowledge Mode: SyncSignal will be cleared by reading the SYNC0 Status Register/SYNC1 Status Register. 16 bits ECAT Type PDI Type RO RO Default 0000h Note 39 Note 39: The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.76 ACTIVATION STATUS REGISTER Offset: 0984h Size: 8 bits ECAT Type PDI Type Default RESERVED RO RO 00000b 2 Start Time Cyclic Operation (Start Time Cyclic Operation Register) plausibility check result when Sync Out Unit was activated. 0: Start Time was within near future 1: Start Time was out of near future RO RO 0b 1 SYNC1 Activation State 0: First SYNC1 pulse is not pending 1: First SYNC1 pulse is pending RO RO 0b 0 SYNC0 Activation State 0: First SYNC0 pulse is not pending 1: First SYNC0 pulse is pending RO RO 0b Bits 7:3 Description DS00001909A-page 284 2015 Microchip Technology Inc. LAN9252 12.14.77 SYNC0 STATUS REGISTER Offset: 0 Size: 8 bits ECAT Type PDI Type Default RESERVED RO RO 0000000b SYNC0 State for Acknowledge Mode SYNC0, in Acknowledge Mode, is cleared by reading this register from PDI. Use only in Acknowledge Mode. RO RO 0b ECAT Type PDI Type Default RESERVED RO RO 0000000b SYNC1 State for Acknowledge Mode SYNC1, in Acknowledge Mode, is cleared by reading this register from PDI. Use only in Acknowledge Mode. RO RO 0b ECAT Type PDI Type Default R/W R/W Bits 7:1 098Eh Description 12.14.78 SYNC1 STATUS REGISTER Offset: Bits 7:1 0 098Fh Size: Description 8 bits 12.14.79 START TIME CYCLIC OPERATION REGISTER Offset: Bits 63:0 0990h-0997h Description Write: Start time (System Time) of cyclic operation in ns. Read: System time of next SYNC0 pulse in ns. Size: 64 bits 00000000h 00000000h Note: Writes to this register depend on the Sync Out Unit Control bit of the Cyclic Unit Control Register. It is only writable if Sync Out Unit Control is 0. Note: When the Auto-activation bit of the Activation Register is 1: The upper 32 bits are automatically extended if only the lower 32 bits are written within one frame. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 2015 Microchip Technology Inc. DS00001909A-page 285 LAN9252 12.14.80 NEXT SYNC1 PULSE REGISTER Offset: Bits 63:0 Note: 0998h-099Fh Size: Description System time of next SYNC1 pulse in ns. 64 bits ECAT Type PDI Type RO RO Default 00000000h 00000000h For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.81 SYNC0 CYCLE TIME REGISTER Offset: Bits 31:0 09A0h-09A3h Size: Description Time between two consecutive SYNC0 pulses in ns. A value of 0 indicates Single shot mode - generate only one SYNC0 pulse. 32 bits ECAT Type PDI Type Default R/W R/W 00000000h Note: Writes to this register depend on the Sync Out Unit Control bit of the Cyclic Unit Control Register. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.82 SYNC1 CYCLE TIME REGISTER Offset: Bits 31:0 09A4h-09A7h Size: Description Time between SYNC1 pulses and SYNC0 pulse in ns. 32 bits ECAT Type PDI Type Default R/W R/W 00000000h Note: Writes to this register depend on the Sync Out Unit Control bit of the Cyclic Unit Control Register. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. DS00001909A-page 286 2015 Microchip Technology Inc. LAN9252 12.14.83 LATCH0 CONTROL REGISTER Offset: 09A8h Size: 8 bits ECAT Type PDI Type Default RESERVED Write as 0. RO RO 000000b 1 LATCH0 Negative Edge 0: Continuous Latch active 1: Single Event (only first event active) R/W R/W 0b 0 LATCH0 Positive Edge 0: Continuous Latch active 1: Single Event (only first event active) R/W R/W 0b Bits 7:2 Note: Description Writes to this register depend on the Latch In Unit 0 bit of the Cyclic Unit Control Register. 12.14.84 LATCH1 CONTROL REGISTER Offset: 09A9h Size: 8 bits ECAT Type PDI Type Default RESERVED Write as 0. RO RO 000000b 1 LATCH1 Negative Edge 0: Continuous Latch active 1: Single Event (only first event active) R/W R/W 0b 0 LATCH1 Positive Edge 0: Continuous Latch active 1: Single Event (only first event active) R/W R/W 0b Bits 7:2 Note: Description Writes to this register depend on the Latch In Unit 1 bit of the Cyclic Unit Control Register. 2015 Microchip Technology Inc. DS00001909A-page 287 LAN9252 12.14.85 LATCH0 STATUS REGISTER Offset: 09AEh Size: 8 bits ECAT Type PDI Type Default RESERVED Write as 0. RO RO 00000b 2 LATCH0 Pin State RO RO 0b 1 Event LATCH0 Negative Edge 0: Negative edge not detected or continuous mode 1: Negative edge detected in single event mode only. RO RO 0b RO RO 0b ECAT Type PDI Type Default RESERVED Write as 0. RO RO 00000b 2 LATCH1 Pin State RO RO 0b 1 Event LATCH1 Negative Edge 0: Negative edge not detected or continuous mode 1: Negative edge detected in single event mode only. RO RO 0b RO RO 0b Bits 7:3 Description Note: 0 Flag cleared by reading the LATCH0 Time Negative Edge Register. Event LATCH0 Positive Edge 0: Positive edge not detected or continuous mode 1: Positive edge detected in single event mode only. Note: Flag cleared by reading the LATCH0 Time Positive Edge Register. 12.14.86 LATCH1 STATUS REGISTER Offset: Bits 7:3 Size: Description Note: 0 09AFh Flag cleared by reading the LATCH1 Time Negative Edge Register. Event LATCH1 Positive Edge 0: Positive edge not detected or continuous mode 1: Positive edge detected in single event mode only. Note: DS00001909A-page 288 8 bits Flag cleared by reading the LATCH1 Time Positive Edge Register. 2015 Microchip Technology Inc. LAN9252 12.14.87 LATCH0 TIME POSITIVE EDGE REGISTER Offset: Bits 63:0 09B0h-09B7h Size: Description This register captures the System Time at the positive edge of the LATCH0 signal. Note: 64 bits ECAT Type PDI Type RO RO Default 00000000h 00000000h Reading this register clears the Event LATCH0 Positive Edge bit of the LATCH0 Status Register Note: Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guarantees reading a consistent value. Clearing the Event LATCH0 Positive Edge bit of the LATCH0 Status Register depends upon setting of the Latch In Unit 0 bit of the Cyclic Unit Control Register. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.88 LATCH0 TIME NEGATIVE EDGE REGISTER Offset: Bits 63:0 09B8h-09BFh Size: Description This register captures the System Time at the negative edge of the LACTH0 signal. Note: 64 bits ECAT Type PDI Type RO RO Default 00000000h 00000000h Reading this register clears the Event LATCH0 Negative Edge bit of the LATCH0 Status Register Note: Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guarantees reading a consistent value. Clearing the Event LATCH0 Negative Edge bit of the LATCH0 Status Register depends upon setting of the Latch In Unit 0 bit of the Cyclic Unit Control Register. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 2015 Microchip Technology Inc. DS00001909A-page 289 LAN9252 12.14.89 LATCH1 TIME POSITIVE EDGE REGISTER Offset: Bits 63:0 09C0h-09C7h Size: Description This register captures the System Time at the positive edge of the LATCH1 signal. Note: 64 bits ECAT Type PDI Type RO RO Default 00000000h 00000000h Reading this register clears the Event LATCH1 Positive Edge bit of the LATCH1 Status Register Note: Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guarantees reading a consistent value. Clearing the Event LATCH1 Positive Edge bit of the LATCH1 Status Register depends upon setting of the Latch In Unit 1 bit of the Cyclic Unit Control Register. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.90 LATCH1 TIME NEGATIVE EDGE REGISTER Offset: Bits 63:0 09C8h-09CFh Size: Description This register captures the System Time at the negative edge of the LATCH1 signal. Note: 64 bits ECAT Type PDI Type RO RO Default 00000000h 00000000h Reading this register clears the Event LATCH1 Negative Edge bit of the LATCH1 Status Register Note: Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guarantees reading a consistent value. Clearing the Event LATCH1 Negative Edge bit of the LATCH1 Status Register depends upon setting of the Latch In Unit 1 bit of the Cyclic Unit Control Register. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. DS00001909A-page 290 2015 Microchip Technology Inc. LAN9252 12.14.91 ETHERCAT BUFFER CHANGE EVENT TIME REGISTER Offset: 09F0h-09F3h Size: Bits Description 31:0 This register captures the local time of the beginning of the frame which causes at least one SyncManager to assert an ECAT event. 32 bits ECAT Type PDI Type Default RO RO 00000000h Note: Register bits [31:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guarantees reading a consistent value. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.92 PDI BUFFER START TIME EVENT REGISTER Offset: 09F8h-09FBh Size: Bits Description 31:0 This register captures the local time when at least one SyncManager asserts a PDI buffer start event. 32 bits ECAT Type PDI Type Default RO RO 00000000h Note: Register bits [31:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guarantees reading a consistent value. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.93 PDI BUFFER CHANGE EVENT TIME REGISTER Offset: 09FCh-09FFh Size: Bits Description 31:0 This register captures the local time when at least one SyncManager asserts a PDI buffer change event. 32 bits ECAT Type PDI Type Default RO RO 00000000h Note: Register bits [31:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guarantees reading a consistent value. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 2015 Microchip Technology Inc. DS00001909A-page 291 LAN9252 12.14.94 PRODUCT ID REGISTER Offset: Bits 63:0 0E00h-0E07h Size: Description Product ID 64 bits ECAT Type PDI Type RO RO Default 0000h 00ssh 9252h rrrrh Note 40 Note 40: The value of “ss” is 0, 0, link_pol_strap_mii, tx_shift_strap[1:0], eeprom_size_strap, chip_mode_strap[1:0]. The value of “rrrr” is the current silicon revision. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.95 VENDOR ID REGISTER Offset: Bits 0E08h-0E0Fh Size: Description 64 bits ECAT Type PDI Type Default 63:32 RESERVED RO RO 00000000h 31:0 Vendor ID RO RO 000004D8h (Microchip) Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.96 DIGITAL I/O OUTPUT DATA REGISTER Offset: Bits 15:0 0F00h-0F01h Size: Description Output Data 16 bits ECAT Type PDI Type Default R/W RO 0000h Note: This register is bit-writable (using logical addressing). Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. DS00001909A-page 292 2015 Microchip Technology Inc. LAN9252 12.14.97 GENERAL PURPOSE OUTPUT REGISTER Offset: Bits 15:0 Note: 0F10h-0F11h Size: Description General Purpose Output Data 16 bits ECAT Type PDI Type Default R/W R/W 0000h For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.98 GENERAL PURPOSE INPUT REGISTER Offset: Bits 15:0 Note: 0F18h-0F19h Size: Description General Purpose Input Data 16 bits ECAT Type PDI Type Default RO RO 0000h For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.99 USER RAM Offset: Bits Note: 0F80h-0FFFh Description User RAM (128 Bytes) Size: 128 Bytes ECAT Type PDI Type Default R/W R/W Undefined For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 2015 Microchip Technology Inc. DS00001909A-page 293 LAN9252 12.14.100 DIGITAL I/O INPUT DATA REGISTER Offset: Bits 15:0 1000h-1001h Size: Description Input Data 16 bits ECAT Type PDI Type Default R/W R/W Undefined Note: This register is part of the Process RAM address space. The Process RAM is also directly addressable via the EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA) and EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA). Note: Process Data RAM is only accessible if EEPROM was correctly loaded (PDI Operational/EEPROM Loaded Correctly bit of ESC DL Status Register = 1) Note: Digital I/O Input Data is written into the Process Data RAM at these addresses if a Digital I/O PDI with inputs is configured. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.101 PROCESS DATA RAM Offset: Bits - 1000h-1FFFh Description Process Data RAM (4 KBytes) Size: 4 KBytes ECAT Type PDI Type Default R/W R/W Undefined Note: Process Data RAM is only accessible if EEPROM was correctly loaded (PDI Operational/EEPROM Loaded Correctly bit of ESC DL Status Register = 1) Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. DS00001909A-page 294 2015 Microchip Technology Inc. LAN9252 13.0 EEPROM INTERFACE The device contains an I2C master controller, which uses the EESCL and EESDA pins. EESCL and EESDA require an external pull-up resistor. Both 1 byte and 2 byte addressed EEPROMs are supported. The size is determined by the eeprom_size_strap. I2C Interface Timing Requirements 13.1 This section specifies the I2C master interface input and output timings. The I2C master interface runs in fast-mode with a rate of 148.8 kHz. FIGURE 13-1: I2C MASTER TIMING DIAGRAM EESDA (in) thd;dat;in tsu;dat;in tsu;dat;out thd;dat;out EESDA (out) S tlow tf tr Sr P EESCL thd;sta TABLE 13-1: thigh tsu;sta tsu;sto I2C MASTER TIMING VALUES Symbol Description Min Typ Max Units fscl EESCL clock frequency - 148.8 - kHz thigh EESCL high time 3.0 - - s tlow EESCL low time 3.0 - - s - 300 ns tr Rise time of EESDA and EESCL tf Fall time of EESDA and EESCL - 300 ns tsu;sta Setup time (provided to slave) of EESCL high before EESDA output falling for repeated start condition 1000 Note 41 - - ns thd;sta Hold time (provided to slave) of EESCL after EESDA output fall- 1000 ing for start or repeated start condition Note 41 - - ns tsu;dat;in Setup time (from slave) EESDA input before EESCL rising 200 Note 42 - - ns thd;dat;in Hold time (from slave) of EESDA input after EESCL falling 0 - - ns tsu;dat;out Setup time (provided to slave) EESDA output before EESCL rising 400 Note 42 - - ns thd;dat;out Hold time (provided to slave) of EESDA output after EESCL fall400 ing Note 42 - - ns Setup time (provided to slave) of EESCL high before EESDA output rising for stop condition - - ns tsu;sto 1000 Note 41 Note 41: These values provide 400 ns of margin compared to the I2C fast-mode specification. Note 42: These values provide ~2100 ns of margin compared to the I2C fast-mode specification. Note 43: These values provide 300 ns of setup margin and 400 ns of hold margin compared to the I2C fast-mode specification. 2015 Microchip Technology Inc. DS00001909A-page 295 LAN9252 14.0 CHIP MODE CONFIGURATION The mode of the chip is controlled by the chip_mode_strap[1:0] (CHIP_MODE1/CHIP_MODE0) hard-strap as follows: TABLE 14-1: CHIP MODE SELECTION CHIP_MODE[1:0] Mode 00 2 port mode. Port 0 = PHY A, Port 1 = PHY B 01 RESERVED 10 3 port downstream mode. Port 0 = PHY A, Port 1 = PHY B, Port 2 = MII 11 3 port upstream mode. Port 0 = MII, Port 1 = PHY B, Port 2 = PHY A Once the mode of the chip is selected, the Process Data Interface (PDI) in use is selected by the PDI Control Register (0x0140). The valid choices are as follows: TABLE 14-2: PDI MODE SELECTION PDI_SELECT PDI MODE 0x04 DIG I/O 0x80 SPI 0x88 HBI Multiplexed 1 Phase 8-bit 0x89 HBI Multiplexed 1 Phase 16-bit 0x8A HBI Multiplexed 2 Phase 8-bit 0x8B HBI Multiplexed 2 Phase 16-bit 0x8C HBI Indexed 8-bit 0x8D HBI Indexed 16-bit others RESERVED Note: The mode of the chip as selected by the chip_mode_strap[1:0] hard-strap is not affected by the PDI selection. Note: Due to pin sharing, when the device is in 3 port mode, the only usable interface is SPI. 14.1 HBI Sub-Configuration The PDI Configuration Register (0x0150) is used for the HBI configuration straps as shown in Table 123, "EtherCAT Core EEPROM Configurable Registers". The PDI Configuration Register (0x0150) is initialized from the contents of the EEPROM. DS00001909A-page 296 2015 Microchip Technology Inc. LAN9252 15.0 GENERAL PURPOSE TIMER & FREE-RUNNING CLOCK This chapter details the General Purpose Timer (GPT) and the Free-Running Clock. 15.1 General Purpose Timer The device provides a 16-bit programmable General Purpose Timer that can be used to generate periodic system interrupts. The resolution of this timer is 100 µs. The GPT loads the General Purpose Timer Count Register (GPT_CNT) with the value in the General Purpose Timer Pre-Load (GPT_LOAD) field of the General Purpose Timer Configuration Register (GPT_CFG) when the General Purpose Timer Enable (TIMER_EN) bit of the General Purpose Timer Configuration Register (GPT_CFG) is asserted (1). On a chip-level reset or when the General Purpose Timer Enable (TIMER_EN) bit changes from asserted (1) to deasserted (0), the General Purpose Timer Pre-Load (GPT_LOAD) field is initialized to FFFFh. The General Purpose Timer Count Register (GPT_CNT) is also initialized to FFFFh on reset. Once enabled, the GPT counts down until it reaches 0000h. At 0000h, the counter wraps around to FFFFh, asserts the GP Timer (GPT_INT) interrupt status bit in the Interrupt Status Register (INT_STS), asserts the IRQ interrupt (if GP Timer Interrupt Enable (GPT_INT_EN) is set in the Interrupt Enable Register (INT_EN)) and continues counting. GP Timer (GPT_INT) is a sticky bit. Once this bit is asserted, it can only be cleared by writing a 1 to the bit. Refer to Section 8.2.3, "General Purpose Timer Interrupt," on page 55 for additional information on the GPT interrupt. Software can write a pre-load value into the General Purpose Timer Pre-Load (GPT_LOAD) field at any time (e.g., before or after the General Purpose Timer Enable (TIMER_EN) bit is asserted). The General Purpose Timer Count Register (GPT_CNT) will immediately be set to the new value and continue to count down (if enabled) from that value. 15.2 Free-Running Clock The Free-Running Clock (FRC) is a simple 32-bit up-counter that operates from a fixed 25 MHz clock. The current FRC value can be read via the Free Running 25MHz Counter Register (FREE_RUN). On assertion of a chip-level reset, this counter is cleared to zero. On de-assertion of a reset, the counter is incremented once for every 25 MHz clock cycle. When the maximum count has been reached, the counter rolls over to zeros. The FRC does not generate interrupts. The free running counter can take up to 160 ns to clear after a reset event. Note: 15.3 General Purpose Timer and Free-Running Clock Registers This section details the directly addressable general purpose timer and free-running clock related System CSRs. For an overview of the entire directly addressable register map, refer to Section 5.0, "Register Map," on page 32. TABLE 15-1: MISCELLANEOUS REGISTERS ADDRESS Register Name (SYMBOL) 08Ch General Purpose Timer Configuration Register (GPT_CFG) 090h General Purpose Timer Count Register (GPT_CNT) 09Ch Free Running 25MHz Counter Register (FREE_RUN) 2015 Microchip Technology Inc. DS00001909A-page 297 LAN9252 15.3.1 GENERAL PURPOSE TIMER CONFIGURATION REGISTER (GPT_CFG) Offset: 08Ch Size: 32 bits This read/write register configures the device’s General Purpose Timer (GPT). The GPT can be configured to generate host interrupts at the interval defined in this register. The current value of the GPT can be monitored via the General Purpose Timer Count Register (GPT_CNT). Refer to Section 15.1, "General Purpose Timer," on page 297 for additional information. Bits 31:30 29 Description Type Default RESERVED RO - General Purpose Timer Enable (TIMER_EN) This bit enables the GPT. When set, the GPT enters the run state. When cleared, the GPT is halted. On the 1 to 0 transition of this bit, the GPT_LOAD field of this register will be preset to FFFFh. R/W 0b 0: GPT Disabled 1: GPT Enabled 28:16 RESERVED RO - 15:0 General Purpose Timer Pre-Load (GPT_LOAD) This value is pre-loaded into the GPT. This is the starting value of the GPT. The timer will begin decrementing from this value when enabled. R/W FFFFh DS00001909A-page 298 2015 Microchip Technology Inc. LAN9252 15.3.2 GENERAL PURPOSE TIMER COUNT REGISTER (GPT_CNT) Offset: 090h Size: 32 bits This read-only register reflects the current general purpose timer (GPT) value. The register should be used in conjunction with the General Purpose Timer Configuration Register (GPT_CFG) to configure and monitor the GPT. Refer to Section 15.1, "General Purpose Timer," on page 297 for additional information. Bits Description Type Default 31:16 RESERVED RO - 15:0 General Purpose Timer Current Count (GPT_CNT) This 16-bit field represents the current value of the GPT. RO FFFFh 2015 Microchip Technology Inc. DS00001909A-page 299 LAN9252 15.3.3 FREE RUNNING 25MHZ COUNTER REGISTER (FREE_RUN) Offset: 09Ch Size: 32 bits This read-only register reflects the current value of the free-running 25MHz counter. Refer to Section 15.2, "Free-Running Clock," on page 297 for additional information. Bits Description Type Default 31:0 Free Running Counter (FR_CNT) This field reflects the current value of the free-running 32-bit counter. At reset, the counter starts at zero and is incremented by one every 25 MHz cycle. When the maximum count has been reached, the counter will rollover to zero and continue counting. RO 00000000h Note: The free running counter can take up to 160nS to clear after a reset event. DS00001909A-page 300 2015 Microchip Technology Inc. LAN9252 16.0 MISCELLANEOUS This chapter describes miscellaneous functions and registers that are present in the device. 16.1 Miscellaneous System Configuration & Status Registers This section details the remainder of the directly addressable System CSRs. These registers allow for monitoring and configuration of various device functions such as the Chip ID/revision, byte order testing, and hardware configuration. For an overview of the entire directly addressable register map, refer to Section 5.0, "Register Map," on page 32. TABLE 16-1: MISCELLANEOUS REGISTERS ADDRESS Register Name (SYMBOL) 050h Chip ID and Revision (ID_REV) 064h Byte Order Test Register (BYTE_TEST) 074h Hardware Configuration Register (HW_CFG) 2015 Microchip Technology Inc. DS00001909A-page 301 LAN9252 16.1.1 CHIP ID AND REVISION (ID_REV) Offset: 050h Size: 32 bits This read-only register contains the ID and Revision fields for the device. Bits Description Type Default 31:16 Chip ID This field indicates the chip ID. RO 9252 15:0 Chip Revision This field indicates the design revision. RO Note 1 Note 1: Default value is dependent on device revision. DS00001909A-page 302 2015 Microchip Technology Inc. LAN9252 16.1.2 BYTE ORDER TEST REGISTER (BYTE_TEST) Offset: 064h Size: 32 bits This read-only register can be used to determine the byte ordering of the current configuration. Byte ordering is a function of the host data bus width and endianess. Refer to Section 9.0, "Host Bus Interface," on page 62 for additional information on byte ordering. The BYTE_TEST register can optionally be used as a dummy read register when assuring minimum write-to-read or read-to-read timing. Refer to Section 9.0, "Host Bus Interface," on page 62 for additional information. For host interfaces that are disabled during the reset state, the BYTE_TEST register can be used to determine when the device has exited the reset state. Note: This register can be read while the device is in the reset or not ready / power savings states without leaving the host interface in an intermediate state. If the host interface is in a reset state, returned data may be invalid. However, during reset, the returned data will not match the normal valid data pattern. Note: It is not necessary to read all fours BYTEs of this register. DWORD access rules do not apply to this register. Bits 31:0 Description Byte Test (BYTE_TEST) This field reflects the current byte ordering 2015 Microchip Technology Inc. Type Default RO 87654321h DS00001909A-page 303 LAN9252 16.1.3 HARDWARE CONFIGURATION REGISTER (HW_CFG) Offset: 074h Size: 32 bits This register allows the configuration of various hardware features. Note: This register can be read while the device is in the reset or not ready / power savings states without leaving the host interface in an intermediate state. If the host interface is in a reset state, returned data may be invalid. Note: It is not necessary to read all fours BYTEs of this register. DWORD access rules do not apply to this register. Bits 31:28 27 Description Type Default RESERVED RO - Device Ready (READY) When set, this bit indicates that the device is ready to be accessed. Upon power-up, RST# reset, return from power savings states, EtherCAT chip level or module level reset, or digital reset, the host processor may interrogate this field as an indication that the device has stabilized and is fully active. RO 0b This rising edge of this bit will assert the Device Ready (READY) bit in the Interrupt Status Register (INT_STS) and can cause an interrupt if enabled. Note: With the exception of the HW_CFG, PMT_CTRL, BYTE_TEST, and RESET_CTL registers, read access to any internal resources is forbidden while the READY bit is cleared. Writes to any address are invalid until this bit is set. Note: This bit is identical to bit 0 of the Power Management Control Register (PMT_CTRL). 26 RESERVED RO - 25 RESERVED RO - 24:22 RESERVED RO - 21:16 RESERVED RO - 15:14 RESERVED RO - 13:12 RESERVED RO - 11:0 RESERVED RO - DS00001909A-page 304 2015 Microchip Technology Inc. LAN9252 17.0 JTAG 17.1 JTAG A IEEE 1149.1 compliant TAP Controller supports boundary scan and various test modes. The device includes an integrated JTAG boundary-scan test port for board-level testing. The interface consists of four pins (TDO, TDI, TCK and TMS) and includes a state machine, data register array, and an instruction register. The JTAG pins are described in Table 3-14, “JTAG Pin Descriptions,” on page 28. The JTAG interface conforms to the IEEE Standard 1149.1 - 2001 Standard Test Access Port (TAP) and Boundary-Scan Architecture. All input and output data is synchronous to the TCK test clock input. TAP input signals TMS and TDI are clocked into the test logic on the rising edge of TCK, while the output signal TDO is clocked on the falling edge. JTAG pins are multiplexed with the GPIO/LED and EEPROM pins. The JTAG functionality is selected when the TESTMODE pin is asserted. The implemented IEEE 1149.1 instructions and their op codes are shown in Table 17-1. TABLE 17-1: IEEE 1149.1 OP CODES INSTRUCTION OP CODE COMMENT BYPASS 0 16'h0000 Mandatory Instruction BYPASS 1 16'hFFFF Mandatory Instruction SAMPLE/PRELOAD 16'hFFF8 Mandatory Instruction EXTEST 16'hFFE8 Mandatory Instruction CLAMP 16'hFFEF Optional Instruction ID_CODE 16'hFFFE Optional Instruction HIGHZ 16'hFFCF Optional Instruction INT_DR_SEL 16'hFFFD Private Instruction Note: The JTAG device ID is 00101445h Note: All digital I/O pins support IEEE 1149.1 operation. Analog pins and the OSCI / OSCO pins do not support IEEE 1149.1 operation. 2015 Microchip Technology Inc. DS00001909A-page 305 LAN9252 17.1.1 JTAG TIMING REQUIREMENTS This section specifies the JTAG timing of the device. FIGURE 17-1: JTAG TIMING ttckp ttckhl ttckhl TCK (Input) tsu th TDI, TMS (Inputs) tdov tdoinvld TDO (Output) TABLE 17-2: JTAG TIMING VALUES Symbol Description ttckp TCK clock period ttckhl TCK clock high/low time Min Max 40 ttckp*0.4 Units ns ttckp*0.6 ns tsu TDI, TMS setup to TCK rising edge 5 ns th TDI, TMS hold from TCK rising edge 5 ns tdov tdoinvld Note: TDO output valid from TCK falling edge TDO output invalid from TCK falling edge 15 0 Notes ns ns Timing values are with respect to an equivalent test load of 25 pF. DS00001909A-page 306 2015 Microchip Technology Inc. LAN9252 18.0 OPERATIONAL CHARACTERISTICS 18.1 Absolute Maximum Ratings* Supply Voltage (VDD12TX1, VDD12TX2, OSCVDD12, VDDCR) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +1.5 V Supply Voltage (VDD33TXRX1, VDD33TXRX2, VDD33BIAS, VDD33, VDDIO) (Note 1) . . . . . . . . . . . . . 0 V to +3.6 V Ethernet Magnetics Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +3.6 V Positive voltage on input signal pins, with respect to ground (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . VDDIO + 2.0 V Negative voltage on input signal pins, with respect to ground (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V Positive voltage on OSCI, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+3.6 V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Lead Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020 HBM ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JEDEC Class 3A Note 1: When powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested to use a clamp circuit. Note 2: This rating does not apply to the following pins: OSCI, RBIAS Note 3: This rating does not apply to the following pins: RBIAS *Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at any condition exceeding those indicated in Section 18.2, "Operating Conditions**", Section 18.5, "DC Specifications", or any other applicable section of this specification is not implied. Note, device signals are NOT 5 volt tolerant. 18.2 Operating Conditions** Supply Voltage (VDD12TX1, VDD12TX2, OSCVDD12, VDDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.14 V to +1.26 V Analog Port Supply Voltage (VDD33TXRX1, VDD33TXRX2, VDD33BIAS, VDD33) . . . . . . . . . . . . . . . +3.0 V to +3.6 V I/O Supply Voltage (VDDIO) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.62 V to +3.6 V Ethernet Magnetics Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.25 V to +3.6 V Ambient Operating Temperature in Still Air (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Note 4 Note 4: 0oC to +70oC for commercial version, -40oC to +85oC for industrial version, -40oC to +105oC for extended industrial version. Extended industrial temperature range is supported with the following restrictions: - 64-QFN package: External regulator required (Internal regulator disabled) and 2.5 V (typ) Ethernet magnetics voltage. **Proper operation of the device is guaranteed only within the ranges specified in this section. After the device has completed power-up, VDDIO and the magnetics power supply must maintain their voltage level with ±10%. Varying the voltage greater than ±10% after the device has completed power-up can cause errors in device operation. Note: Do not drive input signals without power supplied to the device. 2015 Microchip Technology Inc. DS00001909A-page 307 LAN9252 18.3 Package Thermal Specifications TABLE 18-1: 64-PIN QFN PACKAGE THERMAL PARAMETERS Parameter Symbol Value Units Thermal Resistance Junction to Ambient JA 23.6 °C/W Thermal Resistance Junction to Bottom of Case JT JC 0.1 °C/W Measured in still air 1.8 °C/W Airflow 1 m/s Thermal Resistance Junction to Top of Case TABLE 18-2: Comments Measured in still air 64-PIN TQFP-EP PACKAGE THERMAL PARAMETERS Parameter Symbol Value Units Thermal Resistance Junction to Ambient JA 29.0 °C/W Measured in still air Thermal Resistance Junction to Bottom of Case JT JC 0.3 °C/W Measured in still air 12.8 °C/W Airflow 1 m/s Thermal Resistance Junction to Top of Case Note: Comments Thermal parameters are measured or estimated for devices in a multi-layer 2S2P PCB per JESD51. TABLE 18-3: MAXIMUM POWER DISSIPATION Mode Maximum Power (mW) Internal Regulator Disabled, 2.5 V Ethernet Magnetics 568 Internal Regulator Disabled, 3.3 V Ethernet Magnetics 640 Internal Regulator Enabled, 2.5 V Ethernet Magnetics 749 Internal Regulator Enabled, 3.3 V Ethernet Magnetics 821 DS00001909A-page 308 2015 Microchip Technology Inc. LAN9252 18.4 Current Consumption and Power Consumption This section details the device’s typical supply current consumption and power dissipation for 100BASE-TX and power management modes of operation with the internal regulator enabled and disabled. 18.4.1 INTERNAL REGULATOR DISABLED TABLE 18-4: CURRENT CONSUMPTION AND POWER DISSIPATION (REGS. DISABLED) 3.3 V Device Current (mA) 1.2 V Device Current (mA) TX Magnetics Current (mA) (A) (B) (C) Note 5, Note 7 Note 6, Note 7 Note 8 Device Power with 2.5 V Magnetics (mW) Note 9, Note 10 Device Power with 3.3 V Magnetics (mW) Note 9, Note 11 Reset (RST#) Typ. 23.6 28.3 0.0 112 112 D0, 100BASE-TX with Traffic Typ. 58.7 51.0 82.0 461 526 D0, 100BASE-TX Idle Typ. 63.4 49.9 82.0 475 540 D0, PHY Energy Detect Power Down (both PHYs) Typ. 7.9 30.8 0.0 64 63 D0, PHY General Power Down (both PHYs) Typ. 1.5 30.6 0.0 42 42 D1, 100BASE-TX Idle Typ. 63.4 37.5 82.0 460 525 D1, PHY Energy Detect Power Down (both PHYs) Typ. 7.8 17.6 0.0 47 47 D1, PHY General Power Down (both PHYs) Typ. 1.5 17.7 0.0 27 27 D2, 100BASE-TX Idle Typ. 63.4 37.5 82.0 460 525 D2, PHY Energy Detect Power Down (both PHYs) Typ. 7.8 6.3 0.0 34 34 D2, PHY General Power Down (both PHYs) Typ. 1.5 6.1 0.0 13 13 D3, PHY General Power Down (both PHYs) Typ. 1.5 2.7 0.0 9 9 Note 5: VDD33TXRX1, VDD33TXRX2, VDD33BIAS, VDD33, VDDIO Note 6: VDD12TX1, VDD12TX2, OSCVDD12, VDDCR Note 7: Current measurements do not include power applied to the magnetics or the optional external LEDs. Note 8: The Ethernet component current is independent of the supply rail voltage (2.5V or 3.3V) of the transformer. Two copper TP operation is assumed. Current is half if one PHY is using 100BASE-FX mode. Current is zero if both PHYs are using 100BASE-FX mode. Note 9: This includes the power dissipated by the transmitter by way of the current through the transformer. Note 10: 3.3*(A) + 1.2*(B) + (2.5)*(C) @ Typ Note 11: 3.3*(A) + 1.2*(B) + (3.3)*(C) @ Typ 2015 Microchip Technology Inc. DS00001909A-page 309 LAN9252 18.4.2 INTERNAL REGULATOR ENABLED TABLE 18-5: CURRENT CONSUMPTION AND POWER DISSIPATION (REGS. ENABLED) 3.3 V Device Current (mA) TX Magnetics Current (mA) (A) (C) Note 12, Note 13, Note 14 Note 15 Device Power with 2.5 V Magnetics (mW) Note 16, Note 17 Device Power with 3.3 V Magnetics (mW) Note 16, Note 18 Reset (RST#) Typ. 51.2 0.0 169 169 D0, 100BASE-TX with Traffic Typ. 112.0 82.0 576 642 D0, 100BASE-TX Idle Typ. 113.5 82.0 580 646 D0, PHY Energy Detect Power Down (both PHYs) Typ. 39.7 0.0 132 132 D0, PHY General Power Down (both PHYs) Typ. 33.0 0.0 109 109 D1, 100BASE-TX Idle Typ. 100.5 82.0 537 603 D1, PHY Energy Detect Power Down (both PHYs) Typ. 26.0 0.0 86 86 D1, PHY General Power Down (both PHYs) Typ. 19.4 0.0 65 65 D2, 100BASE-TX Idle Typ. 100.5 82.0 537 603 D2, PHY Energy Detect Power Down (both PHYs) Typ. 14.8 0.0 49 49 D2, PHY General Power Down (both PHYs) Typ. 7.8 0.0 26 26 D3, PHY General Power Down (both PHYs) Typ. 4.3 0.0 15 15 Note 12: VDD33TXRX1, VDD33TXRX2, VDD33BIAS, VDD33, VDDIO Note 13: VDD12TX1 and VDD12TX2, are driven by the internal regulator via the PCB. The current is accounted for via VDD33. Note 14: Current measurements do not include power applied to the magnetics or the optional external LEDs. Note 15: The Ethernet component current is independent of the supply rail voltage (2.5V or 3.3V) of the transformer. Two copper TP operation is assumed. Current is half if one PHY is using 100BASE-FX mode. Current is zero if both PHYs are using 100BASE-FX mode. Note 16: This includes the power dissipated by the transmitter by way of the current through the transformer. Note 17: 3.3*(A) + (2.5)*(C) @ Typ Note 18: 3.3*(A) + (3.3)*(C) @ Typ DS00001909A-page 310 2015 Microchip Technology Inc. LAN9252 18.5 DC Specifications TABLE 18-6: NON-VARIABLE I/O DC ELECTRICAL CHARACTERISTICS Parameter Symbol Min Low Input Level VILI High Input Level Typ Max Units -0.3 0.8 V VIHI 2.0 3.6 V VHYS 121 151 mV Input Leakage (VIN = VSS or VDD33) IIH -10 10 µA Input Capacitance CIN 3 pF Pull-Up Impedance (VIN = VSS) RDPU 6 8.9 KΩ Pull-Down Impedance (VIN = VDD33) RDPD 52 79 KΩ Low Input Level VIL -0.3 0.8 V High Input Level VIH 1.2 VDD33+0.3 V Differential Input Level VIN-DIFF 0.1 VDD33TXRXx V Common Mode Voltage VCM 1.0 Input Capacitance CIN Notes IS Type Input Buffer Schmitt Trigger Hysteresis (VIHT - VILT) Note 19 AI Type Input Buffer (FXSDENA/FXSDENB) AI Type Input Buffer (RXPA/RXNA/RXPB/RXNB) VDD33TXRXx-1.3 V 5 pF AI Type Input Buffer (FXLOSEN Input) State A Threshold VTHA -0.3 0.8 V State B Threshold VTHB 1.2 1.7 V State C Threshold VTHC 2.3 VDD33+0.3 V Note 20 ICLK Type Input Buffer (OSCI Input) Low Input Level VILI -0.3 0.35 V High Input Level VIHI OSCVDD12-0.35 3.6 V Input Leakage IILCK -10 10 µA 2015 Microchip Technology Inc. DS00001909A-page 311 LAN9252 TABLE 18-6: NON-VARIABLE I/O DC ELECTRICAL CHARACTERISTICS (CONTINUED) Parameter Symbol Min Low Input Level VIL-VDD33TXRXx High Input Level VIH-VDD33TXRXx Typ Max Units Notes VDD33TXRXx+0.3 -1.48 V Note 21 -1.14 0.3 V Note 21 VDD33TXRXx-1.62 V ILVPECL Input Buffer OLVPECL Output Buffer Low Output Level VOL High Output Level VOH VDD33TXRXx-1.025 Peak-to-Peak Differential (SFF mode) VDIFF-SFF 1.2 1.6 2.0 V Peak-to-Peak Differential (SFP mode) VDIFF-SFP 0.6 0.8 1.0 V VCM 1.0 VDD33TXRXx-1.3 V 40 mV Common Mode Voltage Offset Voltage VOFFSET Load Capacitance V CLOAD 10 Note 22 pF Note 19: This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down and pull-up resistors add +/- 50 µA per-pin (typical). Note 20: OSCI can optionally be driven from a 25 MHz singled-ended clock oscillator. Note 21: LVPECL compatible. Note 22: VOFFSET is a function of the external resistor network configuration. The listed value is recommended to prevent issues due to crosstalk. DS00001909A-page 312 2015 Microchip Technology Inc. LAN9252 TABLE 18-7: VARIABLE I/O DC ELECTRICAL CHARACTERISTICS Parameter 1.8 V Typ 3.3 V Typ Symbol Min Max Units Low Input Level VILI -0.3 High Input Level VIHI Negative-Going Threshold VILT 0.64 0.83 Positive-Going Threshold VIHT 0.81 Schmitt Trigger Hysteresis (VIHT - VILT) VHYS 102 Input Leakage (VIN = VSS or VDDIO) IIH -10 Input Capacitance CIN Pull-Up Impedance (VIN = VSS) RDPU 54 68 82 KΩ Pull-Up Current (VIN = VSS) IDPU 20 27 67 µA Pull-Down Impedance (VIN = VDD33) RDPD 54 68 85 KΩ Pull-Down Current (VIN = VDD33) IDPD 19 26 66 µA Notes VIS Type Input Buffer V 3.6 V 1.41 1.76 V Schmitt trigger 0.99 1.65 1.90 V Schmitt trigger 158 138 288 mV 10 µA 2 pF Note 23 VO8 Type Buffers Low Output Level VOL High Output Level VOH 0.4 VDDIO - 0.4 V IOL = 8 mA V IOH = -8 mA VOD8 Type Buffer Low Output Level VOL 0.4 V IOL = 8 mA Low Output Level VOL 0.4 V IOL = 12 mA High Output Level VOH V IOH = -12 mA V IOL = 12 mA V IOH = -12 mA V IOL = 16 mA V IOH = -16 mA VO12 Type Buffers VDDIO - 0.4 VOD12 Type Buffer Low Output Level VOL 0.4 VOS12 Type Buffers High Output Level VOH VDDIO - 0.4 VO16 Type Buffers Low Output Level VOL High Output Level VOH 2015 Microchip Technology Inc. 0.4 VDDIO - 0.4 DS00001909A-page 313 LAN9252 Note 23: This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down and pull-up resistors add ±50 µA per-pin (typical). TABLE 18-8: 100BASE-TX TRANSCEIVER CHARACTERISTICS Parameter Symbol Min Typ Max Units Notes Peak Differential Output Voltage High VPPH 950 - 1050 mVpk Note 24 Peak Differential Output Voltage Low VPPL -950 - -1050 mVpk Note 24 Signal Amplitude Symmetry VSS 98 - 102 % Note 24 Signal Rise and Fall Time TRF 3.0 - 5.0 ns Note 24 Rise and Fall Symmetry TRFS - - 0.5 ns Note 24 Duty Cycle Distortion DCD 35 50 65 % Note 25 Overshoot and Undershoot VOS - - 5 % - - - 1.4 ns Jitter Note 26 Note 24: Measured at line side of transformer, line replaced by 100 Ω (+/- 1%) resistor. Note 25: Offset from 16 ns pulse width at 50% of pulse peak. Note 26: Measured differentially. DS00001909A-page 314 2015 Microchip Technology Inc. LAN9252 18.6 AC Specifications This section details the various AC timing specifications of the device. Note: The I2C timing adheres to the NXP I2C-Bus Specification. Refer to the NXP I2C-Bus Specification for detailed I2C timing information. Note: The MII/SMI timing adheres to the IEEE 802.3 Specification. Note: The RMII timing adheres to the RMII Consortium RMII Specification R1.2. 18.6.1 EQUIVALENT TEST LOAD Output timing specifications assume the 25 pF equivalent test load, unless otherwise noted, as illustrated in Figure 18-1. FIGURE 18-1: OUTPUT EQUIVALENT TEST LOAD OUTPUT 25 pF 2015 Microchip Technology Inc. DS00001909A-page 315 LAN9252 18.6.2 POWER SEQUENCING TIMING These diagrams illustrates the device power sequencing requirements. The VDDIO, VDD33, VDD33TXRX1, VDD33TXRX2, VDD33BIAS and magnetics power supplies must all reach operational levels within the specified time period tpon. When operating with the internal regulators disabled, VDDCR, OSCVDD12, VDD12TX1 and VDD12TX2 are also included into this requirement. In addition, once the VDDIO power supply reaches 1.0 V, it must reach 80% of its operating voltage level (1.44 V when operating at 1.8 V, 2.0 V when operating at 2.5 V, 2.64 V when operating at 3.3 V) within an additional 15ms. This requirement can be safely ignored if using an external reset as shown in Section 18.6.3, "Reset and Configuration Strap Timing". Device power supplies can turn off in any order provided they all reach 0 volts within the specified time period tpoff. FIGURE 18-2: POWER SEQUENCE TIMING - INTERNAL REGULATORS tpon tpoff VDDIO Magnetics Power VDD33, VDD33BIAS, VDD33TXRX1, VDD33TXRX2 FIGURE 18-3: POWER SEQUENCE TIMING - EXTERNAL REGULATORS tpon tpoff VDDIO Magnetics Power VDD33, VDD33BIAS, VDD33TXRX1, VDD33TXRX2 VDDCR, OSCVDD12, VDD12TX1, VDD12TX2 TABLE 18-9: POWER SEQUENCING TIMING VALUES Symbol Description Min Typ Max Units tpon Power supply turn on time - - 50 ms tpoff Power supply turn off time - - 500 ms DS00001909A-page 316 2015 Microchip Technology Inc. LAN9252 18.6.3 RESET AND CONFIGURATION STRAP TIMING This diagram illustrates the RST# pin timing requirements and its relation to the configuration strap pins and output drive. Assertion of RST# is not a requirement. However, if used, it must be asserted for the minimum period specified. The RST# pin can be asserted at any time, but must not be deasserted until tpurstd after all external power supplies have reached operational levels. Refer to Section 6.2, "Resets," on page 38 for additional information. FIGURE 18-4: All External Power Supplies RST# PIN CONFIGURATION STRAP LATCHING TIMING Vopp tpurstd trstia RST# tcss tcsh Configuration Strap Pins todad Output Drive TABLE 18-10: RST# PIN CONFIGURATION STRAP LATCHING TIMING VALUES Symbol tpurstd Description External power supplies at operational level to RST# deassertion Min Typ Max 25 Units ms trstia RST# input assertion time 200 - - s tcss Configuration strap pins setup to RST# deassertion 200 - - ns tcsh Configuration strap pins hold after RST# deassertion 10 - - ns todad Output drive after deassertion 3 - - us Note: The clock input must be stable prior to RST# deassertion. Note: Device configuration straps are latched as a result of RST# assertion. Refer to Section 6.2.1, "Chip-Level Resets," on page 39 for details. Note: Configuration strap latching and output drive timings shown assume that the Power-On reset has finished first otherwise the timings in Section 18.6.4, "Power-On and Configuration Strap Timing" apply. 2015 Microchip Technology Inc. DS00001909A-page 317 LAN9252 18.6.4 POWER-ON AND CONFIGURATION STRAP TIMING This diagram illustrates the configuration strap valid timing requirements in relation to power-on. In order for valid configuration strap values to be read at power-on, the following timing requirements must be met. FIGURE 18-5: POWER-ON CONFIGURATION STRAP LATCHING TIMING All External Power Supplies Vopp tcfg Configuration Straps TABLE 18-11: POWER-ON CONFIGURATION STRAP LATCHING TIMING VALUES Symbol tcfg Note: Description Configuration strap valid time Min Typ Max Units - - 15 ms Configuration straps must only be pulled high or low. Configuration straps must not be driven as inputs. Device configuration straps are also latched as a result of RST# assertion. Refer to Section 18.6.3, "Reset and Configuration Strap Timing" and Section 6.2.1, "Chip-Level Resets," on page 39 for additional details. DS00001909A-page 318 2015 Microchip Technology Inc. LAN9252 18.6.5 HOST BUS INTERFACE I/O TIMING Timing specifications for the Host Bus Interface are given in Section 9.4.5, "Multiplexed Addressing Mode Timing Requirements," on page 78 and Section 9.5.7, "Indexed Addressing Mode Timing Requirements," on page 98. 18.6.6 SPI/SQI SLAVE INTERFACE I/O TIMING Timing specifications for the SPI/SQI Slave Bus Interface are given in Section 10.3, "SPI/SQI Timing Requirements," on page 119. 18.6.7 I2C EEPROM I/O TIMING Timing specifications for I2C EEPROM access are given in Section 13.1, "I2C Interface Timing Requirements," on page 295. 18.6.8 ETHERCAT MII PORT MANAGEMENT ACCESS I/O TIMING Timing specifications for the MII Port Management access are given in Section 12.9.7, "External PHY Timing," on page 206. 18.6.9 MII I/O TIMING Timing specifications for the MII Port interface are given in Section 12.9.7, "External PHY Timing," on page 206. 18.6.10 JTAG TIMING Timing specifications for the JTAG interface are given in Table 17.1.1, “JTAG Timing Requirements,” on page 306. 2015 Microchip Technology Inc. DS00001909A-page 319 LAN9252 18.7 Clock Circuit The device can accept either a 25 MHz crystal or a 25 MHz single-ended clock oscillator (±50 ppm) input. If the singleended clock oscillator method is implemented, OSCO should be left unconnected and OSCI should be driven with a clock signal that adheres to the specifications outlined throughout Section 18.0, "Operational Characteristics". See Table 18-12 for the recommended crystal specifications. TABLE 18-12: CRYSTAL SPECIFICATIONS PARAMETER SYMBOL MIN NOM Crystal Cut UNITS NOTES AT, typ Crystal Oscillation Mode Fundamental Mode Crystal Calibration Mode Parallel Resonant Mode Frequency MAX Ffund - 25.000 - MHz 802.3 Frequency Tolerance at 25oC Ftol - - ±40 ppm Note 27 802.3 Frequency Stability Over Temp Ftemp - - ±40 ppm Note 27 802.3 Frequency Deviation Over Time Fage - ±3 to 5 - ppm Note 28 - - ±50 ppm Note 29 Ftol - - ±15 ppm Note 30 EtherCAT Frequency Stability Over Temp Ftemp - - ±15 ppm Note 30 EtherCAT Frequency Deviation Over Time Fage - ±3 to 5 - ppm Note 28 - - ±25 ppm Note 31 802.3 Total Allowable PPM Budget EtherCAT Frequency Tolerance at 25oC EtherCAT Total Allowable PPM Budget Shunt Capacitance CO - - 7 pF Load Capacitance CL - - 18 pF Drive Level PW 300 Note 32 - - µW Equivalent Series Resistance R1 - - 100 Ω Note 33 - Note 34 oC OSCI Pin Capacitance - 3 typ - pF Note 35 OSCO Pin Capacitance - 3 typ - pF Note 35 Operating Temperature Range Note 27: The maximum allowable values for frequency tolerance and frequency stability are application dependent. Since any particular application must meet the IEEE ±50 ppm Total PPM Budget, the combination of these two values must be approximately ±45 ppm (allowing for aging). Note 28: Frequency Deviation Over Time is also referred to as Aging. Note 29: The total deviation for 100BASE-TX is ±50 ppm. Note 30: The maximum allowable values for frequency tolerance and frequency stability are application dependent. Since any particular application must meet the EtherCAT ±25 ppm Total PPM Budget, the combination of these two values must be approximately ±15 ppm (allowing for aging). DS00001909A-page 320 2015 Microchip Technology Inc. LAN9252 Note 31: The total deviation for EtherCAT is ±25 ppm. Note 32: The minimum drive level requirement PW is reduced to 100 uW with the addition of a 500 Ω series resistor, if CO 5 pF, CL 12 pF and R180 Ω Note 33: 0 °C for commercial version, -40 °C for industrial and extended industrial versions Note 34: +70 °C for commercial version, +85 °C for industrial version, +105 °C for extended industrial version Note 35: This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included in this value. The OSCI pin, OSCO pin and PCB capacitance values are required to accurately calculate the value of the two external load capacitors. The total load capacitance must be equivalent to what the crystal expects to see in the circuit so that the crystal oscillator will operate at 25.000 MHz. 2015 Microchip Technology Inc. DS00001909A-page 321 LAN9252 19.0 PACKAGE OUTLINES 19.1 64-QFN FIGURE 19-1: DS00001909A-page 322 64-QFN PACKAGE 2015 Microchip Technology Inc. LAN9252 FIGURE 19-2: 64-QFN PACKAGE DIMENSIONS 2015 Microchip Technology Inc. DS00001909A-page 323 LAN9252 19.2 64-TQFP-EP FIGURE 19-3: DS00001909A-page 324 64-TQFP-EP PACKAGE 2015 Microchip Technology Inc. LAN9252 20.0 REVISION HISTORY TABLE 20-1: REVISION HISTORY Revision Level DS00001909A (04-08-15) 2015 Microchip Technology Inc. Section/Figure/Entry Correction Initial Release DS00001909A-page 325 LAN9252 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support DS00001909A-page 326 2015 Microchip Technology Inc. LAN9252 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X] PART NO. Device / [X] Tape and Reel Temperature Option Range Device: LAN9252 Tape and Reel Option: Blank T = Standard packaging (tray) = Tape and Reel(Note 1) Temperature Range: Blank I V = 0C to +70C = -40C to +85C = -40C to +105C Package: ML PT = = 64-pin QFN 64-pin TQFP-EP XX Package Examples: a) LAN9252/ML Standard Packaging (Tray), Commercial Temperature, 64-pin QFN b) LAN9252TI/PT Tape and Reel Industrial Temperature, 64-pin TQFP-EP (Commercial) (Industrial) (Extended Industrial)(Note 2) Note 1: 2: 2015 Microchip Technology Inc. Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Extended industrial temp. support (105ºC) in the 64-QFN only DS00001909A-page 327 LAN9252 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN:9781632771957 QUALITYMANAGEMENTSYSTEM CERTIFIEDBYDNV == ISO/TS16949== DS00001909A-page 328 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2015 Microchip Technology Inc. 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