DG0625: Interfacing RTG4 FPGA with the External DDR3 Memory Through FDDR - Libero SoC v11.7 Demo Guide

Interfacing RTG4 FPGA with External DDR3
Memory Through FD - Libero SoC v11.7
DG0625 Demo Guide
Contents
1 Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
1.2
1.3
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR . . . . . . . . . . . 6
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Demo Design Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Demo Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5.1
DDR_AXI_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5.2
UART_IF_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Demo Design Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.6.1
Simulation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6.2
Running the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Demo Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Programming the Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Running the Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.9.1
Steps to Run the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.9.2
Performing a Single Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.9.3
Performing Burst Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3 Appendix: RTG4 DDR Memory Controller Configuration and Initialization . . . . . . . 27
3.1
3.2
3.3
Importing DDR Configuration Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FDDR Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DDR Memory Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4 Appendix: Finding Correct COM Port Number when Using USB 3.0 . . . . . . . . . . . 31
5 Appendix: Performing Write or Read Operation when Non 64-bit Aligned Address is
Provided . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7 Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1
7.2
7.3
7.4
7.5
7.6
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.1
Email . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.2
My Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.3
Outside the U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 3
36
36
36
36
36
36
36
37
37
2
Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Demo Design Files Top-Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
RTG4 DDR Demo Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
RTG4_DDR_Demo SmartDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DDR_AXI_0 SmartDesign Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
UART_IF_0 SmartDesign Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DO File Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Waveforms Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Invoking Organize Stimulus Files Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Organize Stimulus Files Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Transcript Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Single Write and Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16-Beat AXI Burst Write and Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
RTG4 Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
USB Serial 2.0 Port Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
FlashPro New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FlashPro Project Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FlashPro Program Passed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
RTG4_DDR_Demo_Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RTG4_DDR_Demo - Connection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Single Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Clear Data Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Single Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Burst Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Burst Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
RTG4 FDDR Configuration Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FDDR Configurator - Memory Initialization tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FDDR Configurator - Memory Timing tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
USB 3.0 Serial Port Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Read Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Non 64-bit Aligned Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Converted 64-bit Aligned Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Revision 3
3
Tables
Table 1.
Table 2.
Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
RTG4 Development Kit Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision 3
4
Preface
1
Preface
1.1
Purpose
This demo guide is for RTG4™ field programmable gate arrays (FPGA) devices. It provides instructions
on how to use the corresponding demo design.
1.2
Intended Audience
This document is intended for:
•
•
1.3
FPGA designers
System-level designers
References
See the following web page for a complete and up-to-date listing of RTG4 device documentation:
http://www.microsemi.com/products/fpga-soc/radtolerant-fpgas/rtg4#documents
The following documents are referred in this demo guide:
•
•
•
UG0573: RTG4 FPGA High Speed DDR Interfaces User Guide
UG0617: RTG4 FPGA Development Kit User Guide
CoreUART Handbook
Revision 3
5
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
2
Interfacing RTG4 FPGA with External DDR3
Memory Through FDDR
2.1
Introduction
This demo shows how the FPGA fabric logic can access external double-data rate three (DDR3)
memories using built-in fabric double-data rate (FDDR) in RTG4 devices.
The demo has two parts:
•
•
Simulation
Running the demo on the RTG4 Development Kit
In the demo design, the AXI Master in the FPGA fabric accesses the DDR memory present in the RTG4
Development Kit using the FDDR. A host utility, RTG4_DDR_Demo_Utility is provided along with the
demo design files. Using the utility, you can drive the AXI Master logic. The AXI Master converts the
commands from the utility to AXI transactions for the FDDR to perform the read or write operations on
the external DDR3 memory.
2.2
Design Requirements
Table 1 shows the design requirements.
Table 1 • Design Requirements
Design Requirements
Description
Hardware Requirements
RTG4 Development Kit:
• RTG4-DEV-KIT-ES
• 12 V adapter
• USB A to Mini-B cable
Rev A or later
Host PC or Laptop
Any 64-bit Windows Operating System
Software Requirements
Libero® System-on-Chip (SoC)
v11.7
FlashPro programming software
v11.7
Host PC Drivers
USB to UART drivers
Revision 3
6
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
2.3
Demo Design
2.3.1
Introduction
The demo design files are available for download from the following path in the Microsemi website:
http://soc.microsemi.com/download/rsc/?f=rt4g_dg0625_liberov11p7_df
The demo design files include:
•
•
•
•
•
Demo_Utility
Libero_project
•
RTG4_DDR_Demo
Programming_file
Source_files
readme.txt
Figure 1 shows the top-level structure of the design files. For further details, see the readme.txt file.
Figure 1 • Demo Design Files Top-Level Structure
<download_folder>
RTG4_DDR_Demo_DF
Demo_Utility
Libero_project
RTG4_DDR_Demo
Programming_file
Source_file
readme.txt
Figure 1 shows the top-level view of demo design. In the demo design, the AXI Master implemented in
the FPGA fabric accesses the DDR3 memory present on the RTG4 Development Kit using the FDDR.
The AXI Master logic communicates to the FDDR through CoreAXI interface and the DDR_FIC interface.
The read or write operations initiated by the RTG4_DDR_Demo_Utility are sent to the UART_IF block
using the UART protocol. The AXI Master receives the address and data from the UART_IF block.
During a write operation, the UART_IF block sends the address and data to the AXI Master logic.
During a read operation, the UART_IF block sends the address to the AXI Master. The AXI Master reads
the data from DDR3 memory and stores it in TPSRAM. When the read operation is complete, the data
read is sent to the host PC through UART.
Revision 3
7
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
Figure 2 • RTG4 DDR Demo Block Diagram
57*
)''5&B:LWKB,1,7B
)''5
'
'
5
,
2
''5
6'5$0
'
'
5
3
+
<
''5
&RQWUROOHU
)''5B,1,7
$;,
7UDQVDFWLRQ
&RQWUROOHU
&RUH$%&
''5B),&
&RUH$3%
$3%&RQILJ
5HJ
8$57B,)B)60
&RUH$;,
$;,0DVWHU
8$57&RPPXQLFDWLRQ
&RUH8$57
8VHU*8,
,QWHUIDFH
+RVW3&
7365$0
8$57B,)
)3*$)$%5,&
/HJHQG
8$57&RPPXQLFDWLRQ3URWRFRO
'DWDDQG&RQWURO3DWK8$57B,)DQG$;,B0DVWHU
'DWDDQG&RQWURO3DWKͲ$;,B0DVWHUDQG''50HPRU\
In this demo design, different blocks are configured, as shown below:
•
•
•
•
•
FDDR is configured for DDR3 memory available on the RTG4 Development Kit. The DDR3 memory
is a Micron DRAM (Part Number: MT41K256M8DA-125 IT:K).
DDR_FIC is configured for AXI bus interface.
AXI clock is configured for 80 MHz and DDR3 clock is configured for 320 MHz.
CoreUART IP has the following configuration:
•
Baud Rate: 115200
•
Data Bits: 8
•
Parity: None
RTG4TPSRAM has the following configuration:
•
Write port depth: 256
•
Write port width: 64
•
Read port depth: 1024
•
Read port width: 16
See "Appendix: RTG4 DDR Memory Controller Configuration and Initialization" on page 27 for
information on how to configure the FDDR.
Revision 3
8
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
2.4
Demo Design Features
The RTG4 DDR demo design has the following features:
•
•
•
•
•
2.5
Single AXI read or write transactions
16-beat burst AXI read or write transactions
DDR3 memory model simulation using testbench
Design validation using the RTG4 Development Kit that has the DDR3 memory
Initiation of the read or write transactions using RTG4_DDR_Demo_Utility
Demo Design Description
The demo design consists of the following SmartDesign components:
•
•
DDR_AXI_0: Handles the data transactions between the FDDR and the DDR3 SDRAM.
UART_IF_0: Handles the communication between the host PC and the RTG4 Development Kit.
Figure 3 shows the DDR_AXI_0 and UART_IF_0 connection.
Figure 3 • RTG4_DDR_Demo SmartDesign
Revision 3
9
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
2.5.1
DDR_AXI_0
DDR_AXL0 consists of the FDDR subsystem and the AXI_IF_0 master logic. The AXI_IF_0 master logic
is an RTL code that implements the AXI read and write transactions. It receives the read or write
operations, burst length (RLEN and WLEN), address and data as inputs. Based on inputs received, it
communicates with the DDR3 memory through the FDDR. Figure 4 shows the DDR_AXI_0 SmartDesign
component.
Figure 4 • DDR_AXI_0 SmartDesign Component
Revision 3
10
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
2.5.2
UART_IF_0
The UART_IF_0 SmartDesign component handles the UART communication between the host PC demo
utility and the AXI Master logic. The COREUART_0 IP receives the UART signals from the host PC user
interface. The UART_IF_FSM_0 is a wrapper for the COREUART_0, collects the data from the
COREUART_0 IP and converts the data to the relevant AXI_IF_0 master signals.
For a single write operation, the UART_IF_FSM_0 wrapper receives the address and data from the
demo utility. For a burst write operation, the address and data are received from the demo utility and the
subsequent incremental data are provided by the UART_IF_FSM_0 wrapper.
For a burst read operation, UART_IF_FSM_0 collects the address from the demo utility and sends that to
the AXI_IF_0 master logic. It receives the read data from the AXI_IF_0 master logic and stores it in the
RTG4TPSRAM_0. After completion of the read burst transactions, the UART_IF_FSM_0 wrapper
fetches the stored data from the RTG4TPSRAM_0 and sends it to the COREUART IP. Figure 5 shows
the UART_IF_0 SmartDesign component.
Figure 5 • UART_IF_0 SmartDesign Component
2.6
Demo Design Simulation
The demo design can be simulated using testbench and Micron DDR3 memory model.
The simulation is set to run the following:
•
•
Single AXI write and read operation
16-beat AXI burst write and read operation.
To run the simulation, ensure that the following files are present in the Libero SoC project:
•
•
•
ddr3.v
ddr3_parameters.vh
testbench.v
The default location of the files is:
<Download folder>\RTG4_DDR_Demo_DF\Libero_project\RTG4_DDR_Demo\stimulus
Revision 3
11
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
2.6.1
Simulation Setup
The following steps describe how to setup the Simulation
1.
2.
3.
4.
Launch the Libero SoC software.
Browse the RTG4_DDR_Demo project provided in the design file.
Choose Project > Project Settings > Simulation Options.
Ensure that the DO File tab has the configuration, as shown in Figure 6.
Figure 6 • DO File Settings
5.
Ensure that the Waveforms tab has the configuration, as shown in Figure 7.
Figure 7 • Waveforms Settings
Revision 3
12
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
6.
7.
Go to Design Flow tab.
Right-click Simulate under Verify Pre-Synthesized Design and select Organize Input Files >
Organize Stimulus Files..., as shown in Figure 8.
Figure 8 • Invoking Organize Stimulus Files Window
Revision 3
13
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
8.
Ensure that the Organize Stimulus files window has the configuration, as shown in Figure 9.
Figure 9 • Organize Stimulus Files Window
Revision 3
14
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
2.6.2
Running the Simulation
The following steps describe how to run the simulation:
1.
2.
Right-click Simulate under Verify Pre-Synthesized Design.
Click Open Interactively.
Simulation run time is 700 µs, as shown in Figure 6 on page 12. Figure 10 shows the transcript window of the simulation.
Figure 10 • Transcript Window
Revision 3
15
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
Figure 11 shows the single AXI write and AXI read operation.
Figure 11 • Single Write and Read Operation
Figure 12 shows the 16-beat AXI burst write and read operation.
Figure 12 • 16-Beat AXI Burst Write and Read
Revision 3
16
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
2.7
Demo Setup
This demo design uses the RTG4 Development Kit. Figure 13 shows the RTG4 Development Kit. The
following steps describe how to setup the hardware demo:
1.
Connect the jumpers on the RTG4 Development Kit, as shown in Table 2.
Table 2 • RTG4 Development Kit Jumper Settings
Jumper
Pin (from)
Pin (to)
Comments
J32
1
2
Default
J27
1
2
Default
J26
1
2
Default
J23
1
2
Default
J21
1
2
Default
J19
1
2
Default
J11
1
2
Default
J16
2
3
Default
CAUTION: Ensure that the power supply switch SW6 is switched OFF while connecting the jumpers.
2.
3.
Connect the power supply to the J9 connector, switch ON the power supply switch, SW6.
Connect the host PC USB port to the RTG4 Development Kit J47 USB connector using the USB A to
mini-B cable.
Figure 13 • RTG4 Development Kit
Revision 3
17
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
4.
Ensure that the USB to UART bridge drivers are automatically detected. This can be verified in the
Device Manager of the host PC. The FTDI USB to UART converter enumerates four COM ports.
For USB 2.0, note down the USB Serial Converter C COM port number to use it in the GUI.
Figure 14 shows the USB 2.0 serial port properties. As shown in Figure 14, COM6 is connected to
USB serial converter C. See "Appendix: Finding Correct COM Port Number when Using USB 3.0"
on page 31 for finding the correct COM port in USB 3.0.
Figure 14 • USB Serial 2.0 Port Properties
5.
2.8
If the USB to UART bridge drivers are not installed, download and install the drivers from
www.microsemi.com/soc/documents/CDM_2.08.24_WHQL_Certified.zip.
Programming the Demo Design
The following steps describe how to program the demo design:
1.
2.
3.
4.
5.
6.
7.
8.
Download the demo design from the following link:
http://soc.microsemi.com/download/rsc/?f=rt4g_dg0625_liberov11p7_df
Switch ON the power supply switch SW6.
Launch the FlashPro software.
Click New Project.
In the New Project window, type the project name as RTG4_DDR_Demo.
Click Browse and navigate to the location where you want to save the project.
Select Single device as the Programming mode.
Click OK to save the project.
Revision 3
18
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
Figure 15 • FlashPro New Project
9. Click Configure Device on the FlashPro GUI.
10. Click Browse and navigate to the location where RTG4_DDR_Demo.stp file is located, and select
the file. The default location is: <download_folder>\RTG4_DDR_Demo_DF\Programming_file\.
11. Click Open. The required programming file is selected and is ready to be programmed in the device.
Figure 16 • FlashPro Project Configuration
Revision 3
19
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
12. Click PROGRAM to start programming the device. Wait until the Programmer Status is changed to
RUN PASSED.
Figure 17 • FlashPro Program Passed
Revision 3
20
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
2.9
Running the Demo
The RTG4 DDR demo comes with utility, RTG4_DDR_Demo_Utility that runs on the host PC to
communicate with the RTG4 Development Kit. The UART protocol is used as the underlying
communication protocol between the host PC and the RTG4 Development Kit. Figure 18 shows initial
screen of the RTG4_DDR_Demo_Utility.
Figure 18 • RTG4_DDR_Demo_Utility
The RTG4_DDR_Demo_Utility consists of the following sections:
•
•
•
•
•
Serial Port Configuration: Displays the serial port. Baud rate is fixed at 115200.
Data Transfer Type: Single or Burst.
DDR SDRAM: Provides Address and Data.
DDR Burst Read: Displays the Burst Read Values for the corresponding address.
C: Clears the existing data.
Revision 3
21
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
2.9.1
Steps to Run the GUI
The following steps describe how to run the GUI:
1.
2.
3.
Launch the utility. The default location is:
<download_folder>\\RTG4_DDR_Demo_DF\Demo_Utility\RTG4_DDR.exe.
Select the appropriate COM port from drop down menu. In this case, it is COM 28.
Click Connect. The connection status along with the COM Port and Baud rate is shown in the left
bottom corner of the screen. Figure 19 shows the connection status of the utility.
Figure 19 • RTG4_DDR_Demo - Connection Status
Revision 3
22
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
2.9.2
Performing a Single Data Transfer
For a single write or read operation, the AXI Master logic is configured to transfer a burst length of 1 (that
is, 8 bytes). For a write operation, the utility sends a 32-bit address and 64-bit (8 bytes) data. The data is
then written to the DDR3 SDRAM. For a read operation, the utility sends a 32-bit address and receives
64-bit data from DDR3 and is displayed in the utility.
The following steps describe how to perform a single data transfer:
1.
2.
3.
4.
Select Single (8-bytes) as Data Transfer Type.
A 64-bit aligned address is required in the address field. Enter a 32-bit HEX Address in the range
0x00000000 - 0x03FFFFF8. When a non 64-bit aligned address is provided, the GUI converts it to
64-bit aligned address and performs the write or read. See "Appendix: Performing Write or Read
Operation when Non 64-bit Aligned Address is Provided" on page 33 to perform write or read when
non 64-bit aligned address is provided.
In the Data field, enter a 64-bit data in HEX format.
Click Write. The entered data is written to the DDR3 memory. Figure 20 shows the Address and
Data values entered for a Single Write operation.
Figure 20 • Single Write Operation
Revision 3
23
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
5.
6.
To verify the write operation, perform a read operation to the same address where the data is written.
Press C to clear the data present in the Data field. Figure 21 highlights the Clear button, C.
Figure 21 • Clear Data Field
7.
Click Read to read the data from the DDR3 SDRAM. Figure 22 shows the data read from the DDR3
SDRAM.
Figure 22 • Single Read Operation
8.
Compare the read and write data. The write and read data being same establishes that the write and
read operations to the DDR3 SDRAM were successful.
Revision 3
24
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
2.9.3
Performing Burst Data Transfer
For a burst write or read operation, the AXI Master logic is configured to transfer a burst length of 16 (that
is, 128 bytes). In this demo, 16 transfers of 16-beat burst operations are implemented (16 transfers x 16beat burst data = 2048 bytes data). For a write operation, the utility sends a 32-bit initial address and
64-bit (8 bytes) initial data. After the initial write operation, incremental data is written. For a read
operation, the utility sends a 32-bit address and receives 2048 bytes of data from the DDR3 SDRAM and
the data is displayed in the utility.
The following steps describe how to perform a burst data transfer:
1.
2.
3.
4.
Select Burst (2048-bytes) as Data Transfer Type.
A 64-bit aligned address is required in the address field. Enter a 32-bit HEX Address in the range
0x00000000 - 0x03FFF7F8. When a non 64-bit aligned address is provided, the GUI converts it into
64-bit aligned address and performs the write or read operation. See "Appendix: Performing Write or
Read Operation when Non 64-bit Aligned Address is Provided" on page 33 to perform write or read
when non 64-bit aligned address is provided.
In the Data field, enter a 64-bit data in HEX format.
Click Write. The entered data is written to the Address location specified in the Address filed and
then the data is incremented by 1 and written to the next address location. This is repeated 256
times to write all the 2048 bytes of data. Figure 23 shows the Address and Data values entered for
a Burst Write operation.
Figure 23 • Burst Write Operation
Revision 3
25
Interfacing RTG4 FPGA with External DDR3 Memory Through FDDR
5.
6.
To verify the write operation, perform a read operation to the same address where the data is written.
Click Read. All the 2048 bytes of data written to the DDR3 SDRAM is read, and the read data is
displayed on the DDR Burst Read panel. Figure 24 shows the burst read data.
Figure 24 • Burst Read Operation
7.
2.10
Click Exit to exit the utility.
Conclusion
This demo shows how to perform read or write operations to DDR3 SDRAM using RTG4 FDDR. Options
are provided to simulate the design using a testbench and validate the design on the RTG4 Development
Kit using a GUI interface.
Revision 3
26
Appendix: RTG4 DDR Memory Controller Configuration and Initialization
3
Appendix: RTG4 DDR Memory Controller
Configuration and Initialization
This section describes how to configure and initialize the RTG4 DDR memory controller.
Launch RTG4 DDR Memory Controller with Initialization configurator using the RTG4 DDR Memory
Controller with initialization SgCore in Libero. Use the RTG4 DDR Memory Controller Configurator to
configure the FDDR, select its datapath bus interface (AXI or AHB), and select the DDR clock frequency
as well as the fabric datapath clock frequency.
1.
In the RTG4 DDR Memory Controller with Initialization configurator, under General tab, configure
the settings as shown in Figure 25.
Figure 25 • RTG4 FDDR Configuration Window
Revision 3
27
Appendix: RTG4 DDR Memory Controller Configuration and Initialization
2.
Set the register values for the FDDR registers to match your external DDR memory characteristics.
The FDDR has a set of registers that must be configured at runtime. The configuration values for
these registers represent different parameters. Use the Memory Initialization tab, as shown in
Figure 26 and Memory Timing tab, as shown in Figure 27 on page 29 to enter parameters that
correspond to your DDR Memory and application. Consult your DDR Memory vendor's datasheet for
values to enter in Memory Initialization and Memory Timing tabs. Values you enter in these tabs
are automatically translated to the appropriate register values. When you click a specific parameter,
a brief description of the corresponding register is described in the register description window of the
Fabric External Memory FDDR Configurator. For more details on FDDR configuration registers,
see the UG0573: RTG4 FPGA High Speed DDR Interfaces User Guide.
Figure 26 • FDDR Configurator - Memory Initialization tab
Revision 3
28
Appendix: RTG4 DDR Memory Controller Configuration and Initialization
Figure 27 • FDDR Configurator - Memory Timing tab
3.
3.1
Instantiate the FDDR as part of a user application and make the datapath connections.
Importing DDR Configuration Files
In addition to entering DDR Memory parameters using the Memory Initialization and Timing tabs, you can
import the DDR register values from a file. Click Import Configuration and navigate to the text file with
the DDR register names and values. The DDR3 configuration file for the Micron memory available on the
RTG4 development kit is provided along with the design files.
Note: If you choose to import register values rather than entering them using the GUI, you must specify all the
required register values.
3.2
FDDR Initialization
The RTG4 DDR Memory Controller with initialization Sgcore has a built-in initialization state machine. On
the assertion or de-assertion of the INIT_RESET_N (Active Low) signal, the FDDR block is initialized
with the user configurations. When the configuration phase is complete, the INIT_DONE signal is
asserted and the FDDR block is ready for normal operations. You can have the FDDR initialization start
automatically at power up by connecting the INIT_RESET_N (Active Low) input of the FDDR block to the
POWER_ON_RESET_N (Active Low) signal of the SYSRESET macro.
The clock used for initialization must be a 50 MHz clock which is connected to the INIT_CLK 50 MHz
signal.
Revision 3
29
Appendix: RTG4 DDR Memory Controller Configuration and Initialization
3.3
DDR Memory Settling Time
The RTG4 DDR memory controller block is hard-coded with a DDR memory settling time of 200 µs,
assuming that the clock period of INIT_CLK is 20 ns (frequency 50 MHz). Microsemi recommends that
the initialization frequency be kept at 50 MHz.
See your DDR Memory vendor's datasheet for the correct memory settling time to use. An incorrect
memory settling time may result in the failure of the DDR memory to initialize during operation. If a
different memory settling time is required for your DDR memory or you choose to use a different
INIT_CLK frequency than the recommended 50 MHz, you must edit the program code in the Program tab
of CoreABC to change the load value of the register used to compute the settling time.
Revision 3
30
Appendix: Finding Correct COM Port Number when Using USB 3.0
4
Appendix: Finding Correct COM Port Number
when Using USB 3.0
FTDI USB to UART converter enumerates the four COM ports. In USB 3.0, the four available COM ports
are in Location 0. Figure 28 shows the USB 3.0 Serial port properties.
Figure 28 • USB 3.0 Serial Port Properties
Revision 3
31
Appendix: Finding Correct COM Port Number when Using USB 3.0
The following steps describe how to find out the correct COM port:
1.
2.
Program the RTG4 Development Kit with provided programming file.
Connect each available COM port and click Write.
If wrong COM port is selected, the GUI displays the Read Error message.
3.
Try with all four available COM ports until this message disappears.
Figure 29 shows the Read Error message.
Figure 29 • Read Error
Revision 3
32
Appendix: Performing Write or Read Operation when Non 64-bit Aligned
Address is Provided
5
Appendix: Performing Write or Read
Operation when Non 64-bit Aligned Address
is Provided
When a non 64-bit aligned address is provided in the GUI, the GUI converts it into the 64-bit aligned
address (0, 8, 10, 18, 20, 28, 30, 38 …) and performs the write or read operation.
1.
2.
Enter the non 64-bit aligned 32-bit address in HEX format.
Enter the 64-bit data in HEX format. Figure 30 shows the non 64-bit aligned Address entered in the
GUI.
Figure 30 • Non 64-bit Aligned Address
Revision 3
33
Appendix: Performing Write or Read Operation when Non 64-bit Aligned
Address is Provided
3.
Click Write to perform write operation. GUI converts the address into 64-bit aligned address and
performs the write operation. Figure 31 shows the GUI pop-up information message and converted
64-bit aligned address.
Figure 31 • Converted 64-bit Aligned Address
Revision 3
34
Revision History
6
Revision History
The following table shows important changes made in this document for each revision.
Revision
Changes
Revision 3
(April 2016)
Updated the document for Libero v11.7 software release (SAR 77988).
Revision 2
(November 2015)
Updated the document for Libero v11.6 software release (SAR 73523).
Revision 1
(July 2015)
Initial release
Revision 3
35
Product Support
7
Product Support
Microsemi SoC Products Group backs its products with various support services, including Customer
Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.
This appendix contains information about contacting Microsemi SoC Products Group and using these
support services.
7.1
Customer Service
Contact Customer Service for non-technical product support, such as product pricing, product upgrades,
update information, order status, and authorization.
From North America, call 800.262.1060
From the rest of the world, call 650.318.4460
Fax, from anywhere in the world, 408.643.6913
7.2
Customer Technical Support Center
Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled
engineers who can help answer your hardware, software, and design questions about Microsemi SoC
Products. The Customer Technical Support Center spends a great deal of time creating application
notes, answers to common design cycle questions, documentation of known issues, and various FAQs.
So, before you contact us, please visit our online resources. It is very likely we have already answered
your questions.
7.3
Technical Support
For Microsemi SoC Products Support, visit
http://www.microsemi.com/products/fpga-soc/design-support/fpga-soc-support.
7.4
Website
You can browse a variety of technical and non-technical information on the Microsemi SoC Products
Group home page, at http://www.microsemi.com/products/fpga-soc/fpga-and-soc.
7.5
Contacting the Customer Technical Support
Center
Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be
contacted by email or through the Microsemi SoC Products Group website.
7.5.1
Email
You can communicate your technical questions to our email address and receive answers back by email,
fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.
We constantly monitor the email account throughout the day. When sending your request to us, please
be sure to include your full name, company name, and your contact information for efficient processing of
your request.
The technical support email address is [email protected]
7.5.2
My Cases
Microsemi SoC Products Group customers may submit and track technical cases online by going to My
Cases.
Revision 3
36
Product Support
7.5.3
Outside the U.S.
Customers needing assistance outside the US time zones can either contact technical support via email
([email protected]) or contact a local sales office. Visit About Us for sales office listings and
corporate contacts.
7.6
ITAR Technical Support
For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms
Regulations (ITAR), contact us via [email protected] Alternatively, within My Cases, select Yes
in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web
page.
Revision 3
37
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor
and system solutions for communications, defense & security, aerospace and industrial
markets. Products include high-performance and radiation-hardened analog mixed-signal
integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and
synchronization devices and precise time solutions, setting the world's standard for time; voice
processing devices; RF solutions; discrete components; enterprise storage and communication
solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Powerover-Ethernet ICs and midspans; as well as custom design capabilities and services.
Microsemi is headquartered in Aliso Viejo, Calif, and has approximately 4,800 employees
globally. Learn more at www.microsemi.com.
Microsemi Corporate
Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
E-mail: [email protected]
© 2016 Microsemi Corporation. All
rights reserved. Microsemi and the
Microsemi logo are trademarks of
Microsemi Corporation. All other
trademarks and service marks are the
property of their respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or
the suitability of its products and services for any particular purpose, nor does Microsemi assume any
liability whatsoever arising out of the application or use of any product or circuit. The products sold
hereunder and any other products sold by Microsemi have been subject to limited testing and should not
be used in conjunction with mission-critical equipment or applications. Any performance specifications are
believed to be reliable but are not verified, and Buyer must conduct and complete all performance and
other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely
on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's
responsibility to independently determine suitability of any products and to test and verify the same. The
information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire
risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or
implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such
information itself or anything described by such information. Information provided in this document is
proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
50200625-3/4.16
Similar pages