DS0131: RTG4 FPGA Datasheet

RTG4 FPGA
DS0131 Datasheet
DS0131: RTG4 FPGA Datasheet
Table of Contents
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. Device Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3. Product Briefs and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4. General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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4.1. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2. Overshoot/Undershoot Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3. Power-Up and Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5.1. Quiescent Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6. Average Fabric Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
7. User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7.1. Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7.2. Output Buffer and AC Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.3. Tristate Buffer and AC Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.4. I/O Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.5. Detailed I/O Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.6. Single-Ended I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.7. Memory Interface and Voltage Referenced I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.8. Differential I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.9. I/O Register Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.10. DDR Module Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8. Logic Element Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.1. LUT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.2. Sequential Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9. Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10. FPGA Fabric SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.1. FPGA Fabric Large SRAM (LSRAM)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.2. FPGA Fabric Micro SRAM (µSRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.3. FPGA Fabric Micro PROM (µPROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12. DEVRST_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13. On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14. Clock Conditioning Circuits (CCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15. System Controller SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16. Mathblock Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17. PCIe Electrical and Timing AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18. SpaceWire Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19. List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20. Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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20.1. Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.2. Product Brief . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.3. Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.4. Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.5. Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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21. Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . 89
22. Microsemi Corporate Headquarters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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DS0131: RTG4 FPGA Datasheet
List of Figures
Figure 1. Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Output Buffer and AC Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Tristate Buffer for Enable Path Test Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Timing Model for Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 5. I/O Register Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 6. Timing Model for Output/Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 7. I/O Register Output Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 8. Input DDR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 9. Input DDR Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 10. Output DDR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 11. Output DDR Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 12. LUT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 13. Sequential Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 14. Sequential Module Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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List of Tables
Table 1. RTG4 FPGA Device Status ............................................................................................................................. 1
Table 2. Absolute Maximum Ratings ............................................................................................................................ 2
Table 3. Recommended Operating Conditions ............................................................................................................. 3
Table 4. FPGA Operating Limits ................................................................................................................................... 3
Table 5. Device Storage Temperature and Retention ................................................................................................... 4
Table 6. Package Thermal Resistance ......................................................................................................................... 5
Table 7. Quiescent Supply Current Characteristics ...................................................................................................... 6
Table 8. RTG4 Quiescent Supply Current – Typical Process ....................................................................................... 6
Table 9. Average Temperature and Voltage Derating Factors for Fabric Timing Delays .............................................. 6
Table 10. Maximum I/O Data Rate Summary for Worst-Case Military Conditions ........................................................ 9
Table 11. Maximum I/O Frequency Summary for Worst-Case Military Conditions ..................................................... 10
Table 12. Input Capacitance ....................................................................................................................................... 11
Table 13. I/O Weak Pull-Up/Pull-Down Resistance Values for DDRIO, MSIO, and MSIOD Banks ............................ 11
Table 14. Schmitt Trigger Input Hysteresis ................................................................................................................. 11
Table 15. LVTTL/LVCMOS 3.3 V DC Voltage Specification (Applicable to MSIO I/O Bank Only) .............................. 12
Table 16. LVTTL/LVCMOS 3.3 V Maximum Switching Speeds (Applicable to MSIO I/O Bank Only) ........................ 12
Table 17. LVTTL/LVCMOS 3.3 V AC Test Parameter Specifications (Applicable to MSIO Bank Only) ..................... 12
Table 18. LVTTL/LVCMOS 3.3 V Transmitter Drive Strength Specifications
(Applicable to MSIO Bank Only) ................................................................................................................................. 13
Table 19. LVTTL/LVCMOS 3.3 V Receiver Characteristics for MSIO I/O Banks (Input Buffers) ................................ 13
Table 20. LVTTL/LVCMOS 3.3 V Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers) ....... 13
Table 21. LVCMOS 2.5 V DC Voltage Specification ................................................................................................... 14
Table 22. LVCMOS 2.5 V Maximum AC Switching Speeds ........................................................................................ 14
Table 23. LVCMOS 2.5 V AC Test Parameters and Driver Impedance Specifications ............................................... 14
Table 24. LVCMOS 2.5 V AC Switching Characteristics for Receiver (Input Buffers) ................................................ 15
Table 25. LVCMOS 2.5 V Transmitter Drive Strength Specifications ......................................................................... 15
Table 26. LVCMOS 2.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ...................... 15
Table 27. LVCMOS 1.8 V DC Voltage Specification ................................................................................................... 16
Table 28. LVCMOS 1.8 V AC Switching Characteristics for Receiver (Input Buffers) ................................................ 17
Table 29. LVCMOS 1.8 V Maximum AC Switching Speeds ........................................................................................ 17
Table 30. LVCMOS 1.8 V Transmitter Drive Strength Specifications ......................................................................... 17
Table 31. LVCMOS 1.8 V AC Test Parameters and Driver Impedance Specifications ............................................... 17
Table 32. LVCMOS 1.8 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ...................... 18
Table 33. LVCMOS 1.5 V Minimum and Maximum DC Input and Output Levels ....................................................... 19
Table 34. LVCMOS 1.5 V Maximum AC Switching Speeds ........................................................................................ 19
Table 35. LVCMOS 1.5 V AC Test Parameters and Driver Impedance Specifications ............................................... 19
Table 36. LVCMOS 1.5 V Transmitter Drive Strength Specifications ......................................................................... 19
Table 37. LVCMOS 1.5 V AC Switching Characteristics for Receiver (Input Buffers) ................................................ 20
Table 38. LVCMOS 1.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ...................... 20
Table 39. LVCMOS 1.2 V Minimum and Maximum DC Input and Output Levels ....................................................... 21
Table 40. LVCMOS 1.2 V Maximum AC Switching Speeds ........................................................................................ 21
Table 41. LVCMOS 1.2 V AC Switching Characteristics for Receiver (Input Buffers) ................................................ 22
Table 42. LVCMOS 1.2 V AC Test Parameters and Driver Impedance Specifications ............................................... 22
Table 43. LVCMOS 1.2 V Transmitter Drive Strength Specifications ......................................................................... 22
Table 44. LVCMOS 1.2 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ...................... 22
Table 45. PCI/PCI-X DC Voltage Specification (Applicable to MSIO Bank Only ........................................................ 23
Table 46. PCI/PCIX AC Switching Characteristics for Receiver (Input Buffers) .......................................................... 24
Table 47. PCI/PCIX AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ............................... 24
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Revision 2
DS0131: RTG4 FPGA Datasheet
Table 48. PCI/PCI-X AC Specifications (Applicable to MSIO Bank Only) ................................................................... 24
Table 49. HSTL18 Minimum and Maximum DC Input and Output Levels ................................................................... 25
Table 50. HSTL18 AC Switching Characteristics for Receiver (Input Buffers) ............................................................ 26
Table 51. HSTL18 Minimum and Maximum AC Switching Speeds ............................................................................ 26
Table 52. HSTL18 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ................................. 27
Table 53. HSTL 1.5 V DC Voltage Specification ......................................................................................................... 28
Table 54. HSTL 1.5 V AC Switching Characteristics for Receiver (Input Buffers) ...................................................... 29
Table 55. HSTL 1.5 V AC Specifications .................................................................................................................... 29
Table 56. HSTL 1.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ............................ 30
Table 57. DDR1/SSTL2 Minimum and Maximum DC Input and Output Levels .......................................................... 31
Table 58. DDR1/SSTL2 AC Specifications ................................................................................................................. 31
Table 59. DDR1/SSTL2 AC Switching Characteristics for Receiver (Input Buffers) ................................................... 32
Table 60. DDR1/SSTL2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ........................ 33
Table 61. DDR2/SSTL18 DC Minimum and Maximum Input and Output Levels Specification ................................... 34
Table 62. DDR2/SSTL18 AC Specifications (Applicable to DDRIO Bank Only) ......................................................... 35
Table 63. DDR2/SSTL18 AC Switching Characteristics for Receiver (Input Buffers) ................................................. 36
Table 64. DDR2/SSTL18 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ...................... 37
Table 65. DDR3 SSTL15 DC Voltage Specification (for DDRIO I/O Bank Only) ........................................................ 38
Table 66. DDR3/SSTL15 AC Specifications ............................................................................................................... 38
Table 67. DDR3/STTL15 AC Switching Characteristics for Receiver (Input Buffers) ................................................. 39
Table 68. DDR3/SSTL15 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ...................... 39
Table 69. LPDDR DC Specifications (for DDRIO IO Bank Only) ................................................................................ 40
Table 70. LPDDR Maximum AC Switching Speeds (for DDRIO I/O Bank Only) ........................................................ 40
Table 71. LPDDR AC Switching Characteristics for Receiver (Input Buffers) ............................................................. 41
Table 72. LPDDR AC Specifications (for DDRIO IO Bank Only) ................................................................................ 41
Table 73. LPDDR AC Switching Characteristics for Transmitter (Output and Tristate Buffers) .................................. 42
Table 74. LPDDR-LVCMOS 1.8 V Mode, Minimum and Maximum DC Input and Output Levels
(Applicable to DDRIO I/O Bank Only) ......................................................................................................................... 42
Table 75. LPDDR-LVCMOS 1.8 V Maximum AC Switching Speeds (Applicable to DDRIO I/O Bank Only) .............. 42
Table 76. LPPDR - LVCMOS 1.8 V AC Switching Characteristics for Receiver (Input Buffers) ................................. 43
Table 77. LPDDR-LVCMOS 1.8 V AC Test Parameters and Driver Impedance Specifications (Applicable to DDRIO I/O
Bank Only) .................................................................................................................................................................. 43
Table 78. LPDDR-LVCMOS 1.8 V Mode Transmitter Drive Strength Specification (Applicable to DDRIO I/O
Bank Only) .................................................................................................................................................................. 43
Table 79. LPDDR - LVCMOS 1.8 V AC Switching Characteristics for Transmitter DDRIO I/O Bank (Output and Tristate
Buffers) ........................................................................................................................................................................ 44
Table 80. LVDS DC Voltage Specification (Applicable to MSIO and MSIOD Banks Only) ......................................... 44
Table 81. LVDS25 Receiver Characteristics ............................................................................................................... 45
Table 82. LVDS AC Specifications (Applicable to MSIO and MSIOD Banks Only) .................................................... 45
Table 83. LVDS25 Transmitter Characteristics ........................................................................................................... 46
Table 84. LVDS33 Receiver Characteristics ............................................................................................................... 46
Table 85. LVDS33 Transmitter Characteristics ........................................................................................................... 46
Table 86. B-LVDS DC Voltage Specification (Applicable to MSIO and MSIOD Banks Only) ..................................... 47
Table 87. B-LVDS AC Specifications (Applicable to MSIO and MSIOD Banks Only) ................................................. 47
Table 88. B-LVDS AC Switching Characteristics for Receiver (Input Buffers) ............................................................ 48
Table 89. B-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ................................. 48
Table 90. M-LVDS DC Voltage Specification (Applicable to MSIO and MSIOD Banks Only) ..................................... 48
Table 91. M-LVDS AC Switching Characteristics for Receiver (Input Buffers) ........................................................... 49
Table 92. M-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ................................. 49
Table 93. M-LVDS AC Specifications (Applicable to MSIO and MSIOD Banks Only) ................................................ 49
Table 94. Mini-LVDS DC Voltage Specification (Applicable to MSIO and MSIOD Banks Only) ................................. 50
Table 95. Mini-LVDS AC Specifications (Applicable to MSIO and MSIOD Banks Only) ............................................. 50
Table 96. Mini-LVDS AC Switching Characteristics for Receiver (Input Buffers) ........................................................ 51
Table 97. Mini-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ............................. 51
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Table 98. RSDS DC Voltage Specification (Applicable to MSIO and MSIOD Banks Only) ........................................ 51
Table 99. RSDS AC Switching Characteristics for Receiver (Input Buffers) ............................................................... 52
Table 100. RSDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers) .................................. 52
Table 101. RSDS AC Specifications (Applicable to MSIO and MSIOD Banks Only) .................................................. 52
Table 102. LVPECL DC Voltage Specification (Applicable to MSIO I/O Banks Only) ................................................ 53
Table 103. LVPECL Maximum AC Switching Speeds (Applicable to MSIO I/O Banks Only) ..................................... 53
Table 104. LVPECL Receiver Characteristics ............................................................................................................ 53
Table 105. Input Data Register Propagation Delays ................................................................................................... 55
Table 106. Output/Enable Data Register Propagation Delays .................................................................................... 57
Table 107. Input DDR Propagation Delays ................................................................................................................. 61
Table 108. Output DDR Propagation Delays .............................................................................................................. 64
Table 109. Combinatorial Cell Propagation Delays .................................................................................................... 65
Table 110. Register Delays ......................................................................................................................................... 67
Table 111. RT4G150 Device Global Resource ........................................................................................................... 67
Table 112. RAM1K18 – Dual-Port Mode for Depth × Width Configuration 1Kx18 ...................................................... 68
Table 113. RAM1K18 - Dual-Port Mode for Depth x Width Configuration 2Kx12 ....................................................... 70
Table 114. RAM1K18 - Dual-Port Mode for Depth x Width Configuration 2Kx9 ......................................................... 71
Table 115. RAM1K18 - Two-Port Mode for Depth x Width Configuration 512x36 ...................................................... 72
Table 116. µSRAM (RAM64x18) - in 64x18 Mode ...................................................................................................... 73
Table 117. µSRAM (RAM64x18) - in 128x12 Mode .................................................................................................... 76
Table 118. µSRAM (RAM64x18) - in 128x9 Mode ...................................................................................................... 78
Table 119. µPROM ..................................................................................................................................................... 80
Table 120. JTAG 1532 ................................................................................................................................................ 81
Table 121. DEVRST_N Characteristics ...................................................................................................................... 81
Table 122. Electrical Characteristics of the 50 MHz RC Oscillator ............................................................................. 81
Table 123. RTG4 FPGAs CCC/PLL Specification ...................................................................................................... 82
Table 124. System Controller SPI Characteristics ...................................................................................................... 83
Table 125. Supported I/O Configurations for System Controller SPI (for MSIO Bank Only) ....................................... 83
Table 126. Mathblocks With All Registers Used ......................................................................................................... 84
Table 127. Mathblock With Input Bypassed and Output Registers Used ................................................................... 84
Table 128. Mathblock With Input Register Used and Output in Bypass Mode ............................................................ 85
Table 129. Mathblock With Input and Output in Bypass Mode ................................................................................... 85
Table 130. PCIe Transmitter Parameters ................................................................................................................... 85
Table 131. PCIe Receiver Parameters ....................................................................................................................... 86
Table 132. SERDES Reference Clock AC Specifications ........................................................................................... 86
Table 133. HCSL DC Voltage Specification (Applicable to SERDES REFCLK only) ................................................. 86
Table 134. HCSL AC Specifications (Applicable to SERDES REFCLK only) ............................................................. 87
Table 135. SpaceWire Clock and Data Recovery Characteristics .............................................................................. 87
iii
Revision 2
RTG4 FPGA AC/DC Electrical Characteristics
1. Introduction
RTG4™ FPGAs integrate Microsemi’s fourth-generation flash-based FPGA fabric and high-performance
interfaces such as serialization/deserialization (SERDES) on a single-chip while maintaining the
resistance to radiation-induced configuration upsets in the harshest radiation environments, such as
space flight (LEO, MEO, GEO, HEO, deep space), high altitude aviation, medical electronics, and
nuclear power plant control. The RTG4 family offers up to 151,824 registers, which are hardened by
design against radiation-induced single-event upsets (SEUs). Each RTG4 logic element includes a 4input lookup table (LUT4) with fast carry chains providing high-performance FPGA fabric up to 300 MHz.
There are multiple embedded memory options and embedded multiply-accumulate blocks for digital
signal processing (DSP) up to 300 MHz. A high-speed serial interface provides 3.125 Gbps native
SERDES communication, while double data rate DDR2/DDR3/LPDDR memory controllers provide
high-speed memory interfaces.
2. Device Status
For more information on device status, refer to the "Datasheet Categories" section on page 88.
Table 1 •
RTG4 FPGA Device Status
Device
Status
RT4G150
Preliminary
RT4G075
Preliminary
3. Product Briefs and Pin Descriptions
The product brief and pin descriptions are published separately:
•
RTG4 FPGAs Product Brief
•
RTG4 FPGA Pin Descriptions
R e visio n 2
2-1
RTG4 FPGA AC/DC Electrical Characteristics
4. General Specifications
4.1 Operating Conditions
Stresses beyond those listed in Table 2 may cause permanent damage to the device. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Absolute maximum ratings are stress ratings only; functional operation of the device at these or any other conditions
beyond those listed under the recommended operating conditions specified in Table 2 is not implied.
Table 2 •
Absolute Maximum Ratings
Limits
Symbol
Parameter
Min
Max
Units
-0.3
1.32
V
VPP
Power supply for charge pumps (for normal operation and
-0.3
programming). Must always power this pin.
3.63
V
VDDPLL
Power for eight corner PLLs, PLLs in SERDES PCIe/PCS
-0.3
blocks, and FDDR PLL.
3.63
V
SERDES_x_Lyz_VDDAIO
Tx/Rx analog I/O voltage. Low voltage power for lane-y and
-0.3
Lane-z of SERDES_x. It is a +1.2 V SERDES PMA supply.
1.32
V
SERDES_x_Lyz_VDDAPLL
Analog power for SERDES_x PLL lanes yz. It is a +2.5 V
-0.3
SERDES internal PLL supply.
2.75
V
SERDES_VDDI
Power for SERDES reference clock receiver supply. Must
-0.3
always power this pin.
3.63
V
DC FPGA I/O bank supply voltage for MSIO and JTAG I/O
-0.3
Banks
3.63
V
DC FPGA I/O bank supply voltage for MSIOD and DDRIO I/O
-0.3
Banks
2.75
V
VDD
DC FPGA core supply voltage. Must always power this pin.
VDDIx
Notes
I/O Input voltage for MSIO and JTAG I/O Banks
-0.3
3.63
V
I/O Input voltage for MSIOD and DDRIO I/O Banks
-0.3
2.75
V
TSTG
Storage temperature
-65
150
°C
*
TJ
Junction temperature
-
135
°C
*
VI
Note: * For flash programming and retention maximum limits, refer to Table 4 on page 3. For recommended operating conditions,
refer to Table 3 on page 3. For recommended device storage temperature range, refer to Table 5 on page 4.
1 -2
Revision 2
DS0131: RTG4 FPGA Datasheet
Table 3 •
Recommended Operating Conditions
Symbol
Parameter
Operating Junction Temperature
TJ
Programming Junction Temperature
Min
Typ
Max
Units
-55
25
125
°C
0
25
85
°C
VDD
DC FPGA core supply voltage. Must always
power this pin.
1.14
1.2
1.26
V
VPP
Power supply for charge pumps (for normal
operation and programming). Must always
power this pin.
3.15
3.3
3.45
V
VDDPLL
Power for eight corner PLLs, PLLs in
SERDES PCIe/PCS blocks, and FDDR PLL.
3.15
3.3
3.45
V
SERDES_x_Lyz_VDDAIO
Tx/Rx analog I/O voltage. Low voltage
power for lane-y and Lane-z of SERDES_x.
It is a +1.2 V SERDES PMA supply.
1.14
1.2
1.26
V
SERDES_x_Lyz_VDDAPLL
Analog power for SERDES_x PLL lanes yz.
It is a +2.5 V SERDES internal PLL supply.
2.375
2.5
2.625
V
Power for SERDES reference clock receiver
1.8 V supply. Must always power this pin.
1.71
1.8
1.89
V
Power for SERDES reference clock receiver
2.5 V supply. Must always power this pin.
2.375
2.5
2.625
V
Power for SERDES reference clock receiver
3.3 V supply. Must always power this pin.
3.15
3.3
3.45
V
SERDES_VDDI
SERDES_VREF
VDDIx
0.49 ×
SERDES_V
DDI
Reference voltage for SERDES receiver
reference clocks
0.5 ×
0.51 ×
SERDES_V SERDES_V
DDI
DDI
V
1.2 V DC supply voltage for FPGA I/O Banks
1.14
1.2
1.26
V
1.5 V DC supply voltage for FPGA I/O Banks
1.425
1.5
1.575
V
1.8 V DC supply voltage for FPGA and JTAG
I/O Banks
1.71
1.8
1.89
V
2.5 V DC supply voltage for FPGA and JTAG
I/O Banks
2.375
2.5
2.625
V
3.3 V DC supply voltage for FPGA and JTAG
I/O Banks
3.15
3.3
3.45
V
DC supply voltage for LVDS differential I/O
Banks
2.375
2.5
3.45
V
DC supply voltage for BLVDS, MLVDS, MiniLVDS, RSDS differential I/O Banks
2.375
2.5
2.625
V
DC supply voltage for LVPECL differential
I/O Banks
3.15
3.3
3.45
V
Note: Power supply ramps must all be strictly monotonic, without plateaus.
Table 4 •
FPGA Operating Limits
Programming Temperature
Min TJ = 0°C
Max TJ = 85°C
Operating Temperature
Programming Cycles
Retention (Biased/Unbiased)
Min TJ = -55°C
Max TJ = 125°C
200
10 Years
R e visi on 2
1-3
RTG4 FPGA AC/DC Electrical Characteristics
Table 5 •
Device Storage Temperature and Retention
Storage Temperature (Tstg)
Retention
Min TJ = -55°C
10 Years
Max TJ = 125°C
4.2 Overshoot/Undershoot Limits
For AC signals, the input signal may undershoot during transitions to -0.8 V for no longer than 10% of the period. The
current during the transition must not exceed 100 mA.
For AC signals, the input signal may overshoot during transitions to VDDIx + 0.8 V for no longer than 10% of the
period. The current during the transition must not exceed 100 mA.
Note: The above specification does not apply to the PCI standard. The RTG4 PCI I/Os are compliant to the PCI
standard including the PCI overshoot/undershoot specifications.
4.3 Power-Up and Power-Down Sequence
There is no power-up and power-down sequence required if the device is held in reset by asserting DEVRST_N until
VPP and VDDPLL supplies reach their minimum recommended level as shown in Table 3 on page 3.
If the device cannot be held in reset, the following power-up and power-down requirements apply:
1. VPP requirements:
–
VPP must NOT be the last supply to ramp up and must reach its minimum recommended level before the
last supply (VDD or VDDIx) starts ramping up AND.
–
VPP must have a minimum ramp time of 5 ms from 10% of VPP to the minimum recommended level of
VPP.
2. VDDPLL requirements:
–
All PLLs are held in reset until VDDPLL supply reaches its minimum recommended level OR.
–
VDDPLL must NOT be the last supply to ramp up and must reach its minimum recommended level before
the last supply (VDD or VDDIx) starts ramping up.
For more information, refer to the AC439: Board Design Guidelines for RTG4 FPGA Application Note.
4.4 Thermal Characteristics
4.4.1 Introduction
The temperature variable in the Microsemi SoC Products Group Libero SoC software refers to the junction
temperature, not the ambient, case, or board temperatures. This is an important distinction because dynamic and
static power consumption will cause the chip's junction temperature to be higher than the ambient, case, or board
temperatures.
EQ 1 through EQ 3 give the relationship between thermal resistance, temperature gradient, and power.
TJ – TA
 JA = ------------------P
EQ 1
TJ – TB
 JB = ------------------P
EQ 2
 JC
TJ – TC
= ------------------P
EQ 3
1 -4
Revision 2
DS0131: RTG4 FPGA Datasheet
where
JA = Junction-to-air thermal resistance
JB = Junction-to-board thermal resistance
JC = Junction-to-case thermal resistance
Table 6 •
TJ
= Junction temperature
TA
= Ambient temperature
TB
= Board temperature (measured 1.0 mm away from the package edge)
TC
= Case temperature
P
= Total power dissipated by the device
Package Thermal Resistance
Product
JA
JB
JC
Units
RT4G150 in CG1657
8.21
2.49
0.21
°C/W
Note: JA are estimated at still air.
4.4.2 Theta-JA
Junction-to-ambient thermal resistance (JA) is determined under standard conditions specified by JEDEC (JESD-51),
but it has little relevance in actual performance of the product. It must be used with caution, but it is useful for
comparing the thermal performance of one package to another.
The maximum power dissipation allowed is calculated using EQ 4.
T J(MAX) – T A(MAX)
Maximum Power Allowed = -------------------------------------------- JA
EQ 4
The power consumption of a device can be calculated using the Microsemi SoC Products Group power calculator. The
device's power consumption must be lower than the calculated maximum power dissipation by the package.
If the power consumption is higher than the device's maximum allowable power dissipation, a heat sink can be
attached on top of the case.
4.4.3 Theta-JB
Junction-to-board thermal resistance (JB) measures the ability of the package to dissipate heat from the surface of the
chip to the PCB. As defined by the JEDEC (JESD-51) standard, the thermal resistance from junction to board uses an
isothermal ring cold plate zone concept. The ring cold plate is simply a means to generate an isothermal boundary
condition at the perimeter. The cold plate is mounted on a JEDEC standard board with a minimum distance of 5.0 mm
away from the package edge.
4.4.4 Theta-JC
Junction-to-case thermal resistance (JC) measures the ability of a device to dissipate heat from the surface of the chip
to the top or bottom surface of the package. It is applicable for packages used with external heat sinks. Constant
temperature is applied to the surface under consideration and acts as a boundary condition.
This only applies to situations where all or nearly all of the heat is dissipated through the surface under consideration.
R e visi on 2
1-5
RTG4 FPGA AC/DC Electrical Characteristics
5. Power Consumption
5.1 Quiescent Supply Current
Table 7 •
Quiescent Supply Current Characteristics
Power Supplies/Blocks
Standby Mode
Notes
FPGA Core
On
VPP
On
VDDPLL
0V
SERDES_x_Lyz_VDDAPLL
0V
1
SERDES_x_Lyz_VDDAIO
On
1
VDDIx
On
2, 3
VREF0 - VREF9
On
50 MHz Oscillator
Enabled
Notes:
3. SERDES and DDR blocks are in RESET states.
4. VDDIx supplies to all I/O Banks are set to On in Standby Mode.
5. No Differential I/O or On-Die Termination (ODT) resistor is used.
Table 8 •
RTG4 Quiescent Supply Current – Typical Process
Parameter
IDC
Modes
Conditions
RT4G150
Units
Standby Mode
Typical
(TJ = 25°C)
400
mA
6. Average Fabric Temperature and Voltage Derating Factors
Table 9 •
Average Temperature and Voltage Derating Factors for Fabric Timing Delays
(Normalized to TJ = 125°C, Worst-Case VDD = 1.14 V)
Junction Temperature (°C)
Core Voltage VDD (V)
-55°C
-40°C
0°C
25°C
70°C
85°C
100°C
125°C
1.14
0.92
0.92
0.94
0.94
0.96
0.97
0.98
1.00
1.2
0.83
0.83
0.84
0.85
0.87
0.87
0.88
0.90
1.26
0.75
0.76
0.77
0.77
0.79
0.80
0.80
0.82
1 -6
Revision 2
DS0131: RTG4 FPGA Datasheet
7. User I/O Characteristics
There are three types of I/Os supported in the RTG4 FPGA families: MSIO, MSIOD, and DDRIO I/O. The I/O
standards supported by the different I/O banks is described in the "I/Os" section of the UG0574: RTG4 FPGA Fabric
User Guide.
7.1 Input Buffer
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R e visi on 2
1-7
RTG4 FPGA AC/DC Electrical Characteristics
7.2. Output Buffer and AC Loading
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3&,7HVW6HWXS
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Figure 2 • Output Buffer and AC Loading
1 -8
Revision 2
&ORDG
DS0131: RTG4 FPGA Datasheet
7.3. Tristate Buffer and AC Loading
The tristate path for enable path loadings is described in the respective specifications. The methodology of
characterization is illustrated by the enable path test point shown in Figure 3.
tZL, tZH, tHZ, tLZ
E
OUT
D
Rent to VDDI for tZL, tLZ
PAD
Cent tZL, tLZ, tZH, tHZ
Rent to GND for tZH, tHZ
Data
(D)
Enable
(E)
50%
tZL
50%
50%
tHZ
PAD
50%
tLZ
tZH
90% VDDI
90% VDDI
10% VDDI
10% VDDI
Figure 3 • Tristate Buffer for Enable Path Test Point
7.4 I/O Speeds
Table 10 • Maximum I/O Data Rate Summary for Worst-Case Military Conditions
Single-Ended I/O
MSIO
MSIOD
DDRIO
Units
PCI 3.3 V
630
–
–
Mbps
LVTTL 3.3 V
600
–
–
Mbps
LVCMOS 3.3 V
600
–
–
Mbps
LVCMOS 2.5 V
410
420
700
Mbps
LVCMOS 1.8 V
295
320
700
Mbps
LVCMOS 1.5 V
200
200
400
Mbps
LVCMOS 1.2 V
140
140
550
Mbps
–
–
700
Mbps
MSIO
MSIOD
DDRIO
Units
–
–
700
Mbps
HSTL1.5 V Class I
140
180
400
Mbps
HSTL1.5 V Class II
–
–
400
Mbps
500
500
500
Mbps
LPDDR – LVCMOS 1.8 V Mode
Voltage-Referenced I/O
LPDDR
HSTL 1.8 V
R e visi on 2
1-9
RTG4 FPGA AC/DC Electrical Characteristics
Table 10 • Maximum I/O Data Rate Summary for Worst-Case Military Conditions (continued)
Voltage-Referenced I/O
MSIO
MSIOD
DDRIO
Units
SSTL 2.5 V
575
700
800
Mbps
SSTL 1.8 V
432
430
800
Mbps
SSTL 1.5 V
–
–
800
Mbps
MSIO
MSIOD
DDRIO
Units
LVPECL (input only)
750
–
–
Mbps
LVDS 3.3 V
750
–
–
Mbps
LVDS 2.5 V
750
750
–
Mbps
RSDS
520
700
–
Mbps
BLVDS
500
500
–
Mbps
MLVDS
500
500
–
Mbps
Mini-LVDS
520
700
–
Mbps
–
350
–
Mbps
MSIO
MSIOD
DDRIO
Units
PCI 3.3 V
315
–
–
MHz
LVTTL 3.3 V
300
–
–
MHz
LVCMOS 3.3 V
300
–
–
MHz
LVCMOS 2.5 V
205
210
350
MHz
LVCMOS 1.8 V
147.5
160
350
MHz
LVCMOS 1.5 V
100
100
200
MHz
LVCMOS 1.2 V
70
70
275
MHz
LPDDR - LVCMOS 1.8 V mode
–
–
350
MHz
MSIO
MSIOD
DDRIO
Units
LPDDR
–
–
350
MHz
HSTL1.5 V Class I
70
90
200
MHz
HSTL1.5 V Class II
Differential I/O
HCSL (Input only)
Table 11 • Maximum I/O Frequency Summary for Worst-Case Military Conditions
Single-Ended I/O
Voltage-Referenced I/O
–
–
200
MHz
HSTL 1.8 V
250
250
250
MHz
SSTL 2.5 V
287.5
350
400
MHz
SSTL 1.8 V
216
215
400
MHz
SSTL 1.5 V
–
–
400
MHz
MSIO
MSIOD
DDRIO
Units
LVPECL (input only)
375
–
–
MHz
LVDS 3.3 V
375
–
MHz
LVDS 2.5 V
375
375
–
MHz
RSDS
260
350
–
MHz
BLVDS
250
250
–
MHz
Differential I/O
1 -1 0
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 11 • Maximum I/O Frequency Summary for Worst-Case Military Conditions (continued)
Differential I/O
MSIO
MSIOD
DDRIO
Units
MLVDS
250
250
–
MHz
Mini-LVDS
260
350
–
MHz
–
175
–
MHz
HCSL (Input only)
7.5 Detailed I/O Characteristics
Table 12 • Input Capacitance
Symbol
CIN
Definition
Min
Max
Units
Input Capacitance
–
10
pF
Table 13 • I/O Weak Pull-Up/Pull-Down Resistance Values for DDRIO, MSIO, and MSIOD Banks
VDDI
DDRIO I/O Bank
MSIO I/O Bank
R(WEAK
R(WEAK
PULL-UP)
at VOH K
MSIOD I/O Bank
R(WEAK
R(WEAK
R(WEAK
R(WEAK
PULL-DOWN)
PULL-UP)
at VOL K
at VOH K
PULL-DOWN)
PULL-UP)
PULL-DOWN)
at VOL K
at VOH K
at VOL K
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Notes
3.3 V
–
–
–
–
9.9
14.5
9.98
14.9
–
–
–
–
1, 2
2.5 V
9.98
15.3
10
15.1
10
15
10.1
15.6
9.6
14.1
9.5
13.9
1, 2
1.8 V
11.1
19.3
11.2
20.9
10.4
16.2
10.4
17.3
9.7
14.7
9.7
14.5
1, 2
1.5 V
10
13.4
9.99
13.4
10.7
17.3
10.8
18.9
9.9
15.3
9.8
15
1, 2
1.2 V
10.3
14.5
10.3
14.7
11.3
19.7
11.5
22.7
10.3
16.7
10
16.2
1, 2
Notes:
1. R(WEAK PULL-DOWN) = (VOLspec)/I(WEAK PULL-DOWN MAX)
2. R(WEAK PULL-UP) = (VDDImax - VOHspec)/I(WEAK PULL-UP MIN)
Table 14 • Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value for Schmitt Trigger Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (Typical, unless otherwise noted)
3.3 V LVTTL / LVCMOS / PCI / PCI-X
0.05 × VDDI (Worst-case)
2.5 V LVCMOS
0.05 × VDDI (Worst-case)
1.8 V LVCMOS
0.05 × VDDI (Worst-case)
1.5 V LVCMOS
60 mV
1.2 V LVCMOS
20 mV
R e visi on 2
1-11
RTG4 FPGA AC/DC Electrical Characteristics
7.6. Single-Ended I/O Standards
7.6.1 Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
LVCMOS is a widely used switching standard implemented in CMOS transistors. This standard is defined by JEDEC
(JESD 8-5). The LVCMOS standards supported in RTG4 FPGAs are: LVCMOS12, LVCMOS15, LVCMOS18,
LVCMOS25, and LVCMOS33.
7.6.2 3.3 V LVCMOS/LVTTL
LVCMOS 3.3 V or Low-Voltage Transistor-Transistor Logic (LVTTL) is a general standard for 3.3 V applications.
7.6.2.1 Minimum and Maximum AC/DC Input and Output Levels Specification
Table 15 • LVTTL/LVCMOS 3.3 V DC Voltage Specification (Applicable to MSIO I/O Bank Only)
Symbol
Parameters
Min
Typ
Max
Units
3.15
3.3
3.45
V
Notes
LVTTL/LVCMOS 3.3 V Recommended DC Operating Conditions
VDDI
Supply voltage
LVTTL/LVCMOS 3.3 V DC Input Voltage Specification
VIH (DC)
DC input logic High
2.0
–
3.45
V
VIL (DC)
DC input logic Low
-0.3
–
0.8
V
IIH (DC)
Input current High
–
–
10
µA
IIL (DC)
Input current Low
–
–
10
µA
LVCMOS 3.3 V DC Output Voltage Specification
VOH
DC output logic High
2.4
–
–
V
*
VOL
DC output logic Low
–
–
0.4
V
*
LVTTL 3.3 V DC Output Voltage Specification
VOH
DC output logic High
2.4
–
–
V
VOL
DC output logic Low
–
–
0.4
V
Note: * The VOH/VOL test points selected ensure compliance with LVCMOS 3.3 V JESD8-B requirements.
Table 16 • LVTTL/LVCMOS 3.3 V Maximum Switching Speeds (Applicable to MSIO I/O Bank Only)
Symbol
Parameters
Conditions
Min
Typ
Max
Units
AC Loading: 10 pF / 500  load, maximum
drive
–
–
600
Mbps
LVTTL/LVCMOS 3.3 V Maximum Switching Speed
Dmax
Maximum data rate
(for MSIO I/O Bank)
Table 17 • LVTTL/LVCMOS 3.3 V AC Test Parameter Specifications (Applicable to MSIO Bank Only)
LVTTL/LVCMOS 3.3 V AC Test Parameter Specifications
Symbol
Parameters
Min
Typ
Max
Units
Vtrip
Measuring/trip point for data path
–
1.4
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2K
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ,
tLZ)
–
5
–
pF
Cload
Capacitive loading for data path (tDP)
–
5
–
pF
1 -1 2
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 18 • LVTTL/LVCMOS 3.3 V Transmitter Drive Strength Specifications
(Applicable to MSIO Bank Only)
Output Drive Selection
VOH
Min (V)
VOL
Max (V)
IOH (mA)
IOL (mA)
2 mA
2.4
0.4
2
2
4 mA
2.4
0.4
4
4
8 mA
2.4
0.4
8
8
12 mA
2.4
0.4
12
12
16 mA
2.4
0.4
16
16
7.6.2.2 AC Switching Characteristics
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 3.15 V
AC Switching Characteristics for Receiver (Input Buffers)
Table 19 • LVTTL/LVCMOS 3.3 V Receiver Characteristics for MSIO I/O Banks (Input Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 3.15 V
tPY
tPYS
On-Die Termination
(ODT) in 
Speed Grade
–1
Speed Grade
STD
Speed Grade
–1
Speed Grade
STD
Units
None
2.971
3.495
3.107
3.655
ns
LVTTL/LVCMOS 3.3 V
(for MSIO I/O Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 20 • LVTTL/LVCMOS 3.3 V Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 3.15 V
tZL
tDP
tZH
tHZ
Units
tLZ
Output
Drive
Selection
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
2 mA
4.583
5.392
4.700
5.529
3.817
4.490
3.356
3.948
3.026
3.560
ns
4 mA
3.391
3.989
3.442
4.049
3.051
3.589
3.539
4.164
3.063
3.603
ns
8 mA
3.006
3.536
3.033
3.568
2.799
3.293
3.575
4.206
3.069
3.611
ns
12 mA
2.697
3.173
2.706
3.184
2.609
3.069
3.596
4.231
3.134
3.687
ns
16 mA
2.655
3.124
2.626
3.089
2.560
3.012
3.697
4.349
3.182
3.744
ns
R e visi on 2
1-13
RTG4 FPGA AC/DC Electrical Characteristics
7.6.3 2.5 V LVCMOS
LVCMOS 2.5 V is a general standard for 2.5 V applications and is supported in RTG4 FPGAs in compliance to the
JEDEC specification JESD8-5A.
7.6.3.1 Minimum and Maximum AC/DC Input and Output Levels Specification
Table 21 • LVCMOS 2.5 V DC Voltage Specification
Symbol
Min
Typ
Max
Units
2.5
2.625
V
Notes
LVCMOS 2.5 V Recommended DC Operating Conditions
VDDI
2.375
LVCMOS 2.5 V DC Input Voltage Specification
VIH (DC)
1.7
–
2.75
V
VIL (DC)
-0.3
–
0.7
V
IIH (DC)
–
–
10
µA
IIL (DC)
–
–
10
µA
LVCMOS 2.5 V DC Output Voltage Specification
VOH
1.7
–
–
V
*
VOL
–
–
0.7
V
*
Note: * The VOH/VOL test points selected ensure compliance with LVCMOS 2.5 V JEDEC8-5A requirements.
Table 22 • LVCMOS 2.5 V Maximum AC Switching Speeds
Symbol
Parameters
Conditions
Min
Typ
Max
Units
Dmax
Maximum data rate
(for DDRIO I/O Bank)
AC Loading: 10 pF / 500 load,
maximum drive
–
–
700
Mbps
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC Loading: 10 pF / 500 load,
maximum drive
–
–
410
Mbps
Dmax
Maximum data rate
(for MSIOD I/O Bank)
AC Loading: 10 pF / 500 load,
maximum drive
–
–
420
Mbps
Table 23 • LVCMOS 2.5 V AC Test Parameters and Driver Impedance Specifications
Symbols
Parameters
Min
Typ
Max
Units
LVCMOS 2.5 V AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
1.2
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2K
–

Cent
Capacitive loading for enable path (tZH, tZL,
tHZ, tLZ)
–
5
–
pF
Cload
Capacitive loading for data path (tDP)
–
5
–
pF
1 -1 4
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 24 • LVCMOS 2.5 V Transmitter Drive Strength Specifications
Output Drive Selection
MSIOD I/O
Bank
DDRIO I/O Bank
(with Software Default Fixed
Calibration Codes)
VOH
Min (V)
VOL
Max (V)
IOH (mA)
IOL (mA)
2 mA
2 mA
2 mA
1.7
0.7
2
2
4 mA
4 mA
4 mA
1.7
0.7
4
4
6 mA
6 mA
6 mA
1.7
0.7
6
6
8 mA
8 mA
8 mA
1.7
0.7
8
8
–
10 mA
–
1.7
0.7
10
10
–
12 mA
1.7
0.7
12
12
MSIO
I/O Bank
12 mA
14 mA
–
–
1.7
0.7
14
14
–
–
16 mA
1.7
0.7
16
16
Note: For board design considerations, output slew rates extraction, detailed output buffer resistances and I/V Curve use the
corresponding IBIS models located at:
http://www.microsemi.com/products/fpga-soc/design-resources/ibis-models.
7.6.3.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 25 • LVCMOS 2.5 V AC Switching Characteristics for Receiver (Input Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 2.375 V
tPYS
tPY
On-Die Termination
(ODT) in 
Speed Grade Speed Grade
–1
STD
Speed
Grade
–1
Speed
Grade
STD
Units
LVCMOS 2.5 V (for DDRIO I/O
Bank)
None
2.052
2.414
2.052
2.414
ns
LVCMOS 2.5 V (for MSIO I/O
Bank)
None
3.012
3.544
3.063
3.604
ns
LVCMOS 2.5 V (for MSIOD I/O
Bank)
None
2.763
3.251
2.831
3.331
ns
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 26 • LVCMOS 2.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 2.375 V
tZL
tDP
Output Drive
Selection
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
tZH
Speed
Grade
STD
tHZ
tLZ
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
LVCMOS 2.5 V (for DDRIO I/O Bank with Fixed Code)
2 mA
3.805
4.476
3.826
4.501
3.681
4.331
3.056
3.595
2.929
3.446
ns
4 mA
3.060
3.600
3.028
3.562
2.991
3.519
3.158
3.715
2.945
3.465
ns
6 mA
2.832
3.332
2.780
3.271
2.776
3.266
3.273
3.851
3.072
3.614
ns
8 mA
2.764
3.252
2.706
3.183
2.709
3.187
3.285
3.865
3.099
3.646
ns
12 mA
2.627
3.090
2.558
3.009
2.565
3.018
3.318
3.904
3.120
3.670
ns
R e visi on 2
1-15
RTG4 FPGA AC/DC Electrical Characteristics
Table 26 • LVCMOS 2.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 2.375 V (continued)
tZL
tDP
Output Drive
Selection
16 mA
tZH
tHZ
tLZ
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
2.547
2.997
2.462
2.897
2.480
2.918
3.402
4.002
3.174
3.734
ns
LVCMOS 2.5 V (for MSIO I/O Bank)
2 mA
5.041
5.930
5.135
6.041
4.812
5.661
3.817
4.490
3.425
4.029
ns
4 mA
3.811
4.484
3.851
4.530
3.733
4.392
3.890
4.576
3.466
4.078
ns
6 mA
3.428
4.033
3.434
4.040
3.380
3.976
3.965
4.665
3.502
4.120
ns
8 mA
3.234
3.805
3.226
3.795
3.208
3.774
4.035
4.747
3.546
4.172
ns
12 mA
3.122
3.673
3.106
3.654
3.111
3.660
4.113
4.839
3.551
4.178
ns
14 mA
3.091
3.637
3.024
3.558
3.042
3.579
3.987
4.691
3.579
4.211
ns
LVCMOS 2.5 V (for MSIOD I/O Bank)
2 mA
2.772
3.261
3.538
4.162
3.459
4.069
2.910
3.424
2.653
3.121
ns
4 mA
2.258
2.656
2.921
3.436
2.914
3.428
2.918
3.433
2.651
3.119
ns
6 mA
2.054
2.416
2.739
3.222
2.761
3.248
2.946
3.466
2.678
3.151
ns
8 mA
1.942
2.285
2.538
2.986
2.583
3.039
2.952
3.473
2.675
3.147
ns
10 mA
1.917
2.255
2.366
2.783
2.433
2.862
2.989
3.516
2.709
3.187
ns
7.6.4 1.8 V LVCMOS
LVCMOS 1.8 is a general standard for 1.8 V applications and is supported in RTG4 FPGAs in compliance to the
JEDEC specification JESD8-7A.
7.6.4.1 Minimum and Maximum AC/DC Input and Output Levels
Table 27 • LVCMOS 1.8 V DC Voltage Specification
Symbols
Parameters
Min
Typ
Max
Units
1.710
1.8
1.89
V
LVCMOS 1.8 V Recommended DC Operating Conditions
VDDI
Supply Voltage
LVCMOS 1.8 V DC Input Voltage Specification
VIH(DC)
DC input Logic HIGH
0.65 x VDDI
–
2.75
V
VIL(DC)
DC input Logic LOW
-0.3
–
0.35 × VDDI
V
IIH(DC)
Input Current HIGH
–
–
10
uA
IIL(DC)
Input Current LOW
–
–
10
uA
LVCMOS 1.8 V DC Output Voltage Specification
VOH
DC output Logic HIGH
VDDI - 0.45
–
–
V
VOL
DC output Logic LOW
–
–
0.45
V
1 -1 6
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 28 • LVCMOS 1.8 V Maximum AC Switching Speeds
Symbols
Parameters
Conditions
Min
Typ
Max
Units
LVCMOS 1.8 V Maximum AC Switching Speed
Dmax
Maximum data rate
(for DDRIO I/O Bank)
AC Loading: 10 pF / 500 load,
maximum drive and slew
–
–
700
Mbps
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC Loading: 10 pF / 500 load,
maximum drive
–
–
295
Mbps
Dmax
Maximum data rate
(for MSIOD I/O Bank)
AC Loading: 10 pF/500 load,
maximum drive
–
–
320
Mbps
Table 29 • LVCMOS 1.8 V Transmitter Drive Strength Specifications
Output Drive Selection
MSIOD I/O Bank
DDRIO Bank
VOH
Min (V)
VOL
Max (V)
IOH (mA)
IOL (mA)
2 mA
2 mA
2 mA
VDDI – 0.45
0.45
2
2
4 mA
4 mA
4 mA
VDDI – 0.45
0.45
4
4
6 mA
6 mA
6 mA
VDDI – 0.45
0.45
6
6
8 mA
8 mA
8 mA
VDDI – 0.45
0.45
8
8
10 mA
–
10 mA
VDDI – 0.45
0.45
10
10
12 mA
–
12 mA
VDDI – 0.45
0.45
12
12
–
–
16 mA
VDDI – 0.45
0.45
16
16
MSIO I/O Bank
Table 30 • LVCMOS 1.8 V AC Test Parameters and Driver Impedance Specifications
Symbols
Parameters
Min
Typ
Max
Units
LVCMOS 1.8 V AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
0.9
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Cload
Capacitive loading for data path (tDP)
–
5
–
pF
7.6.4.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 31 • LVCMOS 1.8 V AC Switching Characteristics for Receiver (Input Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.71 V
LVCMOS 1.8 V
(for DDRIO I/O Bank with Fixed
Codes)
LVCMOS 1.8 V (for MSIO I/O Bank)
LVCMOS 1.8 V (for MSIOD I/O
Bank)
tPY
tPYS
Speed Grade Speed Grade
–1
STD
ODT (On Die
Termination) in

Speed Grade
–1
Speed Grade
STD
None
2.209
2.599
2.209
2.599
ns
None
3.340
3.929
3.332
3.920
ns
None
3.023
3.556
3.018
3.550
ns
R e visi on 2
Units
1-17
RTG4 FPGA AC/DC Electrical Characteristics
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 32 • LVCMOS 1.8 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.71 V
Output
Drive
Selection
Slew
Control
tDP
Speed Speed
Grade Grade
–1
STD
tZL
Speed Speed
Grade Grade
–1
STD
LVCMOS 1.8 V (for DDRIO I/O Bank with Fixed Codes)
slow
4.032
4.744
3.988
4.692
2 mA
medium
3.578
4.209
3.599
4.234
4 mA
6 mA
8 mA
10 mA
12 mA
16 mA
tZH
Speed Speed
Grade Grade
–1
STD
tHZ
Speed Speed
Grade Grade
–1
STD
Speed
Grade
–1
tLZ
Speed
Grade
STD
Units
4.052
4.767
3.683
4.333
3.451
4.060
ns
3.601
4.236
3.039
3.575
2.824
3.322
ns
slow
3.673
4.321
3.607
4.243
3.674
4.322
3.823
4.498
3.595
4.229
ns
medium
3.222
3.790
3.223
3.792
3.229
3.799
3.125
3.677
2.885
3.394
ns
slow
3.432
4.038
3.361
3.954
3.430
4.035
3.815
4.488
3.528
4.151
ns
medium
3.016
3.548
3.013
3.545
3.018
3.550
3.108
3.657
2.845
3.347
ns
slow
3.329
3.917
3.251
3.825
3.318
3.904
3.917
4.608
3.628
4.268
ns
medium
2.913
3.427
2.905
3.418
2.911
3.425
3.158
3.715
2.898
3.409
ns
slow
3.197
3.761
3.108
3.656
3.179
3.740
4.028
4.739
3.725
4.382
ns
medium
2.791
3.284
2.775
3.265
2.786
3.278
3.228
3.798
2.945
3.465
ns
slow
3.103
3.651
3.028
3.562
3.084
3.628
3.941
4.637
3.630
4.271
ns
medium
2.733
3.215
2.721
3.201
2.709
3.187
3.177
3.738
2.893
3.403
ns
slow
3.051
3.589
2.966
3.489
3.025
3.559
4.017
4.726
3.737
4.396
ns
medium
2.683
3.157
2.665
3.135
2.659
3.128
3.214
3.781
2.946
3.466
ns
LVCMOS 1.8 V (for MSIO I/O Bank)
2 mA
Default
5.233
6.157
5.274
6.205
5.224
6.146
5.062
5.955
4.552
5.355
ns
4 mA
Default
4.728
5.562
4.709
5.540
4.696
5.525
5.101
6.001
4.593
5.403
ns
6 mA
Default
4.474
5.263
4.427
5.208
4.440
5.224
5.160
6.070
4.612
5.426
ns
8 mA
Default
4.326
5.089
4.264
5.017
4.296
5.054
5.167
6.079
4.629
5.446
ns
10 mA
Default
4.293
5.051
4.156
4.889
4.194
4.934
5.188
6.104
4.627
5.444
ns
12 mA
Default
4.274
5.028
4.078
4.798
4.128
4.857
5.235
6.159
4.627
5.443
ns
LVCMOS 1.8 V (for MSIOD I/O Bank)
2 mA
Default
3.450
4.059
4.336
5.101
4.574
5.381
3.499
4.116
3.169
3.728
ns
4 mA
Default
2.768
3.257
3.588
4.221
3.807
4.479
3.499
4.117
3.165
3.723
ns
6 mA
Default
2.377
2.797
3.143
3.698
3.341
3.931
3.551
4.178
3.193
3.756
ns
8 mA
Default
2.358
2.774
3.093
3.639
3.282
3.861
3.586
4.219
3.211
3.778
ns
1 -1 8
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
7.6.5 1.5 V LVCMOS
LVCMOS 1.5 is a general standard for 1.5 V applications and is supported in RTG4 FPGAs in compliance to the
JEDEC specification JESD8-11A.
7.6.5.1 Minimum and Maximum AC/DC Input and Output Levels Specification
Table 33 • LVCMOS 1.5 V Minimum and Maximum DC Input and Output Levels
Symbols
Parameters
Min
Typ
Max
Units
1.425
1.5
1.575
V
LVCMOS 1.5 V Recommended DC Operating Conditions
VDDI
Supply voltage
LVCMOS 1.5 V DC Input Voltage Specification
VIH (DC)
DC input logic High
0.65 × VDDI
–
2.75
V
VIL (DC)
DC input logic Low
–0.3
–
0.35 × VDDI
V
IIH (DC)
Input current High
–
–
10
µA
IIL (DC
Input current Low
–
–
10
µA
LVCMOS 1.5 V DC Output Voltage Specification
VOH
DC output logic High
VDDI × 0.75
–
–
V
VOL
DC output logic Low
–
–
VDDI × 0.25
V
Min
Typ
Max
Units
Table 34 • LVCMOS 1.5 V Maximum AC Switching Speeds
Symbols
Parameters
Conditions
LVCMOS 1.5 V Maximum AC Switching Speed
Dmax
Maximum data rate
(for DDRIO I/O Bank)
AC loading: 5 pF load / maximum
drive/fast slew
–
–
400
Mbps
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC loading: 5 pF load / maximum
drive
–
–
200
Mbps
Dmax
Maximum data rate
(for MSIOD I/O Bank)
AC loading: 5 pF load / maximum
drive
–
–
200
Mbps
Min
Typ
Max
Units
Table 35 • LVCMOS 1.5 V AC Test Parameters and Driver Impedance Specifications
Symbols
Parameters
Conditions
LVCMOS 1.5 V AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
0.75
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2K
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Cload
Capacitive loading for data path (tDP)
–
5
–
pF
Table 36 • LVCMOS 1.5 V Transmitter Drive Strength Specifications
Output Drive Selection
VOH
Min (V)
VOL
Max (V)
IOH (mA)
IOL (mA)
2 mA
VDDI × 0.75
VDDI × 0.25
2
2
4 mA
4 mA
VDDI × 0.75
VDDI × 0.25
4
4
6 mA
6 mA
6 mA
VDDI × 0.75
VDDI × 0.25
6
6
8 mA
–
8 mA
VDDI × 0.75
VDDI × 0.25
8
8
–
–
10 mA
VDDI × 0.75
VDDI × 0.25
10
10
–
–
12 mA
VDDI × 0.75
VDDI × 0.25
12
12
MSIOD I/O Bank
DDRIO I/O Bank
(with Fixed Code)
2 mA
2 mA
4 mA
MSIO I/O Bank
R e visi on 2
1-19
RTG4 FPGA AC/DC Electrical Characteristics
7.6.5.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 37 • LVCMOS 1.5 V AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ=125°C, VDD=1.14 V, VDDI= 1.425 V
tPYS
tPY
ODT (On Die
Termination)
in 
Speed Grade Speed Grade
–1
STD
Speed
Grade
–1
Speed
Grade
STD
Units
LVCMOS 1.5 V (for DDRIO I/O Bank
with Fixed Codes)
None
2.345
2.759
2.345
2.759
ns
LVCMOS 1.5 V (for MSIO I/O Bank)
None
3.571
4.201
3.558
4.186
ns
LVCMOS 1.5 V (for MSIOD I/O Bank)
None
3.197
3.761
3.183
3.745
ns
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 38 • LVCMOS 1.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ=125°C, VDD=1.14 V, VDDI=1.425 V
tZL
tDP
Output Drive
Selection
Slew
Control
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
tZH
Speed
Grade
STD
tHZ
tLZ
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
LVCMOS 1.5 V (for DDRIO I/O Bank with Fixed Codes)
2 mA
4 mA
6 mA
8 mA
10 mA
12 mA
slow
4.918
5.786
4.828
5.680
4.964
5.840
4.210
4.953
3.879
4.564
ns
medium
4.325
5.088
4.321
5.084
4.367
5.138
3.515
4.135
3.234
3.805
ns
fast
4.019
4.728
4.061
4.778
4.048
4.762
3.029
3.564
2.869
3.375
ns
slow
4.151
4.883
4.123
4.850
4.162
4.896
4.372
5.143
4.100
4.824
ns
medium
3.624
4.264
3.635
4.276
3.630
4.271
3.575
4.206
3.325
3.912
ns
fast
3.363
3.956
3.375
3.971
3.342
3.932
3.071
3.613
2.909
3.422
ns
slow
3.926
4.619
3.857
4.538
3.930
4.623
4.519
5.317
4.216
4.960
ns
medium
3.407
4.008
3.397
3.997
3.413
4.015
3.679
4.328
3.377
3.973
ns
fast
3.142
3.697
3.148
3.703
3.125
3.677
3.113
3.662
2.941
3.460
ns
slow
3.751
4.413
3.681
4.331
3.752
4.414
4.609
5.422
4.181
4.919
ns
medium
3.264
3.840
3.262
3.838
3.255
3.829
3.684
4.334
3.358
3.951
ns
fast
3.029
3.564
3.032
3.567
2.978
3.503
3.119
3.669
2.950
3.470
ns
slow
3.681
4.331
3.601
4.236
3.679
4.328
4.652
5.473
4.256
5.007
ns
medium
3.199
3.763
3.192
3.755
3.194
3.758
3.747
4.408
3.392
3.991
ns
fast
2.967
3.490
2.966
3.489
2.921
3.436
3.149
3.705
2.965
3.488
ns
slow
3.615
4.253
3.550
4.176
3.608
4.245
4.728
5.562
4.334
5.099
ns
medium
3.157
3.714
3.148
3.703
3.141
3.695
3.720
4.376
3.425
4.029
ns
fast
2.927
3.443
2.922
3.438
2.876
3.384
3.146
3.701
2.986
3.513
ns
7.320
6.157
7.243
6.089
7.163
6.423
7.557
5.782
6.802
ns
LVCMOS 1.5 V (for MSIO I/O Bank)
2 mA
1 -2 0
Default
6.222
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 38 • LVCMOS 1.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ=125°C, VDD=1.14 V, VDDI=1.425 V (continued)
tZL
tDP
tZH
tHZ
tLZ
Output Drive
Selection
Slew
Control
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
4 mA
Default
5.679
6.681
5.556
6.536
5.556
6.537
6.474
7.617
5.806
6.831
ns
6 mA
Default
5.633
6.627
5.409
6.364
5.423
6.380
6.490
7.635
5.830
6.859
ns
8 mA
Default
5.588
6.574
5.229
6.152
5.273
6.203
6.568
7.727
5.858
6.892
ns
LVCMOS 1.5 V (for MSIOD I/O Bank)
2 mA
Default
3.424
4.028
4.359
5.128
4.719
5.552
4.153
4.886
3.753
4.415
ns
4 mA
Default
2.930
3.447
3.825
4.500
4.125
4.853
4.224
4.969
3.789
4.458
ns
6 mA
Default
2.910
3.423
3.771
4.436
4.052
4.767
4.253
5.003
3.813
4.486
ns
7.6.6 1.2 V LVCMOS
LVCMOS 1.2 is a general standard for 1.2 V applications and is supported in RTG4 FPGAs in compliance to the
JEDEC specification JESD8-12A.
7.6.6.1 Minimum and Maximum Input and Output Levels Specification
Table 39 • LVCMOS 1.2 V Minimum and Maximum DC Input and Output Levels
Symbols
Parameters
Conditions
Min
Typ
Max
Units
1.140
1.2
1.26
V
LVCMOS 1.2 V Recommended DC Operating Conditions
VDDI
Supply voltage
LVCMOS 1.2 V DC Input Voltage Specification
VIH (DC)
DC input logic High
0.65 × VDDI
–
2.75
V
VIL (DC)
DC input logic Low
- 0.3
–
0.35 × VDDI
V
IIH (DC)
Input current High
–
–
10
µA
IIL (DC)
Input current Low
–
–
10
µA
LVCMOS 1.2 V DC Output Voltage Specification
VOH
DC output logic High
VDDI × 0.75
–
–
V
VOL
DC output logic Low
–
–
VDDI × 0.25
V
Min
Typ
Max
Units
Table 40 • LVCMOS 1.2 V Maximum AC Switching Speeds
Symbols
Parameters
Conditions
LVCMOS 1.2 V Maximum AC Switching Speed
Dmax
Maximum data rate
(for DDRIO I/O Bank)
AC loading: 2.5 pF load /
maximum drive/fast slew
–
–
550
Mbps
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC loading: 2.5 pF load /
maximum drive
–
–
140
Mbps
Dmax
Maximum data rate
(for MSIOD I/O Bank)
AC loading: 2.5 pF load /
maximum drive
–
–
140
Mbps
R e visi on 2
1-21
RTG4 FPGA AC/DC Electrical Characteristics
Table 41 • LVCMOS 1.2 V AC Test Parameters and Driver Impedance Specifications
Symbols
Parameters
Conditions
Min
Typ
Max
Units
LVCMOS 1.2 V AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
0.6
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2K
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Cload
Capacitive loading for data path (tDP)
–
5
–
pF
Table 42 • LVCMOS 1.2 V Transmitter Drive Strength Specifications
Output Drive Selection
MSIO I/O Bank
MSIOD I/O Bank
VOH (V)
VOL (V)
DDRIO I/O Bank
(with Fixed Code)
Min
Max
IOH (mA)
IOL (mA)
2 mA
2 mA
2 mA
VDDI × 0.75
VDDI × 0.25
2
2
4 mA
4 mA
4 mA
VDDI × 0.75
VDDI × 0.25
4
4
–
6 mA
VDDI × 0.75
VDDI × 0.25
6
6
–
7.6.6.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 43 • LVCMOS 1.2 V AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ=125°C, VDD=1.14 V, VDDI= 1.14 V
tPYS
tPY
ODT (On Die
Termination)
in 
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
LVCMOS 1.2 V (for DDRIO I/O Bank with
Fixed Codes)
None
2.549
2.999
2.549
2.999
ns
LVCMOS 1.2 V (for MSIO I/O Bank)
None
4.264
5.017
4.230
4.976
ns
LVCMOS 1.2 V (for MSIOD I/O Bank)
None
3.568
4.198
3.551
4.178
ns
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 44 • LVCMOS 1.2 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ=125°C, VDD=1.14 V, VDDI= 1.14 V
tZL
tDP
Output
Drive
Selection
Slew
Control
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
tZH
Speed
Grade
STD
tHZ
tLZ
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
LVCMOS 1.2 V (for DDRIO I/O Bank with Fixed Code)
2 mA
4 mA
1 -2 2
slow
5.975
7.029
5.947
6.996
6.032
7.096
5.570
6.553
5.070
5.965
ns
medium
5.159
6.069
5.184
6.099
5.209
6.128
4.659
5.481
4.249
4.999
ns
fast
4.746
5.583
4.780
5.623
4.756
5.595
4.020
4.729
3.765
4.429
ns
slow
5.320
6.259
5.267
6.197
5.353
6.298
5.908
6.950
5.287
6.220
ns
medium
4.571
5.378
4.585
5.394
4.571
5.378
4.814
5.664
4.349
5.117
ns
fast
4.199
4.940
4.209
4.952
4.126
4.854
4.093
4.815
3.819
4.493
ns
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 44 • LVCMOS 1.2 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ=125°C, VDD=1.14 V, VDDI= 1.14 V (continued)
tZL
tDP
Output
Drive
Selection
6 mA
tZH
tHZ
tLZ
Slew
Control
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
slow
5.087
5.985
5.053
5.945
5.115
6.018
6.066
7.137
5.459
6.422
ns
medium
4.389
5.164
4.397
5.173
4.378
5.151
4.910
5.776
4.412
5.190
ns
fast
4.026
4.736
4.031
4.742
3.952
4.649
4.137
4.867
3.839
4.516
ns
LVCMOS 1.2 V (for MSIO I/O Bank)
2 mA
Default
9.759
11.481
9.615
11.312
9.367
11.020
9.320
10.965
8.522
10.026
ns
4 mA
Default
8.847
10.408
8.610
10.129
8.509
10.010
9.395
11.053
8.573
10.086
ns
LVCMOS 1.2 V (for MSIOD I/O Bank)
2 mA
Default
4.482
5.273
5.809
6.834
6.405
7.535
5.726
6.737
5.142
6.049
ns
4 mA
Default
4.230
4.977
5.014
5.899
5.513
6.486
5.836
6.866
5.190
6.106
ns
7.6.7 3.3 V PCI/PCIX
Peripheral Component Interface (PCI) for 3.3 V standards specify support for 33 MHz and 66 MHz PCI bus
applications.
7.6.7.1 Minimum and Maximum Input and Output Levels Specification
Table 45 • PCI/PCI-X DC Voltage Specification (Applicable to MSIO Bank Only
Symbols
Parameters
Conditions
Min
Typ
Max
Units
3.15
3.3
3.45
V
PCI/PCIX Recommended DC Operating Conditions
VDDI
Supply voltage
PCI/PCIX DC Input Voltage Specification
VI
DC input voltage
0
–
3.45
V
IIH(DC)
Input current High
–
–
10
µA
IIL(DC)
Input current Low
–
–
10
µA
PCI/PCIX DC Output Voltage Specification
VOH
DC output logic High
Per PCI Specification
V
VOL
DC output logic Low
Per PCI Specification
V
R e visi on 2
1-23
RTG4 FPGA AC/DC Electrical Characteristics
Table 46 • PCI/PCI-X AC Specifications (Applicable to MSIO Bank Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
–
–
630
Mbps
PCI/PCI-X AC Specifications
Dmax
Maximum data rate (MSIO I/O AC Loading:
Bank)
specifications
per
JEDEC
PCI/PCI-X AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path (falling edge)
–
0.615 × VDDI
–
V
Vtrip
Measuring/trip point for data path (rising edge)
–
0.285 × VDDI
–
V
Rtt_test
Resistance for data test path
–
25
–

Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2K
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Cload
Capacitive loading for data path (tDP)
–
10
–
pF
7.6.7.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 47 • PCI/PCIX AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 3.15 V
tPYS
tPY
ODT (On Die
Termination) in 
Speed Grade
–1
Speed Grade
STD
Speed Grade
–1
Speed Grade
STD
Units
None
3.080
3.623
3.215
3.782
ns
PCI/PCIX (for MSIO
I/O Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 48 • PCI/PCIX AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI= 3.15 V
tDP
PCI/PCIX (for MSIO
I/O Bank)
1 -2 4
tZL
tZH
tHZ
tLZ
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
2.593
3.051
2.589
3.046
2.516
2.960
3.673
4.321
3.184
3.746
ns
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
7.7. Memory Interface and Voltage Referenced I/O Standards
7.7.1 High-Speed Transceiver Logic (HSTL)
The High-Speed Transceiver Logic (HSTL) standard is a general purpose high-speed bus standard sponsored by IBM
(EIA/JESD8-6). RTG4 FPGA devices support two classes of the 1.5 V HSTL. These differential versions of the
standard require a differential amplifier input buffer and a push-pull output buffer.
7.7.1.1 Minimum and Maximum Input and Output Levels Specification
Table 49 • HSTL18 Minimum and Maximum DC Input and Output Levels
Symbols
Parameters
Conditions
Min
Typ
Max
Units Notes
HSTL 1.5 V Recommended DC Operating Conditions
VDDI
Supply voltage
1.71
1.8
1.89
V
VTT
Termination voltage
0.838
0.900
0.964
V
VREF
Input reference voltage
0.838
0.900
0.964
V
HSTL18 DC Input Voltage Specification
VIH (DC)
DC input logic High
VREF
+ 0.125
–
1.89
V
VIL (DC)
DC input logic Low
- 0.3
–
VREF
- 0.125
V
IIH (DC)
Input current High
–
–
10
µA
IIL (DC)
Input current Low
–
–
10
µA
HSTL18 V DC Output Voltage Specification
HSTL18 Class I
VOH
DC output logic High
VTT +0.603
–
–
V
VOL
DC output logic Low
–
–
VTT - 0.603
V
IOH at VOH
Output minimum source DC current (Applicable to MSIO
Bank Only)
4.5
–
–
mA
IOL at VOL
Output minimum sink current (Applicable to MSIO Bank
Only)
-4.5
–
–
mA
IOH at VOH
Output minimum source DC current (Applicable to MSIOD
Bank Only)
4.0
–
–
mA
IOL at VOL
Output minimum sink current (Applicable to MSIOD Bank
Only)
-4.0
–
–
mA
IOH at VOH
Output minimum source DC current (Applicable to DDRIO
Bank Only)
5.4
–
–
mA
IOL at VOL
Output minimum sink current (Applicable to DDRIO Bank
Only)
-5.4
–
–
mA
DC output logic High
VTT + 0.603
–
–
V
VOL
DC output logic Low
–
–
VTT - 0.603
IOH at VOH
Output minimum source DC current (Applicable to DDRIO
Bank Only)
11.4
–
–
mA
IOL at VOL
Output minimum sink current
Only)
-11.4
–
–
mA
0.25
–
–
V
HSTL18 Class II
VOH
(Applicable to DDRIO Bank
HSTL18 V DC Differential Voltage Specifications
VID
DC input differential voltage
R e visi on 2
1-25
RTG4 FPGA AC/DC Electrical Characteristics
Table 50 • HSTL18 Minimum and Maximum AC Switching Speeds
Symbols
Parameters
Conditions
Min
Typ
Max
Units
0.5
–
–
V
0.5 × VDDI 0.175
–
(0.5 × VDDI)
+ 0.175
V
Maximum Data Rate (for DDRIO
AC loading: 3 pF / 50 load
IO Bank)
–
–
500
Mbps
Maximum Data Rate (for MSIO
IO Bank)
–
–
500
Mbps
500
Mbps
HSTL18 AC Differential Voltage Specifications
VDIFF
AC input differential voltage
Vx
AC differential cross point voltage
HSTL18 V Maximum AC Switching Speed
Dmax
AC loading: 3 pF / 50 load
Maximum Data Rate (for MSIOD
AC loading: 3 pF / 50 load
IO Bank)
Rref
Supported Output Driver
Calibrated Impedance (for
DDRIO IO Bank)
Reference Resistor = 150 
–
20, 42
–

RTT
Effective impedance Value (ODT) Reference Resistor = 150 
–
50, 75, 150
–

HSTL18 AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
0.9
–
V
Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Rtt_test
Reference resistance for data test path for HSTL18 Class I (tDP)
–
50
–

Rtt_test
Reference resistance for data test path for HSTL18 Class II (tDP)
–
25
–

Cload
Capacitive loading for data path (tDP)
–
5
–
pF
7.7.1.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 51 • HSTL18 AC Switching Characteristics for Receiver (Input Buffers)
tPY
Speed Grade
–1
Speed Grade
STD
Units
None
1.743
2.051
ns
50
1.743
2.051
ns
75
1.743
2.051
ns
150
1.743
2.051
ns
None
1.780
2.094
ns
50
1.780
2.094
ns
75
1.780
2.094
ns
150
1.780
2.094
ns
ODT (On Die Termination) in

HSTL18 (for DDRIO I/O Bank with Fixed Code)
Pseudo-Differential
True-Differential
1 -2 6
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 51 • HSTL18 AC Switching Characteristics for Receiver (Input Buffers) (continued)
tPY
ODT (On Die Termination) in

Speed Grade
–1
Speed Grade
STD
Units
None
2.481
2.919
ns
50
2.481
2.919
ns
75
2.481
2.919
ns
150
2.481
2.919
ns
None
2.445
2.876
ns
50
2.445
2.876
ns
75
2.445
2.876
ns
150
2.445
2.876
ns
None
2.439
2.869
ns
50
2.439
2.869
ns
75
2.439
2.869
ns
150
2.439
2.869
ns
None
2.418
2.845
ns
50
2.418
2.845
ns
75
2.418
2.845
ns
150
2.418
2.845
ns
HSTL18 (for MSIO I/O Bank)
Pseudo-Differential
True-Differential
HSTL18 (For MSIOD I/O Bank)
Pseudo-Differential
True-Differential
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 52 • HSTL18 AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
tZL
tDP
Speed
Grade
–1
tZH
tHZ
tLZ
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
HSTL18 Class I
For DDRIO I/O Bank
Single Ended
3.006
3.536
2.678
3.150
2.723
3.203
3.721
4.378
3.777
4.443
ns
Differential
2.966
3.489
2.946
3.466
2.914
3.428
3.718
4.374
3.766
4.430
ns
Single Ended
3.912
4.602
3.675
4.323
3.748
4.409
4.640
5.459
4.265
5.018
ns
Differential
4.185
4.923
4.004
4.711
3.984
4.687
4.650
5.471
4.270
5.023
ns
For MSIO I/O Bank
For MSIOD I/O Bank
Single Ended
1.933
2.274
2.406
2.830
2.551
3.001
3.312
3.896
3.043
3.580
ns
Differential
2.163
2.545
2.972
3.496
2.961
3.484
3.327
3.914
3.050
3.588
ns
R e visi on 2
1-27
RTG4 FPGA AC/DC Electrical Characteristics
Table 52 • HSTL18 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) (continued)
tZL
tDP
Speed
Grade
–1
tZH
tHZ
tLZ
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
HSTL Class II
For DDRIO I/O Bank
Single Ended
2.857
3.361
2.604
3.064
2.629
3.093
3.727
4.385
3.781
4.448
ns
Differential
2.824
3.322
2.792
3.285
2.761
3.248
3.726
4.384
3.767
4.432
ns
7.7.1.3 Minimum and Maximum Input and Output Levels Specification
Table 53 • HSTL 1.5 V DC Voltage Specification
Symbols
Parameters
Conditions
Min
Typ
Max
Units
HSTL 1.5 V Recommended DC Operating Conditions
VDDI
Supply voltage
1.425
1.5
1.575
V
VTT
Termination voltage
0.698
0.750
0.803
V
VREF
Input reference voltage
0.698
0.750
0.803
V
HSTL 1.5 V DC Input Voltage Specification
VIH (DC)
DC input logic High
VREF + 0.1
–
1.575
V
VIL (DC)
DC input logic Low
–0.3
–
VREF – 0.1
V
IIH (DC)
Input current High
–
–
10
µA
IIL (DC)
Input current Low
–
–
10
µA
VDDI – 0.4
–
–
V
HSTL 1.5 V DC Output Voltage Specification
HSTL 1.5 V Class I
VOH
DC output logic High
VOL
DC output logic Low
IOH at VOH
Output minimum source DC current (for MSIO Bank)
IOL at VOL
Output minimum sink current (for MSIO Bank)
IOH at VOH
Output minimum source DC current (for MSIOD Bank)
IOL at VOL
Output minimum sink current (for MSIOD Bank)
IOH at VOH
Output minimum source DC current (for DDRIO Bank)
IOL at VOL
Output minimum sink current (for DDRIO Bank)
–
–
0.4
V
- 8.0
–
–
mA
8.0
–
–
mA
- 7.8
–
–
mA
7.8
–
–
mA
- 8.0
–
–
mA
8.0
–
–
mA
HSTL 1.5 V Class II (Applicable to DDRIO Bank Only)
VOH
DC output logic High
VDDI – 0.4
–
–
V
VOL
DC output logic Low
–
–
0.4
V
IOH at VOH
Output minimum source DC current
- 16.0
–
–
mA
IOL at VOL
Output minimum sink current
16.0
–
–
mA
0.2
–
–
V
HSTL 1.5 V DC Differential Voltage Specifications
VID
1 -2 8
DC input differential voltage
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 54 • HSTL 1.5 V AC Specifications
Symbols
Parameters
Conditions
Min
Typ
Max
Units
HSTL 1.5 V AC Differential Voltage Specifications
VDIFF
AC input differential voltage
0.4
–
–
V
Vx
AC differential cross point voltage
0.68
–
0.9
V
Maximum data date - Class I - MSIO
AC loading: 3 pF / 50  load
bank only
–
–
140
Mbps
Maximum data rate - Class I - MSIOD
AC loading: 3 pF / 50 load
bank only
–
–
180
Mbps
Maximum data rate - Class I - DDRIO AC loading: per JEDEC
bank only
specifications
–
–
400
Mbps
Maximum data rate - Class II DDRIO bank only
AC loading: per JEDEC
specifications
–
–
400
Mbps
HSTL 1.5 V Maximum AC Switching Speed
Dmax
HSTL 1.5 V Impedance Specification
Rref
Supported output driver calibrated
impedance (for DDRIO I/O Bank)
Reference resistance = 191 
–
25.5, 47.8
–

RTT
Effective impedance value (ODT for
DDRIO I/O Bank only)
Reference resistance = 191 
–
47.8
–

HSTL 1.5 V AC Test Parameters Specification
Vtrip
Measuring/trip point for data path
–
0.75
–
V
Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Rtt_test
Reference resistance for data test path for HSTL15 Class I (tDP)
–
50
–

Rtt_test
Reference resistance for data test path for HSTL15 Class II (tDP)
–
25
–

Cload
Capacitive loading for data path (tDP)
–
5
–
pF
7.7.1.4 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 55 • HSTL 1.5 V AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.425 V
tPY
ODT (On Die
Termination) in 
Speed Grade
–1
Speed Grade
STD
Units
None
1.764
2.075
ns
47.8
1.764
2.075
ns
None
1.781
2.095
ns
47.8
1.781
2.095
ns
Pseudo-Differential
None
2.640
3.106
ns
True-Differential
None
2.485
2.923
ns
Pseudo-Differential
None
2.572
3.026
ns
True-Differential
None
2.457
2.891
ns
HSTL (for DDRIO I/O Bank with Fixed Code)
Pseudo-Differential
True-Differential
HSTL (For MSIO I/O Bank)
HSTL (For MSIOD I/O Bank)
R e visi on 2
1-29
RTG4 FPGA AC/DC Electrical Characteristics
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 56 • HSTL 1.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.425 V
tDP
Speed
Grade
–1
tZL
tZH
tHZ
tLZ
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
HSTL Class I
For DDRIO I/O Bank
Single Ended
3.560
4.188
3.254
3.828
3.297
3.879
4.439
5.222
4.490
5.282
ns
Differential
3.528
4.150
3.564
4.193
3.547
4.173
4.538
5.339
4.391
5.166
ns
For MSIO I/O Bank
Single Ended
5.103
6.003
4.697
5.526
4.786
5.631
5.919
6.963
5.446
6.407
ns
Differential
5.368
6.315
5.024
5.910
4.996
5.878
5.477
6.443
5.889
6.928
ns
For MSIOD I/O Bank
Single Ended
2.512
2.955
2.771
3.260
2.981
3.507
3.988
4.692
3.639
4.281
ns
Differential
2.734
3.216
3.346
3.936
3.332
3.920
3.659
4.305
3.967
4.667
ns
HSTL Class II
For DDRIO I/O Bank
Single Ended
3.379
3.975
3.162
3.720
3.188
3.750
4.446
5.231
4.488
5.280
ns
Differential
3.353
3.945
3.387
3.985
3.371
3.966
4.534
5.334
4.394
5.169
ns
7.7.2 Stub-Series Terminated Logic
Stub-Series Terminated Logic (SSTL) for 2.5 V (SSTL2), 1.8 V (SSTL18), and 1.5 V (SSTL15) is supported in RTG4
FPGAs. SSTL2 is defined by JEDEC standard JESD8-9B and SSTL18 is defined by JEDEC standard JESD8-15.
RTG4 SSTL I/O configurations are designed to meet double data rate standards DDR/2/3 for general purpose memory
buses. Double data rate standards are designed to meet their JEDEC specifications as defined by JEDEC standard
JESD79F for DDR, JEDEC standard JESD79-2F for DDR, JEDEC standard JESD79-3D for DDR3, and JEDEC
standard JESD209A for LPDDR.
7.7.3 Stub-Series Terminated Logic 2.5 V (SSTL2)
SSTL2 Class I and Class II are supported in RTG4 FPGAs and also comply with reduced and full drive of double data
rate (DDR) standards. RTG4 FPGA I/Os supports both standards for single-ended signaling and differential signaling
for SSTL2. This standard requires a differential amplifier input buffer and a push-pull output buffer.
1 -3 0
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
7.7.3.1 Minimum and Maximum DC Input and Output Levels Specification
Table 57 • DDR1/SSTL2 Minimum and Maximum DC Input and Output Levels
Symbols
Parameters
Conditions
Min
Typ
Max
Units
Recommended DC Operating Conditions
VDDI
Supply voltage
2.375
2.5
2.625
V
VTT
Termination voltage
1.164
1.250
1.339
V
VREF
Input reference voltage
1.164
1.250
1.339
V
SSTL2 DC Input Voltage Specification - Applicable to All Banks
VIH (DC)
DC input logic High
VREF + 0.15
–
2.625
V
VIL (DC)
DC input logic Low
- 0.3
–
VREF - 0.15
V
IIH (DC)
Input current High
–
–
10
µA
IIL (DC)
Input current Low
–
–
10
µA
SSTL2 DC Output Voltage Specification
SSTL2 Class I (DDR Reduced Drive)
VOH
DC output logic High
VTT + 0.608
–
–
V
VOL
DC output logic Low
–
–
VTT - 0.608
V
IOH at VOH
Output minimum source DC current
8.1
–
–
mA
IOL at VOL
Output minimum sink current
-8.1
–
–
mA
SSTL2 Class II (DDR Full Drive)
VOH
DC output logic High
VTT + 0.81
–
–
V
VOL
DC output logic Low
–
–
VTT - 0.81
V
IOH at VOH
Output minimum source DC current
16.2
–
–
mA
IOL at VOL
Output minimum sink current
-16.2
–
–
mA
0.3
–
–
V
SSTL2 DC Differential Voltage Specification
VID (DC)
DC input differential voltage
Table 58 • DDR1/SSTL2 AC Specifications
Symbols
Parameters
Conditions
Min
Typ
Max
Units
SSTL2 Maximum AC Switching Speeds
Dmax
Maximum data rate (for
DDRIO I/O Bank)
AC loading: per JEDEC
specifications
–
–
800
Mbps
Dmax
Maximum data rate (for
MSIO I/O Bank)
AC loading: 3 pF/25 load
–
–
575
Mbps
Dmax
Maximum data rate (for
MSIOD I/O Bank)
AC loading: 3 pF/25 load
–
–
700
Mbps
0.7
–
–
V
0.5 × VDDI
- 0.2
–
0.5 × VDDI
+ 0.2
V
SSTL2 AC Differential Voltage Specifications
VDIFF
AC Input Differential Voltage
Vx
AC Differential Cross Point
Voltage
R e visi on 2
1-31
RTG4 FPGA AC/DC Electrical Characteristics
Table 58 • DDR1/SSTL2 AC Specifications (continued)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
–
20, 42
–

SSTL2 Impedance Specifications
Supported output driver
Reference resistor
calibrated impedance (for
= 150 
DDRIO I/O Bank)
SSTL2 AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
1.25
–
V
Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Rtt_test
Reference resistance for data test path for SSTL2 Class I
(tDP)
–
50
–

Rtt_test
Reference resistance for data test path for SSTL2 Class II
(tDP)
–
25
–

Cload
Capacitive loading for data path (tDP)
–
5
–
pF
7.7.3.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 59 • DDR1/SSTL2 AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI= 2.375 V
tPY
ODT (On Die
Termination) in 
Speed Grade
–1
Speed Grade
STD
Units
Pseudo-Differential
None
1.730
2.035
ns
True-Differential
None
1.751
2.060
ns
Pseudo-Differential
None
2.319
2.728
ns
True-Differential
None
2.271
2.672
ns
Pseudo-Differential
None
2.285
2.688
ns
True-Differential
None
2.250
2.647
ns
SSTL2 (DDRIO I/O Bank)
SSTL2 (MSIO I/O Bank)
SSTL2 (MSIOD I/O Bank)
1 -3 2
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 60 • DDR1/SSTL2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI= 2.375 V
tDP
tZL
tZH
tHZ
tLZ
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
Single Ended
2.568
3.021
2.244
2.640
2.259
2.658
3.016
3.548
3.080
3.623
ns
Differential
2.505
2.947
2.452
2.885
2.457
2.891
3.011
3.542
3.071
3.613
ns
Single Ended
2.874
3.381
2.668
3.139
2.747
3.232
3.477
4.090
3.203
3.768
ns
Differential
3.148
3.703
2.953
3.474
2.939
3.458
3.486
4.101
3.208
3.774
ns
Single Ended
1.616
1.901
1.943
2.286
2.037
2.396
2.713
3.192
2.519
2.964
ns
Differential
1.845
2.171
2.383
2.804
2.376
2.795
2.729
3.210
2.527
2.973
ns
Single Ended
2.436
2.866
2.181
2.566
2.180
2.565
3.020
3.553
3.080
3.623
ns
Differential
2.370
2.788
2.309
2.716
2.315
2.723
3.014
3.546
3.068
3.609
ns
Single Ended
2.818
3.315
2.629
3.093
2.719
3.199
3.473
4.086
3.201
3.766
ns
Differential
3.095
3.641
2.816
3.313
2.804
3.299
3.482
4.097
3.205
3.771
ns
Single Ended
1.690
1.988
1.857
2.185
1.965
2.312
2.716
3.195
2.519
2.964
ns
Differential
1.909
2.246
2.215
2.606
2.207
2.597
2.730
3.212
2.529
2.975
ns
SSTL2 Class I
DDRIO I/O Bank
MSIO I/O Bank
MSIOD I/O Bank
SSTL2 Class II
DDRIO I/O Bank
MSIO I/O Bank
MSIOD I/O Bank
R e visi on 2
1-33
RTG4 FPGA AC/DC Electrical Characteristics
7.7.4 Stub-Series Terminated Logic 1.8 V (SSTL18)
SSTL18 Class I and Class II are supported in RTG4 FPGAs, and also comply with the reduced and full drive double
date rate (DDR2) standard. RTG4 FPGA I/Os support both standards for single-ended signaling and differential
signaling for SSTL18. This standard requires a differential amplifier input buffer and a push-pull output buffer.
7.7.4.1 Minimum and Maximum Input and Output Levels Specification
Table 61 • DDR2/SSTL18 DC Minimum and Maximum Input and Output Levels Specification
Symbols
Parameters
Conditions
Min
Typ
Max
Units Notes
Recommended DC Operating Conditions
VDDI
Supply voltage
1.71
1.8
1.89
V
VTT
Termination voltage
0.838
0.900
0.964
V
VREF
Input reference voltage
0.838
0.900
0.964
V
SSTL18 DC Input Voltage Specification
VIH (DC)
DC input logic High
VREF + 0.125
–
1.89
V
VIL (DC)
DC input logic Low
–0.3
–
VREF – 0.125
V
IIH (DC)
Input current High
–
–
10
µA
IIL (DC)
Input current Low
–
–
10
µA
SSTL18 DC Output Voltage Specification
SSTL18 Class I (DDR2 Reduced Drive)
VOH
DC output logic High
VTT + 0.603
–
–
V
VOL
DC output logic Low
–
–
VTT– 0.603
V
IOH at VOH
Output minimum source DC current (Applicable to
MSIO and MSIOD banks)
4.7
–
–
mA
1
IOL at VOL
Output minimum sink current (Applicable to MSIO and
MSIOD banks)
-4.7
–
–
mA
1
IOH at VOH
Output minimum source DC current (Applicable to
DDRIO bank only)
6.3
–
–
mA
1
IOL at VOL
Output minimum sink current (Applicable to DDRIO
bank only)
-6.3
–
–
mA
1
SSTL18 Class II (DDR2 Full Drive)
3
VOH
DC output logic High
VTT + 0.603
–
–
V
VOL
DC output logic Low
–
–
VTT - 0.603
V
IOH at VOH
Output minimum source DC current (Applicable to
MSIO and MSIOD banks)
9.3
–
–
mA
2
IOL at VOL
Output minimum sink current (Applicable to MSIO and
MSIOD banks)
-9.3
–
–
mA
2
IOH at VOH
Output minimum source DC current (Applicable to
DDRIO bank only)
13.4
–
–
mA
Notes:
1. MSIO and MSIOD Bank SSTL18/DDR2 Reduced Drive does not have a standard test point. This is defined to fit within the DDR2
"Reduced Drive" IV Curve minimums.
2. MSIO IO Bank SSTL18/DDR2 Class II does not meet the standard JEDEC Test Points. Use Provided Lower Current Values as
specified.
3. To meet JEDEC Electrical Compliance, use DDR2 Full Drive Transmitter.
1 -3 4
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 61 • DDR2/SSTL18 DC Minimum and Maximum Input and Output Levels Specification (continued)
Symbols
IOL at VOL
Parameters
Conditions
Output minimum sink current (Applicable to DDRIO
bank only)
Min
Typ
Max
Units Notes
-13.4
–
–
mA
0.25
–
–
V
SSTL18 DC Differential Voltage Specification
VID (DC)
DC input differential voltage
Notes:
1. MSIO and MSIOD Bank SSTL18/DDR2 Reduced Drive does not have a standard test point. This is defined to fit within the DDR2
"Reduced Drive" IV Curve minimums.
2. MSIO IO Bank SSTL18/DDR2 Class II does not meet the standard JEDEC Test Points. Use Provided Lower Current Values as
specified.
3. To meet JEDEC Electrical Compliance, use DDR2 Full Drive Transmitter.
Table 62 • DDR2/SSTL18 AC Specifications (Applicable to DDRIO Bank Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
0.5
–
–
V
0.5 × VDDI
- 0.175
–
0.5 × VDDI
+ 0.175
V
SSTL18 AC Differential Voltage Specification
VDIFF (AC)
AC input differential voltage
Vx (AC)
AC differential cross point voltage
SSTL18 Maximum AC Switching Speed
Dmax
Maximum data rate (for AC loading: per JEDEC
DDRIO I/O Bank)
specification
–
–
800
Mbps
Dmax
Maximum Data Rate (for AC loading: 3 pF/25 
MSIO IO Bank)
load
–
–
432
Mbps
Dmax
Maximum Data Rate (for AC loading: 3 pF/25 
MSIOD IO Bank)
load
–
–
430
Mbps
SSTL18 Impedance Specifications
Rref
Supported output driver
Reference resistor
calibrated impedance (for
= 150 
DDRIO I/O Bank)
–
20, 42
–

RTT
Effective impedance value Reference resistor
(ODT)
= 150 
–
50, 75,
150
–

SSTL18 AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
0.9
–
V
Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Rtt_test
Reference resistance for data test path for SSTL18
Class I (tDP)
–
50
–

Rtt_test
Reference resistance for data test path for SSTL18
Class II (tDP)
–
25
–

Cload
Capacitive loading for data path (tDP)
–
5
–
pF
R e visi on 2
1-35
RTG4 FPGA AC/DC Electrical Characteristics
7.7.4.2. AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 63 • DDR2/SSTL18 AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.71 V
tPY
Speed Grade
–1
Speed Grade
STD
Units
None
1.743
2.051
ns
50
1.743
2.051
ns
75
1.743
2.051
ns
150
1.743
2.051
ns
None
1.780
2.094
ns
50
1.780
2.094
ns
75
1.780
2.094
ns
150
1.780
2.094
ns
None
2.481
2.919
ns
50
2.481
2.919
ns
75
2.481
2.919
ns
150
2.481
2.919
ns
None
2.445
2.876
ns
50
2.445
2.876
ns
75
2.445
2.876
ns
150
2.445
2.876
ns
None
2.439
2.869
ns
50
2.439
2.869
ns
75
2.439
2.869
ns
150
2.439
2.869
ns
None
2.418
2.845
ns
50
2.418
2.845
ns
75
2.418
2.845
ns
150
2.418
2.845
ns
On-Die Termination (ODT) in 
SSTL18 (for DDRIO I/O Bank with Fixed Codes)
Pseudo differential
True differential
SSTL18 (For MSIO IO Bank)
Pseudo differential
True differential
SSTL18 (For MSIOD IO Bank)
Pseudo differential
True differential
1 -3 6
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 64 • DDR2/SSTL18 AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.71 V
tDP
Speed
Grade
–1
tZL
tZH
tHZ
tLZ
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
SSTL18 Class I
DDRIO I/O Bank
Single Ended
3.006
3.536
2.678
3.150
2.723
3.203
3.721
4.378
3.777
4.443
ns
Differential
2.966
3.489
2.946
3.466
2.939
3.458
3.810
4.482
3.673
4.321
ns
MSIO I/O Bank
Single Ended
3.912
4.602
3.675
4.323
3.748
4.409
4.640
5.459
4.265
5.018
ns
Differential
4.185
4.923
4.005
4.712
3.985
4.688
4.291
5.048
4.618
5.433
ns
MSIOD I/O Bank
Single Ended
1.933
2.274
2.406
2.830
2.551
3.001
3.312
3.896
3.043
3.580
ns
Differential
2.163
2.545
2.972
3.496
2.961
3.484
3.057
3.596
3.298
3.880
ns
SSTL18 Class II
DDRIO I/O Bank
Single Ended
2.857
3.361
2.604
3.064
2.629
3.093
3.727
4.385
3.781
4.448
ns
Differential
2.824
3.322
2.792
3.285
2.786
3.278
3.816
4.489
3.682
4.332
ns
MSIO I/O Bank
Single Ended
3.856
4.536
3.620
4.259
3.715
4.371
4.636
5.454
4.264
5.016
ns
Differential
4.120
4.847
3.844
4.522
3.825
4.500
4.289
5.046
4.615
5.429
ns
MSIOD I/O Bank
Single Ended
2.048
2.409
2.308
2.715
2.470
2.906
3.318
3.904
3.046
3.584
ns
Differential
2.286
2.689
2.757
3.244
2.746
3.230
3.061
3.601
3.303
3.886
ns
R e visi on 2
1-37
RTG4 FPGA AC/DC Electrical Characteristics
7.7.5 Stub-Series Terminated Logic 1.5 V (SSTL15)
SSTL15 Class I and Class II are supported in RTG4 FPGAs, and also comply with the reduced and full drive double
data rate (DDR3) standard. RTG4 FPGA I/Os supports both standards for single-ended signaling and differential
signaling for SSTL18. This standard requires a differential amplifier input buffer and a push-pull output buffer.
7.7.5.1 Minimum and Maximum AC/DC Input and Output Levels Specification
Table 65 • DDR3 SSTL15 DC Voltage Specification (for DDRIO I/O Bank Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
Recommended DC Operating Conditions
VDDI
Supply voltage
1.425
1.5
1.575
V
VTT
Termination voltage
0.698
0.750
0.803
V
VREF
Input reference voltage
0.698
0.750
0.803
V
SSTL15 DC Input Voltage Specification
VIH(DC)
DC input logic High
VREF + 0.1
–
1.575
V
VIL(DC)
DC input logic Low
- 0.3
–
VREF - 0.1
V
IIH (DC)
Input current High
–
–
10
µA
IIL (DC)
Input current Low
–
–
10
µA
SSTL15 DC Output Voltage Specification
SSTL15 Class II (DDR3 Full Drive)
VOH
DC output logic High
0.8 × VDDI
–
–
V
VOL
DC output logic Low
–
–
0.2 × VDDI
V
IOH at VOH
Output minimum source DC current
13.4
–
–
mA
IOL at VOL
Output minimum sink current
- 13.4
–
–
mA
0.2
–
–
V
SSTL15 Differential Voltage Specification
VID
DC input differential voltage
Note: *To meet JEDEC Electrical Compliance, use DDR3 Full Drive Transmitter.
Table 66 • DDR3/SSTL15 AC Specifications
Symbols
Parameters
Conditions
Min
Typ
Max
Units
0.7
–
–
V
0.5 × VDDI
- 0.150
–
0.5 × VDDI
+ 0.150
V
–
–
800
Mbps
SSTL15 AC Differential Voltage Specification
VDIFF
AC input differential voltage
Vx
AC differential cross point voltage
SSTL15 Maximum AC Switching Speed (for DDRIO I/O Banks Only)
Dmax
Maximum data rate
AC loading: per JEDEC
specifications
SSTL15 AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
0.75
–
V
Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Rtt_test
Reference resistance for data test path for SSTL15 Class
I (tDP)
–
50
–

1 -3 8
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 66 • DDR3/SSTL15 AC Specifications (continued)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
Rtt_test
Reference resistance for data test path for SSTL15 Class
II (tDP)
–
25
–

Cload
Capacitive loading for data path (tDP)
–
5
–
pF
7.7.5.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 67 • DDR3/STTL15 AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.425 V
tPY
Speed Grade
–1
ODT (On Die
Termination) in 
Speed Grade
STD
Units
DDR3/SSTL15 (for DDRIO I/O Bank) – Calibration Mode Only
Pseudo-Differential
True-Differential
None
1.765
2.076
ns
20
1.765
2.076
ns
30
1.765
2.076
ns
40
1.765
2.076
ns
60
1.765
2.076
ns
120
1.765
2.076
ns
None
1.780
2.094
ns
20
1.780
2.094
ns
30
1.780
2.094
ns
40
1.780
2.094
ns
60
1.780
2.094
ns
120
1.780
2.094
ns
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 68 • DDR3/SSTL15 AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.425 V
tDP
Speed
Grade
–1
tZL
Speed
Grade
STD
Speed
Grade
–1
tZH
Speed
Grade
STD
Speed
Grade
–1
tHZ
tLZ
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
DDR3 Reduced Drive/SSTL15 Class I (for DDRIO I/O Bank)
Single Ended
3.549
4.175
3.182
3.743
3.210
3.777
4.439
5.222
4.491
5.283
ns
Differential
3.513
4.133
3.415
4.018
3.594
4.229
4.502
5.297
4.392
5.167
ns
DDR3 Full Drive/SSTL15 Class II (for DDRIO I/O Bank)
Single Ended
3.432
4.038
3.193
3.757
3.228
3.798
4.438
5.221
4.491
5.283
ns
Differential
3.511
4.130
3.386
3.983
3.527
4.149
4.497
5.290
4.386
5.160
ns
R e visi on 2
1-39
RTG4 FPGA AC/DC Electrical Characteristics
7.7.6 Low Power Double Data Rate (LPDDR)
LPDDR reduced and full drive low power double data rate standards are supported in RTG4 FPGA I/Os. This standard
requires a differential amplifier input buffer and a push-pull output buffer. This I/O standard is supported in DDRIO I/O
Bank only.
7.7.6.1 Minimum and Maximum AC/DC Input and Output Levels Specification
Table 69 • LPDDR DC Specifications (for DDRIO IO Bank Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
Notes
Recommended DC Operating Conditions
VDDI
Supply voltage
1.71
1.8
1.89
V
VTT
Termination voltage
0.838
0.900
0.964
V
VREF
Input reference voltage
0.838
0.900
0.964
V
LPDDR DC Input Voltage Specification
VIH (DC)
DC input logic High
0.7 × VDDI
–
1.89
V
VIL (DC)
DC input logic Low
-0.3
–
0.3 × VDDI
V
IIH (DC)
Input current High
–
–
10
µA
IIL (DC)
Input current Low
–
–
10
µA
LPDDR DC Output Voltage Specification
LPDDR Reduced Drive
VOH
DC output logic High
0.9 × VDDI
–
–
V
VOL
DC output logic Low
–
–
0.1 × VDDI
V
IOH at VOH
Output minimum source DC current
0.1
–
–
mA
IOL at VOL
Output minimum sink current
-0.1
–
–
mA
LPDDR Full Drive
*
VOH
DC output logic High
0.9 × VDDI
–
–
V
VOL
DC output logic Low
–
–
0.1 × VDDI
V
IOH at VOH
Output minimum source DC current
0.1
–
–
mA
IOL at VOL
Output minimum sink current
-0.1
–
–
mA
0.4 × VDDI
–
–
V
LPDDR DC Differential Voltage Specification
VID (DC)
DC input differential voltage
Note: *To meet JEDEC Electrical Compliance, use LPDDR Full Drive Transmitter.
Table 70 • LPDDR Maximum AC Switching Speeds (for DDRIO I/O Bank Only)
Symbols
Dmax
1 -4 0
Parameters
Maximum data rate
Conditions
AC loading: per JEDEC specifications
R ev i si o n 2
Min
Typ
Max
Units
–
–
700
Mbps
DS0131: RTG4 FPGA Datasheet
Table 71 • LPDDR AC Specifications (for DDRIO IO Bank Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
LPDDR AC Differential Voltage Specification
VDIFF (AC)
AC Input differential voltage
0.6 × VDDI
–
–
V
Vx (AC)
AC Differential Cross Point Voltage
0.4 × VDDI
–
0.6 × VDDI
V
LPDDR Impedance Specifications
Rref
Supported Output Driver Calibrated
Impedance
Reference Resistor =
150 
–
20,42
–

RTT
Effective impedance Value - ODT
Reference Resistor =
150 
–
50, 75,
150
–

LPDDR AC Test Parameters Specifications
Vtrip
Measuring/Trip Point for Data Path
–
0.9
–
V
Cent
Capacitive Loading for Enable Path (tZH,
tZL, tHZ, tLZ)
–
5
–
pF
Rtt_test
Reference resistance for Data Test Path
for LPDDR (tDP)
–
50
–

Cload
Capacitive Loading for Data Path (tDP)
–
5
–
pF
7.7.6.2 AC Switching Characteristics
Table 72 • LPDDR AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ=125°C, VDD=1.14 V, VDDI= 1.71 V
tPY
ODT (On Die
Termination) in 
Speed Grade
–1
Speed Grade
STD
Units
None
1.744
2.052
ns
50
1.744
2.052
ns
75
1.744
2.052
ns
150
1.744
2.052
ns
None
1.781
2.095
ns
50
1.781
2.095
ns
75
1.781
2.095
ns
150
1.781
2.095
ns
LPDDR (for DDRIO I/O Bank with Fixed Codes)
Pseudo-Differential
True-Differential
R e visi on 2
1-41
RTG4 FPGA AC/DC Electrical Characteristics
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 73 • LPDDR AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ=125°C, VDD=1.14 V, VDDI= 1.71 V
tDP
Speed
Grade
–1
tZL
Speed
Grade
STD
Speed
Grade
–1
tZH
tHZ
tLZ
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
LPDDR Reduced Drive (for DDRIO I/O Bank)
Single Ended
3.006
3.536
2.678
3.150
2.723
3.203
3.721
4.378
3.777
4.443
ns
Differential
2.967
3.490
2.946
3.466
2.939
3.458
3.810
4.482
3.673
4.321
ns
LPDDR Full Drive (for DDRIO I/O Bank)
Single Ended
2.857
3.361
2.604
3.064
2.629
3.093
3.727
4.385
3.781
4.448
ns
Differential
2.825
3.323
2.792
3.285
2.761
3.248
3.726
4.384
3.767
4.432
ns
7.7.6.3 Minimum and Maximum AC/DC Input and Output Levels Specification using LPDDR-LVCMOS 1.8 V
Mode
Table 74 • LPDDR-LVCMOS 1.8 V Mode, Minimum and Maximum DC Input and Output Levels
(Applicable to DDRIO I/O Bank Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
1.710
1.8
1.89
V
LPDDR-LVCMOS 1.8 V Recommended DC Operating Conditions
VDDI
Supply Voltage
LPDDR-LVCMOS 1.8 V Mode DC Input Voltage Specification
VIH(DC)
DC input Logic HIGH
0.65 x VDDI
–
2.75
V
VIL(DC)
DC input Logic LOW
-0.3
–
0.35 x VDDI
V
IIH(DC)
Input current HIGH
–
–
10
uA
IIL(DC)
Input current LOW
–
–
10
uA
LPDDR-LVCMOS 1.8 V Mode DC Output Voltage Specification
VOH
DC output Logic HIGH
VDDI - 0.45
–
–
V
VOL
DC output Logic LOW
–
–
0.45
V
Table 75 • LPDDR-LVCMOS 1.8 V Maximum AC Switching Speeds (Applicable to DDRIO I/O Bank Only)
Symbols
Dmax
1 -4 2
Parameters
Maximum Data Rate
(for DDRIO I/O Bank)
Conditions
AC loading: per JEDEC
specifications
R ev i si o n 2
Min
Typ
Max
Units
–
–
700
Mbps
DS0131: RTG4 FPGA Datasheet
Table 76 • LPDDR-LVCMOS 1.8 V AC Test Parameters and Driver Impedance Specifications (Applicable to DDRIO I/O
Bank Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
LPDDR- LVCMOS 1.8 V AC Test Parameters Specifications
Vtrip
Measuring/Trip Point for Data Path
–
0.9
–
V
Rent
Resistance for Enable Path (tZH, tZL,
tHZ, tLZ)
–
2K
–

Cent
Capacitive Loading for Enable Path
(tZH, tZL, tHZ, tLZ)
–
5
–
pF
Cload
Capacitive Loading for Data Path (tDP)
–
5
–
pF
Table 77 • LPDDR-LVCMOS 1.8 V Mode Transmitter Drive Strength Specification (Applicable to DDRIO I/O Bank Only)
Output Drive
Selection
VOH
Min (V)
VOL
Max (V)
IOH (mA)
IOL (mA)
2 mA
VDDI – 0.45
0.45
2
2
4 mA
VDDI – 0.45
0.45
4
4
6 mA
VDDI – 0.45
0.45
6
6
8 mA
VDDI – 0.45
0.45
8
8
10 mA
VDDI – 0.45
0.45
10
10
12 mA
VDDI – 0.45
0.45
12
12
16 mA
VDDI – 0.45
0.45
16
16
Notes
*
Note: * 16mA Drive Strengths, All Slews, meet LPDDR JEDEC electrical compliance
7.7.6.4 AC Switching Characteristics
Table 78 • LPPDR - LVCMOS 1.8 V AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.71 V
tPYS
tPY
LPDDR-LVCMOS 1.8 mode
(for DDRIO I/O Bank with Fixed
Codes)
ODT (On Die
Termination)
in 
Speed Grade
–1
Speed
Grade
STD
Speed Grade
–1
Speed
Grade
STD
Units
None
2.209
2.599
2.209
2.599
ns
R e visi on 2
1-43
RTG4 FPGA AC/DC Electrical Characteristics
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 79 • LPDDR - LVCMOS 1.8 V AC Switching Characteristics for Transmitter DDRIO I/O Bank (Output and Tristate
Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.71 V
tZL
tDP
Output Drive
Selection
2 mA
4 mA
6 mA
8 mA
10 mA
12 mA
16 mA
tZH
tHZ
tLZ
Slew
Control
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
slow
4.032
4.744
3.988
4.692
4.052
4.767
3.683
4.333
3.451
4.060
ns
medium
3.578
4.209
3.599
4.234
3.601
4.236
3.039
3.575
2.824
3.322
ns
slow
3.673
4.321
3.607
4.243
3.674
4.322
3.823
4.498
3.595
4.229
ns
medium
3.222
3.790
3.223
3.792
3.229
3.799
3.125
3.677
2.885
3.394
ns
slow
3.432
4.038
3.361
3.954
3.430
4.035
3.815
4.488
3.528
4.151
ns
medium
3.016
3.548
3.013
3.545
3.018
3.550
3.108
3.657
2.845
3.347
ns
slow
3.329
3.917
3.251
3.825
3.318
3.904
3.917
4.608
3.628
4.268
ns
medium
2.913
3.427
2.905
3.418
2.911
3.425
3.158
3.715
2.898
3.409
ns
slow
3.197
3.761
3.108
3.656
3.179
3.740
4.028
4.739
3.725
4.382
ns
medium
2.791
3.284
2.775
3.265
2.786
3.278
3.228
3.798
2.945
3.465
ns
slow
3.103
3.651
3.028
3.562
3.084
3.628
3.941
4.637
3.630
4.271
ns
medium
2.733
3.215
2.721
3.201
2.709
3.187
3.177
3.738
2.893
3.403
ns
slow
3.051
3.589
2.966
3.489
3.025
3.559
4.017
4.726
3.737
4.396
ns
medium
2.683
3.157
2.665
3.135
2.659
3.128
3.214
3.781
2.946
3.466
ns
7.8 Differential I/O Standards
Configuration of the I/O modules as a differential pair is handled by Microsemi SoC Products Group Libero® Systemon-Chip (SoC) software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be
used in conjunction with the embedded Input register (InReg), Output register (OutReg), Enable register (EnReg), and
Double Data Rate registers (DDR).
7.8.1 LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard.
7.8.1.1 Minimum and Maximum Input and Output Levels
Table 80 • LVDS DC Voltage Specification (Applicable to MSIO and MSIOD Banks Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
LVDS Recommended DC Operating Conditions
VDDI
Supply voltage
2.5 V range
2.375
2.5
2.625
V
VDDI
Supply voltage
3.3 V range
3.15
3.3
3.45
V
DC Input voltage
2.5 V range
0
–
2.925
V
VI
DC input voltage
3.3 V range
0
–
3.45
V
IIH (DC)
Input current High
–
–
10
µA
IIL (DC)
Input current Low
–
–
10
µA
LVDS DC Input Voltage Specification
VI
1 -4 4
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 80 • LVDS DC Voltage Specification (Applicable to MSIO and MSIOD Banks Only) (continued)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
LVDS DC Output Voltage Specification
VOH
DC output logic High
1.25
1.425
1.6
V
VOL
DC output logic Low
0.9
1.075
1.25
V
250
350
450
mV
LVDS Differential Voltage Specification
VOD
Differential output voltage swing
VOCM
Output common mode voltage
1.125
1.25
1.375
V
VICM
Input common mode voltage
0.05
1.25
2.35
V
VID
Input differential voltage
100
350
600
mV
Table 81 • LVDS AC Specifications (Applicable to MSIO and MSIOD Banks Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
LVDS Maximum AC Switching Speed
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC loading: 12 pF / 100 
differential load
–
–
750
Mbps
Dmax
Maximum data rate
(for MSIOD I/O Bank)
AC loading: 10 pF / 100 
differential load
–
–
750
Mbps
–
100
–

LVDS Impedance Specification
Rt
Termination resistance
LVDS AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
Cross point
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2K
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
7.8.1.2 LVDS25 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 82 • LVDS25 Receiver Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 2.375 V
tPY
LVDS (for MSIO I/O Bank)
LVDS (for MSIOD I/O Bank)
On-Die Termination (ODT) in 
Speed Grade
–1
Speed Grade
STD
Units
None
2.263
2.662
ns
100
2.263
2.662
ns
None
2.241
2.636
ns
100
2.241
2.636
ns
R e visi on 2
1-45
RTG4 FPGA AC/DC Electrical Characteristics
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 83 • LVDS25 Transmitter Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 2.375 V
tDP
LVDS (for MSIO I/O
Bank)
tZL
tZH
tHZ
tLZ
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
3.333
3.921
2.915
3.429
2.898
3.409
3.409
4.010
3.161
3.719
ns
LVDS (for MSIOD I/O Bank)
No pre-emphasis
2.031
2.389
2.295
2.700
2.262
2.661
2.692
3.167
2.518
2.962
ns
Min pre-emphasis
1.949
2.293
2.295
2.700
2.262
2.661
2.692
3.167
2.518
2.962
ns
Med pre-emphasis
1.912
2.249
2.295
2.700
2.262
2.661
2.692
3.167
2.518
2.962
ns
7.8.1.3 LVDS33 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 84 • LVDS33 Receiver Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 3.15 V
tPY
On Die Termination (ODT)
in 
Speed Grade
–1
Speed Grade
STD
Units
None
2.190
2.576
ns
100 
2.190
2.576
ns
LVDS33 (for MSIO I/O
Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 85 • LVDS33 Transmitter Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 3.15 V
tDP
LVDS33 (for MSIO
I/O Bank)
1 -4 6
tZL
tZH
tHZ
tLZ
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
2.978
3.503
2.455
2.888
2.445
2.877
2.917
3.432
2.903
3.415
ns
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
7.8.2 B-LVDS
Bus LVDS (B-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications.
Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers.
7.8.2.1 Minimum and Maximum AC/DC Input and Output Levels Specification
Table 86 • B-LVDS DC Voltage Specification (Applicable to MSIO and MSIOD Banks Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
2.375
2.5
2.625
V
Bus-LVDS Recommended DC Operating Conditions
VDDI
Supply voltage
Bus-LVDS DC Input Voltage Specification
VI
DC input voltage
0
–
2.925
V
IIH (DC)
Input current High
–
–
10
µA
IIL (DC)
Input current Low
–
–
10
µA
Bus-LVDS DC Output Voltage Specification (for MSIO I/O Bank only)
VOH
DC output logic High
1.25
1.425
1.6
V
VOL
DC output logic Low
0.9
1.075
1.25
V
Bus-LVDS Differential Voltage Specification
VOD
Differential output voltage swing
65
–
460
mV
VOCM
Output common mode voltage
1.1
–
1.5
V
VICM
Input common mode voltage
0.05
–
2.4
V
VID
Input differential voltage
0.1
–
VDDI
V
Min
Typ
Max
Units
–
–
500
Mbps
–
–
500
Mbps
–
27
–

Table 87 • B-LVDS AC Specifications (Applicable to MSIO and MSIOD Banks Only)
Symbols
Parameters
Conditions
Bus-LVDS Maximum AC Switching Speed
AC loading: 2 pF / 100 
differential load
Dmax
Maximum data rate
(for MSIO I/O Bank)
Dmax
Maximum Data Rate (for MSIOD AC Loading: 2 pF / 100 
IO Bank)
differential load
Bus-LVDS Impedance Specifications
Rt
Termination resistance
Bus-LVDS AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
Cross
point
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2K
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
R e visi on 2
1-47
RTG4 FPGA AC/DC Electrical Characteristics
7.8.2.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 88 • B-LVDS AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 2.375 V
tPY
On-Die Termination
(ODT) in 
Bus-LVDS (for MSIO I/O Bank)
Bus-LVDS (for MSIOD I/O Bank)
Speed Grade
–1
Speed Grade
STD
Units
None
2.263
2.662
ns
100
2.263
2.662
ns
None
2.241
2.636
ns
100
2.241
2.636
ns
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 89 • B-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 2.375 V
tDP
Bus-LVDS (for
MSIO I/O Bank)
tZL
tZH
tHZ
tLZ
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
3.376
3.972
2.906
3.419
2.886
3.395
3.193
3.757
3.415
4.018
ns
7.8.3 M-LVDS
M-LVDS specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop
and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers.
7.8.3.1 Minimum and Maximum Input and Output Levels
Table 90 • M-LVDS DC Voltage Specification (Applicable to MSIO and MSIOD Banks Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
Notes
2.375
2.5
2.625
V
*
M-LVDS Recommended DC Operating Conditions
VDDI
Supply voltage
M-LVDS DC Input Voltage Specification
VI
DC input voltage
0
–
2.925
V
IIH (DC)
Input current High
–
–
10
µA
IIL (DC)
Input current Low
–
–
10
µA
M-LVDS DC Output Voltage Specification
VOH
DC output logic High
1.25
1.425
1.6
V
VOL
DC output logic Low
0.9
1.075
1.25
V
M-LVDS Differential Voltage Specification
VOD
Differential output voltage Swing
300
–
650
mV
VOCM
Output common mode voltage
0.3
–
2.1
V
VICM
Input common mode voltage
0.3
–
1.2
V
1 -4 8
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 90 • M-LVDS DC Voltage Specification (Applicable to MSIO and MSIOD Banks Only) (continued)
Symbols
VID
Parameters
Conditions
Min
Typ
Max
Units
50
–
2400
mV
Input differential voltage
Notes
Note: *Only M-LVDS TYPE I is supported
Table 91 • M-LVDS AC Specifications (Applicable to MSIO and MSIOD Banks Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
–
–
500
Mbps
–
–
500
Mbps
–
50
–

M-LVDS Maximum AC Switching Speeds
AC loading: 2 pF / 100  differential
load
Dmax
Maximum data rate
(for MSIO I/O Bank)
Dmax
Maximum data rate (for MSIOD AC Loading: 2 pF / 100 differential
IO Bank only)
load
M-LVDS Impedance Specification
Rt
Termination resistance
M-LVDS AC Test Parameters Specifications
VTrip
Measuring/trip point for data path
–
Cross
point
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2K
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
7.8.3.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 92 • M-LVDS AC Switching Characteristics for Receiver (Input Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI= 2.375 V
tPY
On-Die Termination (ODT) in 
M-LVDS (for MSIO I/O Bank)
M-LVDS (for MSIOD I/O Bank)
Speed Grade
–1
Speed Grade
STD
Units
None
2.263
2.662
ns
100
2.263
2.662
ns
None
2.241
2.636
ns
100
2.241
2.636
ns
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 93 • M-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI= 2.375 V
tDP
M-LVDS (for
MSIO I/O Bank)
tZL
tZH
tHZ
tLZ
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
3.376
3.972
2.906
3.419
2.886
3.395
3.439
4.046
3.182
3.744
ns
R e visi on 2
1-49
RTG4 FPGA AC/DC Electrical Characteristics
7.8.4 Mini-LVDS
Mini-LVDS is an unidirectional interface from the timing controller to the column drivers and is designed to the Texas
Instruments Standard SLDA007A.
7.8.4.1 Mini-LVDS Minimum and Maximum Input and Output Levels
Table 94 • Mini-LVDS DC Voltage Specification (Applicable to MSIO and MSIOD Banks Only)
Symbols
Parameters
Min
Typ
Max
Units
2.375
2.5
2.625
V
0
–
2.925
V
Recommended DC Operating Conditions
VDDI
Supply voltage
Mini-LVDS DC Input Voltage Specification
VI
DC Input voltage
Mini-LVDS DC Output Voltage Specification
VOH
DC output logic High
1.25
1.425
1.6
V
VOL
DC output logic Low
0.9
1.075
1.25
V
300
–
600
mV
1
–
1.4
V
Mini-LVDS Differential Voltage Specification
VOD
Differential output voltage swing
VOCM
Output common mode voltage
VICM
Input common mode voltage
0.3
–
1.2
V
VID
Input differential voltage
100
–
600
mV
Table 95 • Mini-LVDS AC Specifications (Applicable to MSIO and MSIOD Banks Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
Mini-LVDS Maximum AC Switching Speed
Dmax
Maximum data rate (MSIO I/O Bank)
AC loading: 2 pF / 100 
differential load
–
–
520
Mbps
Dmax
Maximum data rate (MSIOD I/O Bank)
AC loading: 10 pF / 100 
differential load
–
–
700
Mbps
–
100
–

Mini-LVDS Impedance Specification
Rt
Termination resistance
Mini-LVDS AC Test Parameters Specifications
VTrip
Measuring/trip point for data path
–
Cross
point
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2K
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
1 -5 0
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
7.8.4.2. AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 96 • Mini-LVDS AC Switching Characteristics for Receiver (Input Buffers)
Worst-case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI= 2.375 V
tPY
On-Die Termination (ODT)
in 
Speed Grade
–1
Speed Grade
STD
Units
None
2.263
2.662
ns
100
2.263
2.662
ns
None
2.241
2.636
ns
100
2.241
2.636
ns
Mini-LVDS (for MSIO I/O Bank)
Mini-LVDS (for MSIOD I/O Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 97 • Mini-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI= 2.375 V
tDP
tZL
tZH
tHZ
tLZ
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
Mini-LVDS (for
MSIO I/O Bank)
3.358
3.950
2.902
3.414
2.887
3.396
3.417
4.020
3.170
3.729
ns
Mini-LVDS (for
MSIOD I/O Bank)
2.019
2.375
2.190
2.577
2.171
2.554
2.695
3.170
2.518
2.962
ns
7.8.5 RSDS
Reduced Swing Differential Signaling (RSDS) is similar to an LVDS high-speed interface using differential signaling.
RSDS has a similar implementation to LVDS devices and is only intended for point-to-point applications.
7.8.5.1 Minimum and Maximum Input and Output Levels
Table 98 • RSDS DC Voltage Specification (Applicable to MSIO and MSIOD Banks Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
2.375
2.5
2.625
V
0
–
2.925
V
Recommended DC Operating Conditions
VDDI
Supply voltage
RSDS DC Input Voltage Specification
VI
DC input voltage
RSDS DC Output Voltage Specification
VOH
DC output logic High
1.25
1.425
1.6
V
VOL
DC output logic Low
0.9
1.075
1.25
V
RSDS Differential Voltage Specification
VOD
Differential output voltage swing
100
–
600
mV
VOCM
Output common mode voltage
0.5
–
1.5
V
VICM
Input common mode voltage
0.3
–
1.5
V
VID
Input differential voltage
100
–
600
mV
R e visi on 2
1-51
RTG4 FPGA AC/DC Electrical Characteristics
Table 99 • RSDS AC Specifications (Applicable to MSIO and MSIOD Banks Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
RSDS Maximum AC Switching Speed
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC loading: 2 pF / 100 
differential load
–
–
520
Mbps
Dmax
Maximum data rate
(for MSIOD I/O Bank)
AC loading: 10 pF / 100 
differential load
–
–
700
Mbps
–
100
–

RSDS Impedance Specification
Rt
Termination resistance
RSDS AC Test Parameters Specifications
VTrip
Measuring/trip point for data path
–
Cross
point
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2K
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
7.8.5.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 100 • RSDS AC Switching Characteristics for Receiver (Input Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 2.375 V
tPY
On-Die Termination (ODT) in 
Speed Grade
–1
Speed Grade
STD
Units
None
2.263
2.662
ns
100
2.263
2.662
ns
None
2.241
2.636
ns
100
2.241
2.636
ns
RSDS (for MSIO I/O Bank)
RSDS (for MSIOD I/O Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 101 • RSDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 2.375 V
tDP
RSDS (for MSIO I/O
Bank)
tZL
tZH
tHZ
tLZ
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Speed
Grade
–1
Speed
Grade
STD
Units
3.358
3.950
2.959
3.481
2.940
3.459
3.402
4.002
3.152
3.708
ns
RSDS (for MSIOD I/O Bank)
No pre-emphasis
2.077
2.444
2.056
2.419
2.041
2.401
1.915
2.253
1.992
2.344
ns
Min pre-emphasis
2.031
2.389
2.295
2.700
2.262
2.661
2.519
2.963
2.671
3.142
ns
Med pre-emphasis
1.949
2.293
2.295
2.700
2.262
2.661
2.519
2.963
2.671
3.142
ns
Max pre-emphasis
1.912
2.249
2.295
2.700
2.262
2.661
2.519
2.963
2.671
3.142
ns
1 -5 2
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
7.8.6 LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit
be carried through two signal lines. Similar to LVDS, two pins are needed. It also requires external resistor termination.
RTG4 FPGAs support only LVPECL receivers and do not support LVPECL transmitters.
7.8.6.1 Minimum and Maximum Input and Output Levels
Table 102 • LVPECL DC Voltage Specification (Applicable to MSIO I/O Banks Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
3.15
3.3
3.45
V
0
–
3.45
V
2.8
V
300
1,000
mV
Min
Typ
Max
Units
–
–
750
Mbps
Recommended DC Operating Conditions
VDDI
Supply voltage
LVPECL DC Input Voltage Specification
VI
DC input voltage
LVPECL Differential Voltage Specification
VICM
Input common mode voltage
0.3
VIDIFF
Input differential voltage
100
Table 103 • LVPECL Maximum AC Switching Speeds (Applicable to MSIO I/O Banks Only)
Symbols
Parameters
Conditions
LVPECL AC Specifications
Fmax
Maximum data rate (for MSIO I/O Bank)
7.8.6.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 104 • LVPECL Receiver Characteristics
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 3.15 V
tPY
LVPECL (for MSIO I/O Bank)
On-Die Termination (ODT) in

Speed Grade
–1
Speed Grade
STD
Units
None
2.263
2.662
ns
100
2.263
2.662
ns
R e visi on 2
1-53
RTG4 FPGA AC/DC Electrical Characteristics
7.9. I/O Register Specifications
7.9.1 Input Register
)
'
*
$
'
%
(1
,QSXW,2%XIIHU
&
$/Q
4
4
(1
$/Q
$'Q
$'Q
'
6/Q
)OLS)ORS
6/Q
6'
6'
(
&/.
&/.
Figure 4 • Timing Model for Input Register
W,&.03:/
W,&.03:+
&/.
W,68'
'
W,+'
$'Q
6'
W,686/Q
6/Q
W,5(0$/Q
W,:$/Q
$/Q
W,68(
W,5(&$/Q
W,+(
(1
W,$/Q4
4
W,&/.4
Figure 5 • I/O Register Input Timing Diagram
1 -5 4
R ev i si o n 2
W,+6/Q
DS0131: RTG4 FPGA Datasheet
Table 105 • Input Data Register Propagation Delays
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Description
Speed Grade
–1
Speed Grade
STD
Measuring
Nodes
(from, to)*
SET
Filter
OFF
SET
Filter
ON
SET
Filter
OFF
SET
Filter
ON
Units
tICLKQ
Clock-to-Q of the Input Register
E,G
0.217
0.217
0.256
0.256
ns
tISUD
Data Setup Time for the Input Register
A,E
0.72
1.663
0.847
1.79
ns
tIHD
Data Hold Time for the Input Register
A,E
-0.109
0.552
-0.128
0.533
ns
tISUE
Enable Setup Time for the Input Register
B,E
0.964
0.964
1.134
1.134
ns
tIHE
Enable Hold Time for the Input Register
B,E
-0.296
-0.296
-0.348
-0.348
ns
tISUSL
Synchronous Load Setup Time for the Input Register
D,E
0.823
0.823
0.968
0.968
ns
tIHSL
Synchronous Load Hold Time for the Input Register
D,E
-0.17
-0.17
-0.2
-0.2
ns
Asynchronous Clear-to-Q of the Input Register
(ADn=1)
C,G
1.103
1.103
1.298
1.298
ns
Asynchronous Preset-to-Q of the Input Register
(ADn=0)
C,G
1.104
1.104
1.299
1.299
ns
tIREMALn
Asynchronous Load Removal Time for the Input
Register
C,E
-0.237
-0.237
-0.278
-0.278
ns
tIRECALn
Asynchronous Load Recovery Time for the Input
Register
C,E
0.38
0.38
0.447
0.447
ns
tIWALn
Asynchronous Load Minimum Pulse Width for the
Input Register
C,C
0.825
0.825
0.971
0.971
ns
tICKMPWH
Clock Minimum Pulse Width High for the Input
Register
E,E
0.24
0.24
0.282
0.282
ns
tICKMPWL
Clock Minimum Pulse Width Low for the Input
Register
E,E
0.155
0.155
0.183
0.183
ns
tIALn2Q
R e visi on 2
1-55
RTG4 FPGA AC/DC Electrical Characteristics
7.9.2 Output/Enable Register
$
)
'
'
%
$/Q
&
$'Q
'
6/Q
'
)OLS)ORS
6'
6'
&/.
4
$/Q
$'Q
6/Q
*
(1
(1
(
-
&/.
+
,
'
4
(1
$/Q
$'Q
)OLS)ORS
6/Q
6'
&/.
2XWSXW(QDEOH5HJLVWHUV
Figure 6 • Timing Model for Output/Enable Register
1 -5 6
R ev i si o n 2
2XWSXW,2%XIIHUZLWK(QDEOH&RQWURO
DS0131: RTG4 FPGA Datasheet
W2&.03:/
W2&.03:+
W2+'(
&ON
W268(
W2+'
W268'
'
$'Q
6'
W2686/Q
W2+'6/Q
6/Q
(1
W25(0$/Q
$/Q
W25(&$/Q
W2$/Q4
2XW
C
W2&/.4
Figure 7 • I/O Register Output Timing Diagram
Table 106 • Output/Enable Data Register Propagation Delays
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Speed Grade
STD
Measuring
Nodes
(from, to)*
SET
Filter
OFF
SET
Filter
ON
SET
Filter
OFF
SET
Filter
ON
Units
tOCLKQ
Clock-to-Q of the Output/Enable Register
E,G or E,I
0.316
0.316
0.371
0.371
ns
tOSUD
Data Setup Time for the Output/Enable Register
A,E or J,E
0.619
1.562
0.728
1.671
ns
tOHD
Data Hold Time for the Output/Enable Register
A,E or J,E
-0.135
0.526
-0.159
0.502
ns
tOSUE
Enable Setup Time for the Output/Enable
Register
B,E
0.974
0.974
1.145
1.145
ns
tOHE
Enable Hold Time for the Output/Enable
Register
B,E
-0.290
-0.290
-0.342
-0.342
ns
tOSUSL
Synchronous Load Setup Time for the
Output/Enable Register
D,E
0.827
0.827
0.973
0.973
ns
tOHSL
Synchronous Load Hold Time for the
Output/Enable Register
D,E
-0.165
-0.165
-0.195
-0.195
ns
Asynchronous Clear-to-Q of the Output/Enable
Register (ADn=1)
C,G or C,I
1.165
1.165
1.371
1.371
ns
Asynchronous Preset-to-Q of the Output/Enable
Register (ADn=0)
C,G or C,I
1.198
1.198
1.410
1.410
ns
tOALn2Q
R e visi on 2
1-57
RTG4 FPGA AC/DC Electrical Characteristics
Table 106 • Output/Enable Data Register Propagation Delays
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Speed Grade
STD
Measuring
Nodes
(from, to)*
SET
Filter
OFF
SET
Filter
ON
SET
Filter
OFF
SET
Filter
ON
Units
tOREMALn
Asynchronous Load Removal Time for the
Output/Enable Register
C,E
-0.233
-0.233
-0.275
-0.275
ns
tORECALn
Asynchronous Load Recovery Time for the
Output/Enable Register
C,E
0.448
0.448
0.527
0.527
ns
tOWALn
Asynchronous Load Minimum Pulse Width for
the Output/Enable Register
C,C
0.700
0.700
0.823
0.823
ns
tOCKMPWH
Clock Minimum Pulse Width High for the
Output/Enable Register
E,E
0.247
0.247
0.29
0.29
ns
tOCKMPWL
Clock Minimum Pulse Width Low for the
Output/Enable Register
E,E
0.137
0.137
0.161
0.161
ns
1 -5 8
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
7.10. DDR Module Specification
7.10.1 Input DDR Module
'
(1
$/Q
$
)
$/Q
$'Q
*
6/Q
)OLS)ORS
6'
6'
&/.
45
4
(1
$'Q
6/Q
&
'
(
%
&/.
'
$/Q
$'Q
4
'
'
4
(1
/DWFK
4)
$/Q
$'Q
6/Q
&/.
)OLS)ORS
6'
&/.
''5B,1
Figure 8 • Input DDR Module
R e visi on 2
1-59
RTG4 FPGA AC/DC Electrical Characteristics
7.10.2 Input DDR Timing Diagram
W''5,&.03:/
W''5,&.03:+
&/.
W''5,68'
'
W''5,+'
$'Q
6'
W''5,686/Q
6/Q
W''5,:$/
W''5,+(
$/Q
W''5,5(0$/
W''5,5(&$/
W''5,68(
(1
W''5,$/4
45
W''5,&/.4
W''5,$/4
4)
W''5,&/.4
Figure 9 • Input DDR Timing Diagram
1 -6 0
R ev i si o n 2
W''5,+6/Q
DS0131: RTG4 FPGA Datasheet
7.10.3 Timing Characteristics
Table 107 • Input DDR Propagation Delays
Worst-Case Military Conditions: TJ = 125°C, VDD=1.14 V
Speed Grade
–1
Speed Grade
STD
Parameter
Description
Measuring
Nodes
(from, to)
tDDRICLKQ1
Clock-to-Out Out_QR for Input DDR
B,C
0.217
0.217
0.256
0.256
ns
tDDRICLKQ2
Clock-to-Out Out_QF for Input DDR
B,D
0.214
0.214
0.252
0.252
ns
tDDRISUD
Data Setup for Input DDR
A,B
0.72
1.663
0.847
1.79
ns
tDDRIHD
Data Hold for Input DDR
A,B
-0.109
0.552
-0.128
0.533
ns
tDDRISUE
Enable Setup for Input DDR
E,B
0.964
0.964
1.134
1.134
ns
tDDRIHE
Enable Hold for Input DDR
E,B
-0.296
-0.296
-0.348
-0.348
ns
tDDRISUSLn
Synchronous Load Setup for Input
DDR
G,B
0.823
0.823
0.968
0.968
ns
tDDRIHSLn
Synchronous Load Hold for Input
DDR
G,B
-0.17
-0.17
-0.2
-0.2
ns
Asynchronous Clear-to-Out QR for
Input DDR (ADn=1)
F,C
1.103
1.103
1.298
1.298
ns
Asynchronous Preset-to-Out QR for
Input DDR (ADn=0)
F,C
1.104
1.104
1.299
1.299
ns
Asynchronous Clear-to-Out QF for
Input DDR (ADn=1)
F,D
1.093
1.093
1.286
1.286
ns
Asynchronous Preset-to-Out QF for
Input DDR (ADn=0)
F,D
1.097
1.097
1.29
1.29
ns
tDDRIREMAL
Asynchronous Load Removal time
for Input DDR
F,B
-0.237
-0.237
-0.278
-0.278
ns
tDDRIRECAL
Asynchronous Load Recovery time
for Input DDR
F,B
0.38
0.38
0.447
0.447
ns
tDDRIWAL
Asynchronous Load Minimum Pulse
Width for Input DDR
F,F
0.825
0.825
0.971
0.971
ns
tDDRICKMPWH
Clock Minimum Pulse Width High for
Input DDR
B,B
0.24
0.24
0.282
0.282
ns
tDDRICKMPWL
Clock Minimum Pulse Width Low for
Input DDR
B,B
0.155
0.155
0.183
0.183
ns
tDDRIAL2Q1
tDDRIAL2Q2
R e visi on 2
SET Filter
OFF
SET Filter
ON
SET Filter
OFF
SET Filter
ON
Units
1-61
RTG4 FPGA AC/DC Electrical Characteristics
7.10.4 Output DDR Module
$
'
'5
%
(1
$/Q
&
'
')
$/Q
6/Q
)OLS)ORS
6'
6'
&/.
(1
(
*
4
&/.
)
'
4)
4
(1
$/Q
$'Q
)OLS)ORS
6/Q
6'
&/.
''5 B 287
Figure 10 • Output DDR Module
1 -6 2
45
$'Q
$'Q
6/Q
4
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
W''5268(
W''52&.03:/
W''52&.03:+
&ON
W''52+'(
W''52+'5
W''5268'5
'5
W''5268')
W''52+')
')
$'Q
6'
W''52686/Q
W''52+'6/Q
6/Q
(1
W''52:$/
W''525(0$/
$/Q
W''525(&$/
C
W''52&/.4
W''52$/4
2XW
Figure 11 • Output DDR Timing Diagram
R e visi on 2
1-63
RTG4 FPGA AC/DC Electrical Characteristics
7.10.5 Timing Characteristics
Table 108 • Output DDR Propagation Delays
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Speed Grade
STD
Measuring
Nodes
(from, to)
SET Filter
OFF
SET Filter
ON
SET Filter
OFF
SET Filter
ON
Units
Parameter
Description
tDDROCLKQ
Clock-to-Out of DDR for Output
DDR
E,G
0.272
0.272
0.32
0.32
ns
tDDROSUDF
DF Data Setup for Output DDR
F,E
0.148
1.091
0.174
1.117
ns
tDDROSUDR
DR Data Setup for Output DDR
A,E
0.196
1.139
0.23
1.173
ns
tDDROHDF
DF Data Hold for Output DDR
F,E
0
0.661
0
0.661
ns
tDDROHDR
DR Data Hold for Output DDR
A,E
0
0.661
0
0.661
ns
tDDROSUE
Enable Setup for Output DDR
B,E
0.433
0.433
0.509
0.509
ns
tDDROHE
Enable Hold for Output DDR
B,E
0
0
0
0
ns
tDDROSUSLn
Synchronous Load Setup for
Output DDR
D,E
0.203
0.203
0.238
0.238
ns
tDDROHSLn
Synchronous Load Hold for
Output DDR
D,E
0
0
0
0
ns
Asynchronous Clear-to-Out for
Output DDR (ADn=1)
C,G
0.523
0.523
0.615
0.615
ns
Asynchronous Preset-to-Out for
Output DDR (ADn=0)
C,G
0.545
0.545
0.641
0.641
ns
tDDROREMAL
Asynchronous Load Removal
time for Output DDR
C,E
0
0
0
0
ns
tDDRORECAL
Asynchronous Load Recovery
time for Output DDR
C,E
0.035
0.035
0.041
0.041
ns
tDDROWAL
Asynchronous Load Minimum
Pulse Width for Output DDR
C,C
0.700
0.700
0.823
0.823
ns
tDDROCKMPWH
Clock Minimum Pulse Width
High for the Output DDR
E,E
0.078
0.078
0.091
0.091
ns
tDDROCKMPWL
Clock Minimum Pulse Width
Low for the Output DDR
E,E
0.164
0.164
0.193
0.193
ns
tDDROAL2Q
1 -6 4
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
8. Logic Element Specifications
8.1 LUT4
The RTG4 FPGAs offer a fully permutable 4-input LUT. In this section, timing characteristics are presented for a
sample of the library. For more details, refer to the RTG4 Macro Library Guide.
tPD
A
PAD
B
PAD
AND4 OR
Any
Combinational
Logic
C
PAD
PAD
D/S (where
applicable)
PAD
VDD
A, B, C, D, S
Y
50%
tPD = Max(tPD(RR), tPD(RF), tPD(FF), tPD(FR))
50%
where edges are applicable for the particular
combinatorial cell
GND
VDD
50%
50%
OUT
GND
VDD
tPD
tPD
(RR)
(FF)
tPD
OUT
tPD
(RF)
(FR)
50%
50%
GND
Figure 12 • LUT4
8.1.1 Timing Characteristics
Table 109 • Combinatorial Cell Propagation Delays
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Combinatorial Cell
Equation
Parameter
Speed Grade
–1
Speed Grade
STD
Units
INV
Y = !A
tPD
0.113
0.133
ns
AND2
Y=A·B
tPD
0.207
0.244
ns
NAND2
Y = !(A · B)
tPD
0.171
0.201
ns
OR2
Y=A+B
tPD
0.207
0.244
ns
NOR2
Y = !(A + B)
tPD
0.171
0.201
ns
XOR2
Y=AB
tPD
0.207
0.244
ns
XOR3
Y=ABC
tPD
0.368
0.433
ns
AND3
Y=A·B·C
tPD
0.368
0.433
ns
AND4
Y=A·B·C·D
tPD
0.492
0.579
ns
R e visi on 2
1-65
RTG4 FPGA AC/DC Electrical Characteristics
8.2 Sequential Module
RTG4 FPGAs offer a separate flip-flop which can be used independently from the LUT. The flip-flop has a data input
and optional enable, synchronous load (clear or preset), and asynchronous load (clear or preset).
'
4
(1
$/Q
$'Q
)OLS)ORS
6/Q
6'
&/.
Figure 13 • Sequential Module
Figure 14 shows a configuration with SD = 0 (synchronous clear) and ADn = 1 (asynchronous clear) for a flip-flop.
W&.03:+
&/.
W68'
'
W&.03:/
W+'
6'
$'Q
(
W686/
W+6/
W68( W+(
6/Q
W5(0$/Q
$/Q
W:$/Q
W5(&$/Q
W$/Q4
4
W&/.4
Figure 14 • Sequential Module Timing Diagram
1 -6 6
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
8.2.1 Timing Characteristics
Table 110 • Register Delays
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Speed Grade
STD
SET Filter
OFF
SET Filter
ON
SET Filter
OFF
SET Filter
ON
Units
tCLKQ
Clock-to-Q of the Core Register
0.341
0.341
0.401
0.401
ns
tSUD
Data Setup Time for the Core Register
0.312
1.255
0.367
1.31
ns
tHD
Data Hold Time for the Core Register
-0.053
0.608
-0.062
0.599
ns
tSUE
Enable Setup Time for the Core Register
0.595
0.595
0.7
0.7
ns
tHE
Enable Hold Time for the Core Register
-0.434
-0.434
-0.51
-0.51
ns
tSUSL
Synchronous Load Setup Time for the Core Register
0.621
0.621
0.73
0.73
ns
tHSL
Synchronous Load Hold Time for the Core Register
-0.267
-0.267
-0.314
-0.314
ns
Asynchronous Clear-to-Q of the Core Register
(ADn=1)
1.153
1.153
1.357
1.357
ns
Asynchronous Preset-to-Q of the Core Register
(ADn=0)
1.213
1.213
1.426
1.426
ns
tREMALn
Asynchronous Load Removal Time for the Core
Register
-0.514
-0.514
-0.604
-0.604
ns
tRECALn
Asynchronous Load Recovery Time for the Core
Register
0.403
0.403
0.474
0.474
ns
tWALn
Asynchronous Load Minimum Pulse Width for the
Core Register
0.832
0.832
0.979
0.979
ns
tCKMPWH
Clock Minimum Pulse Width High for the Core
Register
0.213
0.213
0.251
0.251
ns
tCKMPWL
Clock Minimum Pulse Width Low for the Core
Register
0.148
0.148
0.175
0.175
ns
tALn2Q
9. Global Resource Characteristics
The RTG4 FPGA devices offer a powerful, low skew global routing network which provides an effective clock
distribution throughout the FPGA fabric. Refer to the RTG4 FPGA Fabric User Guide for the positions of various global
routing resources.
Table 111 • RT4G150 Device Global Resource
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Speed Grade
STD
Min
Max
Min
Max
Units
tRCKL
Input Low Delay for Global Clock
1.637
1.644
1.926
1.934
ns
tRCKH
Input High Delay for Global Clock
2.151
2.161
2.531
2.543
ns
tRCKSW
Maximum Skew for Global Clock
0.012
ns
0.010
R e visi on 2
1-67
RTG4 FPGA AC/DC Electrical Characteristics
10. FPGA Fabric SRAM
Refer to the UG0574: RTG4 FPGA Fabric User Guide for more information.
10.1 FPGA Fabric Large SRAM (LSRAM) Table 112 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 1Kx18
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Speed Grade
STD
SET Filter
OFF
SET Filter
ON
SET Filter
OFF
SET Filter
ON
Units
tCY
Clock Period with all pipelines enabled
4.514
4.514
5.311
5.311
ns
tCLKMPWH
Clock Minimum Pulse Width High
0.613
0.613
0.721
0.721
ns
tCLKMPWL
Clock Minimum pulse Width Low
0.393
0.393
0.463
0.463
ns
Address Setup Time (ECC = OFF or
ECC = BYPASS)
1.63
2.573
1.917
2.86
ns
Address Setup Time (ECC = PIPELINE)
1.743
2.686
2.051
2.994
ns
Address Hold Time (ECC = OFF or
ECC = BYPASS)
-0.021
0.64
-0.025
0.636
ns
Address Hold Time (ECC = PIPELINE)
-0.495
0.166
-0.582
0.079
ns
tDSU
Data Setup Time
1.951
2.894
2.295
3.238
ns
tDHD
Data Hold Time
0.000
0.661
0.000
0.661
ns
Block Select Setup Time (ECC = OFF or ECC
= BYPASS)
1.909
2.852
2.246
3.189
ns
Block Select Setup Time
(ECC = PIPELINE)
1.619
2.562
1.905
2.848
ns
Block Select Hold Time (ECC = OFF or ECC =
BYPASS)
-0.675
-0.014
-0.794
-0.133
ns
Block Select Hold Time
(ECC = PIPELINE)
-0.675
-0.014
-0.794
-0.133
ns
tADDRSU
tADDRHD
tBLKSU
tBLKHD
tRDENPIPESU
Pipelined Read Enable Setup Time
(A_DOUT_EN, B_DOUT_EN)
1.15
2.093
1.353
2.296
ns
tRDENPIPEHD
Pipelined Read Enable Hold Time
(A_DOUT_EN, B_DOUT_EN)
-0.089
0.572
-0.105
0.556
ns
tRSTREM
Asynchronous Reset Removal Time
0.694
1.355
0.817
1.478
ns
tRSTREC
Asynchronous Reset Recovery Time
-0.591
0.352
-0.695
0.248
ns
tRSTMPW
Asynchronous Reset Minimum Pulse Width
0.324
0.324
0.381
0.381
ns
tSRSTSU
Synchronous Reset Setup Time
2.424
3.367
2.852
3.795
ns
tSRSTHD
Synchronous Reset Hold Time
-1.009
-0.348
-1.187
-0.526
ns
tRDESU
Read Enable Setup Time
1.059
2.002
1.246
2.189
ns
tRDEHD
Read Enable Hold Time
-0.018
0.643
-0.022
0.639
ns
1 -6 8
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 112 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 1Kx18
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Speed Grade
STD
SET Filter
OFF
SET Filter
ON
SET Filter
OFF
SET Filter
ON
Units
Write Enable Setup Time with Simple write
mode (ECC = OFF or
ECC = BYPASS)
1.007
1.95
1.185
2.128
ns
Write Enable Setup Time with Read Before
Write mode (ECC = OFF or
ECC = BYPASS)
1.344
2.287
1.581
2.524
ns
Write Enable Setup Time with Feed Through
mode (ECC = OFF or
ECC = BYPASS)
1.336
2.279
1.572
2.515
ns
Write Enable Setup Time with
ECC = PIPELINE
1.468
2.411
1.727
2.67
ns
Write Enable Hold Time with Simple write
mode (ECC = OFF or ECC = BYPASS)
0.03
0.691
0.035
0.696
ns
Write Enable Hold Time with Read Before
Write mode (ECC = OFF or
ECC = BYPASS)
0.103
0.764
0.121
0.782
ns
Write Enable Hold Time with Feed Through
mode (ECC = OFF or
ECC = BYPASS)
0.102
0.763
0.12
0.781
ns
Write Enable Hold Time with
ECC = PIPELINE
0.030
0.691
0.035
0.696
ns
Read Access Time with OUTPUT=PIPELINE
2.31
2.31
2.718
2.718
ns
Read Access Time with ECC=OFF,
OUTPUT=BYPASS
5.968
5.968
7.021
7.021
ns
Read Access Time with ECC=BYPASS,
OUTPUT=BYPASS
6.176
6.176
7.266
7.266
ns
Read Access Time with ECC=PIPELINE,
OUTPUT=BYPASS
4.365
4.365
5.135
5.135
ns
tR2Q
Asynchronous Reset to Output Propagation
Delay
1.953
1.953
2.297
2.297
ns
Fmax
Maximum Frequency with all pipelines enabled
300
250
300
250
MHz
Parameter
tWESU
tWEHD
tCLK2Q
Description
R e visi on 2
1-69
RTG4 FPGA AC/DC Electrical Characteristics
Table 113 • RAM1K18 - Dual-Port Mode for Depth x Width Configuration 2Kx12
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Speed Grade
STD
SET Filter
OFF
SET Filter
ON
SET Filter
OFF
SET Filter
ON
Units
tCY
Clock Period with all pipelines enabled
4.514
4.514
5.311
5.311
ns
tCLKMPWH
Clock Minimum Pulse Width High
0.613
0.613
0.721
0.721
ns
tCLKMPWL
Clock Minimum pulse Width Low
0.393
0.393
0.463
0.463
ns
tADDRSU
Address Setup Time
1.63
2.573
1.917
2.86
ns
tADDRHD
Address Hold Time
-0.021
0.64
-0.025
0.636
ns
tDSU
Data Setup Time
1.951
2.894
2.295
3.238
ns
tDHD
Data Hold Time
0.000
0.661
0.000
0.661
ns
tBLKSU
Block Select Setup Time
1.909
2.852
2.246
3.189
ns
tBLKHD
Block Select Hold Time
-0.675
-0.014
-0.794
-0.133
ns
tRDENPIPESU
Pipelined Read Enable Setup Time
(A_DOUT_EN, B_DOUT_EN)
1.15
2.093
1.353
2.296
ns
tRDENPIPEHD
Pipelined Read Enable Hold Time (A_DOUT_EN,
B_DOUT_EN)
-0.089
0.572
-0.105
0.556
ns
tRSTREM
Asynchronous Reset Removal Time
0.694
1.355
0.817
1.478
ns
tRSTREC
Asynchronous Reset Recovery Time
-0.591
0.352
-0.695
0.248
ns
tRSTMPW
Asynchronous Reset Minimum Pulse Width
0.324
0.324
0.381
0.381
ns
tSRSTSU
Synchronous Reset Setup Time
2.424
3.367
2.852
3.795
ns
tSRSTHD
Synchronous Reset Hold Time
-1.009
-0.348
-1.187
-0.526
ns
tRDESU
Read Enable Setup Time
1.059
2.002
1.246
2.189
ns
tRDEHD
Read Enable Hold Time
-0.018
0.643
-0.022
0.639
ns
Write Enable Setup Time in Simple Write mode
1.007
1.95
1.185
2.128
ns
Write Enable Setup Time in Read Before Write
mode
1.344
2.287
1.581
2.524
ns
Write Enable Setup Time in Feed Through mode
1.336
2.279
1.572
2.515
ns
Write Enable Hold Time in Simple Write mode
0.03
0.691
0.035
0.696
ns
Write Enable Hold Time in Read Before Write
mode
0.103
0.764
0.121
0.782
ns
Write Enable Hold Time in Feed Through mode
0.102
0.763
0.12
0.781
ns
Read Access Time with Pipeline Register
2.31
2.31
2.718
2.718
ns
Read Access Time without Pipeline Register
6.022
6.022
7.085
7.085
ns
tR2Q
Asynchronous Reset to Output Propagation
Delay
1.953
1.953
2.297
2.297
ns
Fmax
Maximum Frequency with all pipelines enabled
300
250
300
250
MHz
tWESU
tWEHD
tCLK2Q
1 -7 0
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 114 • RAM1K18 - Dual-Port Mode for Depth x Width Configuration 2Kx9
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Speed Grade
STD
SET
Filter
OFF
SET
Filter ON
SET
Filter
OFF
SET
Filter ON
Units
tCY
Clock Period with all pipelines enabled
4.514
4.514
5.311
5.311
ns
tCLKMPWH
Clock Minimum Pulse Width High
0.613
0.613
0.721
0.721
ns
tCLKMPWL
Clock Minimum pulse Width Low
0.393
0.393
0.463
0.463
ns
tADDRSU
Address Setup Time
1.63
2.573
1.917
2.86
ns
tADDRHD
Address Hold Time
-0.021
0.64
-0.025
0.636
ns
tDSU
Data Setup Time
1.951
2.894
2.295
3.238
ns
tDHD
Data Hold Time
0.000
0.661
0.000
0.661
ns
tBLKSU
Block Select Setup Time
1.909
2.852
2.246
3.189
ns
tBLKHD
Block Select Hold Time
-0.675
-0.014
-0.794
-0.133
ns
tRDENPIPESU
Pipelined Read Enable Setup Time (A_DOUT_EN,
B_DOUT_EN)
1.15
2.093
1.353
2.296
ns
tRDENPIPEHD
Pipelined Read
B_DOUT_EN)
-0.089
0.572
-0.105
0.556
ns
tRSTREM
Asynchronous Reset Removal Time
0.694
1.355
0.817
1.478
ns
tRSTREC
Asynchronous Reset Recovery Time
-0.591
0.352
-0.695
0.248
ns
tRSTMPW
Asynchronous Reset Minimum Pulse Width
0.324
0.324
0.381
0.381
ns
tSRSTSU
Synchronous Reset Setup Time
2.424
3.367
2.852
3.795
ns
tSRSTHD
Synchronous Reset Hold Time
-1.009
-0.348
-1.187
-0.526
ns
tRDESU
Read Enable Setup Time
1.059
2.002
1.246
2.189
ns
tRDEHD
Read Enable Hold Time
-0.018
0.643
-0.022
0.639
ns
Write Enable Setup Time in Simple Write mode
1.007
1.95
1.185
2.128
ns
Write Enable Setup Time in Read Before Write mode
1.344
2.287
1.581
2.524
ns
Write Enable Setup Time in Feed Through mode
1.336
2.279
1.572
2.515
ns
Write Enable Hold Time in Simple Write mode
0.03
0.691
0.035
0.696
ns
Write Enable Hold Time in Read Before Write mode
0.103
0.764
0.121
0.782
ns
Write Enable Hold Time in Feed Through mode
0.102
0.763
0.12
0.781
ns
Read Access Time with Pipeline Register
2.31
2.31
2.718
2.718
ns
Read Access Time without Pipeline Register
5.964
5.964
7.017
7.107
ns
tR2Q
Asynchronous Reset to Output Propagation Delay
1.953
1.953
2.297
2.297
ns
Fmax
Maximum Frequency with all pipelines enabled
300
250
300
250
MHz
tWESU
tWEHD
tCLK2Q
Enable
Hold
Time
(A_DOUT_EN,
R e visi on 2
1-71
RTG4 FPGA AC/DC Electrical Characteristics
Table 115 • RAM1K18 - Two-Port Mode for Depth x Width Configuration 512x36
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Speed Grade
STD
SET
Filter
OFF
SET Filter
ON
SET
Filter
OFF
SET Filter
ON
Units
tCY
Clock Period with all pipelines enabled
4.514
4.514
5.311
5.311
ns
tCLKMPWH
Clock Minimum Pulse Width High
0.613
0.613
0.721
0.721
ns
tCLKMPWL
Clock Minimum pulse Width Low
0.393
0.393
0.463
0.463
ns
Address Setup Time (ECC = OFF or ECC = BYPASS)
1.63
2.573
1.917
2.86
ns
Address Setup Time (ECC = PIPELINE)
1.743
2.686
2.051
2.994
ns
Address Hold Time (ECC = OFF or ECC = BYPASS)
-0.021
0.64
-0.025
0.636
ns
Address Hold Time (ECC = PIPELINE)
-0.495
0.166
-0.582
0.079
ns
tDSU
Data Setup Time
1.951
2.894
2.295
3.238
ns
tDHD
Data Hold Time
-0.601
0.06
-0.707
-0.046
ns
Block Select Setup Time (ECC = OFF or ECC = BYPASS)
1.909
2.852
2.246
3.189
ns
Block Select Setup Time (ECC = PIPELINE)
1.619
2.562
1.905
2.848
ns
Block Select Hold Time (ECC = OFF or ECC = BYPASS)
-0.675
-0.014
-0.794
-0.133
ns
Block Select Hold Time (ECC = PIPELINE)
-0.675
-0.014
-0.794
-0.133
ns
1.15
2.093
1.353
2.296
ns
-0.089
0.572
-0.105
0.556
ns
tADDRSU
tADDRHD
tBLKSU
tBLKHD
tRDPLESU
Pipelined Read
B_DOUT_EN)
Enable
Setup
Time
(A_DOUT_EN,
tRDPLEHD
Pipelined Read
B_DOUT_EN)
Enable
Hold
Time
(A_DOUT_EN,
tRSTREM
Asynchronous Reset Removal Time
0.694
1.355
0.817
1.478
ns
tRSTREC
Asynchronous Reset Recovery Time
-0.591
0.352
-0.695
0.248
ns
tRSTMPW
Asynchronous Reset Minimum Pulse Width
0.324
0.324
0.381
0.381
ns
tSRSTSU
Synchronous Reset Setup Time
2.424
3.367
2.852
3.795
ns
tSRSTHD
Synchronous Reset Hold Time
-1.009
-0.348
-1.187
-0.526
ns
tRDESU
Read Enable Setup Time without ECC pipeline
1.059
2.002
1.246
2.189
ns
tRDEHD
Read Enable Hold Time without ECC pipeline
-0.018
0.643
-0.022
0.639
ns
Write Enable Setup Time (ECC = OFF or
ECC = BYPASS)
1.007
1.950
1.185
2.128
ns
Write Enable Setup Time (ECC = PIPELINE)
1.468
2.411
1.727
2.67
ns
Write Enable Hold Time (ECC = OFF or
ECC = BYPASS)
0.030
0.691
0.035
0.696
ns
Write Enable Setup Time (ECC = PIPELINE)
-0.546
0.115
-0.643
0.018
ns
tWESU
tWEHD
1 -7 2
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 115 • RAM1K18 - Two-Port Mode for Depth x Width Configuration 512x36
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Speed Grade
STD
SET
Filter
OFF
SET Filter
ON
SET
Filter
OFF
SET Filter
ON
Units
Read Access Time with OUTPUT = PIPELINE
2.31
2.31
2.718
2.718
ns
Read Access Time with ECC = OFF,
OUTPUT = BYPASS
5.657
5.657
6.655
6.655
ns
Read Access Time with ECC = BYPASS,
OUTPUT = BYPASS
5.904
5.904
6.945
6.945
ns
Read Access Time with ECC = PIPELINE,
OUTPUT = BYPASS
4.365
4.365
5.135
5.135
ns
tR2Q
Asynchronous Reset to Output Propagation Delay
1.953
1.953
2.297
2.297
ns
Fmax
Maximum Frequency with all pipelines enabled
300
250
300
250
MHz
Parameter
tCLK2Q
Description
10.2 FPGA Fabric Micro SRAM (µSRAM)
Table 116 • µSRAM (RAM64x18) - in 64x18 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Speed Grade
STD
SET
Filter
OFF
SET
Filter ON
SET
Filter
OFF
SET
Filter ON
Units
tCY
Read Clock Period with all pipelines enabled
3.956
3.956
4.654
4.654
ns
tCLKMPWH
Read Clock Minimum Pulse Width High
0.719
0.719
0.846
0.846
ns
tCLKMPWL
Read Clock Minimum pulse Width Low
3.243
3.243
3.815
3.815
ns
Read Address Setup Time with
INPUT = PIPELINE
2.373
3.316
2.792
3.735
ns
Read Address Setup Time with
INPUT = BYPASS, ECC = PIPELINE
4.583
5.526
5.391
6.334
ns
Read Address Setup Time with
INPUT = BYPASS, ECC = OFF,
OUTPUT = PIPELINE
5.097
6.040
5.997
6.940
ns
Read Address Setup Time with
INPUT = BYPASS, ECC = BYPASS,
OUTPUT = PIPELINE
7.115
8.058
8.370
9.313
ns
tADDRSU
R e visi on 2
1-73
RTG4 FPGA AC/DC Electrical Characteristics
Table 116 • µSRAM (RAM64x18) - in 64x18 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Speed Grade
STD
SET
Filter
OFF
SET
Filter ON
SET
Filter
OFF
SET
Filter ON
Units
Read Address Hold Time with
INPUT = PIPELINE
-1.209
-0.548
-1.423
-0.762
ns
Read Address Hold Time with
INPUT = BYPASS, ECC = PIPELINE
-2.908
-2.247
-3.421
-2.760
ns
Read Address Hold Time with
INPUT = BYPASS, ECC = OFF,
OUTPUT = PIPELINE
-2.763
-2.102
-3.250
-2.589
ns
Read Address Hold Time with
INPUT = BYPASS, ECC = BYPASS,
OUTPUT = PIPELINE
-4.373
-3.712
-5.145
-4.484
ns
Read Block Select Setup Time with
INPUT = PIPELINE
1.786
2.729
2.101
3.044
ns
Read Block Select Setup Time with
INPUT = BYPASS, ECC=PIPELINE
2.816
3.759
3.313
4.256
ns
Read Block Select Setup Time with
INPUT = BYPASS, ECC = OFF,
OUTPUT = PIPELINE
2.779
3.722
3.269
4.212
ns
Read Block Select Setup Time with
INPUT = BYPASS, ECC = BYPASS,
OUTPUT = PIPELINE
4.276
5.219
5.030
5.973
ns
Read Block Select Hold Time with
INPUT = PIPELINE
-0.567
0.094
-0.667
-0.006
ns
Read Block Select Hold Time with INPUT = BYPASS,
ECC = PIPELINE
-1.162
-0.501
-1.368
-0.707
ns
Read Block Select Hold Time with
INPUT = BYPASS, ECC = OFF,
OUTPUT = PIPELINE
-1.028
-0.367
-1.210
-0.549
ns
Read Block Select Hold Time with
INPUT = BYPASS, ECC = BYPASS,
OUTPUT = PIPELINE
-2.637
-1.976
-3.102
-2.441
ns
tBLKMPW
Read Block Select Minimum Pulse Width Low
0.459
0.459
0.540
0.540
ns
tRSTREM
Read Asynchronous Reset Removal Time
0.652
0.652
0.767
0.767
ns
tRSTREC
Read Asynchronous Reset Recovery Time
-0.634
-0.634
-0.746
-0.746
ns
tRSTMPW
Asynchronous Reset Minimum Pulse Width
0.459
0.459
0.540
0.540
ns
tRDENADDRSU
Read Address Read Enable Setup Time
(A_ADDR_EN, B_ADDR_EN)
1.295
2.238
1.524
2.467
ns
tRDENADDRHD
Read Address Read Enable Hold Time (A_ADDR_EN,
B_ADDR_EN)
-0.151
0.510
-0.178
0.483
ns
tRDSRSTADDRSU
Read Address Synchronous Reset Setup Time
(A_ADDR_SRST_N, B_ADDR_SRST_N)
1.318
2.261
1.550
2.493
ns
Parameter
tADDRHD
tBLKSU
tBLKHD
1 -7 4
Description
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 116 • µSRAM (RAM64x18) - in 64x18 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Speed Grade
STD
SET
Filter
OFF
SET
Filter ON
SET
Filter
OFF
SET
Filter ON
Units
tRDSRSTADDRHD
Read Address Synchronous Reset Hold Time
(A_ADDR_SRST_N, B_ADDR_SRST_N)
-0.184
0.477
-0.217
0.444
ns
tRDENPIPESU
Pipelined Read Enable Setup Time (A_DOUT_EN,
B_DOUT_EN)
1.241
2.184
1.460
2.403
ns
tRDENPIPEHD
Pipelined Read Enable Hold Time (A_DOUT_EN,
B_DOUT_EN)
-0.106
0.555
-0.125
0.536
ns
tRDSRSTPIPESU
Pipelined Read Synchronous Reset Setup Time
(A_DOUT_SRST_N, B_DOUT_SRST_N)
2.287
3.230
2.691
3.634
ns
tRDSRSTPIPEHD
Pipelined Read Synchronous Reset Hold Time
(A_DOUT_SRST_N, B_DOUT_SRST_N)
-0.975
-0.314
-1.147
-0.486
ns
tCCY
Write Clock Period all pipeline enabled
3.956
3.956
4.654
4.654
ns
tCCLKMPWH
Write Clock Minimum Pulse Width High
0.502
0.502
0.590
0.590
ns
tCCLKMPWL
Write Clock Minimum Pulse Width Low
1.948
1.948
2.292
2.292
ns
Write Block Setup Time (ECC = OFF or ECC =
BYPASS)
1.317
2.260
1.549
2.492
ns
Write Block Setup Time (ECC = PIPELINE)
1.909
2.852
2.246
3.189
ns
Write Block Hold Time (ECC = OFF or ECC =
BYPASS)
-0.216
0.445
-0.254
0.407
ns
Write Block Hold Time (ECC = PIPELINE)
-0.834
-0.173
-0.982
-0.321
ns
tDINCSU
Write Input Data setup Time
1.787
2.730
2.103
3.046
ns
tDINCHD
Write Input Data hold Time
-0.612
0.049
-0.720
-0.059
ns
Write Address Setup Time (ECC = OFF or ECC =
BYPASS)
1.255
2.198
1.476
2.419
ns
Write Address Setup Time (ECC = PIPELINE)
1.941
2.884
2.284
3.227
ns
Write Address Hold Time (ECC = OFF or ECC =
BYPASS)
-0.168
0.493
-0.198
0.463
ns
Write Address Hold Time (ECC = PIPELINE)
-0.788
-0.127
-0.927
-0.266
ns
Write Enable Setup Time (ECC = OFF or ECC =
BYPASS)
1.120
2.063
1.317
2.260
ns
Write Enable Setup Time (ECC = PIPELINE)
1.659
2.602
1.951
2.894
ns
Write Enable Hold Time (ECC = OFF or ECC =
BYPASS)
-0.134
0.527
-0.157
0.504
ns
Write Enable Hold Time (ECC = PIPELINE)
-0.668
-0.007
-0.785
-0.124
ns
tBLKCSU
tBLKCHD
tADDRCSU
tADDRCHD
tWECSU
tWECHD
R e visi on 2
1-75
RTG4 FPGA AC/DC Electrical Characteristics
Table 116 • µSRAM (RAM64x18) - in 64x18 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Speed Grade
STD
SET
Filter
OFF
SET
Filter ON
SET
Filter
OFF
SET
Filter ON
Units
Read Access Time with OUTPUT = PIPELINE
1.980
1.980
2.329
2.329
ns
Read Access Time with ECC = PIPELINE, OUTPUT =
BYPASS
4.899
4.899
5.764
5.764
ns
Read Access Time with INPUT = PIPELINE, ECC =
OFF, OUTPUT = BYPASS
4.754
4.754
5.593
5.593
ns
Read Access Time with INPUT = PIPELINE, ECC =
BYPASS, OUTPUT = BYPASS
7.246
7.246
8.524
8.524
ns
Read Address to Out Data Access time with INPUT =
BYPASS, ECC = OFF,
OUPUT = BYPASS
6.598
6.598
7.762
7.762
ns
Read Address to Out Data Access Time with INPUT =
BYPASS, ECC = BYPASS,
OUPUT = BYPASS
9.007
9.007
10.596
10.596
ns
Read Block Select to Out Disable Time with INPUT =
BYPASS, ECC = OFF,
OUPUT = BYPASS
3.876
3.876
4.560
4.560
ns
Read Block Select to Out Disable Time with INPUT =
BYPASS, ECC = BYPASS,
OUPUT = BYPASS
5.485
5.485
6.452
6.452
ns
tR2Q
Read Asynchronous Reset to Output Propagation
Delay
1.406
1.406
1.655
1.655
ns
Fmax
Maximum Frequency with all pipelines enabled
300
250
300
250
MHz
Parameter
tCLK2Q
tADDR2Q
tBLK2Q
Description
Table 117 • µSRAM (RAM64x18) - in 128x12 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Speed Grade
STD
SET
Filter
OFF
SET
Filter ON
SET
Filter
OFF
SET
Filter ON
Units
tCY
Read Clock Period with all pipelines enabled
3.956
3.956
4.654
4.654
ns
tCLKMPWH
Read Clock Minimum Pulse Width High
0.719
0.719
0.846
0.846
ns
tCLKMPWL
Read Clock Minimum pulse Width Low
3.243
3.243
3.815
3.815
ns
Read Address Setup Time with
INPUT = PIPELINE
3.595
4.538
4.229
5.172
ns
Read Address Setup Time with
INPUT = BYPASS, OUTPUT = PIPELINE
5.097
6.040
5.997
6.940
ns
tADDRSU
1 -7 6
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 117 • µSRAM (RAM64x18) - in 128x12 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Speed Grade
STD
SET
Filter
OFF
SET
Filter ON
SET
Filter
OFF
SET
Filter ON
Units
Read Address Hold Time with
INPUT = PIPELINE
-1.114
-0.453
-1.310
-0.649
ns
Read Address Hold Time with
INPUT = BYPASS, OUTPUT = PIPELINE
-2.763
-2.102
-3.250
-2.589
ns
Read Block Select Setup Time
INPUT = PIPELINE
1.786
2.729
2.101
3.044
ns
Read Block Select Setup Time
INPUT = BYPASS, OUTPUT = PIPELINE
2.779
3.722
3.269
4.212
ns
Read Block Select Hold Time
INPUT = PIPELINE
-0.567
0.094
-0.667
-0.006
ns
Read Block Select Hold Time INPUT = BYPASS,
OUTPUT = PIPELINE
-1.028
-0.367
-1.210
-0.549
ns
tBLKMPW
Read Block Select Minimum Pulse Width Low
0.459
0.459
0.540
0.540
ns
tRSTREM
Read Asynchronous Reset Removal Time
0.652
0.652
0.767
0.767
ns
tRSTREC
Read Asynchronous Reset Recovery Time
-0.634
-0.634
-0.746
-0.746
ns
tRSTMPW
Asynchronous Reset Minimum Pulse Width
0.459
0.459
0.540
0.540
ns
tRDENADDRSU
Read Address Read Enable Setup Time
(A_ADDR_EN, B_ADDR_EN)
1.295
2.238
1.524
2.467
ns
tRDENADDRHD
Read Address Read Enable Hold Time (A_ADDR_EN,
B_ADDR_EN)
-0.151
0.510
-0.178
0.483
ns
tRDSRSTADDRSU
Read Address Synchronous Reset Setup Time
(A_ADDR_SRST_N, B_ADDR_SRST_N)
1.318
2.261
1.550
2.493
ns
tRDSRSTADDRHD
Read Address Synchronous Reset Hold Time
(A_ADDR_SRST_N, B_ADDR_SRST_N)
-0.184
0.477
-0.217
0.444
ns
tRDENPIPESU
Pipelined Read Enable Setup Time (A_DOUT_EN,
B_DOUT_EN)
1.241
2.184
1.460
2.403
ns
tRDENPIPEHD
Pipelined Read Enable Hold Time (A_DOUT_EN,
B_DOUT_EN)
-0.106
0.555
-0.125
0.536
ns
tRDSRSTPIPESU
Pipelined Read Synchronous Reset Setup Time
(A_DOUT_SRST_N, B_DOUT_SRST_N)
2.287
3.230
2.691
3.634
ns
tRDSRSTPIPEHD
Pipelined Read Synchronous Reset Hold Time
(A_DOUT_SRST_N, B_DOUT_SRST_N)
-0.975
-0.314
-1.147
-0.486
ns
tCCY
Write Clock Period all pipeline enabled
3.956
3.956
4.654
4.654
ns
tCCLKMPWH
Write Clock Minimum Pulse Width High
0.502
0.502
0.590
0.590
ns
tCCLKMPWL
Write Clock Minimum Pulse Width Low
1.948
1.948
2.292
2.292
ns
tBLKCSU
Write Block Setup Time
1.317
2.260
1.549
2.492
ns
tBLKCHD
Write Block Hold Time
-0.216
0.445
-0.254
0.407
ns
Parameter
tADDRHD
tBLKSU
tBLKHD
Description
R e visi on 2
1-77
RTG4 FPGA AC/DC Electrical Characteristics
Table 117 • µSRAM (RAM64x18) - in 128x12 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Speed Grade
STD
SET
Filter
OFF
SET
Filter ON
SET
Filter
OFF
SET
Filter ON
Units
tDINCSU
Write Input Data Setup Time
1.787
2.730
2.103
3.046
ns
tDINCHD
Write Input Data Hold Time
-0.656
0.005
-0.772
-0.111
ns
tADDRCSU
Write Address Setup Time
1.255
2.198
1.476
2.419
ns
tADDRCHD
Write Address Hold Time
-0.168
0.493
-0.198
0.463
ns
tWECSU
Write Enable Setup Time
1.120
2.063
1.317
2.260
ns
tWECHD
Write Enable Hold Time
-0.134
0.527
-0.157
0.504
ns
Read Access Time with OUTPUT = PIPELINE
1.980
1.980
2.329
2.329
ns
Read Access Time with INPUT = PIPELINE, OUTPUT
= BYPASS
4.666
4.666
5.490
5.490
ns
tADDR2Q
Read Address to Out Data Access time with INPUT =
BYPASS, OUPUT = BYPASS
6.494
6.494
7.640
7.640
ns
tBLK2Q
Read Block Select to Out Disable Time with INPUT =
BYPASS, OUPUT = BYPASS
3.794
3.794
4.463
4.463
ns
tR2Q
Read Asynchronous Reset to Output Propagation
Delay
1.399
1.399
1.646
1.646
ns
Fmax
Maximum Frequency with all pipelines enabled
300
250
300
250
MHz
tCLK2Q
Table 118 • µSRAM (RAM64x18) - in 128x9 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Speed Grade
STD
SET
Filter
OFF
SET Filter
ON
SET
Filter
OFF
SET Filter
ON
Units
tCY
Read Clock Period with all pipelines enabled
3.956
3.956
4.654
4.654
ns
tCLKMPWH
Read Clock Minimum Pulse Width High
0.719
0.719
0.846
0.846
ns
tCLKMPWL
Read Clock Minimum pulse Width Low
3.243
3.243
3.815
3.815
ns
Read Address Setup Time with
INPUT = PIPELINE
3.595
4.538
4.229
5.172
ns
Read Address Setup Time with
INPUT = BYPASS, OUTPUT = PIPELINE
5.097
6.040
5.997
6.940
ns
Read Address Hold Time with
INPUT = PIPELINE
-1.114
-0.453
-1.310
-0.649
ns
Read Address Hold Time with
INPUT = BYPASS, OUTPUT = PIPELINE
-2.763
-2.102
-3.250
-2.589
ns
tADDRSU
tADDRHD
1 -7 8
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 118 • µSRAM (RAM64x18) - in 128x9 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Speed Grade
STD
SET
Filter
OFF
SET Filter
ON
SET
Filter
OFF
SET Filter
ON
Units
Read Block Select Setup Time
INPUT = PIPELINE
1.786
2.729
2.101
3.044
ns
Read Block Select Setup Time
INPUT = BYPASS, OUTPUT = PIPELINE
2.779
3.722
3.269
4.212
ns
Read Block Select Hold Time
INPUT = PIPELINE
-0.567
0.094
-0.667
-0.006
ns
Read Block Select Hold Time INPUT = BYPASS,
OUTPUT = PIPELINE
-1.028
-0.367
-1.210
-0.549
ns
tBLKMPW
Read Block Select Minimum Pulse Width Low
0.459
0.459
0.540
0.540
ns
tRSTREM
Read Asynchronous Reset Removal Time
0.652
0.652
0.767
0.767
ns
tRSTREC
Read Asynchronous Reset Recovery Time
-0.634
-0.634
-0.746
-0.746
ns
tRSTMPW
Asynchronous Reset Minimum Pulse Width
0.459
0.459
0.540
0.540
ns
tRDENADDRSU
Read Address Read Enable Setup Time
(A_ADDR_EN, B_ADDR_EN)
1.295
2.238
1.524
2.467
ns
tRDENADDRHD
Read Address Read Enable Hold Time (A_ADDR_EN,
B_ADDR_EN)
-0.151
0.510
-0.178
0.483
ns
tRDSRSTADDRSU
Read Address Synchronous Reset Setup Time
(A_ADDR_SRST_N, B_ADDR_SRST_N)
1.318
2.261
1.550
2.493
ns
tRDSRSTADDRHD
Read Address Synchronous Reset Hold Time
(A_ADDR_SRST_N, B_ADDR_SRST_N)
-0.184
0.477
-0.217
0.444
ns
tRDENPIPESU
Pipelined Read Enable Setup Time (A_DOUT_EN,
B_DOUT_EN)
1.241
2.184
1.460
2.403
ns
tRDENPIPEHD
Pipelined Read Enable Hold Time (A_DOUT_EN,
B_DOUT_EN)
-0.106
0.555
-0.125
0.536
ns
tRDSRSTPIPESU
Pipelined Read Synchronous Reset Setup Time
(A_DOUT_SRST_N, B_DOUT_SRST_N)
2.287
3.230
2.691
3.634
ns
tRDSRSTPIPEHD
Pipelined Read Synchronous Reset Hold Time
(A_DOUT_SRST_N, B_DOUT_SRST_N)
-0.975
-0.314
-1.147
-0.486
ns
tCCY
Write Clock Period all pipeline enabled
3.956
3.956
4.654
4.654
ns
tCCLKMPWH
Write Clock Minimum Pulse Width High
0.502
0.502
0.590
0.590
ns
tCCLKMPWL
Write Clock Minimum Pulse Width Low
1.948
1.948
2.292
2.292
ns
tBLKCSU
Write Block Setup Time
1.317
2.260
1.549
2.492
ns
tBLKCHD
Write Block Hold Time
-0.216
0.445
-0.254
0.407
ns
tDINCSU
Write Input Data Setup Time
1.787
2.730
2.103
3.046
ns
tDINCHD
Write Input Data Hold Time
-0.656
0.005
-0.772
-0.111
ns
tADDRCSU
Write Address Setup Time
1.255
2.198
1.476
2.419
ns
tADDRCHD
Write Address Hold Time
-0.168
0.493
-0.198
0.463
ns
Parameter
tBLKSU
tBLKHD
Description
R e visi on 2
1-79
RTG4 FPGA AC/DC Electrical Characteristics
Table 118 • µSRAM (RAM64x18) - in 128x9 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Speed Grade
STD
SET
Filter
OFF
SET Filter
ON
SET
Filter
OFF
SET Filter
ON
Units
tWECSU
Write Enable Setup Time
1.120
2.063
1.317
2.260
ns
tWECHD
Write Enable Hold Time
-0.134
0.527
-0.157
0.504
ns
Read Access Time with OUTPUT = PIPELINE
1.980
1.980
2.329
2.329
ns
Read Access Time with INPUT = PIPELINE, OUTPUT
= BYPASS
4.653
4.653
5.474
5.474
ns
tADDR2Q
Read Address to Out Data Access time with INPUT =
BYPASS, OUPUT = BYPASS
6.477
6.477
7.620
7.620
ns
tBLK2Q
Read Block Select to Out Disable Time with INPUT =
BYPASS, OUPUT = BYPASS
3.794
3.794
4.463
4.463
ns
tR2Q
Read Asynchronous Reset to Output Propagation
Delay
1.399
1.399
1.646
1.646
ns
Fmax
Maximum Frequency with all pipelines enabled
300
250
300
250
MHz
Speed Grade
–1
Speed Grade
STD
Units
27.114
31.897
ns
tCLK2Q
10.3 FPGA Fabric Micro PROM (µPROM)
Table 119 • µPROM
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Description
tCY
Read Clock Period
tCLKMPWH
Read Clock Minimum Pulse Width High
10
10
ns
tCLKMPWL
Read Clock Minimum pulse Width Low
10
10
ns
tADDRSU
Read Address Setup Time
5.847
6.879
ns
tADDRHD
Read Address Hold Time
0.466
0.548
ns
tRSTREC
Read Asynchronous Reset Recovery Time
8.055
9.476
ns
tRSTREM
Read Asynchronous Reset Removal Time
0
0
ns
tRSTMPW
Asynchronous Reset Minimum Pulse Width
7.448
8.762
ns
tCLK2Q
Read Access Time
0.751
0.883
ns
tR2Q
Read Asynchronous Reset to Output Propagation Delay
5.322
6.261
ns
1 -8 0
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
11. JTAG
Table 120 • JTAG 1532
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
FTCKMAX
Description
Speed Grade
–1
Speed Grade
STD
Units
25
25
MHz
TCK maximum frequency
12. DEVRST_N
Table 121 • DEVRST_N Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
All Devices/Speed Grades
Symbol
Description
TRAMPDEVRSTN
Min
DEVRST_N ramp rate
Typ
Max
10
Units
Notes
ns
*
Note: * Slower ramp rates are susceptible to noise.
13. On-Chip Oscillator
Table 122 describes the electrical characteristics of the available on-chip oscillators in the RTG4 FPGAs.
Table 122 • Electrical Characteristics of the 50 MHz RC Oscillator
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
F50RC
Description
Operating frequency
Condition
Min
–
Typ
50
Max
–
Units
MHz
ACC50RC
Accuracy
–
1
%
CYC50RC
Output duty cycle
–
49–51
%
JIT50RC
Output jitter (peak to peak)
200
ps
IDYN50RC
Operating current
Period Jitter
Cycle-to-Cycle Jitter
320
–
R e visi on 2
8.5
ps
–
mA
1-81
RTG4 FPGA AC/DC Electrical Characteristics
14. Clock Conditioning Circuits (CCC)
Table 123 • RTG4 FPGAs CCC/PLL Specification
Military Worst-Case Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Min
Typ
Max
Units
10
–
200
MHz
0.078
–
400
MHz
1
500
–
1000
MHz
2
Delay increments in programmable
delay blocks
–
75
Number of programmable values in
each programmable delay block
–
–
Acquisition time
–
Output duty cycle
48
Clock conditioning
frequency fIN_CCC
Conditions
circuitry
input
Clock conditioning circuitry output
frequency fOUT_CCC
PLL VCO frequency
Output Clock Jitter
Period Jitter
(peak-to-peak)
–
Notes
ps
64
–
500
µs
52
%
max(80, ± 1% x (1/fOUT_CCC))
ps
Note:
1. The minimum output clock frequency is limited by the PLL. For more information, refer to the Fabric PLL Circuitry section in the RTG4
FPGA Clocking Resources User Guide.
2. The PLL is used in conjunction with the Clock Conditioning Circuitry. Performance will be limited by the CCC output frequency.
1 -8 2
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
15. System Controller SPI Characteristics Table 124 • System Controller SPI Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
All Devices/Speed Grades
Symbol
Description
Conditions
Min
Typ
Max
Units
Notes
sp1
SC_SPI_SCK minimum
period
20
–
–
ns
sp2
SC_SPI_SCK minimum
pulse width high
10
–
–
ns
sp3
SC_SPI_SCK minimum
pulse width low
10
–
–
ns
sp4
SC_SPI_SCK,
SC_SPI_SDO,
SC_SPI_SS rise time
(10%-90%) 1
–
1.43
–
ns
*
–
1.45
–
ns
*
sp5
SC_SPI_SCK,
SC_SPI_SDO,
SC_SPI_SS fall time
(10%-90%) 1
IO Configuration: LVTTL 3.3
V- 16 mA
AC Loading: 35 pF
Test Conditions:
Voltage, 25 C
Typical
IO Configuration: LVTTL 3.3
V- 16 mA
AC Loading: 35 pF
Test Conditions:
Voltage, 25 C
Typical
sp6
Data from master
(SC_SPI_SDO) setup
time
160
–
–
ns
sp7
Data from master
(SC_SPI_SDO) hold
time
160
–
–
ns
sp8
SC_SPI_SDI setup time
20
–
–
ns
sp9
SC_SPI_SDI hold time
20
–
–
ns
Note: *For specific Rise/Fall Times, board design considerations and detailed output buffer resistances, use the corresponding IBIS
models located on the Microsemi SoC Products Group website: http://www.microsemi.com/products/fpga-soc/designresources/ibis-models. Use the supported I/O Configurations for the System Controller SPI in Table 125.
Table 125 • Supported I/O Configurations for System Controller SPI (for MSIO Bank Only)
Voltage Supply
I/O Drive Configuration
Units
3.3 V
20
mA
2.5 V
16
mA
1.8 V
12
mA
1.5 V
8
mA
1.2 V
4
mA
R e visi on 2
1-83
RTG4 FPGA AC/DC Electrical Characteristics
16. Mathblock Timing Characteristics
The fundamental building block in any digital signal processing algorithm is the multiply-accumulate function. Each
RTG4 mathblock supports 18x18 signed multiplication, dot product, and built-in addition, subtraction, and
accumulation units to combine multiplication results efficiently.
Table 126 • Mathblocks With All Registers Used
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Mathblock With All Registers Used
Parameter
Description
Speed Grade
–1
Speed Grade
STD
SET Filter
OFF
SET Filter
ON
SET Filter
OFF
SET Filter
ON
Units
tMISU
Input, Control Register Setup time
-0.180
0.763
-0.212
0.731
ns
tMIHD
Input, Control Register Hold time
0.463
1.124
0.545
1.206
ns
tMOCDINSU
CDIN Input Setup time
1.252
2.195
1.473
2.416
ns
tMOCDINHD
CDIN Input Hold time
0.027
0.688
0.031
0.692
ns
tMSRSTENSU
Synchronous Reset/Enable Setup time
0.622
0.622
0.731
0.731
ns
tMSRSTENHD
Synchronous Reset/Enable Hold time
0.125
0.125
0.147
0.147
ns
tMARSTREM
Asynchronous Reset Removal time
0.375
0.375
0.441
0.441
ns
tMARSTREC
Asynchronous Reset Recovery time
-0.018
-0.018
-0.022
-0.022
ns
tMOCQ
Output Register Clock to Out delay
0.941
0.941
1.107
1.107
ns
tMCLKMP
CLK Minimum period
2.498
3.441
2.939
3.882
ns
Table 127 • Mathblock With Input Bypassed and Output Registers Used
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Mathblock With Input Bypassed and Output Registers
Used
Parameter
Description
Speed Grade
–1
Speed Grade
STD
SET Filter
OFF
SET Filter
ON
SET Filter
OFF
SET Filter
ON
Units
tMOSU
Output Register Setup time
2.174
3.117
2.558
3.501
ns
tMOHD
Output Register Hold time
-0.259
0.402
-0.305
0.356
ns
tMOCDINSU
CDIN Input Setup time
1.252
2.195
1.473
2.416
ns
tMOCDINHD
CDIN Input Hold time
0.027
0.688
0.031
0.692
ns
tMSRSTENSU
Synchronous Reset/Enable Setup time
0.593
0.593
0.698
0.698
ns
tMSRSTENHD
Synchronous Reset/Enable Hold time
0.125
0.125
0.147
0.147
ns
tMARSTREM
Asynchronous Reset Removal time
0.375
0.375
0.441
0.441
ns
tMARSTREC
Asynchronous Reset Recovery time
-0.018
-0.018
-0.022
-0.022
ns
tMOCQ
Output Register Clock to Out delay
0.941
0.941
1.107
1.107
ns
tMCLKMP
CLK Minimum period
2.498
3.441
2.939
3.882
ns
1 -8 4
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
Table 128 • Mathblock With Input Register Used and Output in Bypass Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Mathblock With Input Register Used and Output in
Bypass Mode
Parameter
Speed Grade
–1
Description
Speed Grade
STD
SET Filter
OFF
SET Filter
ON
SET Filter
OFF
SET Filter
ON
Units
tMISU
Input Register Setup time
-0.180
0.763
-0.212
0.731
ns
tMIHD
Input Register Hold time
0.463
1.124
0.545
1.206
ns
tMSRSTENSU
Synchronous Reset/Enable Setup time
0.622
0.622
0.731
0.731
ns
tMSRSTENHD
Synchronous Reset/Enable Hold time
0.098
0.098
0.116
0.116
ns
tMARSTREM
Asynchronous Reset Removal time
0.375
0.375
0.441
0.441
ns
tMARSTREC
Asynchronous Reset Recovery time
-0.018
-0.018
-0.022
-0.022
ns
tMICQ
Input Register Clock to Output delay
3.262
3.262
3.838
3.838
ns
tMCDIN2Q
CDIN to Output delay
2.935
2.935
3.453
3.453
ns
Table 129 • Mathblock With Input and Output in Bypass Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Mathblock With Input and Output in Bypass Mode
Parameter
Description
Speed Grade
STD
SET Filter
OFF
SET Filter
ON
SET Filter
OFF
SET Filter
ON
Units
tMIQ
Input to Output delay
2.995
2.995
3.523
3.523
ns
tMCDIN2Q
CDIN to Output delay
2.066
2.066
2.43
2.43
ns
17. PCIe Electrical and Timing AC and DC Characteristics
PCIe® is a high-speed, packet-based, point-to-point, low pin count, serial interconnect bus. The RTG4 FPGAs has up
to four hard high-speed serial interface blocks. Each SERDES block contains a PCIe system block. The PCIe system
is connected to the SERDES block.
Table 130 • PCIe Transmitter Parameters
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Description
Min
Typ
Max
Units
0.8
–
1.2
V
–
–
20
mV
0.125
–
–
UI
VTX-DIFF-PP
Differential swing PCIe Gen1
VTX-CM-AC-P
Output common mode voltage PCIe Gen1
VTX-RISE-FALL
Rise and fall time (20% to 80%) PCIe Gen1
ZTX-DIFF-DC
Output impedance – differential
80
–
120

LTX-SKEW
Lane-to-lane TX skew within a SERDES block PCIe
Gen1
–
–
500 ps
+ 2 UI
ps
RLTX-DIFF
Return loss differential mode PCIe Gen1
-10
–
–
dB
RLTX-CM
Return loss common mode PCIe Gen1
-6
–
–
dB
TRESET-LOCK
Transmit PLL lock time from reset
–
–
10
µs
R e visi on 2
1-85
RTG4 FPGA AC/DC Electrical Characteristics
Table 131 • PCIe Receiver Parameters
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Description
VRX-DIFF-PP-CC
Input levels PCIe Gen1
Input common mode range (DC coupled)
VRX-CM-DC-P
Note: PCIe standard mandates AC coupling
Min
Typ
Max
Units
0.175
–
1.2
V
NA
NA
NA
–
–
–
150
mV
0.175
–
–
mV
VRX-CM-AC-P
Input common mode range (AC coupled)
VRX-DIFF-PP-CC
Differential input sensitivity Gen1
ZRX-DIFF-DC
Differential input termination
80
100
120

REXT
External calibration resistor
1,188
1,200
1,212

CDRRESET-LOCK
CDR relock time from reset
–
–
15
µs
RLRX-DIFF
Return loss differential mode PCIe Gen1
-10
–
–
dB
RLRX-CM
Return loss common mode PCIe Gen1
-6
–
–
dB
CID
CID limit (set by 8B/10B coding, not the receiver PLL)
–
–
4
UI
VRX-IDLE-DET-DIFF-PP
Signal detect limit
65
–
175
mV
Table 132 • SERDES Reference Clock AC Specifications
Worst-Case Military Conditions: TJ = 125°C, Worst-Case VDD = 1.14V
Symbols
Description
Min
Typ
Max
Units
FREFCLK
Reference Clock Frequency
100
–
160
MHz
TRISE
Reference Clock Rise Time
0.6
–
4
V/ns
TFALL
Reference Clock Fall Time
0.6
–
4
V/ns
TCYC
Reference Clock Duty Cycle
40
–
60
%
Mmrefclk
Reference Clock Mismatch
-300
–
300
ppm
SSCref
Reference Spread Spectrum Clock
0
–
5000
ppm
Table 133 • HCSL DC Voltage Specification (Applicable to SERDES REFCLK only)
Symbols
Parameters
Min
Typ
Max
Units
2.375
2.5
2.625
V
0
–
2.625
V
Recommended DC Operating Conditions
VDDI
Supply Voltage
HCSL DC Input Voltage Specification
VI
DC Input voltage
HCSL Differential Voltage Specification
VICM
Input common mode voltage
0.05
–
2.4
V
VIDIFF
Input differential voltage
100
–
1100
mV
1 -8 6
R ev i si o n 2
DS0131: RTG4 FPGA Datasheet
SERDES REFCLK input also supports LVDS standard. For DC specification refer to Table 80 on page 44.
Table 134 • HCSL AC Specifications (Applicable to SERDES REFCLK only)
Symbols
Parameters
Min
Typ
Max
Units
–
–
350
Mbps
–
100
-

Max
Units
HCSL Maximum AC Switching Speed
Fmax
Maximum Data Rate
HCSL Impedance Specifications
Rt
Termination Resistance
18. SpaceWire Clock and Data Recovery
Table 135 • SpaceWire Clock and Data Recovery Characteristics
Symbol
Description
Conditions
Min
Typ
FSWCLK
Recovered Clock Frequency
1
200
MHz
DSW
Recovered Data Rate
2
400
Mbps
TSWCLKCYC
Recovered Clock Duty Cycle
TSWDSS
Rx input data to strobe separation
JITSWIN
Jitter on Data or Strobe inputs
JITSWCLK
Recovered Clock Jitter
50
%
500 × (1/FSWCLK)
ns
200
Period Jitter
(peak to peak)
200
ps
ps
LVTTL
Refer "3.3 V LVCMOS/LVTTL" section on page 12 for
AC/DC Specifications
LVDS
Refer "LVDS" section on page 44 for AC/DC
Specifications
Supported Receiver I/O Standards
R e visi on 2
1-87
Datasheet Information
List of Changes
The following table lists critical changes that were made in each revision of the datasheet.
Revision
Changes
Revision 2
(May 2016)
Updated "Power-Up and Power-Down Sequence" section (SAR 77111).
Revision 1
(June 2015)
Initial release.
Page
4
NA
Datasheet Categories
Categories
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This version contains information that is considered to be final.
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Revision 2
3- 88
DS0131: RTG4 FPGA Datasheet
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