Application Notes

AN11142
GreenChip TEA1755 integrated PFC and flyback controller
Rev. 1 — 12 November 2012
Application note
Document information
Info
Content
Keywords
GreenChip, TEA1755, PFC, flyback, high-efficiency, adaptor, notebook,
PC power, low-power Standby power mode
Abstract
The TEA1755 is a member of the new generation of combined
PFC and flyback controller ICs, used for efficient switched mode power
supplies. Burst mode enhances the overall efficiency of the system at
low-output power and improves the audible noise performance. The
TEA1755 has a high level of integration allowing cost-effective design of
power supplies using the minimum number of external components. The
TEA1755 is fabricated in a Silicon-On-Insulator (SOI) process, enabling it
to operate at a wide voltage range.
AN11142
NXP Semiconductors
GreenChip TEA1755 integrated PFC and flyback controller
Revision history
Rev
Date
Description
v.1
20121112
first issue
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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GreenChip TEA1755 integrated PFC and flyback controller
1. Introduction
The TEA1755 is a combination controller comprising an integrated PFC and flyback
controller in an SO16 package. Both controllers operate in Quasi-Resonant (QR) mode
and in Discontinuous Conduction Mode (DCM) with valley detection and are
independently switched.
The PFC output power is on-time controlled for simplicity. It is not necessary to sense the
phase of the mains voltage. The flyback output power is current mode controlled providing
good input voltage ripple suppression.
The integrated communication circuitry between the controllers does not require
adjustment.
Remark: The voltage and current levels contained in this application note are typical
values The specification of the pin level spreading is given in the TEA1755T and
TEA1755LT data sheets.
Remark: In all cases where a parameter value in this application note is different from that
in the applicable data sheet, the data sheet is leading.
1.1 Scope
This application note describes the functionality of the TEA1755 and the adjustments
needed within the power converter application.
Excluded from this document are the large signal parts of the PFC/flyback power stages
and the coil/transformer design and data.
1.2 The TEA1755 GreenChip controller
The GreenChip features allow the design of reliable, cost-effective and efficient Switched
Mode Power Supplies (SMPS) using the minimum number of external components.
1.2.1 Key features
•
•
•
•
•
•
•
AN11142
Application note
PFC and flyback controller integrated in one SO16 package
Switching frequencies of PFC and flyback controller are independent of each other
No external hardware required for the communication between both controllers
High level of integration, resulting in a low external component count
Integrated mains voltage enable and brownout protection
Fast-latch reset function implemented
Power-down functionality for very low Standby mode power requirements
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1.2.2 System features
•
•
•
•
•
•
•
•
•
Safe restart mode for system fault conditions
High voltage start-up current source (5 mA)
Reduction of HV current source (1 mA) in safe restart mode
Wide VCC range (13.4 V to 38 V)
MOSFET driver voltage limited
Easy control of start-up behavior and VCC circuit
General-purpose input for latched protection
Internal IC overtemperature protection
Accurate PFC switch on/switch off control using flyback switching frequency
measurement
• One high-voltage spacer between the HV pin and the next active pin
• Open pin protection on the VINSENSE, VOSENSE, PFCAUX, FBCTRL and FBAUX
pins
1.2.3 PFC features
• Dual-output voltage boost converter
• QR/DCM operation with valley switching
• Frequency limitation (139 kHz) to reduce switching losses and ElectroMagnetic
Interference (EMI)
•
•
•
•
•
ton controlled
Mains input voltage compensation for control loop for good transient response
OverCurrent Protection (OCP)
Soft-start and soft-stop
Open/short-circuit detection for PFC feedback loop: no external OverVoltage
Protection (OVP) circuit necessary
• Adjustable delay for switching off the PFC
• Overriding the PFC switch on/switch off functionality
1.2.4 Flyback features
• Burst/FR/QR/DCM operation with valley switching
• Frequency Reduction (FR) with an adjustable minimum peak current and valley
switching to maintain high efficiency at low output power levels
•
•
•
•
•
•
•
AN11142
Application note
Burst mode enhances the overall efficiency at low-output power
Burst mode benefits the reduction of audible noise
Frequency limitation (130 kHz) to reduce switching losses and EMI
Current mode controlled
Overcurrent protection
Soft-start
Accurate OVP through auxiliary winding
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• Time-out protection for output overloads and open feedback loop, available as safe
restart (TEA1755T) or latched (TEA1755LT) protection
• VCC undervoltage prevention during burst mode
1.3 Application schematic
Refer to Figure 1 (part 1) and Figure 2 (part 2) for an overview of a typical application.
F1
mains
inlet
LF1
R1
LF2
CX1
BD1
-
L1
+
R2
C1
D1
L2
9
C2
BC1
A
7
R18
12
C3
1
R6
R5
R6B
R5A
C8
R19
Q9
C5
D2
B
switch signal
R31
Q1
R42
D4
R8
R9
D3
R43
Q8
Q2
R14
R12
R13
C9
R11
R16
C6
R16A
R10
C10
R15
R22
C
R17
switch signal
C4
PFCDRIVER
R27
13
FBSENSE
VOSENSE
9
R45
10
16
1
4
TEA1755
3
12
8
E
C14
R23
11
7
2
6
5
GND
R3
D23A
R23A
C13
VINSENSE
PFCAUX
14 15
D
D5
VCC
FBAUX
FBCTRL
F
PFCCOMP
LATCH
PFCTIMER
PFCSENSE
HVS
U1
FBDRIVER
C23
HV
R7
R26
R25
C17
4
C24
C22
R4
C21
C20
U2A-1
C19
RT2
NTC
C18
3
aaa-005245
Fig 1.
TEA1755 application schematic (part 1)
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T1
A
2
11
U3
D30
VCC
C30
4
SELREG
GND
B
TEA1792
4
2 6
n.c.
5
1
SRSENSE
DRIVER
1
3
R30
R32
Q4
Vout+
7, 8
C31
R33
D50
L4
R53
C
L3
1
R51
D
R57
5
C50
6
C51
R52
C52
C27
C29
U2A-2
R54
C28
2
9, 10
Vout-
E
CY1
U5
BC2
VSENSE
3
PSENSE
R50
SWDET
1
5 TEA1703 2
4
6
VCC
GND
OPTO
F
R34
R37
U2-2 1
R24
U2-1
C15
C16
Q7
R35
4
C34
2
3
C35
R36
U4
R38
D52
R55
C53
R56
019aab986
Fig 2.
TEA1755 application schematic (part 2)
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2. Pin description
Table 1.
Pin description
Pin
Name
Functional description
1
VCC
Supply voltage: Vstartup = 22.3 V, Vth(UVLO) = 13.4 V.
At mains switch-on, the capacitor connected to this pin is charged to Vstartup
by the internal HV current source. When the VCC is < 0.6 V, the charge
current is limited to 1.1 mA. This feature prevents overheating of the IC if the
VCC pin is short-circuited. When the pin voltage is between 0.6 V and
Vth(UVLO), the charge current is 5 mA to enable a fast start-up. When it is
between Vth(UVLO) and Vstartup, the charge current is limited to 1 mA again to
reduce the safe restart duty cycle. This results in a reduction of the input
power during fault conditions. When Vstartup is reached, the HV current
source is pinched off and VCC is regulated to Vstartup until the flyback starts.
See Section 3.2 for a complete description of the start-up sequence.
2
GND
3
FBCTRL
Ground connection.
Control input for flyback for direct connection of the optocoupler.
At a control voltage of 4.9 V, the flyback delivers maximum power. The
flyback enters FR mode at a control voltage of 4 V and burst mode at a
control-voltage of approximately 1.2 V. It exits burst mode at 2.8 V. The
flyback driver stops switching when FBCTRL is lower than 0.77 V. The
built-in logic controls an internal 29 A current source that is connected to
the pin. This current source can be used to implement a time-out function to
detect an open control loop or a short circuit of the output voltage. The
time-out function is disabled by connecting a resistor of 180 k between this
pin and ground.
4
FBAUX
Input from auxiliary winding for transformer demagnetization detection,
mains dependent OverPower Protection (OPP) and OverVoltage Protection
(OVP) of the flyback.
The combination of demagnetization and the valley detection on the HV pin
determine the switch-on moment of the flyback controller in the valley. A
flyback OVP is detected at a current higher than 300 A to the FBAUX pin.
Internal filtering prevents false detection of an OVP. The flyback OPP starts
at a current lower than 100 A from the FBAUX pin.
5
LATCH
General-purpose latched protection input.
When Vstartup (on the VCC pin) is reached, the LATCH pin is charged to
582 mV before the PFC and flyback controllers can be switched on. The
latched protection is triggered when the pin is pulled below 494 mV and the
PFC and the flyback are switched off.
The logic controls an internal 30.5 A current source which is connected to
the pin. Using this current source, an optional Negative Temperature
Coefficient (NTC) resistor can be directly connected to the LATCH pin for
temperature protection.
6
AN11142
Application note
PFCCOMP
Frequency compensation pin for the PFC control loop.
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Table 1.
Pin description …continued
Pin
Name
Functional description
7
VINSENSE
Sense input for mains voltage. The VINSENSE pin has six functions:
•
•
•
•
•
•
•
mains start level: Vstart(VINSENSE) = 1.16 V;
mains stop level (brownout): Vstop(VINSENSE) = 0.89 V;
mains voltage compensation for the PFC control loop gain bandwidth;
fast-latch reset: Vflr = 0.75 V;
dual-boost switch-over point: Vbst(dual) high = 2.28 V or low = 2.08 V
(see Section 4) for more information
Standby mode: Vth(pd) = 385 mV
Exit Standby mode: Vth(pd)exit = 460 mV
The voltage on the VINSENSE pin must be an averaged DC value,
representing the AC line voltage. The pin is not used for sensing the phase
of the mains voltage.
8
PFCAUX
Input from an auxiliary winding of the PFC coil for demagnetization timing
and valley detection to control PFC switching.
Connect the auxiliary winding using a 5 k series resistor to prevent
damage to the input because of EMI surges.
9
VOSENSE
Sense input for the PFC output voltage.
VOSENSE pin, open-loop and short-circuit detection;
Vth(stop)(VOSENSE) = 1 V;
VOSENSE pin, start level Vth(start)VOSENSE = 1.1 V;
PFC output voltage regulation; Vreg(VOSENSE) = 2.5 V;
PFC soft OVP (cycle-by-cycle): Vovp(VOSENSE) = 2.62 V;
Control output for the output voltage of the PFC; dual-boost current:
Ibst(dual) = 8.1 A
10
FBSENSE
Flyback current sense input.
On this pin, the sum of three voltages across three resistors is measured.
Selecting the proper resistor values:
•
•
Prevents or minimizes the risk of saturation of the flyback transformer;
•
Allows a system that operates line voltage independently.
Allows some adjustment for switching on or switching off the PFC
controller;
The maximum Vsense(fb)max level is 545 mV at dV/dt = 0 mV/s. The
Vsense(fb)min level is 232 mV at dV/dt = 0 mV/s. Vsense(fb)min is related to the
adjustable peak current through the flyback transformer when flyback is
running in burst mode or frequency reduction mode. There are two internal
current sources connected to this pin, Istart(soft)fb and Iadj(FBSENSE).
The internal logic controls a 60 A current source Istart(soft)fb. The current
source is used to implement a soft-start function for the flyback controller.
The flyback driver only starts when the internal current source can charge
the soft-start capacitor to a voltage of more than 0.55 V. Therefore a
minimum soft-start resistor of 15 k is required to guarantee the flyback
controller is switched on. The current source Iadj(FBSENSE) = 2.1 A. It is
intended to support the adjustment for switch on and switch off the PFC.
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Table 1.
Pin description …continued
Pin
Name
Functional description
11
PFCSENSE
PFC overcurrent protection input.
This input is used to limit the maximum peak current in the PFC core. The
PFCSENSE is a switching-cycle-by-switching-cycle protection. The PFC
MOSFET switches off when the PFCSENSE reaches 495 mV at
dV/dt = 0 mV/s.
The logic controls a 60 A current source which is connected to this pin.
This current source is used to implement a soft-start and soft-stop function
for the PFC to prevent audible noise. The PFC driver only starts when the
internal current source can charge the soft-start capacitor to a voltage of
more than 0.5 V. A soft-start resistor of at least 15 k is required to
guarantee the PFC starts-up.
12
PFCDRIVER
PFC MOSFET gate-driver output
13
FBDRIVER
Flyback MOSFET gate-driver output
14
PFCTIMER
This pin enables the use of two options:
•
Option 1: The timer delays the switching off the PFC when the load of
the flyback is removed or minimized. The PFC is switched off when two
conditions are met:
– the filtered flyback operating frequency < 53 kHz (only valid during
FR mode) and,
– the voltage across the PFCTIMER pin is high ( 3 V).
•
Option 2: When an external voltage supply is connected to this pin, the
typical PFC behavior is overridden. The PFC is switched on when the
VPFCTIMER is forced  1.03 V. The PFC is switched off when the
voltage  4.4 V.
15
HVS
High-voltage safety spacer, not connected.
16
HV
High-voltage input for the internal start-up current source (output on the VCC
pin) and valley sensing of the flyback.
Valley detection input: The combination of demagnetization detection at the
FBAUX pin and valley detection at the HV pin determine the switch-on
moment of the flyback MOSFET in the valley.
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3. System description and calculation
3.1 PFC and flyback start conditions
Figure 3 and Figure 4 show the conditions for switching on the PFC and the flyback during
initial start-up. If start-up problems occur, check these conditions to find the cause of the
problem. Some of the conditions are dynamic signals (see Figure 5). Check them using
an oscilloscope.
FBSENSE (soft-start) ≥ 0.55 V
LATCH ≥ 582 mV
PFCSENSE (soft-start) ≥ 0.5 V
VINSENSE ≥ 1.16 V
AND
PFC switch
on signal
FBCTRL < 7.75 V
AND
flyback switch
on signal
VOSENSE ≥ 1.1 V
IPFCCOMP > -55 μA
PFC switch on signal
aaa-002535
aaa-002534
Fig 3.
Switching on the PFC during initial start-up
Fig 4.
Switching on the flyback during initial start-up
3.2 Initial start-up sequence
At switch-on with a low mains voltage the TEA1755 power supply has the following
start-up sequence (see Figure 5):
1. The HV current source is set to 1.1 mA and the electrolytic capacitor CVCC is charged
to 0.60 V to enable short-circuit detection on the VCC pin.
2. At VCC = 0.60 V, the HV current source is set to 5 mA and the CVCC is quickly charged
to Vth(UVLO).
3. At VCC = Vth(UVLO), the HV current source is set to 1 mA and the VCC electrolytic
capacitor is charged to Vstartup.
4. At Vstartup, the HV current source is switched off. The 30.5 A LATCH pin current
source is switched on to charge the LATCH pin capacitor. The PFCSENSE and
FBSENSE soft-start current sources are switched on.
5. When the LATCH pin is charged to 582 mV, the PFC can start switching when the
VOSENSE = 1.1 V and VINSENSE = 1.16 V.
6. Two additional conditions for enabling the PFC driver are:
a. charge the soft-start capacitor on PFCSENSE to 0.5 V.
b. charge the capacitor connected to the PFCCOMP pin to either 1.92 V or 3.32 V
depending on the VINSENSE voltage and wait until IPFCCOMP < 55 A.
7. Conditions to enable the flyback driver are:
a. all conditions for enabling the PFC are met.
b. charge the soft-start capacitor on the FBSENSE pin to 0.55 V.
c. ensure that the voltage on the FBCTRL pin is lower than 7.75 V. Normally, the
voltage on the FBCTRL pin is lower than 7.75 V at the first flyback switching cycle,
unless the FBCTRL pin is open. When flyback starts, the FBCTRL time-out current
source is switched on.
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8. When flyback has reached its nominal output voltage, the auxiliary winding takes over
the VCC supply. If the flyback feedback loop signal is missing, the time-out protection
on the FBCTRL pin is triggered. Both converters are switched off, VCC drops to the
Vth(UVLO) level and the IC restarts at step 3 of the start-up cycle. Step 3 is the safe
restart cycle for the TEA1755T. The TEA1755LT is latched off and does not return to
step 3. Instead, VCC starts cycling between Vth(UVLO) and Vstartup without restarting.
IHV
Vstartup
Vth(UVLO)
Vtrip
VCC
Vstart(VINSENSE)
VINSENSE
Ven(PFCCOMP)
PFCCOMP
Ven(LA TCH)
LATCH
PROTECTION
soft start
PFCSENSE
PFCDRIVER
soft start
FBSENSE
FBDRIVER
Vto(FBCTRL)
FBCTRL
Vstart(fb)
VOSENSE
VO
charging VCC
capacitor
Fig 5.
starting
converters
normal
operation
protection
restart
014aaa744
Start-up sequence at low mains voltage
The charge time of the soft-start capacitors can be chosen independently for the PFC and
the flyback.
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3.3 VCC cycle in safe restart mode
In safe restart mode, the controller goes through the steps 3 to 8 as described in
Section 3.2.
3.4 Mains voltage sensing and brownout
The mains input voltage is measured through the VINSENSE pin. When the VINSENSE
pin has reached Vstart(VINSENSE) (1.16 V), the PFC starts switching. However, only if the
other start conditions are also met (see Section 3.1).
When the voltage on the VINSENSE pin  Vstop(VINSENSE) (0.89 V), the PFC stops
switching. However, the flyback driver continues switching until the maximum flyback
on-time protection ton(fb)max (38.5 s) is triggered. When this protection is triggered, the IC
stops switching and enters safe restart mode.
The voltage on the VINSENSE pin must be an average DC value, representing the mains
input voltage. The system works optimally using a time constant of approximately 150 ms
on the VINSENSE pin.
R1
BD1
mains
inlet
-
CX1
+
C1
R2
R3
VINSENSE
R4
7
C20
IC
2
GND
019aab491
Fig 6.
VINSENSE circuitry
3.4.1 Discharging the mains input capacitor
Discharge the X-capacitors in the ElectroMagnetic Compatibility (EMC) input filter using a
time constant of  < 1 s for safety reasons.
Use Equation 1 to determine the replacement resistor value of RV:
R   R3 + R4 
R V = R + ----------------------------------R + R3 + R4
(1)
Where:
• R = R1 = R2
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A 90 W adapter often uses a value of 220 nF for CX1. Therefore, the RV value must be
lower than or equal to:

1
R V  ------------ = ------------------ = 4.55 M
CX1
220 nF
(2)
3.4.2 Brownout voltage adjustment
The rectified AC input voltage is measured using R1 and R2. Make sure that both
resistors have the same value because each resistor alternately senses half the sine
wave. Equation 3 shows the calculation for the average rectified line voltage value:
2 2
V avg = ----------------  V  AC  RMS

(3)
The V (AC) brownout RMS level is calculated using Equation 4:
 RV + R3 + R4 

V bo  AC  = ----------------  V stop  VINSENSE   --------------------------------------R4
2 2
(4)
Where: Vstop(VINSENSE) = 0.89 V
At a brownout threshold of 68 V (AC) and in compliance to IEC-60950 chapter 2.1.1.7
discharge of capacitors in equipment (Ref. 3). Example values are shown in Table 2.
Table 2.
VINSENSE component values
CX1
R1
R2
R3
R4
220 nF
2 M
2 M
560 k
47 k
330 nF
1.5 M
1.5 M
820 k
47 k
470 nF
1 M
1 M
1.1 M
47 k
A 3.3 F value for C20 and a 47 k R4, gives the recommended ~150 ms time constant
on the VINSENSE pin.
3.4.3 Minimizing the influence of the dark-current of the optocoupler
The TEA1755 enters Standby mode when VINSENSE  Vth(pd) (385 mV) and exit Standby
mode when VINSENSE  Vth(pd)exit (460 mV). The Standby mode functionality is achieved
by pulling the VINSENSE voltage down to ground using an optocoupler.
The transistor of an optocoupler is not ideal, it always conducts a leakage current. The
optocoupler transistor leakage current is known as dark-current. Dark-current current is
temperature and voltage dependent. Figure 7 shows the proposed circuit that can handle
dark-current up to 10 A.
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VCC (pin 1)
line
R1
C13
R45
R2
R3
D1001A
D1001B
neutral
4
R1000
U2A-1
LTV-817B
R1001
(optional)
gate Q8 and Q9
3
VINSENSE (pin 7)
Q11
BC547
R4
C20
D1000
C21
R8
019aab513
Fig 7.
The proposed VSENSE circuit for minimizing the influence of the dark current
The VINSENSE voltage must reach the Vth(pd)exit before the internal HV current source is
enabled. The VCC supply voltage increases and supports any dark-current needed for the
optocoupler. The optocoupler dark-current no longer influences the VINSENSE voltage.
Add the red colored components to the schematic shown in Figure 1. Diode D1001A and
D1001B are available in one component. Remove two resistors (R42 and R43) in Figure 1
when Figure 7 is added.
3.5 Internal OverTemperature Protection (OTP)
The IC has an internal temperature protection to protect the IC from overheating. When
the junction temperature exceeds the thermal shutdown temperature, the IC stops
switching. As long as the OTP is active, the VCC capacitor is not recharged from the HV
mains. If the VCC supply voltage is not sufficient, the OTP circuit is supplied from the HV
pin. OTP is a latched protection.
3.6 LATCH pin
The LATCH pin is a general-purpose input pin which can be used to latch off both
converters. The pin sources a bias current IO(LATCH) of 30.5 A for the direct connection of
a NTC. When the voltage on the LATCH pin is pulled below Vprot(LATCH), switching of both
converters is stopped immediately. VCC starts cycling between the Vth(UVLO) (13.4 V) and
Vstartup (22.3 V) without a restart. Switching off the mains input voltage and then switching
it on triggers the fast-latch reset circuit and resets the latch (see Section 3.7).
At start-up, the LATCH pin is charged above Ven(LATCH) (582 mV) before both converters
are enabled. Charging of the LATCH pin starts when VCC = Vstartup.
A 10 nF capacitor is placed between the LATCH pin and the IC GND pin to prevent false
triggering. In addition, when the LATCH pin function is not used add a 10 nF capacitor.
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IC
5
LATCH
R26
2
C19
GND
RT2
aaa-002536
Fig 8.
Usage of the LATCH pin protection
Latching on application overtemperature occurs when the total resistance value of the
NTC plus the series resistor drops under the following:
0.495 V
R OTP = -------------------- = 16.13 k
30.5 A
(5)
3.7 Fast-latch reset
Switching off the mains input voltage and then switching on resets the latched protection.
After the mains input is switched off, the voltage on the VINSENSE pin drops  Vflr
(0.75 V). The voltage drop triggers the fast-latch reset circuit but does not reset the
latched protection. After the mains input is switched on, the voltage on the VINSENSE pin
rises again. The latch is reset when the level has passed Vflr + Vflr(hys) (0.86 V). The
system restarts when the VCC pin is charged to Vstartup (See step 4 of Section 3.2).
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4. PFC description and calculation
The PFC controller operates in either QR mode or DCM mode with valley detection to
reduce the switch-on losses. The maximum switching frequency of the PFC is limited to
fsw(PFC)max (139 kHz) to reduce switching losses. If necessary, one or more valleys are
skipped to keep the frequency below 139 kHz.
The PFC is designed as a dual-boost converter with two output voltage levels that are
dependent on the mains input voltage range. The advantage is that the overall system
efficiency at low mains is improved because of the reduction of the PFC switching losses.
In low and medium power adapters (< 120 W), the contribution of PFC switching losses to
the total losses is relatively high.
An internal current source of 8.1 A (Ibst(dual)) on the VOSENSE pin controls the
dual-output voltage. The mains input voltage measured at the VINSENSE pin is used to
control the internal current source as shown in Figure 9. This current source, in
combination with the resistors connected to the VOSENSE pin, sets the lower PFC output
voltage. At high mains, the current source is switched off. The maximum PFC output
voltage is unaffected by the current source accuracy. In a typical adapter, with a
385 V (DC) PFC output voltage at high mains, the PFC output voltage is 250 V (DC) at
low mains. A voltage of 2.3 V at the VINSENSE pin corresponds with a mains input
voltage of approximately 170 V (AC). The small slope at the transfer function ensures a
stable switchover of the PFC output voltage without hiccups.
2.08 V
2.28 V
VVINSENSE
-8.1 μA
II(VOSENSE)
Fig 9.
aaa-004486
Transfer function of VINSENSE voltage to dual-boost current at VOSENSE
The PFC is switched off to ensure high efficiency during low output currents. After switch
off, the electrolytic bulk capacitor voltage VCbulk drops to line voltage  2 .
4.1 PFC output power and voltage control
The PFC of the TEA1755 is on-time controlled, therefore it is not necessary to measure
the mains phase angle. The on-time is kept constant during the half sine wave to obtain a
good Power Factor (PF) and a class-D Mains Harmonics Reduction (MHR).
The PFC output voltage is controlled using the VOSENSE pin. At the VOSENSE pin,
there is a transconductance error amplifier with a reference voltage of 2.5 V
(Vreg(VOSENSE)). The error on the VOSENSE pin is converted with 77 A/V (gm) to a
current on the PFCCOMP pin. The voltage on the PFCCOMP pin, in combination with the
voltage on pin VINSENSE, determines the PFC on-time.
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ramp oscillator
Idch
IC
VM
+
-
C
S
voltage
comparator
Ich
V-
current
multiplier
VVINSENSE 7
VR
V+
V/I
TRANSDUCER
VS
I2
Q
12
VPFCDRIVER
S
I1
Vosc
VVOSENSE 11
R
I2
Vp
transconductance
amplifier
ton limiting
circuit
Icomp
+
- VREF
R1
PFC
OSCILLATOR
VALLEY
DETECTION
VVALLEY
6
8
VPFCCOMP
VPFCAUX
C2
compensation
network
C1
019aab492
Fig 10. TEA1755 PFC converter on-time control
A network with one resistor and two capacitors at the PFCCOMP pin is used to stabilize
the PFC control loop. The equation for a boost converter transfer function contains the
square of the mains input voltage. In a typical application, this results in a low regulation
bandwidth for low mains input voltages and a high regulation bandwidth for high input
voltages. The result can be that at high mains input voltages, it can be difficult to meet the
MHR requirements. The TEA1755 uses the mains input voltage measured through the
VINSENSE pin to compensate the control loop gain as a function of the mains input
voltage. As a result the gain is constant over the entire mains input voltage range.
The voltage on the VINSENSE pin must be an average DC value, representing the mains
input voltage. The system works optimally with a time constant of approximately 150 ms
on the VINSENSE pin.
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4.1.1 Setting the PFC output voltage
The PFC output voltage is set using a resistor divider between the PFC output voltage and
the VOSENSE pin. In normal mode, the PFC output voltage is regulated so that the
voltage on the VOSENSE pin is equal to Vreg(VOSENSE) (2.5 V).
D1
PFC stage
VO(PFC)
C3
R6
R6A
8.1 μA
VINSENSE
2.1 V
place C4 and R7
as close as
possible to the IC
9 VVOSENSE
IC
2
C4
R7
GND
aaa-005246
Fig 11. TEA1755 PFC converter output voltage setting
The VOSENSE pin has an integrated protection circuit to detect an open circuit pin (see
Section 4.3.2). The open-circuit pin protection operates reliably when
R7  Vth(stop)VOSENSE(min) / Ibst(dual)max = 0.95 V / 9.1 A = 104.4 k. The first possible
resistor value (below the 104.4 k) available in the E96 series is 102 k.
Remark: MAX is the maximum limiting current value. In data sheet, it is a negative
number. Normally, we calculate using positive numbers, so it is called in this application
note the maximum value.
Selecting a larger value for R7 can override PFC open-loop protection. The maximum
bulk electrolytic capacitor voltage (Vbulk(PFC)high) can be calculated using Equation 6:
R6 + R6A + R7
V bulk  PFC high = 2.5 V   ------------------------------------- + 1


R7
(6)
The PFC converter only operates correctly when Vbulk(max) > Vmains(max)  2 + 10 V
(voltage margin). In a universal mains adapter, the highest line voltage is typically 264 V.
Therefore, Vbulk(max) = 264  2 +10  383 V. Using this information together with
Equation 6 the minimum resistor divider value is calculated (see Equation 7):
R6 + R6A + R7 V bulk  PFC high – 2.5 383 – 2.5
-------------------------------------  ------------------------------------------------  ----------------------  153.34
R7
2.5
2.5
(7)
Rewriting Equation 7 results in:
R6 + R6A
R6 + R6A + R7 R7
------------------------ = ------------------------------------- – ------- = 153.34 – 1 = 152.34
R7
R7
R7
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Vbulk(PFC)low is calculated using:
R6 + R6A
V bulk  PFC low = V reg  VOSENSE  + ------------------------   V reg  VOSENSE  – I bst  dual   R7 
R7
(9)
At low line voltages, the recommended value for Vbulk(PFC)low  250 V.
Equation 9 looks as follows when rewritten with the values:
3
(10)
R6 + R6A = 152.34  R7 = 152.34  102  10 = 15539 k
(11)
V bulk  PFC low = 2.5 + 152.34   2.5 – 8.1  10
–6
 102  10   258 V
With R6 + R6A equal to:
3
If R6 = R6A, therefore R6 =15539 / 2 = 7769 k = 7.77 M.
The calculated Vbulk(PFC)low value fits with the recommended minimum value of 250 V at
low line voltages. Lowering the R7 value results in an increased Vbulk(PFC)low and
Vbulk(PFC)high. Table 3 shows some calculation examples using R6 = 7680 k and
R6A = 7870 k (R6 + R6A = 15550 k).
Table 3.
R6 and R6A calculated using different R7 values
R7 (k)
R6 + R6A / R7
Vbulk(PFC)low (V)
Vbulk(PFC)high (V)
102
152.45
258
386
100
155.55
265
394
97.6
159.32
275
403
Remark: The selected R7 values in Table 3 are standard values of the E96 series
When R7  104.4 k and Vbulk(PFC)low  250 V meet their requirements, the results are
within limits.
Capacitor C4 (see Figure 1) filters noise and prevents protection modes false triggering
because of MOSFET switching noise. False triggering of the Vovp(VOSENSE) protection can
cause audible noise and disturbance of the AC mains input current.
A time constant between 500 ns and 1 s at the VOSENSE pin is sufficient, resulting in a
4.7 nF C4 capacitor value.
Place R7 and C4 as close as possible to the IC between the VOSENSE pin and the GND
pin.
4.1.2 Calculation of the PFC soft-start and soft-stop components
Soft-start and soft-stop are implemented using the RC network connected to the
PFCSENSE pin.
To enable PFC driver start-up, resistor RSS1 must be  15 k minimum value to ensure
that the Vstart(soft)PFC voltage of 0.5 V is reached. See Section 3.2 for a description of
start-up.
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Istart(soft)PFC ≤ 60 μA
Q1
RSS1
SOFT-START
SOFT-STOP
CONTROL
11
PFCSENSE
CSS1
OCP
0.5 V
Rsense
IC
019aab493
Fig 12. PFC soft-start and soft-stop
The total soft-start or soft-stop time is t soft-start = 3  R SS1  C SSI . Switching off the PFC
always ends with a soft-stop. However, there is an exception to this rule. The switched on
PFC does not generate a soft-stop when the system enters burst mode even though CSS1
charges up to Vsense(PFC)max after switching off the PFC. The charged CSS1 capacitor
allows a fast restart of the PFC when applicable.
Keep the soft-start time of the PFC shorter than the soft-start time of the flyback controller.
It is also recommended that the soft-start time is kept within a range of 2 ms to 5 ms.
Using C6 = 100 nF and R11 = 15 k results in a soft-start time of 4.5 ms.
4.2 PFC demagnetizing and valley detection
The PFC MOSFET is switched on after the transformer is demagnetized. The internal
circuitry connected to the PFCAUX pin detects the end of the secondary stroke. It also
detects the voltage across the PFC MOSFET. The next primary stroke is started when the
voltage across the PFC MOSFET is at its minimum level. When the voltage is at the
minimum level, switching losses and ElectroMagnetic Interference (EMI) (valley
switching) are reduced.
To reduce the switching losses, the PFC converter maximum switching frequency is
limited to 139 kHz. If necessary, one or more valleys are skipped to keep the frequency
under 139 kHz.
When demagnetization is not detected on the PFCAUX pin, the controller generates a
Zero-Current Signal (ZCS) 48 s (tto(demag)PFC) after the last PFC gate signal. If a valley
signal is not detected on this pin, the controller generates a valley signal 4.2 s
(tto(demag)PFC) after demagnetization was detected.
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L1
C1
9
C2
L2
D1
7
C3
1
5
Q1
R9
R27
PFCDRIVER
12
IC
PFCAUX
8
2
GND
019aab478
Fig 13. TEA1755 PFCAUX circuitry
4.2.1 Design of the PFCAUX winding and circuit
Set the voltage on pin PFCAUX as high as possible within the absolute maximum voltage
rating of  25 V. This setting guarantees valley detection at low ringing amplitudes.
The number of turns of the PFCAUX winding is calculated using Equation 12.
V PFCAUX
25 V
N aux  max  = ----------------------  N p = ------------------  N p
V L  max 
V L  max 
(12)
• VPFCAUX is the absolute maximum rating of the PFCAUX pin
• VL(max) is the maximum voltage across the PFC primary winding
The PFC output voltage at the PFC OVP level determines the maximum voltage across
the PFC primary winding and is calculated using Equation 13:
V ovp  VOSENSE 
2.62 V
V L  max  = ------------------------------------  V O  PFC  = ----------------  V O  PFC 
V reg  VOSENSE 
2.5 V
(13)
When a PFC coil with a higher number of auxiliary turns is used, place a resistor voltage
divider between the auxiliary winding and the PFCAUX pin. The total resistive value of the
divider must be 10 k to prevent a valley detection delay due to parasitic capacitance.
The polarity of the signal at the PFCAUX pin is reversed compared to the PFC MOSFET
drain signal.
Add a 5 k resistor between the PFC auxiliary winding and the PFCAUX pin to protect
against electrical overstress during lightning surge events. Place the resistor as close as
possible to the IC to prevent incorrect valley switching of the PFC because of external
disturbances.
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4.3 PFC protection modes
4.3.1 VOSENSE overvoltage protection
Overvoltage can occur across the bulk electrolytic capacitor during the initial start-up and
large load changes. The relative slow response of the PFC control loop causes this
overvoltage. The PFC control loop response must be relatively slow to guarantee a good
power factor and meet the MHR requirements. The OverVoltage Protection (OVP) on the
VOSENSE pin limits the overvoltage.
When the Vovp(VOSENSE) level = 2.62 V is detected, the PFC MOSFET is switched off
immediately regardless of the on-time setting. The switching of the MOSFET is blocked
until the voltage on the VOSENSE pin drops < 2.62 V again. OVP is also triggered when
the resistor between the VOSENSE pin and ground is open. The peak voltage during an
overshoot across the electrolytic bulk capacitor is calculated using Equation 14.
V ovp  VOSENSE 
2.62 V
V O  PFC pk = ------------------------------------  V O  PFC nom = ----------------  V O  PFC nom
V reg  VOSENSE 
2.5 V
(14)
4.3.2 VOSENSE open and short pin detection
The VOSENSE pin senses the PFC output voltage. The VOSENSE pin has an integrated
protection circuit to detect an open and short circuited pin. The VOSENSE pin also senses
that one of the resistors in the voltage divider is open making the VOSENSE pin failsafe.
It is not necessary to add an external OVP circuit for the PFC.
When the pin is open, an internal current source pulls VVOSENSE up and VOVP(VOSENSE) is
detected. The PFC stops switching when VOVP(VOSENSE) is detected and an internal
voltage clamp limits the maximum VOSENSE voltage. The same condition applies when
only resistor R7 is open (see Figure 11). The internal voltage clamp again limits the
maximum VOSENSE voltage to acceptable values.
The PFC is not switching when VVOSENSE  VVth(stop)VOSENSE, this condition is applicable
when VOSENSE is short ciruited to ground. The same condition is applicable if only
resistor R6 or R6A (see Figure 11) is open. However under the condition that
R7  104.4 kΩ (see Section 4.1.1).
4.3.3 VINSENSE open pin detection
The VINSENSE pin senses the mains input voltage, The VINSENSE pin has a protection
circuit to detect an open pin. An internal current source pulls down the pin to
 Vstop(VINSENSE) (0.89 V) when the pin is open.
4.3.4 Overcurrent protection
The overcurrent protection limits the maximum current through the PFC MOSFET and
PFC coil. The current is measured via a current sense resistor in series with the MOSFET
source. The MOSFET is switched off immediately when the voltage on the PFCSENSE
pin exceeds the Vsense(PFC)max level of 495 mV at dV/dt = 0 mV/s. OCP is a
cycle-by-cycle protection.
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To avoid false triggering of the PFC OCP by the flyback converter switching, use a
100 mV margin. False triggering of the Vsense(PFC)max protection can cause interference to
the AC mains input current. Place a small capacitor between 100 pF and 220 pF next to
the PFCSENSE pin to suppress any external disturbance.
The current sense resistor is calculated using Equation 15:
V sense  PFC max – V m arg in
0.495 V – 0.1 V
R ocp  PFC  = ------------------------------------------------------------ = -------------------------------------I pQR  PFC max
I pQR  PFC max
(15)
Where: the maximum PFC peak current is IpQR(PFC)max at the high output load and low
mains.
The maximum peak current for the PFC operating in Quasi-Resonant (QR) mode is
calculated using Equation 16:
I pQR  PFC max
P o  max 
2 2  ------------------  1.1
2 2  P i  max   1.1

= -------------------------------------------- = --------------------------------------------V  AC min
V  AC min
(16)
Where:
• Po(max) is the maximum output power of the flyback
• Factor 1.1 is used to compensate the dead-time between zero-current in the PFC
inductor at the end of the secondary stroke and the detection of the first valley in
quasi-resonant mode
•  is the expected efficiency of the total converter at maximum output power
• V(AC)min is minimum mains input voltage.
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5. Flyback description and calculation
5.1 Flyback output power control
The TEA1755 flyback system waits until the transformer is demagnetized and at least one
valley has appeared before it is magnetized again for the next cycle. The FBAUX pin
detects demagnetization via the auxiliary winding. The HV pin detects the bottom of the
valley via the drain of the MOSFET or the central tap of the primary winding.
The output power (PO) of the flyback is calculated using Equation 17:
1
2
P O = ---  L p  I pk  f s  
2
(17)
Where:
•
•
•
•
Lp is the flyback transformer primary inductance
Ipk is the flyback transformer primary peak current
fs is the flyback controller operating frequency
 is the flyback controller efficiency
Lp is selected at the start of the design. The primary peak current controls the (high)
output power in QR and DCM mode. The switching frequency is a result of external
application parameters and IC parameters.
External application parameters are the transformer turns ratio, primary inductance, the
drain source capacitance, input voltage, output voltage and the feedback signal from the
control loop. IC parameters are the oscillator setting, the peak current setting and the
demagnetization and valley detection.
The primary current Ipk is fixed at medium and low output power. The power is controlled
by changing the operating frequency. Output power and operating frequency are linearly
related during this type of control. In this application note, it is called operating in
frequency reduction mode (See Section 5.1.1.3). The minimum switching frequency in FR
mode is 25 kHz. At even lower output powers, the IC enters the burst mode which
minimizes audible noise.
The burst mode is a hysteresis controlled system, used during low output-power. The
primary peak current Ipk and operating frequency of the flyback are both fixed when the
system supports power to the output.
Using VFBCTRL as a hysteresis input results in a variable amount of FBDRIVER switching
pulses combined with a changing burst mode repetition frequency.
The flyback input voltage is measured using the FBAUX pin and it is used to implement an
OverPower Protection (OPP). OPP keeps the maximum output power of the flyback
converter constant over the input voltage.
The flyback has an accurate OverVoltage Protection (OVP) circuit. The overvoltage is
measured through the FBAUX pin. Both flyback and PFC controllers are switched off in a
latched protection when an overvoltage is detected.
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5.1.1 Four TEA1755 operation modes
At initial start-up, the flyback always starts at the maximum output power. This means that
the system starts up in Quasi-resonant mode. The flyback of the TEA1755 passes through
four operation modes (see Figure 14) from maximum to minimum output power:
•
•
•
•
Quasi-Resonant (QR) mode
Discontinuous Conduction Mode (DCM)
Frequency Reduction (FR) mode
Burst Mode (BM)
The internal demagnetization detection and valley switching circuitry is active in all four
operating modes.
FR
DCM
QR
fsw(fb)max
flyback
switching
frequency
PFC off
PFC on
QR: Quasi Resonant
DCM: Discontinuous Conduction Mode
FR: Frequency Reduction
BM: Burst Mode
burst mode
frequency
FR minimum
frequency
BM
0.77
2.4
2.8
4.0
VFBCTRL (V)
4.9
aaa-002672
Fig 14. Flyback operation modes
5.1.1.1
Quasi-resonant mode
The flyback operates in quasi-resonant mode at high and maximum output power. The
peak current controls the output power (see Section 5.1). A lower peak current than the
maximum allowed value results in lower output power and a higher operating frequency
until the maximum operating frequency is reached. The quasi-resonant mode can easily
be recognized. The next primary switching cycle starts when the bottom of the first valley
is detected.
The voltage on the FBCTRL pin sets the primary peak current (Ipk). Place the 220 pF
noise filter capacitor (C15) as close as possible to the FBCTRL pin to avoid flyback
controller interference by the PFC MOSFET switching. The voltage on the FBCTRL pin is
measured back at the FBSENSE pin and is calculated using Equation 18 (only valid in QR
mode or DCM):
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V Rsense  fb   0.315  V FBCTRL – 1.1591 – I adj  FBSENSE    R16 + R17 
(18)
Where:
• VFBCTRL is allowed to vary between the 4 V and 4.9 V (only valid in QR mode and
DCM mode)
• Iadj(FBSENSE) related to a current source inside the IC, connected to the FBSENSE pin
• Resistors R16 and R17 are found in the circuit diagram, see Figure 15.
T1
Vi (DC)
Doutput
Lp
Coutput
Rcomp
RSERIES = R17 + R16
FBSENSE
Iadj(FBSENSE)
R17
FBDRIVER
R16
Q2
R16A
Rsense
C23
019aaa039
C10
FBSENSE has two internal reference levels:
(1) Vsense(fb)max = 545 mV at dV/dt = 0 mV/s
(2) Vsense(fb)min = 232 mV at dV/dt = 0 mV/s
Fig 15. Most important components for adjusting the flyback in the application
Equation 19 defines the peak current Ipk through the flyback transformer:
V sense  fb  – I adj  FBSENSE    R16 + R17 
I pk = ---------------------------------------------------------------------------------------------------R sense
(19)
Vsense(fb)max determines the maximum peak current Ipk(max). R16A is not mentioned in
Equation 18 and Equation 19, but R16A is explained in Section 5.1.5. Decreasing the
output power results in the flyback entering discontinuous conduction mode when the
maximum switching frequency is reached.
5.1.1.2
Discontinuous conduction mode
Reducing the peak current (Ipk) and skipping more valleys decreases the output power. It
results in a switching frequency close to but never higher than fsw(PFC)max (139 kHz). The
operating mode switches from DCM to FR mode when VFBCTRL  4 V (Vstart(red)f)).
Sometimes DCM is not reached when the selected primary inductance of the inductor is
too large. In this case, flyback skips DCM when it is reducing power. It jumps directly from
QR mode to FR mode.
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5.1.1.3
Frequency reduction mode and PFC switch on/switch off control
The voltage across the FBCTRL pin in Frequency reduction mode does not set the peak
current, instead it sets the operating frequency. The minimum primary peak current Ipk(min)
through the flyback transformer is kept constant during FR mode.
The ratio Ipk(min) : Ipk(max) mainly depends on the sense resistor Rsense value assuming that
the core is not saturated at Ipk(max). Decreasing the output power reduces the operating
frequency. As a result of the frequency reduction, more valleys are skipped.
The flyback operating frequency during FR mode determines when the PFC is switched
on or switched off.
Decreasing the output-power from maximum to minimum switches off the PFC before it
has reached 25 % of the nominal output current. Switching off the PFC improves the
overall efficiency at low output power.
Increasing the output-power from minimum to maximum starts the PFC up before it has
reached 50 % of the nominal output current. Starting up the PFC improves the power
factor of the line current at high output power.
The PFC switch-on/switch-off state depends on the primary inductance value, the output
power and the line voltage. It is therefore, important to select the right inductance value to
ensure enough hysteresis between the PFC switch-on/switch off state, especially at low
line voltages (see Section 5.1.2).
The following three options are used to switch on the PFC:
1. The PFC is using the flyback operating frequency during FR mode (f  fsw(fb)swon(PFC)).
2. VFBCTRL  Ven(PFC)FBCTRL (3.75 V), applicable at initial start-up or when the flyback
operating frequency cannot reach fsw(fb)swon(PFC).
3. When the duty-cycle of the FBDRIVER  50 %.
Option 3 is useful during line dips, assuming that some residual line voltage is present that
can support power. The flyback can support more power to the output when its input
voltage is higher (because of the switched on PFC), it can therefore, hold the nominal
output voltage for a longer time.
Table 4.
PFC switch on and switch off signals[1]
Options
PFC switch-on signal
PFC switch off signal
1
fsw(fb)  73 kHz
fsw(fb)  53 kHz
2
VFBCTRL  3.75 V
3
FBDRIVER  50 %
[1]
The table does not list the PFC table override function. See Section 5.2.1 and Section 5.2.2.
Remark: VINSENSE  Vstop(VINSENSE) switches off the PFC, regardless which PFC
switch-on signal is used.
The minimum operating frequency during FR mode is 25 kHz. This frequency is above the
audible frequency for humans.
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5.1.1.4
Burst mode
Requesting less output power activates the frequency clamp and the flyback controller
starts to operate in burst mode. The PFC continues to operate if it was switching. The
PFC stops switching when VPFCTIMER  Vstop(PFCTIMER) (3 V). The internal circuitry of the
TEA1755 is partly shut down, resulting in a reduced supply current.
The peak current Ipk(min) during burst mode is equal to the value in FR mode.
The burst mode repetition frequency and amount of FBDRIVER pulses depends on the
feedback loop and output power.
The maximum burst mode repetition frequency is preferably below the 700 Hz, some
adjustment can be made by changing the value of R34. A relatively low burst mode
repetition frequency minimizes the risk on audible noise.
The flyback driver operating frequency is fixed at fsw(fb)burst (36.5 kHz) during BM and
starts when the FBCTRL > Vth(burst)on (2.4 V). Starting the driver results in a fast reduction
in the control voltage and the driver continues to operate until
FBCTRL < Vth(burst)off (0.77 V).VFBDRIVER voltage is constant LOW during the increase of
VFBCTRL up to 2.4 V.
The FBCTRL voltages for BM and higher output powers are tuned to each other. This
tuning benefits the design allowing standard feedback component values for the feedback
loop.
Requesting more output power results in a higher control voltage overshoot (> 2.4 V)
when the driver starts. However, the IC remains in BM as long as VFBCTRL  2.8 V.
Requesting more output power results in VFBCTRL > Vth(burst)exit (2.8 V) and the IC
switches to FR mode. Figure 16 shows this behavior.
load
Vout
2.8 V
2.4 V
25 kHz = flyback frequency
0.77 V
FBCTRL
flyback active
burst mode
FBDRIVER
aaa-002676
Fig 16. TEA1755 in burst mode
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5.1.1.5
VCC undervoltage protection during burst mode
The duty cycle and repetition frequency during BM are both very low when the flyback
output power is close to no-load. This low output power results in a very low VCC for the
IC.
The IC prevents VCC < Vth(UVLO). It allows the FDRIVER to switch for a few cycles until
VCC has increased its value with 0.8 V (Vprot(UVLO) = Vth(UVLO) + 0.8 V). These cycles have
no impact on the output voltage because all the energy is transferred to the auxiliary
winding when VCC is just above Vth(UVLO).
5.1.2 The relationship between inductance value and the PFC hysteresis
The TEA1755 operates at a fixed minimum peak current (Ipk(min)) to control the output
power during the FR mode, see Section 5.1. The value of Ipk(min) is calculated using
Equation 23.
The MOSFET on-time depends on the selected inductance value and input voltage. The
ton is linearly related to the inductance value and inversely proportional to the input
voltage. The relationship between the MOSFET ton and toff is fixed based on:
• the transformer turns ratio
• the output voltage excluding the influence of the short valley time
The relatively large inductance results in the flyback running in QR mode at low line
voltages although the flyback controller is running in FR mode. This situation is easy to
recognize. FBDRIVER is immediately activated at the bottom of the first valley. (Normal
operation usually skips valleys during FR mode). Figure 17 shows the operation of a
flyback controller at low and lower line voltages.
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Is
(1)
Ipk(min) = fixed value
tp
ts
tp
ts
tvalley
tx
T = 1 / fs
Is
(2)
Ipk(min) = fixed value
tp + tx
ts
tp + tx
ts
tvalley
T + tx = 1 / fs-low
aaa-005247
(1) Flyback controller driven at low line voltages assuming a relatively large primary inductance for the flyback transformer.
(2) Flyback controller driven at very low line voltages assuming a relatively large primary inductance for the flyback transformer.
Fig 17. Operating frequency as a function of low line voltages, assuming a relatively large selected primary
inductance value for the flyback transformer
Lowering the line voltage results in a lower operating frequency and output power when
the selected primary inductance is relatively high.
In practice, the flyback driver supports a limited amount of power at low line voltages.
Requesting more power activates the feedback loop and the PFC controller starts up at a
lower output power than was originally intended. The hysteresis between PFC switch-on
and switch-off becomes smaller therefore at low line voltages. The PFC starts switching
when VFBCTRL  Ven(PFC)FBCTRL = 3.75 V, if the flyback operating frequency cannot reach
fsw(fb)swon.
Normally, a relatively large primary inductance value is preferred because it minimizes
switching losses. However, it must not result in unwanted system behavior at low line
voltages because of lost hysteresis. Limiting the maximum inductance value prevents any
unwanted system behavior at low line voltages. In addition, a longer valley time makes the
hysteresis between PFC switch-on and switch-off even smaller. It is recommended to
keep the valley time close to 1.1 s.
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It is helpful to have an indication of the acceptable maximum transformer primary
inductance value at the start of the design. Several assumptions are made when
calculating these inductance values as shown in Figure 18. Therefore, these values are
only for use as indications.
019aaa041
800
Lp
(μH)
(5)
(4)
600
(3)
(2)
(1)
400
200
75
95
115
135
155
PO (W)
Lp = f(PO).
Assumptions: Minimum voltage across the buffer capacitor (C3) is approximately 100 V (DC) at
50 % of the nominal output power.
(1) N  (VO + Vf) = 80 V.
(2) N  (VO + Vf) = 92 V.
(3) N  (VO + Vf) = 104 V.
(4) N  (VO + Vf) = 118 V.
(5) N  (VO + Vf) = 130 V.
Fig 18. Indication of the maximum primary inductance value, related to output power and
N  (VO + Vf)
Figure 18 shows an indication for the maximum primary flyback inductance value at
different output powers and turn ratios.
The following effects are seen for the primary inductance:
• Selecting a higher value results in a reduction of the PFC switch on and switch off
hysteresis
• Selecting a lower value results in lower efficiency (related to more overall switching
losses)
The inductance values shown in Figure 18 result in the loss of some hysteresis at
 115 V (AC) line voltage. However, the hysteresis is usually still acceptable at 90 V (AC),
assuming that the voltage across C3 does not drop under approximately 100 V (DC) at
50 % of the nominal load.
Usually this minimum voltage condition is achieved when C3 in F is equal to the nominal
output power in W as a rule of thumb. The assumption is the minimum line voltage is
90 V RMS / 60 Hz and PPFC(swon)  0.5  Pnominal
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The following methods can be used to select the inductance value:
• using Figure 18
• using Equation 20
N   VO + Vf 
–6
– 1.0005
L p =  ---------------------------------  43061  10   I O  nom    V O + V f  


104.3
(20)
Where:
•
•
•
•
•
IO(nom) stands for the nominal output current according to the type plate of the adapter
VO the output voltage
Vf the forward voltage across the secondary diode
Lp the flyback transformer primary inductance
N the turns ratio between the primary and secondary windings (Np/Ns)
Equation 20 gives some deviation at a low and a high value of the N   V O + V f  product.
It is recommended to keep this value between 80 V and 130 V.
Example:
• IO(nom) = 4.62 A
• VO = 19.5 V
• Vf = 0.1 V
• N   V O + V f  = 104.5
104.5
–6
– 1.0005
–6
L p =  -------------  43061  10   4.62   19.5 + 0.1  
= 475  10 H
 104.3
(21)
The final value used is 450 H.
5.1.3 Relationship between Ipk(min) and the required PFC(swon)/PFC(swoff) level
The PFC is switched on and switched off usually between 50 % and 25 % of the nominal
output current of the flyback. The PFC is only switched on or switched off when the
flyback controller is running in FR mode. The PFC switches on at a flyback operating
frequency of 73 kHz (fsw(fb)swon(PFC)) and switches off the PFC at 53 kHz (fsw(fb)swoff(PFC)).
The recommended PFC switch off output power is 30.3 % of the typical output-power. The
margin between 30.3 % and the 25 % requirement is used for a range of tolerances. Use
components with a tolerance values that comply with those given in in the bill of materials
section of UM10514 . Allowing more tolerance for the components requires a larger
margin for the recommended output power when a 25 % power requirement is met.Using
this information results in Equation 22:
1
2
0.303  I O  nom    V O + V f  = ---  L p  I pk  min   f sw  fb swoff  PFC    fb
2
(22)
or:
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I pk  min  =
2  0.303  I O  nom    V O + V f 
---------------------------------------------------------------------------L p  f sw  fb swoff  PFC    fb
(23)
Where:
•
•
•
•
•
•
•
0.303 is the recommended multiplying factor related to PFC(swoff)
VO is the output voltage
IO(nom) is the nominal output current according to the type of adapter plate
Vf is forward voltage across the secondary diode
Lp is the primary inductances of the flyback transformer
fsw(fb)swoff(PFC) is 53000
fb is the efficiency of the flyback (use relatively high values, such as 0.94 to 0.96)
Example:
•
•
•
•
•
IO(nom) = 4.62 A
VO = 19.5 V
Vf = 0.1 V
Lp = 450 H
fb = 0.95
I pk  min  =
2  0.303  4.62   19.5 + 0.1 
--------------------------------------------------------------------------- = 1.556 A
–6
450  10  53000  0.95
(24)
PFC(swon) is calculated using Equation 25:
2
PFC  swon  = 0.5  L p  I pk  min   f sw  fb swon  PFC    fb
(25)
Using the data results in:
PFC  swon  = 0.5  450  10
–6
2
 1.556  73000  0.95 = 37.8 W
(26)
This value can be translated into an output current Iout(en), see
37.8
PFC  swon  =
I OUT  en  = ---------------------------------------------------- = 1.93 A
19.5 + 0.1
VO + Vf
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5.1.4 The influence of Rsense and the R16/R17 series resistance
The sense resistor, Rsense, together with the series impedance R16 and R17, has four
functions:
• prevent or minimize the risk of saturation of the flyback transformer
• allow enough power to the output (assuming the inductance is not going into
saturation)
• allow some adjustment for switching on or switching off the PFC at a certain output
power level. The value of Rsense is more dominant for this adjustment than the value
of R16, as its influence is much smaller
• R17 and C23 prevent FBSENSE being charged negative because of disturbances
across Rsense
The saturation level (Isat) of the transformer and the value of the sense resistor are
important design parameters. Section 5.1.4.1 shows the calculation for the transformer
saturation level. Next, the maximum peak current (Ipk(max)) through the transformer is
determined. This value is preferably below the transformer saturation level.
5.1.4.1
Calculating the flyback transformer saturation current Isat
The transformer saturation level is calculated using Equation 28.
N p  B max  A e
I sat = -----------------------------------Lp
(28)
Example based on the following assumptions:
•
•
•
•
Np = 32 turns
Bmax = 390 mT (PQ3220, material PC44, Bmax at 100 C)
Ae = 170  106 m2 (from transformer supplier data sheet)
Lp = 450  106
–6
32  0.39  170  10
Result: I sat = ------------------------------------------------------ = 4.715 A
–6
450  10
Values for Ae and Bmax are contained in the transformer data sheet. The Bmax value
depends on temperature. It decreases rapidly at high operating temperatures. Therefore,
select the Bmax value at high operating temperatures. Core saturation does not occur
when the maximum peak current (Ipk(max)) is less than the saturation current (Isat).
Section 5.1.4.2 shows the calculation of Ipk(max). A saturated core deteriorates the overall
system performance. It results in more stress, EMI and in the worst case, a possible
system failure.
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5.1.4.2
Calculation of Ipk(max) for flyback operating in Quasi-resonant mode
The flyback peak current in QR mode is calculated using Equation 29:
2
– b + b – 4  a  c
I pk  max  = ------------------------------------------------------2a
(29)
Where:
• a = N  Vi(DC)min  Lp
• b = 2  IO  Lp  {N  (VO + Vf) + Vi(DC)min}
• c = 2  IO  tvalley  N  Vi(DC)min  (VO + Vf)
For a, b and c:
•
•
•
•
•
VO is the output voltage
N is the turns ratio between the primary and secondary windings (Np/Ns)
Vf is the forward voltage across the secondary diode
Lp is the inductance value of the primary winding
tvalley is the valley time, sometimes also described as dead-time. This time is usually
around the 1.1 s
• Vi(DC)min is the minimum voltage across electrolytic bulk capacitor C3 during a
load-step. The customer defines the load step but the maximum value of the load step
is limited to the nominal output power. In this example, Vi(DC)min = 75 V (DC). The
voltage depends on the load step, the value of the Cbulk and when the PFC is
switched on during the mains cycle. It is recommended that this value is checked in
every application.
Examples:
• a = 5.3333  75  450  106 = 180  103
• b = 2  4.62  450  106  {5.3333  (19.5 + 0.1) + 75} = 746.499  103
• c = 2  4.62  1.1  106  5.3333  75  (19.5 + 0.1) = 79.6875  103
I pk  max   at I O = 4.62 A  =
–3
–3 2
–3
–3
746.50  10 +  – 746.50  10  – 4  180  10  – 79.69  10
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- = 4.25 A
–3
2  180  10
(30)
The calculated peak current is under the 4.71 A saturation level (see Section 5.1.4.1).
Allow a margin between the calculated value and the saturation level of the core. For
example, the system could still run into a problem during a peak load. Check carefully for
these instances in the final design.
Assuming the PFC has been switched on for some time, Equation 31 shows the results
using a peak output current of 5.7 A and Vbulk = 250 V (DC).
• a1 = 5.3333  250  450  106 = 0.6
• b1 = 2  5.70  450  106  {5.3333  (19.5 + 0.1) + 250} = 1.8188
• c1 = 2  5.70  1.1  106  5.3333  250  (19.5 + 0.1) = 32.77  103
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I pk  max   at I O = 5.7 A  =
2
(31)
–3
1.82 +  – 1.82  – 4  0.6  – 32.77  10
--------------------------------------------------------------------------------------------------------- = 3.05 A
2  0.6
Select the highest Ipk(max) value (with IO = 4.62 A and IO = 5.7 A). Compare the Ipk(max)
value with the Isat value. The highest Ipk(max) value must be lower than the Isat value.
If so, use the Isat value for Ipmax to allow a better maximum output power margin.
5.1.4.3
Calculation of the current sense resistor Rsense
The next step is calculating the Rsense value, see Equation 32:
V sense  fb max – V sense  fb min
0.545 – 0.232
0.313
R sense = ------------------------------------------------------------------- = ------------------------------------------- = ------------------------------------------I pk  max  – I pk  min  I pk  max  – I pk  min 
I pk  max  – I pk  min 
(32)
Remark: fill in the highest for Ipk(max) level (see Section 5.1.4.2).
Using the saturation current Isat for Ipk(max) is often preferred (assuming that Isat > Ipk(max))
because it allows a higher maximum output power.
Using the highest peak current of all (Isat = 4.715 A, see Section 5.1.2) results in a value
for Rsense as calculated in Equation 33:
0.313
R sense = ---------------------------------  0.100 
4.715 – 1.556
5.1.4.4
(33)
Calculation of the series resistance R16 and R17
Equation 34 calculates the series resistance of R16 and R17:
I pk  max   V sense  fb min – I pk  min   V sense  fb max
R SERIES = --------------------------------------------------------------------------------------------------------------------I adj  FBSENSE    I pk  max  – I pk  min  
(34)
I pk  max   0.232 – I pk  min   0.545
= ---------------------------------------------------------------------------------–6
2.1  10   I pk  max  – I pk  min  
A typical 90 W adapter example:
4.715  0.232 – 1.556  0.545
- = 37.1 k
R SERIES = ----------------------------------------------------------------------–6
2.1  10   4.715 – 1.556 
(35)
The value of R17 is often roughly between 680  and 1.2 k. Its purpose is to prevent
C10 being charged in an unwanted way because of spikes across Rsense which can trigger
the internal ESD protection. Selecting a value between these two limits allows some
freedom for trimming R16 or the delay compensation resistor R16A. When the R17 value
is chosen as 1000  then the R16 value = 37100   1000  = 36100 .
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5.1.5 Calculation of the delay compensation resistors Rcomp and R16A
Rcomp and R16A are intended to compensate the sum of the following three delays:
• the internal delay time of the IC
• the switch off time of the MOSFET
• the delay time related to R17  C23 (filter in front of the FBSENSE pin)
The transformer still conducts current on the primary side during the sum of all these
delay times. These delay times are translated into an extra current IDELAY through the
transformer (see Figure 19) which results in extra output energy. The amount of extra
energy depends on the input voltage.
The current flows through two resistors placed in series, R5 and R5A. The combined
resistance of R5 and R5A resistors is called Rcomp. It is recommended to select
Rcomp  13.6 M.
Rcomp is calculated using Equation 36:
(36)
R comp = R5 + R5A
Resistors Rcomp and R16A compensate for the unwanted current (IDELAY) using a
corresponding delay time.
The voltage across R16A is translated to the current IPRESET with the corresponding
preset time. When the preset values cancel the delay values, the system is compensated.
The voltage across resistor R16A depends on the current passing through it.
IDELAY
IPRESET
IPREFERRED
tPRESET
tDELAY
tPREFERRED
019aaa042
Fig 19. Principle of delay compensation
An example calculation for a typical 90 W adapter: R comp = 6.8 + 6.8 = 13.6 M
The IC internal delay time, MOSFET switch off response time and the R17  C23 time
constant determine the final delay time. A minimum RC time is required to filter out
disturbances on the FBSENSE pin.
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An RC time selection that is too large cannot follow the input voltage ramp-up properly. All
other delays are subtracted first from the flyback MOSFET conducting time. The
remaining time must be at least 5.5 times the minimum RC time required for filtering out
interference on the FBSENSE pin.
td(FBDRIVER) defines the internal delay of the TEA1755 at 80 ns. Switching off the MOSFET
usually takes around 60 ns.
Remark: Check the time for switching off the MOSFET (td(MOSFET)off) in the final
application because using different MOSFETs and gate resistors can change its duration.
The conduction time of the flyback MOSFET is shortest when the input voltage is at its
highest. The highest value is usually 390 V (DC). Equation 37 shows the calculation for
R17  C23:
L p  I pk  min 
------------------------------ – t d  FBDRIVER  – t d  MOSFET off
–9
390  10
R17  C23  ----------------------------------------------------------------------------------------------------------5.5
(37)
An example calculation for a typical 90 W adapter:
–6
450  10  1.556
---------------------------------------------- – 80 – 60
–9
390  10
R17  C23  ----------------------------------------------------------------------  301 ns
5.5
(38)
A commonly used RC time for this filter is 220 ns using 1 k for R17 and 220 pF for C23.
The RC time value is used in the subsequent equations. The tolerance of capacitor C23 is
 10 %.
Using a maximum tolerance of 10 % for C23 limits the impact on the overall spreading for
the PFC(swon) on and PFC(swoff) level.
The output follows the input with a delay of just one RC time after roughly five RC times.
The total delay time is calculated using Equation 39:
t d = t d  int  + t d  MOSFET off + R17  C23
(39)
An example for a typical 90 W adapter:
t d = 80  10
–9
+ 60  10
–9
3
+ 1  10  220  10
– 12
= 360 ns
(40)

  R sense  R COMP  t d
1
R16A =  ----------------------------------------------------------  -------------------------------------------------
–9
Lp
  1 + 8.4  10  R comp  
(41)
The R16A value is calculated using Equation 41:
An example for a typical 90 W adapter:

  0.100  13.6  10 6  360  10 –9
1
- = 976 
R16A =  ----------------------------------------------------------   ---------------------------------------------------------------------------–6
  1 + 8.4  10 – 9  R comp  

450  10
AN11142
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5.1.6 Calculation of the flyback soft-start components
Soft-start is implemented using the RC network connected to the FBSENSE pin.
The sum of R16, R16A and R17 must be > 15 k to ensure Vstart(soft)fb (0.55 V) is reached
and flyback start-up is enabled. See the TEA1755T and TEA1755LT data sheets
(Ref. 1/Ref. 2).
In general, the R16A and R17 values are much smaller than the value of R16. Therefore,
the soft-start time is:  soft –s tart  3  R16  C10 .
Make tsoft-start for flyback longer than for the PFC. Keep tsoft-start in the range of 5 ms to
10 ms. When C10 = 68 nF and R16 = 36 k, the total tsoft-start is approximately 7 ms.
5.2 Two PFCTIMER pin options
The PFCTIMER pin can be used to extend the PFC operating time when the output power
drops below the PFC switch off level. This option prevents the PFC from constantly
switching on and off because of fast, large dynamic load changes at the output.
Preventing this results in reduced audible noise. This option is further described in
Section 5.2.1.
Another option for the PFCTIMER pin is overriding the PFC switch-on (PFC(swon)) and
switch off (PFC(swoff)) functionality. Refer to Section 5.2.2 for more information about this
subject.
5.2.1 Option 1: adjustable PFC(swoff) time
A capacitor connected to an internal current source determines the adjustable PFC(swoff)
time. Capacitor C24 charges from 0 V to 3 V during this adjustable time, the PFC typically
switches off using a soft-stop when VPFCTIMER > 3 V. Equation 43 shows how this time is
calculated.
V stop  PCFTIMER 
C24  3 V
t d  PFC swoff = C24   -------------------------------------------- = ------------------------I source  PFCTIMER 
4.7 A
(43)
Example: a capacitance of 1.5 F for C24 results in a 0.96 s delay approximately.
Typically, after the PFC is switched off, C24 is charged to 3.8 V.
Remark: Always connect a capacitor with a minimum value of 1 nF to the PFCTIMER pin.
Table 5 shows the behavior and conditions of the PFCTIMER pin when it is not overridden
by an external source.
Table 5.
PFC(swon)
PFC(swoff)
Activation signal
fsw(fb)  73 kHz or
VFBCTRL  3.75 V
fsw(fb)  53 kHz and
VPFCTIMER  3 V
Activation delay
no delay
adjustable
Zo or Isource(PFCTIMER)
resistor impedance = 5.3 k
Isource(PFCTIMER) = 4.7 A
Condition
0 < VPFCTIMER < 3 V
3 < VPFCTIMER < 3.8 V
[1]
AN11142
Application note
PFCTIMER adjustable PFC disable time
Typical status without
overriding signal[1]
The PFC can only be switched on or switched off when the flyback is running in FR mode.
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Capacitor CPFCTIMER discharges when the PFC switches on.
An operating PFC continues switching when Po drops within the range of Po(PFC)swon (see
Figure 20). An output power below the PFC off level for a short time results in charging of
capacitor CPFCTIMER. However, CPFCTIMER immediately discharges when the output power
is back in the Po(PFC)swon/Po(PFC)swoff range if the PFCTIMER voltage was still under 3 V.
The PFCDRIVER signal operates continuously during these load changes at the output
(see Figure 20).
Applying less power than Po(PFC)swoff during a time that allows VPFCTIMER to rise above the
3 V causes the PFC to switch off.
The PFC switches on immediately when Po > Po(PFC)swon and the CPFCTIMER is
discharged.
PO(PFC)swon
PO(PFC)swoff
PO
t
VPCFTIMER
3
1
t
PCFTIMER
active
on hold
t
aaa-005290
Fig 20. Control of the PFCTIMER pin when PFC is not overridden
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5.2.2 Option 2: Overriding the PFC(swon) and PFC(swoff) functions
The PFC in the TEA1755 is typically switched on or switched off using the filtered flyback
operating frequency. However, the PFCTIMER allows overriding of this functionality, if
necessary (see Table 5). The conditions for overriding the PFC are as follows:
• the disabled PFC is overridden (PFC(swon)) when VPFCTIMER ≤ 1.0 V but
VPFCTIMER > 1 V immediately switches off the PFC again.
• the enabled PFC is overridden (PFC(swoff)) when VPFCTIMER ≥ 4.4 V but
VPFCTIMER < 4.4 V switches on PFC again.
The TEA1755 does not allow overriding of the PFC during flyback burst mode. All other
flyback operation modes enable overriding of the PFC(swon) and PFC(swoff)
functionality.
The recommended CPFCTIMER capacitor value is 1 nF. The recommended capacitance
value results in the shortest PFCTIMER pin response time to an external signal. Correct
timing is important if an external signal is used to override the PFC, especially when
switching on the PFC.
Keep VPFCTIMER close to the 4.4 V (Vth(off)PFCTIMER) when the PFC is switched off. This
action minimizes the external driver current required to override the PFC. In addition,
together with the small PFCTIMER capacitance, it allows the fastest response on the
external PFC switch on signal.
Table 6 shows the behavior and required conditions of the PFCTIMER pin when it is
overridden by an external source.
Table 6.
Typical
status
PFCTIMER behavior and required conditions when overridden by an external source
Override
signal state
change
PFC(swoff) PFC(swoff)
PFC(swon)
PFC(swon) PFC(swoff)
PFC(swon)
VPFCTIMER Time delay
(td(PFCTIMER))
Override trigger
(Ith(PFCTIMER))
Condition
1 V  VPFCTIMER  10 V 
PFC state is not changing
 4.4 V
none
1V
minimize any
delay
Ith(PFCTIMER) >> +4.7 A
 4.4 V
possible
negligible
delay
4.4 V  VPFCTIMER  10 V but
resistor impedance 5.3 kso
Ith(PFCTIMER) = VPFCTIMER / 5.3 k VPFCTIMER < 4.4 V 
PFC(swon); use
VPFCTIMER(max)  4.4 V[2] and
CPFCTIMER = 1 nF
1V
none
0 V  VPFCTIMER  1 V but
VPFCTIMER > 1 V 
PFC(swoff); use
VPFCTIMER(max)  4.4 V[1] and
CPFCTIMER = 1 nF
0 V  VPFCTIMER  3 V  PFC
state is not changing
[1]
VPFCTIMER refers to the recommended value before overriding to allow the fast PFC(swon).
[2]
VPFCTIMER refers to the recommended value when overridden to allow the lowest required external sourcing current.
AN11142
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Two circuit solutions for overriding the PFC(swon) and PFC(swoff) functionality are shown
in Figure 21 and Figure 22. The optocoupler transistor operates as a current source. The
constant current through the optocoupler diode determines the transistor current setting.
The figure notes describe the condition the circuit overrides. All solutions can handle
optocoupler dark-current up to 10 A.
override
signal
VCC
R
1.3 MΩ
IC
14
R
D
PFCTIMER
1
2
GND
CPCFTIMER
1 nF
1
U1
U1
3
2
aaa-002539
Override a switched off PFC by pulling down VPFCTIMER.
Fig 21. Switching on the PFC by overriding its switch off mode
override
signal
VCC
4
U1
R1
3
IC
14
2
GND
PFCTIMER
CPCFTIMER
1 nF
3
1
Zprot
6.8 V
U1
1
2
aaa-005295
Zprot protects the PFCTIMER pin when the PFC is not switched off by the external override signal.
Fig 22. Switching off the PFC by overriding its switch-on mode
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GreenChip TEA1755 integrated PFC and flyback controller
5.3 Flyback protection mode
5.3.1 Short-circuit on the FBCTRL pin
If the FBCTRL pin is shorted to ground, switching of the flyback controller is inhibited.
5.3.2 Open FBCTRL pin
As shown in Figure 23, the FBCTRL pin is connected to an internal 7 V voltage source via
an internal 13.2 k resistor. When the voltage on the FBCTRL pin exceeds 5.5 V, this
connection is disabled. The FBCTRL pin is biased with an internal 29 A current source.
When the voltage on the FBCTRL pin > Vto(FBCTRL) (7.7 V), a fault is assumed. Flyback
and PFC switching is blocked and the controller:
• TEA1755T: enters the safe restart mode
• TEA1755LT: triggers the latched protection
An internal switch pulls the FBCTRL pin down when the controller is blocked.
5.3.3 Time-out flyback control loop
A time-out function can be created to protect against an output short-circuit at initial
start-up or against an open control loop situation. This feature is made when a resistor is
mounted in series with a capacitor between the FBCTRL pin and ground. Triggering the
time-out protection generates:
• TEA1755T: a safe restart
• TEA1755LT: a latched protection
When the voltage on the FBCTRL pin > 5.5 V (see Figure 23), the switch in series with the
13.2 k resistor is opened. The FBCTRL pin and therefore the RC combination is biased
with a 29 A current source (Ito(FBCTRL)).
When the voltage on the FBCTRL pin > 7.75 V, flyback and PFC switching is blocked and
the controller enters the relevant protection mode. The resistor and capacitor are both
used to set the time delay required to reach 7.75 V on the FBCTRL pin. The resistor is
also necessary to separate the relatively large time-out capacitor from the control loop
response. Use a resistor value  30 k.
The time-out time tto is calculated using Equation 44:
d Vto  FBCTRL 
I to  FBCTRL   R
t to = – R  C  In  ------------------------------------------- + C  -------------------------------I to  FBCTRL 
V to  FBCTRL enable
(44)
Remark: dvto(FBCTRL) value 2.25 V in Equation 44 is related to Vto(FBCTRL), it is the trip
value minus enable value: 7.75 V  5.5 V = 2.25 V.
An example based on the following assumptions:
• R24 = 39 k
• C16 = 330 nF
3
t to = – 39  10  330  10
AN11142
Application note
–9
–6
3
2.25
29  10  39  10
–9
 In  -------------------------------------------------- + 330  10  ---------------------–6


5.5
29  10
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If time-out protection is not required, it is disabled by placing a resistor of 180 k between
the FBCTRL pin and ground.
The result of Equation 45 is:
(46)
t to = 20.4 ms + 25.6 ms = 46 ms
5.5 V
7V
29 μA
7.75 V
13.2 kΩ
FBCTRL
time-out
aaa-002674
a. Circuit diagram
7.75 V
5.5 V
VFBCTRL
output
voltage
intended output
voltage not reached
within time-out time
restart
intended output
voltage reached
within time-out time
aaa-002675
b. Timing diagram
Fig 23. Time-out protection
5.3.4 Overvoltage protection flyback
The IC has an internal latched overvoltage protection circuit which switches off both
controllers when an overvoltage is detected at the output of the flyback. The IC detects
overvoltage on the flyback transformer secondary winding during the secondary stroke by
measuring the voltage on the auxiliary winding.
A series resistor between the auxiliary winding and the FBAUX pin converts this voltage to
a current through the FBAUX pin.
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D5
T1
primary
VCC
D23A
C13
1
D_output
4
IC
R23
FBAUX
2
R23A
auxiliary
secondary
ROVP = R23
GND
ROPP = R23 + R23A
019aab496
Fig 24. Flyback OVP and OPP circuit
When a 300 A current Iovp(FBAUX) is applied to the FBAUX pin, the IC detects an
overvoltage. An internal integrator filters noise and voltage spikes. The output of the
integrator is used as an input for a counter. The counter has been added as an extra filter
to prevent false OVP detection which can occur during ESD or lightning events.
If the integrator detects an overvoltage, the counter increases its value by one. If another
overvoltage is detected during the next switching cycle, the counter increases its value by
one again. If no overvoltage is detected during the next switching cycle, the counter
subtracts its value by two. (The minimum value is zero.) If the value reaches six, the IC
assumes a true overvoltage and activates the latched protection. Both converters are
switched off immediately and VCC starts cycling between Vth(UVLO) and Vstartup without a
restart.
Switching off the mains input voltage and then switching on again, triggers the fast-latch
reset circuit and resets the latch.
Resistor Rovp sets the OVP level:
R ovp
aux
N
----------   V O + V f  – V clamp  FBAUX  – V f  D23A 
 Ns 
= ------------------------------------------------------------------------------------------------------------------I ovp  FBAUX 
(47)
N aux
 ----------   V O + V f  – 0.92 – V f  D23A 
 Ns 
= ----------------------------------------------------------------------------------------300 A
Where:
•
•
•
•
•
•
Ns is the number of turns on the secondary winding.
Naux is the number of turns on the flyback transformer auxiliary winding.
Vclamp(FBAUX) is the FBAUX pin positive clamp voltage.
Vf(D23A) is the forward voltage of D23A at a current of 300 A.
VO is the output voltage
Vf is the forward voltage across the secondary diode
Take the tolerances on Iovp(FBAUX) into account for the Vovp(VOSENSE) level calculation to
avoid OVP triggering during normal operation.
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5.3.5 OverPower Protection (OPP)
The maximum power that the flyback can support depends on its input voltage. A higher
input voltage allows more output power which can result in more stress during fault
conditions. The OPP circuit is implemented to limit the output power to a predefined value
at higher input voltages. Triggering the OPP circuit results in activation of the time-out
protection (see Section 5.3.3 for more information).
The design of the circuit starts with calculating the required flyback input voltage that
matches the predefined OPP level. Equation 48 shows the calculation
V bulk  opp min
P opp
2  L p  I sat  ---------- fb
= ----------------------------------------------------------------------------------------------------------------------------------------------2  L p  I sat P opp
P opp
2
N  L p  I sat – -----------------------------  ----------- – 2  N  t valley  ---------- VO + Vf 
 fb
 fb
(48)
Where:
• N is the turn ratio between primary turns and secondary windings of the flyback
transformer
•
•
•
•
•
•
•
Lp is the primary inductances of the flyback transformer
Isat is the calculated maximum peak current
VO is the output voltage of the flyback
Vf is forward voltage across the secondary diode (or conducting MOSFET)
Popp is the requested maximum output power of the flyback
tvalley is the measured valley time
fb is the efficiency of the flyback. Use relatively high values, such as 0.94 to 0.96
The example is based on the following assumptions:
•
•
•
•
•
•
•
N = 5.3333 (see Section 5.1.4.2)
Isat = 4.715 A (see Section 5.1.4.1)
VO = 19.5 V (see Section 5.1.2)
Vf = 0.1 V (see Section 5.1.2)
Popp = 131.3 W; the assumed and preferred OPP level of the flyback
tvalley = 1.1 s (see Section 5.1.4.2)
fb = 0.95 (see Section 5.1.3)
Using these values in Equation 46 results in: Vbulk(opp)min = 143.4 V (DC).
The preferred OPP output power level is almost independent of the line voltage when
Vbulk(opp)min < Vbulk(PCF)low. Refer to Section 4.1.1 for more information about Vbulk(PCF)low.
Keep a margin of 50 V between Vbulk(PCF)low and Vbulk(opp)min. A transformer running very
close to saturation has a negative effect on the tolerance of the OPP circuit. Using at least
a margin of 50 V minimizes this effect.
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During the flyback primary stroke, the input voltage is sensed by measuring the current
drawn from the FBAUX pin. A resistor, placed between the flyback transformer auxiliary
winding and the FBAUX pin, converts the voltage to the current IFBAUX. The IC uses the
current information to reduce the setting of the maximum flyback peak current measured
through the FBSENSE pin.
See Figure 24 for the limitation of the maximum VFBSENSE level as a function of IFBAUX.
VFBSENSE
(mV)
545
400
-360
-100
IFBAUX (μA)
0
aaa-002678
Fig 25. OPP maximum FBSENSE voltage
The total OPP resistance (R23 + R23A) determines the IFBAUX current during the flyback
primary stroke (see Figure 25). The OVP resistor R23 has to be calculated before the
remaining part of the OPP resistor R23A can be calculated.
The value of R23A is calculated using Equation 49:
N aux  V bulk  opp min
– V clamp  FBAUX 
----------------------------------------------Np
R23A = ------------------------------------------------------------------------------------------ – R ovp
I start  opp FBAUX
N aux  V bulk  opp min
----------------------------------------------- – 0.7
Np
= ------------------------------------------------------------ – R ovp
–6
100  10
(49)
Calculation example based on the following assumptions:
•
•
•
•
Naux = 7 turns
Np = 32 turns
Vclamp(FBAUX) is the FBAUX pin negative clamp voltage.
Vbulk(opp)min = 143.4 V(DC)
7  143.3
--------------------- – 0.7
3
32
R23A = ---------------------------------- – R ovp = 306  10 – R ovp
–6
100  10
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The OPP resistance (Ropp) is limited by Equation 51.
V th  comp FBAUX_MIN 60 mV
R opp  ------------------------------------------------- = ---------------- = 923 k
I prot  FBAUX _MAX
65 nA
(51)
It is recommended to keep a margin to this maximum resistor value. The recommended
maximum value for Ropp  650 k. Larger resistor values can result in a slower output
voltage rise during initial start-up which can trigger the time-out protection (See
Section 5.3.3).
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6. Summary of calculations for flyback adjustment
See Figure 1 application schematic for component reference numbers.
T1
Vi (DC)
Doutput
Lp
Coutput
Rcomp
RSERIES = R17 + R16
FBSENSE
Iadj(FBSENSE)
R17
Q2
FBDRIVER
R16
R16A
Rsense
C23
019aaa039
C10
FBSENSE has two internal reference levels:
(1) Vstart(soft)fb = 545 mV at dV/dt = 0 mV/s
(2) Vsense(fb)min = 232 mV at dV/dt 0 mV/s
a. Most important components for adjusting the flyback in the application
019aaa041
800
Lp
(μH)
(5)
(4)
600
(3)
(2)
(1)
400
200
75
95
115
135
155
PO (W)
Lp as a function of PO
Assumptions: Minimum voltage across Cbulk (C3) is approximately 100 V (DC) at 50 % of the
nominal output power.
(1) N  (VO + Vf) = 80 V
(2) N  (VO + Vf) = 92 V
(3) N  (VO + Vf) = 104 V
(4) N  (VO + Vf) = 118 V
(5) N  (VO + Vf) = 130 V
b. Indication of the maximum inductance value, related to output power and N  (VO + Vf)
Fig 26. Most important components and maximum inductance value for adjusting the
flyback in the application
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Step 1: Use the graph in Figure 26 to determine an indication for the maximum primary
inductance value or use Equation 52:
N   VO + Vf 
–6
– 1.0005
L p =  ---------------------------------  43061  10   I O  nom    V O + V f  


104.3
(52)
Step 2: Select a transformer and calculate the saturation current:
N p  B max  A e
I sat = -----------------------------------Lp
(53)
Step 3: Calculate the required peak current through the flyback transformer. Calculate this
value at nominal output power in combination with the minimum Vbulk and when the PFC
is operating at maximum peak output power. Calculate using both values for Ipk(max) but
only use the highest value of these two parameters.
A common rule is that Isat > Ipk(max). Selecting the higher Isat value for Ipk(max) prevents
transformer saturation and allows a power margin. In general, the calculation is carried
out using Ipk(max) = Isat.
2
– b + b – 4  a  c
I pk  max  = ------------------------------------------------------2a
(54)
Where:
• a = N  Vi(DC)min  Lp
• b = 2  IO  Lp  {N  (VO + Vf) + Vi(DC)min}
• c = 2  IO  tvalley  N  Vi(DC)min  (VO + Vf)
Step 4: Calculate Ipk(min) (related to switching off the PFC):
I pk  min  =
2  0.303  I O  nom    V O + V f 
---------------------------------------------------------------------------L p  53000   fb
(55)
fb is the flyback efficiency. Use a relatively high value, for example, approximately 0.94 to
0.96.
Step 5: Calculate the value of Rsense:
V sense  fb max – V sense  fb min
0.545 – 0.232
0.313
R sense = ------------------------------------------------------------------- = ------------------------------------------- = ------------------------------------------I pk  max  – I pk  min  I pk  max  – I pk  min 
I pk  max  – I pk  min 
(56)
Step 6: Calculate the value of RSERIES:
I pk  max   V sense  fb min – I pk  min   V sense  fb max
R SERIES = --------------------------------------------------------------------------------------------------------------------I adj  FBSENSE    I pk  max  – I pk  min  
(57)
I pk  max   0.232 – I pk  min   0.545
= ---------------------------------------------------------------------------------–6
2.1  10   I pk  max  – I pk  min  
The RSERIES resistance comprises two components, R16 and R17. The common value for
R17 is between 820  and 1.2 k. A typical value that is used often is 1 k.
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Step 7: Checking/calculating the R17  C23 time constant:
L p  I pk  min 
------------------------------ – t d  int  – t d  MOSFET off
–9
390  10
R17  C23  ns   ----------------------------------------------------------------------------------------5.5
(58)
Where:
• td(FBDRIVER) = 80 ns
• td(MOSFET)off  60 ns (The value can be different in other applications. Check on the
application board.)
In general, the calculation often shows that R17  C23  220 ns. If so, 220 ns is sufficient
for the constant R17  C23. A smaller value can be acceptable but is not preferred.
Step 8: Calculate the delay time:
t d = t d  int  + t d  MOSFET off + R17  C23
(59)
Remark: The commonly used value for R17  C23 is 220 ns (see step 7).
Step 9: Calculate the compensating resistor Rcomp:
(60)
R comp = R5 + R5A
Calculate the value of R16A:
R sense  R comp  t d


1
-   --------------------------------------------R16A =  -----------------------------------------------------–9


Lp
 1 + 8.4  10  R comp
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7. PCB layout considerations
A good layout is an important part of the final design. It minimizes many kinds of
disturbances and makes the overall performance more robust with less risk of EMI.
Guidelines for the improvement of the layout of the PCB are as follows:
• Separate large signal grounds from small signal grounds (see Figure 28). A triangular
symbol indicates small signal grounds. All other ground symbols are related to large
signal grounds
• Make the print area within the indicated large signal loops (see Figure 28) as small as
possible. Each indicated large signal loop has its own color. Make the copper tracks
as short and wide as possible
• The connection between both MOSFETs (PFC and flyback) and the IC driver outputs
must be as short as possible (green line in Figure 28). Use wide tracks. Increase the
distance between the copper tracks and/or preferably using a separate guided ground
track for both connections minimizes the coupling between the PFCDRIVER and
FBDRIVER. A circuit diagram according to Figure 27 can be added in case it is
impossible to locate the MOSFET and IC close to each other.
• The power ground and small signal ground are only connected with one short copper
track (make this track as short and as wide as possible). Preferably it should become
one spot (connection between ground 4a and ground 6a, shown as a green line in
Figure 28)
• Use a ground shield underneath the IC, connect this ground shield to the GND pin of
the IC
• Connect all series connected resistors that are fixed to an IC pin as close as possible
to that pin
• Connect heatsinks which are connected to the component nearest corresponding
ground signal. Make this connection as short as possible. Connect the heatsink of
diode bridge BD1 to ground 1, Q1 to 4 and Q2 to 4b. In typical applications, all three
components are often mounted on a single heatsink. If so, make one wide copper
track that connects all three grounds to each other. Also combine in this copper track
ground 2
• Connect the grounds of 6b to each other
• Make a local "star ground" from ground 6a, 6b, 6c, and 7. Ground 6a is the middle of
the star and is connected to the GND pin (the ground of the IC)
• Grounds marked 7 do not have to be a star ground
• Place the Y-capacitor across grounds 1 and 8. Use one copper track, separated from
all others for this connection. Alternatively in a typical application setup, use the
heatsinks connection copper track for this purpose.
• Place C4, C15, C23 and C22 (in order of priority) as close as possible to the IC.
Reduce coupling between the PFC switching signals (PFC driver and PFCAUX) and
the flyback sense signals (FBSENSE and FBCTRL) as much as possible. The
coupling reduction minimizes the risk of electromagnetic interference and audible
noise
• Figure 28 shows an overview of the hierarchy of the different grounds at the bottom
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• Connect the anode of the TL431 (ground 8) to ground 9 using one special separate
connecting copper track. Minimize all other currents in this special track. Make the
connection as close as possible to the output
• Place the TEA1792 close to the power MOSFET Q4
• Connect the ground of the TEA1792 directly to a wide and short copper track to the
source of Q4
• Connect the series resistor R32 directly between the drain of Q4 and the VCC pin of
the IC. Use a separate copper track for this purpose
• Make the connection between MOSFET Q4 and the TEA1792 driver pin as short as
possible (green line in Figure 28). Use a guided ground track
• Make the connection between R50 and SWDET of the TEA1703 as short as possible
and place the resistor close to the IC
Remark: It is recommended to use the circuit shown in Figure 27 when the distance
between the IC drive output and corresponding MOSFET are relatively large.
input
IC
DRIVER
Rch
Dch
Qswitch
Qdch
2
GND
Rdch
Rsense
aaa-005304
Transistor is mounted close to the MOSFET with wide and short tracks.
See Section 7for the layout rules.
Fig 27. Switching off the MOSFET when the distance between IC and MOSFET is large
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GreenChip TEA1755 integrated PFC and flyback controller
F1
mains
inlet
LF1
R1
LF2
CX1
R2
BD1
-
L1
+
D1
L2
9
1
C1
C2
2
3
BC1
A
7
R18
12
1
C3
R6
R5
4a
R6B
R5A
R19
Q9
C5
D2
D3
B
switch signal
R31
Q1
R42
D4
R8
R9
C8
6c
R43
Q8
Q2
6b
R12
R14
R13
C9
R11
R16
C6
R16A
R10
C10
4
R15
R22
4b
C
R17
switch signal
C4
C23
7
7
7
PFCDRIVER
R27
13
FBSENSE
16
1
4
11
IC
3
12
8
7
2
6
5
GND
R3
E
C14
6b
10
D23A
R23A
HV
VOSENSE
9
R45
C13
VINSENSE
PFCAUX
14 15
D
D5
6b
6b
R23
VCC
FBAUX
FBCTRL
F
PFCCOMP
LATCH
PFCTIMER
PFCSENSE
HVS
U1
FBDRIVER
R7
6a
R26
R25
C17
4
C24
R4
C22
C21
C20
U2A-1
RT2
NTC
C19
C18
3
7
7
7
7
7
7
7
7
7
6c
7
large signal current loop
7
4
6a
6b
large signal current loop
large signal current loop
1
2
3
4a
4b
8
9
aaa-005268
Fig 28. PCB layout considerations (part 1)
AN11142
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T1
A
2
11
U3
D30
VCC
C30
4
SELREG
GND
B
TEA1792
4
2 6
n.c.
5
1
SRSENSE
DRIVER
1
3
R30
R32
Q4
Vout+
7, 8
C31
R33
D50
L4
R53
C
L3
1
R51
D
R57
5
C50
6
C51
R52
C52
C27
C29
U2A-2
R54
C28
2
9, 10
Vout-
E
CY1
VSENSE
3
PSENSE
1
8
U5
BC2
8
R50
SWDET
1
5 TEA1703 2
4
6
VCC
GND
OPTO
8
F
R34
R37
U2-2 1
Q7
R35
4
R24
U2-1
C15
C16
C34
2
3
C35
R36
U4
7
R38
D52
9
R55
C53
R56
8
019aab801
large signal current loop
large signal current loop
large signal current loop
Fig 29. PCB layout considerations (part 2)
AN11142
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8. Abbreviations
Table 7.
AN11142
Application note
Abbreviations
Acronym
Description
BM
Burst Mode
DCM
Discontinuous Conduction Mode
EMI
ElectroMagnetic Interference
FR
Frequency Reduction
HV
High Voltage
MHR
Mains Harmonics Reduction
OCP
OverCurrent Protection
OTP
OverTemperature Protection
OVP
OverVoltage Protection
PCB
Printed-Circuit Board
PFC
Power Factor Converter/Controller/Correction
QR
Quasi-Resonant
SMPS
Switched Mode Power Supply
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9. References
AN11142
Application note
[1]
TEA1755T — HV start-up DCM/QR flyback controller with integrated DCM/QR PFC
controller
[2]
TEA1755LT — HV start-up DCM/QR flyback controller with integrated DCM/QR
PFC controller
[3]
UM10514 — Notebook adaptor using the TEA1755
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10. Legal information
10.1 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
10.2 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
AN11142
Application note
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
10.3 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
GreenChip — is a trademark of NXP B.V.
All information provided in this document is subject to legal disclaimers.
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11. Contents
1
1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.3
2
3
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.5
3.6
3.7
4
4.1
4.1.1
4.1.2
4.2
4.2.1
4.3
4.3.1
4.3.2
4.3.3
4.3.4
5
5.1
5.1.1
5.1.1.1
5.1.1.2
5.1.1.3
5.1.1.4
5.1.1.5
5.1.2
5.1.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
The TEA1755 GreenChip controller . . . . . . . . . 3
Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
System features . . . . . . . . . . . . . . . . . . . . . . . . 4
PFC features . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Flyback features . . . . . . . . . . . . . . . . . . . . . . . . 4
Application schematic . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 7
System description and calculation. . . . . . . . 10
PFC and flyback start conditions . . . . . . . . . . 10
Initial start-up sequence . . . . . . . . . . . . . . . . . 10
VCC cycle in safe restart mode . . . . . . . . . . . . 12
Mains voltage sensing and brownout . . . . . . . 12
Discharging the mains input capacitor . . . . . . 12
Brownout voltage adjustment . . . . . . . . . . . . . 13
Minimizing the influence of the dark-current
of the optocoupler . . . . . . . . . . . . . . . . . . . . . . 13
Internal OverTemperature Protection (OTP). . 14
LATCH pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Fast-latch reset . . . . . . . . . . . . . . . . . . . . . . . . 15
PFC description and calculation . . . . . . . . . . 16
PFC output power and voltage control . . . . . . 16
Setting the PFC output voltage. . . . . . . . . . . . 18
Calculation of the PFC soft-start and
soft-stop components . . . . . . . . . . . . . . . . . . . 19
PFC demagnetizing and valley detection . . . . 20
Design of the PFCAUX winding and circuit . . 21
PFC protection modes . . . . . . . . . . . . . . . . . . 22
VOSENSE overvoltage protection . . . . . . . . . 22
VOSENSE open and short pin detection . . . . 22
VINSENSE open pin detection . . . . . . . . . . . . 22
Overcurrent protection . . . . . . . . . . . . . . . . . . 22
Flyback description and calculation . . . . . . . 24
Flyback output power control . . . . . . . . . . . . . 24
Four TEA1755 operation modes . . . . . . . . . . 25
Quasi-resonant mode . . . . . . . . . . . . . . . . . . . 25
Discontinuous conduction mode. . . . . . . . . . . 26
Frequency reduction mode and PFC
switch on/switch off control . . . . . . . . . . . . . . . 27
Burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
VCC undervoltage protection during burst
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
The relationship between inductance value
and the PFC hysteresis . . . . . . . . . . . . . . . . . 29
Relationship between Ipk(min) and the required
PFC(swon)/PFC(swoff) level . . . . . . . . . . . . . 32
5.1.4
5.1.4.1
5.1.4.2
5.1.4.3
5.1.4.4
5.1.5
5.1.6
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
6
7
8
9
10
10.1
10.2
10.3
11
The influence of Rsense and the R16/R17
series resistance . . . . . . . . . . . . . . . . . . . . . .
Calculating the flyback transformer saturation
current Isat . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculation of Ipk(max) for flyback operating
in Quasi-resonant mode. . . . . . . . . . . . . . . . .
Calculation of the current sense resistor
Rsense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculation of the series resistance R16
and R17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculation of the delay compensation
resistors Rcomp and R16A . . . . . . . . . . . . . . .
Calculation of the flyback soft-start
components . . . . . . . . . . . . . . . . . . . . . . . . . .
Two PFCTIMER pin options. . . . . . . . . . . . . .
Option 1: adjustable PFC(swoff) time . . . . . .
Option 2: Overriding the PFC(swon) and
PFC(swoff) functions . . . . . . . . . . . . . . . . . . .
Flyback protection mode . . . . . . . . . . . . . . . .
Short-circuit on the FBCTRL pin . . . . . . . . . .
Open FBCTRL pin . . . . . . . . . . . . . . . . . . . . .
Time-out flyback control loop . . . . . . . . . . . . .
Overvoltage protection flyback. . . . . . . . . . . .
OverPower Protection (OPP). . . . . . . . . . . . .
Summary of calculations for flyback
adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB layout considerations . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
34
35
36
36
37
39
39
39
41
43
43
43
43
44
46
49
52
56
57
58
58
58
58
59
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 12 November 2012
Document identifier: AN11142
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