Application Notes

AN10861
GreenChip III TEA1752 integrated PFC and flyback controller
Rev. 01 — 16 July 2010
Application note
Document information
Info
Content
Keywords
GreenChip III, TEA1752, PFC, flyback, high efficiency, adaptor, notebook,
PC power
Abstract
The TEA1752 is a member of the new generation of PFC and flyback
combination controller ICs, used for efficient switched mode power
supplies. It has a high level of integration which allows the design of a
cost-effective power supply with a minimum number of external
components. The TEA1752 is fabricated in a Silicon On Insulator (SOI)
process, enabling it to operate a wide voltage range.
AN10861
NXP Semiconductors
GreenChip III TEA1752 integrated PFC and flyback controller
Revision history
Rev
Date
Description
01
20100716
First issue
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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GreenChip III TEA1752 integrated PFC and flyback controller
1. Introduction
The TEA1752 is a combination controller with a PFC and flyback controller integrated into
an SO-16 package. Both controllers operate in Quasi-Resonance (QR) mode and in
Discontinuous Conduction Mode (DCM) with valley detection. Both controllers are
switched independently.
The PFC output power is on-time controlled for simplicity. It is not necessary to sense the
phase of the mains voltage. The flyback output power is current mode controlled for good
suppression of the input voltage ripple.
The communication circuitry between the controllers is integrated and no adjustment is
needed.
The voltage and current levels mentioned in this application note are typical values. A
detailed description of the pin level spreading can be found in the TEA1752T_LT data
sheet.
1.1 Scope
This application note describes the functionality of the TEA1752 and the adjustments
needed within the power converter application.
The large signal parts of the PFC and the flyback power stages, the design and the data
for the coil and the transformer are dealt with in a separate application note.
1.2 The TEA1752 GreenChip III controller
The features of the GreenChip III allow a power supply engineer to design a reliable,
cost-effective and efficient switched mode power supply with a minimum number of
external components.
1.2.1 Key features
•
•
•
•
•
•
PFC and flyback controller integrated in one SO-16 package
Switching frequencies of PFC and flyback are independent of each other
No external hardware required for the communication between both controllers
High level of integration, resulting in minimal external component count
Integrated mains voltage enable and brownout protection
Fast latch reset function implemented
1.2.2 System features
•
•
•
•
•
•
•
AN10861
Application note
Safe restart mode for system fault conditions
High voltage start-up current source (5.4 mA)
Reduction of HV current source (1 mA) in Safe restart mode
Wide VCC range (38 V)
MOSFET driver voltage limited
Easy control of start-up behavior and VCC circuit
General purpose input for latched protection
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• Internal IC overtemperature protection
• One high-voltage spacer between the HV pin and the next active pin
• Open pin protection on the VINSENSE, VOSENSE, PFCAUX, FBCTRL and FBAUX
pins
1.2.3 PFC features
• Dual output voltage boost converter
• QR/DCM operation with valley switching
• Frequency limitation (250 kHz) to reduce switching losses and ElectroMagnetic
Interference (EMI)
•
•
•
•
•
ton controlled
Mains input voltage compensation for control loop for good transient response
OverCurrent Protection (OCP)
Soft start and soft stop
Open/short detection for PFC feedback loop: no external Overvoltage Protection
(OVP) circuit necessary
• Adjustable delay for turning off the PFC
1.2.4 Flyback features
• QR/DCM operation with valley switching
• Frequency Reduction (FR) with fixed minimum peak current and valley switching to
maintain high efficiency at low output power levels without audible noise
•
•
•
•
•
•
Frequency limitation (125 kHz) to reduce switching losses and EMI
Current mode controlled
Overcurrent protection
Soft start
Accurate OVP through auxiliary winding
Time-out protection for output overloads and open flyback feedback loop, available as
safe restart (TEA1752T) or latched (TEA1752LT) protection
1.3 Application schematic
Figure 1 shows the complete functional schematic of the TEA1752 application.
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C2
12
1
BC1
T1
2
R5
C3
−
VCC
GND
1
R6
8
TEA1791
C30
4
R5A
D2
2 4
D4
Q1
R8
R9
R18
U3
D30
D3
C5
LF2
C8
11
1
R6A
Q2
R14
R13
C9
CX1
R12
n.c.
5
n.c.
6
n.c.
7
n.c.
R30
R32
R11
R16
R1
3
SRSENSE
C1
7
DRIVER
+
BD1
D1
L2
9
R2
C6
Q4
R16A
Vout +
R10
C10
7, 8
R15
R33
L3
C31
C27
R17
BC2
PFCDRIVER
R27
PFCAUX
C25
VCC
HV
FBSENSE
10
16
1
OPTIONAL
see section 5.2, 5.2.1
Application schematic
R20
R23
4
3
7
VINSENSE
2
6
5
R34
R37
FBAUX
FBCTRL
4
C21
C20
C19
PFCCOMP
1
C34
R24
R35
C15
3
2
C35
R36
R25
RT2
NTC
Θ
R4
D23A
U2
8
C29
Vout −
C12 6
TEA1752
Q3
C22
R23A
12
R29
C24
Fig 1.
13
C13
C14
11
R3
R28
9
C23
LATCH
PFCSENSE
CY1
14 15
FBDRIVER
U1
PFCTIMER
VOSENSE
Θ
C4
GND
mains
inlet
RT1
NTC
C28
5
HVS
R7
9, 10
D5
C17
U4
R38
R26
C18
C16
019aaa027
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GreenChip III TEA1752 integrated PFC and flyback controller
Rev. 01 — 16 July 2010
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LF1
F1
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GreenChip III TEA1752 integrated PFC and flyback controller
2. Pin description
Table 1.
Pin description
Pin
Name
Functional description
1
VCC
Supply voltage: Vstartup = 22 V, Vth(UVLO) = 15 V.
At mains switch-on, the capacitor connected to this pin is charged to Vstartup
by the internal HV current source. When the pin voltage is lower than 0.65 V,
the charge current is limited to 1 mA to prevent overheating of the IC if the
VCC pin is short-circuited. When the pin voltage is between 0.65 V and
Vth(UVLO), the charge current is 5.4 mA to enable a fast start-up. When it is
between Vth(UVLO) and Vstartup, the charge current is limited to 1 mA again to
reduce the safe restart duty cycle. This results in a reduction of the input
power during fault conditions. When Vstartup is reached, the HV current
source is pinched off and VCC is regulated to Vstartup until the flyback starts.
See Section 3.2 for a complete description of the start-up sequence.
2
GND
3
FBCTRL
Ground connection.
Control input for flyback for direct connection of the optocoupler.
At a control voltage of 2 V the flyback delivers maximum power. At a control
voltage of 1.5 V the flyback enters the Frequency reduction mode. At 1.3 V
the flyback stops switching. There is an internal 30 μA current source
connected to the pin, which is controlled by the internal logic. This current
source can be used to implement a time-out function to detect an open
control loop or a short circuit of the output voltage. The time-out function can
be disabled with a resistor of 100 kΩ between this pin and ground.
4
FBAUX
Input from auxiliary winding for transformer demagnetization detection,
mains dependent OverPower Protection (OPP) and OverVoltage Protection
(OVP) of the flyback.
The combination of the demagnetization detection and the valley detection
at pin HV determines the switch-on moment of the flyback in the valley. A
flyback OVP is detected at a current higher than 300 μA to the FBAUX pin.
Internal filtering prevents false detection of an OVP. The flyback OPP starts
at a current lower than −100 μA from the FBAUX pin.
5
LATCH
General purpose latched protection input.
When Vstartup (on pin 1) is reached, this pin is charged to 1.35 V before the
PFC and the flyback can be enabled. The latched protection is triggered
when the pin is pulled below 1.25 V and the PFC and the flyback are
disabled.
An internal 80 μA current source is connected to the pin, which is controlled
by the internal logic. Because of this current source, a
Negative Temperature Coefficient (NTC) resistor for temperature protection
can be directly connected to this pin.
6
PFCCOMP
Frequency compensation pin for the PFC control loop.
7
VINSENSE
Sense input for mains voltage. This pin has five functions:
•
•
•
•
•
mains enable level: Vstart(VINSENSE) = 1.15 V;
mains stop level (brownout): Vstop(VINSENSE) = 0.89 V;
mains voltage compensation for the PFC control loop gain bandwidth;
fast latch reset: Vflr = 0.75 V;
dual boost switchover point: Vbst(dual) = 2.2 V.
The voltage on pin VINSENSE must be an averaged DC value, representing
the AC line voltage. The pin is not used for sensing the phase of the mains
voltage.
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GreenChip III TEA1752 integrated PFC and flyback controller
Table 1.
Pin description …continued
Pin
Name
Functional description
8
PFCAUX
Input from an auxiliary winding of the PFC coil for demagnetization timing
and valley detection to control PFC switching.
The auxiliary winding needs to be connected via a 5 kΩ series resistor to
prevent damage to the input because of lightning surges.
9
VOSENSE
Sense input for the output voltage of the PFC.
VOSENSE pin, open-loop and short circuit detection:
Vth(ol)(VOSENSE) = 1.15 V;
Regulation of the PFC output voltage: Vreg(VOSENSE) = 2.5 V;
PFC soft OVP (cycle-by-cycle): Vovp(VOSENSE) = 2.63 V;
Control output for the output voltage of the PFC:
- dual boost current: Ibst(dual) = −15 μA.
10
FBSENSE
Current sense input for flyback.
At this pin the sum of three voltages across three resistors is measured.
Selecting the proper resistor values:
•
•
•
Prevents or minimizes the risk of saturation of the flyback transformer;
Allows some adjustment for enabling or disabling the PFC;
Allows a system that operates line voltage independently.
The maximum setting level for Vsense(fb)max is 0.63 V at dV/dt = 0 mV/μs.
The level of Vsense(fb)min is 0.30 V at dv/dt = 0 mV/μs and is related to the
fixed peak current through the flyback transformer when the flyback is
running in Frequency reduction mode. There are two internal current
sources connected to this pin, Istart(soft)fb and Iadj(FBSENSE).
Istart(soft)fb is an internal current source of 60 μA, which is controlled by the
internal logic. The current source is used to implement a soft start function
for the flyback. The flyback only starts when the internal current source can
charge the soft start capacitor to a voltage of more than 0.63 V. Therefore a
minimum soft start resistor of 16 kΩ is required to guarantee the enabling of
the flyback. The current source Iadj(FBSENSE) is 3 μA. It is intended to support
the adjustment for enabling and disabling the PFC.
11
PFCSENSE
Overcurrent protection input for PFC.
This input is used to limit the maximum peak current in the PFC core. The
PFCSENSE is a switching-cycle-by-switching-cycle protection. When it
reaches 0.52 V at dV/dt = 50 mV/μs the PFC MOSFET is switched off.
An internal 60 μA current source is connected to this pin, which is controlled
by the internal logic. This current source is used to implement a soft start
and soft stop function for the PFC to prevent audible noise. The PFC only
starts when the internal current source can charge the soft start capacitor to
a voltage of more than 0.5 V. A soft start resistor of at least 12 kΩ is required
to guarantee the enabling of the PFC.
AN10861
Application note
12
PFCDRIVER
Gate driver output for PFC MOSFET.
13
FBDRIVER
Gate driver output for flyback MOSFET.
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Table 1.
Pin description …continued
Pin
Name
Functional description
14
PFCTIMER
Timer pin to delay the turning off of the PFC when the load of the flyback is
removed or minimized.
The PFC is enabled when the voltage across this pin is low (≤ 1.27 V). It is
disabled when the voltage is high (≥ 3.6 V).
15
HVS
High-voltage safety spacer, not connected.
16
HV
High-voltage input for the internal start-up current source (output at pin 1)
and valley sensing of the flyback.
The combination of the demagnetization detection at the FBAUX pin and the
valley detection at the HV pin determine the switch-on moment of the
flyback in the valley.
3. System description and calculation
3.1 PFC and flyback start conditions
Figure 2 and Figure 3 show the conditions for enabling the PFC and the flyback. If start-up
problems occur these conditions can be checked to find the cause of the problem. Some
of the conditions are dynamic signals (see Figure 4) and should be checked with an
oscilloscope.
LATCH > 1.35 V
LATCH > 1.35 V
PFCSENSE (soft start) > 0.5 V
FBSENSE (soft start) > 0.63 V
VINSENSE > 1.15 V
AND
enable PFC
AND
VOSENSE > 1.15 V
enable flyback
VOSENSE > 1.15 V
PFCCOMP > 3.5 V
FBCTRL < 4.5 V
fsw(fb)swon(PFC) > 86 kHz
019aaa028
Fig 2.
PFC start condition
019aaa029
Fig 3.
Flyback start conditions
3.2 Start-up sequence
At switch-on with a low mains voltage the TEA1752 power supply has the following
start-up sequence (see Figure 4):
1. The HV current source is set to 1.0 mA and the VCC elcap is charged to 0.65 V to
detect a possible short circuit at pin VCC.
2. At VCC = 0.65 V, the HV current source is set to 5.4 mA and the VCC elcap is quickly
charged to Vth(UVLO).
3. At VCC = Vth(UVLO), the HV current source is set to 1.0 mA again and the VCC elcap is
charged to Vstartup.
4. At Vstartup, the HV current source is switched off and the 80 μA LATCH pin current
source is switched on to charge the LATCH pin capacitor. At the same time the
PFCSENSE and FBSENSE soft start current sources are switched on.
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5. When the LATCH pin is charged to 1.35 V the PFC and the flyback can start
switching, but only when the VINSENSE pin has reached a level of 1.15 V.
6. Four extra conditions have to be met for enabling the PFC: The soft start capacitor at
pin PFCSENSE must be charged to 0.5 V, the voltage on the VOSENSE pin must be
greater than 1.15 V, the capacitors connected to the PFCCOMP pin should be
charged to 3.5 V and fsw(fb)swon(PFC) must be greater than 86 kHz.
Remark: The last condition is automatically met by the TEA1752 during (initial)
start-up. This can be measured at the PFCTIMER pin. It is internally forced down to a
low voltage, which means that the PFC is enabled.
7. The soft start capacitor at pin FBSENSE must be charged to 0.63 V and the voltage
on pin FBCTRL must be lower than 4.5 V to enable the flyback. Normally, the voltage
on pin FBCTRL is lower than 4.5 V at the first flyback switching cycle, unless the
FBCTRL pin is open. When the flyback starts, the FBCTRL time-out current source is
switched on.
8. When the flyback has reached its nominal output voltage, the VCC supply of the IC is
taken over by the auxiliary winding. If the flyback feedback loop signal is missing, the
time-out protection at the FBCTRL pin is triggered, both converters are switched off,
VCC drops to Vth(UVLO) and the IC continues with step 3 of the start-up cycle. This is
the safe restart cycle.
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IHV
Vstartup
Vth(UVLO)
Vtrip
VCC
Vstart(VINSENSE)
VINSENSE
Ven(PFCCOMP)
PFCCOMP
Ven(LA TCH)
LATCH
PROTECTION
soft start
PFCSENSE
PFCDRIVER
soft start
FBSENSE
FBDRIVER
Vto(FBCTRL)
FBCTRL
Vstart(fb)
VOSENSE
VO
charging VCC
capacitor
Fig 4.
starting
converters
normal
operation
protection
restart
019aaa030
Start-up sequence at low mains voltage
The charge time of the soft start capacitors can be chosen independently for the PFC and
the flyback, based on their values.
3.3 VCC cycle in safe restart protection mode
In Safe restart mode the controller goes through the steps 3 to 8 as described in
Section 3.2.
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3.4 Mains voltage sensing and brownout
The mains input voltage is measured through the VINSENSE pin. When the VINSENSE
pin has reached Vstart(VINSENSE) (1.15 V) the PFC can start switching, but only if the other
start conditions are met as well, see Section 3.1. As soon as the voltage on pin
VINSENSE drops below Vstop(VINSENSE) (0.89 V), the PFC stops switching. The flyback
however, continues switching until its maximum on-time protection, ton(fb)max (40 μs) is
triggered. When this protection is triggered, the IC stops switching and enters Safe restart
mode.
The voltage on pin VINSENSE must be an average DC value, representing the mains
input voltage. The system works optimally with a time constant of approximately 150 ms at
the VINSENSE pin. The high time constant on pin VINSENSE prevents a fast restart of
the PFC after a mains dropout, therefore the voltage at the VINSENSE pin is clamped to
100 mV below the Vstart(VINSENSE) level. This guarantees a fast PFC restart after recovery
of the mains input voltage.
R1
mains
inlet
−
CX1
BD1
+
C1
R2
R3
VINSENSE
R4
7
C20
TEA1752
2
GND
019aaa031
Fig 5.
VINSENSE circuitry
3.4.1 Discharge of mains input capacitor
The X-capacitors in the ElectroMagnetic Compatibility (EMC) input filtering must be
discharged with a time constant of τ < 1 second for safety reasons (see Ref. 1).
In a typical 90 W adapter application with CX1 = 220 nF, the replacement value resistor
value RV is determined by:
R × ( R3 + R4 )
R V = R + -------------------------------R + R3 + R4
(1)
Where:
• R = R1 = R 2
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The value of RV must be lower than or equal to the following:
τ
1
R V ≤ ------------ = ------------------ = 4.55 MΩ
CX1
220 nF
3.4.2 Brownout voltage adjustment
The rectified AC input voltage is measured via R1 and R2. Each resistor alternately
senses half the sine wave, so both resistors must have the same value. The average
voltage sensed at the connection of R1 and R2 is calculated with Equation 2:
2× 2
V avg = ---------------- ⋅ V acrms
π
(2)
The V (AC) brownout RMS level is calculated with Equation 3:
( RV + R3 + R4 )
π
V brownout ( AC ) = ---------------- × V stop ( VINSENSE ) × -----------------------------------R4
2× 2
(3)
Where: Vstop(VINSENSE) = 0.89 V
At a brownout threshold of 68 V (AC) and in compliance with IEC-60950 chapter 2.1.1.7
"discharge of capacitors in equipment" (Ref. 1). Example values are shown in Table 2.
Table 2.
VINSENSE component values
CX1
R1
R2
R3
R4
220 nF
2 MΩ
2 MΩ
560 kΩ
47 kΩ
330 nF
1.5 MΩ
1.5 MΩ
820 kΩ
47 kΩ
470 nF
1 MΩ
1 MΩ
1.1 MΩ
47 kΩ
A value of 3.3 μF for capacitor C20, with 47 kΩ at R4, gives the recommended time
constant of ~150 ms at the VINSENSE pin.
3.5 Internal Overtemperature Protection (OTP)
The IC has an internal temperature protection to protect the IC from overheating by
overloads at the VCC pin. When the junction temperature exceeds the thermal shutdown
temperature, the IC stops switching. As long as the OTP is active, the VCC capacitor is not
recharged from the HV mains. The OTP circuit is supplied from the HV pin if the VCC
supply voltage is not sufficient. The OTP is a latched protection.
3.6 LATCH pin
The LATCH pin is a general purpose input pin, which can be used to latch both converters
off. The pin sources a bias current IO(LATCH) of 80 μA for the direct connection of an NTC.
When the voltage on this pin is pulled below 1.25 V, switching of both converters is
stopped immediately and VCC starts cycling between the Vth(UVLO) and Vstartup without a
restart. Switching off and then switching on the mains input voltage triggers the fast latch
reset circuit and resets the latch (see Section 3.7).
At start-up, the LATCH pin has to be charged to above 1.35 V before both converters can
be enabled. Charging of the LATCH pin starts when VCC = Vstartup.
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No internal filtering is present at the LATCH pin. A 10 nF capacitor must be placed
between this pin and the IC GND pin to prevent false triggering, also when the LATCH pin
function is not used.
TEA1752
5
LATCH
RT2
2
C19
Θ
4
1
3
2
U1
GND
R26
019aaa032
Fig 6.
Usage of the LATCH pin protection
Latching on application overtemperature occurs when the total resistance value of the
NTC and its series resistor drops below the following:
V prot ( LATCH )
1.25 V = 15.6 kΩ
= --------------R OTP = ------------------------------80 μA
I O ( LATCH )
(4)
The optocoupler triggers the latch if the driven optotransistor conducts more than 80 μA.
3.7 Fast latch reset
Switching off and then switching on the mains input voltage resets the latched protection.
After the mains input is switched off, the voltage on pin VINSENSE drops below Vflr
(0.75 V). This triggers the fast latch reset circuit, but does not reset the latched protection.
After the mains input is switched on, the voltage on pin VINSENSE rises again. The latch
is reset when the level has passed 0.85 V. The system restarts when the VCC pin is
charged to Vstartup (See step 4 of Section 3.2).
4. PFC description and calculation
The PFC operates in QR mode or DCM mode with valley detection to reduce the
switch-on losses. The maximum switching frequency of the PFC is limited to 250 kHz to
reduce switching losses. If necessary, one or more valleys are skipped to keep the
frequency below 250 kHz.
The PFC of the TEA1752 is designed as a dual boost converter with two output voltage
levels that are dependent on the mains input voltage range. The advantage is that the
overall system efficiency at low mains is improved because of the reduction of the PFC
switching losses. In low and medium power adapters (< 120 W) the contribution of PFC
switching losses to the total losses is relatively high.
The dual output voltage is controlled by an internal current source of 15 μA at pin
VOSENSE. As shown in Figure 7, the mains input voltage measured at pin VINSENSE is
used to control the internal current source. This current source, in combination with the
resistors at pin VOSENSE, sets the lower PFC output voltage. At high mains, the current
source is switched off. Therefore, the maximum PFC output voltage is not affected by the
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accuracy of the current source. In a typical adapter with a PFC output voltage of
385 V (DC) at high mains, the PFC output voltage is 250 V (DC) at low mains. A voltage of
2.2 V at pin VINSENSE corresponds with a mains input voltage of approximately
180 V (AC). The small slope at the transfer function ensures a stable switchover of the
PFC output voltage without hiccups.
2.2 V
0
VVINSENSE
−15 μA
II(VOSENSE)
Fig 7.
019aaa033
Transfer function of VINSENSE voltage to dual boost current at VOSENSE
The PFC is switched off to ensure high efficiency during low output currents and standby
(no output current). After switch-off the bulk elcap voltage drops to line voltage × 2 .
4.1 PFC output power and voltage control
The PFC of the TEA1752 is on-time controlled, therefore it is not necessary to measure
the mains phase angle. The on-time is kept constant during the half sine wave to obtain a
good Power Factor (PF) and a class-D Mains Harmonics Reduction (MHR).
The PFC output voltage is controlled through the VOSENSE pin. At the VOSENSE pin
there is a transconductance error amplifier with a reference voltage of 2.5 V. The error at
the VOSENSE pin is converted with 80 μA/V to a current on pin PFCCOMP. The voltage
on pin PFCCOMP, in combination with the voltage on pin VINSENSE, determines the PFC
on-time.
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GreenChip III TEA1752 integrated PFC and flyback controller
ramp oscillator
Idischarge
VM +
−
TEA1752
C
S
voltage
comparator
Icharge
V−
current
multiplier
VVINSENSE 7
VR
V+
V/I
TRANSDUCER
VS
I2
Q
12
VPFCDRIVER
S
I1
Vosc
VPFCSENSE 11
R
I2
Vp
transconductance
amplifier
ton limiting
circuit
ICOMP
+
− VREF
R1
PFC
OSCILLATOR
VALLEY
DETECTION
VVALLEY
6
8
VPFCCOMP
VPFCAUX
C2
compensation
network
C1
019aaa034
Fig 8.
PFC on-time control
A network with one resistor and two capacitors at the PFCCOMP pin is used to stabilize
the PFC control loop. The mathematical equation for the transfer function of a boost
converter contains the square of the mains input voltage. In a typical application this
results in a low regulation bandwidth for low mains input voltages and a high regulation
bandwidth at high input voltage. The result might be that at high mains input voltages it
can be difficult to meet the MHR requirements. The TEA1752 uses the mains input
voltage measured through the VINSENSE pin to compensate the control loop gain as a
function of the mains input voltage. As a result the gain is constant over the entire mains
input voltage range.
The voltage at the VINSENSE pin must be an average DC value, representing the mains
input voltage. The system works optimally with a time constant of approximately 150 ms at
the VINSENSE pin.
4.1.1 Setting the PFC output voltage
The PFC output voltage is set with a resistor divider between the PFC output voltage and
the VOSENSE pin. In Normal mode, the PFC output voltage is regulated so that the
voltage on the VOSENSE pin is equal to V reg ( VOSENSE ) = 2.5 V .
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GreenChip III TEA1752 integrated PFC and flyback controller
D1
PFC stage
VO(PFC)
C3
R5
VINSENSE
2.2 V
1.5 μA
R6
place C4 and R7
as close as
possible to the IC
9 VOSENSE
TEA1752
2
C4
R7
GND
019aaa035
Fig 9.
PFC output voltage setting
Two resistors of 4.7 MΩ (1 %) can be used between the bulk elcap and the
VOSENSE pin. The dimensioning of the Ibst(dual) current source (−15 μA) has been
adapted to the use of these resistor values. With a resistor value of 4.7 MΩ for R5 and R6
and 60 kΩ to 62 kΩ for R7 a universal mains adapter has a PFC output voltage of
approximately 380 V to 390 V at high mains and 240 V to 250 V at low mains.
The resistor R7 (1 %) between the VOSENSE pin and ground can be calculated with
Equation 5:
( R5 + R6 ) × V reg ( VOSENSE )
R7 = -----------------------------------------------------------------( V O ( PFC ) – V reg ( VOSENSE ) )
(5)
Example with a regulated PFC output voltage of 382 V:
4.7 MΩ + 4.7 MΩ ) × 2.5 V = 62 kΩ ( 1 % )
R7 = (--------------------------------------------------------------------( 382 V – 2.5 V )
At low mains the 15 μA current source Ibst(dual) is active. The lower PFC output voltage can
be calculated with Equation 6:
R5 + R6 + R7
V O ( PFC )low = --------------------------------- ⋅ ( V reg ( VOSENSE ) – I bst ( dual ) ⋅ R7 )
R7
(6)
Example for calculating the lower PFC output voltage:
• R5 and R6 = 4.7 MΩ
• R7 = 62 kΩ
4.7 MΩ + 4.7 MΩ + 62 kΩ
V O ( PFC )low = -------------------------------------------------------------------- ⋅ ( 2.5 V – 15 μA ⋅ 62 kΩ ) = 240 V
62 kΩ
The function of capacitor C4 at the VOSENSE pin is to filter noise and to prevent false
triggering of the protection modes because of MOSFET switching noise, mains surge
events or ElectroStatic Discharge (ESD) events. False triggering of the Vovp(VOSENSE)
protection can cause audible noise and disturbance of the AC mains input current. False
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GreenChip III TEA1752 integrated PFC and flyback controller
triggering of the Vth(ol)(VOSENSE) protection causes a safe restart cycle. A time constant of
500 ns to 1 ms at the VOSENSE pin should be sufficient, which results in a value of 10 nF
for capacitor C4.
It is advisable to place R7 and C4 as close as possible to the IC between the VOSENSE
pin and the IC GND pin.
4.1.2 Calculation of the PFC soft start and soft stop components
The soft start and soft stop are implemented through the RC network at the PFCSENSE
pin.
RSS1 must have a minimum value of 12 kΩ to ensure that the voltage Vstart(soft)PFC of 0.5 V
is reached to enable the start-up of the PFC. See Section 3.2 for a description of start-up.
Istart(soft)PFC ≤ 60 μA
Q1
RSS1
SOFT START
SOFT STOP
CONTROL
11
PFCSENSE
CSS1
OCP
0.5 V
Rsense
TEA1752
019aaa036
Fig 10. PFC soft start and soft stop
The total soft start or soft stop time is: t softstart = 3 × R SS1 × C SSI
It is advised to keep the soft start time of the PFC shorter than the soft start time of the
flyback. It is also advised that the soft start time is kept within a range of 2 ms to 5 ms.
With C6 = 100 nF and R11 = 12 kΩ, the total soft start time is 3.6 ms.
4.2 PFC demagnetizing and valley detection
The PFC MOSFET is switched on after the transformer is demagnetized. The internal
circuitry connected to the PFCAUX pin detects the end of the secondary stroke. It also
detects the voltage across the PFC MOSFET. The next primary stroke is started when the
voltage across the PFC MOSFET is at its minimum in order to reduce switching losses
and electromagnetic interference (EMI) (valley switching).
The maximum switching frequency of the PFC is limited to 250 kHz to reduce the
switching losses. If necessary, one or more valleys are skipped to keep the frequency
below 250 kHz.
If no demagnetization signal is detected on pin PFCAUX, the controller generates a Zero
Current Signal (ZCS) 50 μs after the last PFC gate signal. If no valley signal is detected
on this pin, the controller generates a valley signal 4 μs after demagnetization was
detected.
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GreenChip III TEA1752 integrated PFC and flyback controller
L1
9
C1
C2
L2
D1
7
C3
1
5
Q1
R27
PFCDRIVER
12
PFCAUX
TEA1752
8
2
GND
019aaa037
Fig 11. PFCAUX circuitry
4.2.1 Design of the PFCAUX winding and circuit
It is advised to set the voltage on pin PFCAUX as high as possible, but still within the
absolute maximum voltage rating of ± 25 V. Doing this improves the valley detection at
low ringing amplitudes.
Taking into account its absolute maximum rating of ± 25 V, the voltage on pin PFCAUX
must be set as high as possible to guarantee valley detection at low ringing amplitudes.
The number of turns of the PFCAUX winding can be calculated with Equation 7:
V PFCAUX
25 V
N aux_max = ---------------------- × N p = -------------- × N p
V Lmax
V Lmax
(7)
• VPFCAUX is the absolute maximum rating of the PFCAUX pin
• VLmax is the maximum voltage across the PFC primary winding
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GreenChip III TEA1752 integrated PFC and flyback controller
The PFC output voltage at the PFCOVP level determines the maximum voltage across the
PFC primary winding and can be calculated with Equation 8:
V ovp ( VOSENSE )
2.63 V
V Lmax = ------------------------------------ × V O ( PFC ) = ---------------- × V O ( PFC )
2.5 V
V reg ( VOSENSE )
(8)
When a PFC coil with a higher number of auxiliary turns is used, a resistor voltage divider
can be placed between the auxiliary winding and pin PFCAUX. The total resistive value of
the divider should be lower than 10 kΩ to prevent delay of the valley detection by parasitic
capacitance.
The polarity of the signal at the PFCAUX pin must be reversed compared to the PFC
MOSFET drain signal.
It is recommended to have a 5 kΩ resistor between the PFC auxiliary winding and pin
PFCAUX to protect the pin against electrical overstress, for example, during lightning
surge events. This resistor should be placed as close as possible to the IC to prevent
incorrect valley switching of the PFC because of external disturbances.
4.3 PFC protection modes
4.3.1 VOSENSE overvoltage protection
Overvoltage can occur across the bulk elcap during the initial start-up and large load
changes. This overvoltage is caused by the relative slow response of the PFC control
loop. The PFC control loop response must be relatively slow to guarantee a good power
factor and meet the MHR requirements. The OverVoltage Protection (OVP) at the
VOSENSE pin limits the overvoltage. When the Vovp(VOSENSE) level of 2.63 V is detected,
the PFC MOSFET is switched off immediately regardless of the on-time setting. The
switching of the MOSFET remains blocked until the voltage on pin VOSENSE drops
below 2.63 V again.
When the resistor between the VOSENSE pin and ground is open, the OVP is also
triggered.
The peak voltage across the bulk elcap generated by the PFC because of an overshoot
and limited by the PFC OVP can be calculated with Equation 9:
V ovp ( VOSENSE )
2.63 V
V O ( PFC )peak = ------------------------------------ ⋅ V O ( PFC )nominal = ---------------- ⋅ V O ( PFC )nominal
2.5 V
V reg ( VOSENSE )
(9)
4.3.2 VOSENSE open and short pin detection
The VOSENSE pin, which is sensing the PFC output voltage, has an integrated protection
circuit to detect an open and short circuited pin. This pin can also sense that one of the
resistors in the voltage divider is open. Therefore the VOSENSE pin is completely
fail-safe. It is not necessary to add an external OVP circuit for the PFC. An internal current
source pulls the pin down to below the Vth(ol)(VOSENSE) detection level (1.15 V) when the
pin is open. When Vth(ol)(VOSENSE) is detected, level switching of the PFC and the flyback
MOSFETs is blocked until the voltage on pin VOSENSE rises to above 1.15 V again.
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GreenChip III TEA1752 integrated PFC and flyback controller
4.3.3 VINSENSE open pin detection
The VINSENSE pin, which senses the mains input voltage, has an integrated protection
circuit for detecting an open pin. An internal current source pulls the pin down to below
Vstop(VINSENSE) (0.89 V) when the pin is open.
4.3.4 Overcurrent protection
The overcurrent protection limits the maximum current through the PFC MOSFET and
PFC coil. The current is measured via a current sense resistor in series with the MOSFET
source. The MOSFET is switched off immediately when the voltage at pin PFCSENSE
exceeds the Vsense(PFC)max level of 0.52 V at dV/dt = 50 mV/μs. The OCP is a
switching-cycle-by-switching-cycle protection.
It is recommended to take into account a margin of 0.1 V to avoid false triggering of the
PFC OCP by switching of the flyback. False triggering of the Vsense(PFC)max protection can
cause disturbances to the AC mains input current. It is also advised that a small capacitor
between 100 pF and 220 pF is placed directly at the PFCSENSE pin to suppress external
disturbance.
The current sense resistor can be calculated with Equation 10:
V sense ( PFC )max – V m arg in
0.52 V – 0.1 V
R OCP ( PFC ) = ------------------------------------------------------------ = ----------------------------------I pQR ( PFC )max
I pQR ( PFC )max
(10)
Where: IpQR(PFC)max is the maximum PFC peak current at the high load and low mains.
The maximum peak current for the PFC operating in Quasi-resonant mode can be
calculated with Equation 11:
I pQR ( PFC )max
P o ( max )
2 2 ⋅ ------------------ ⋅ 1.1
2 2 ⋅ P i ( max ) ⋅ 1.1
η
= -------------------------------------------- = -------------------------------------------Vac min
Vac min
(11)
Where:
• Po(max) is the maximum output power of the flyback
• 1.1 is a factor to compensate for the dead time between zero current in the PFC
inductor at the end of the secondary stroke and the detection of the first valley in
Quasi-resonant mode
• η is the expected efficiency of the total converter at maximum output power
• Vacmin is minimum mains input voltage.
5. Flyback description and calculation
5.1 Flyback output power control
An important aspect of the TEA1752 flyback system is that it waits until the transformer is
demagnetized and at least one valley has appeared before it is magnetized again for the
next cycle. The FBAUX pin detects demagnetization via the auxiliary winding. The HV pin
detects the bottom of the valley via the drain of the MOSFET or the central tap of the
primary winding.
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GreenChip III TEA1752 integrated PFC and flyback controller
The output power (PO) of the flyback can be calculated with Equation 12:
1
2
P O = --- ⋅ L p ⋅ I p ⋅ fs ⋅ η
2
(12)
Where:
•
•
•
•
Lp stands for the primary inductance of the flyback transformer
Ip stands for the peak current through the flyback transformer
fS stands for operating frequency of the flyback
η stands for the efficiency of the flyback
Lp is selected at the start of the design, so the setting of the primary peak current controls
the output power. The switching frequency is a result of external application parameters
and internal IC parameters.
External application parameters are the transformer turns ratio, the primary inductance,
the drain source capacitance, the input voltage, the output voltage and the feedback
signal from the control loop. Internal IC parameters are the oscillator setting, the setting of
the peak current and the detection of demagnetization and valley.
Another logical method of controlling the output power is keeping the primary peak current
Ip fixed and changing the operating frequency. Output power and operating frequency are
linearly related during this type of control. This method is usually only done at low output
power. In this application note it is called "operating in Frequency reduction mode"
(See Section 5.1.1.3).
The input voltage of the flyback is measured through pin FBAUX and used to implement
an OverPower Protection (OPP). The OPP keeps the maximum output power of the
flyback constant over the input voltage.
The flyback has an accurate OVP circuit. The overvoltage is measured through pin
FBAUX. Both controllers (flyback and PFC) are switched off in a latched protection when
an overvoltage is detected.
5.1.1 Three different operation modes of the TEA1752
At initial start-up, the flyback always starts at the maximum output power. This means that
the system starts up in the so-called Quasi-resonant mode. The flyback of the TEA1752
passes through three operation modes (see Figure 12) from maximum to minimum output
power:
• Quasi-Resonant (QR) mode
• Discontinuous Conduction Mode (DCM
• Frequency Reduction (FR) mode
Demagnetization detection and valley switching circuitry inside the IC is active in all three
different operation modes.
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GreenChip III TEA1752 integrated PFC and flyback controller
FR
DCM
QR
fsw(max)
(FB)
flyback
switching
frequency
PFC off
PFC on
1.5 V
VFBCTRL
019aaa038
Fig 12. Flyback operation modes
5.1.1.1
Quasi-resonant mode
The flyback operates in Quasi-resonant mode at high and maximum output power. The
output power is controlled by the peak current (see Section 5.1). A lower peak current
than the maximum allowed value results in lower output power and a higher operating
frequency until the maximum operating frequency is reached. The Quasi-resonant mode
can easily be recognized. The next primary switching cycle starts when the bottom of the
first valley is detected.
The primary peak current (Ip) is set by the voltage on pin FBCTRL. It is advised to place a
10 nF noise filter capacitor (C15) as close as possible to the FBCTRL pin to avoid
disturbance of the flyback by switching of the PFC MOSFET. The voltage on pin FBCTRL
is measured back at the FBSENSE pin and can be calculated with Equation 13 (only valid
during QR mode or DCM):
V sense ( fb ) ≅ 0.66 × V FBCTRL – I adj ( FBSENSE ) × ( R16 + R17 ) – 0.69 V
(13)
Where:
• VFBCTRL is allowed to vary between the 1.5 V and 2.0 V (only valid during QR mode or
DCM mode)
• Iadj(FBSENSE) is related to a current source inside the IC, connected to the FBSENSE
pin
• Resistors R16 and R17 can be found in the circuit diagram, see Figure 13.
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GreenChip III TEA1752 integrated PFC and flyback controller
T1
Vi (DC)
D_output
Lp
C_output
RCOMP
RSERIES = R17 + R16
FBSENSE
Iadj(FBSENSE)
R17
FBDRIVER
R16
Q2
R16A
Rsense
C23
019aaa039
C10
FBSENSE has two internal reference levels:
(1) Vsense(fb)max = 0.630 V at dV/dt = 0 mV/μs
(2) Vsense(fb)min = 0.300 V at dV/dt = 0 mV/μs
Fig 13. Most important components for adjusting the flyback in the application
The peak current Ip through the flyback transformer is defined by:
V sense ( fb ) – I adj ( FBSENSE ) × { R16 + R17 }
I p = ---------------------------------------------------------------------------------------------------R sense
(14)
The maximum peak current Ipmax is determined by Vsense(fb)max. R16A is not mentioned in
Equation 14, but this is explained in Section 5.1.5. Usually the required output power
continues to drop after the initial start-up. This results in the flyback entering the
Discontinuous conduction mode when the maximum switching frequency is reached.
5.1.1.2
Discontinuous conduction mode
In DCM the output power is reduced by a further reduction of the peak current (Ip) and by
skipping one or more valleys at the same time. In this mode the switching frequency is
kept more or less constant. The exact switching frequency depends on the detection of
the valleys, but it is never higher than the maximum frequency.
The output power is decreased by reducing the peak current and as a result more valleys
are skipped until the voltage across FBCTRL drops below 1.5 V. When this happens the
operating mode shifts from DCM to FR mode.
Sometimes the DCM is not reached when the selected primary inductance value of the
transformer is too large. In such a situation the flyback skips the DCM when it is reducing
power, it jumps directly from the QR mode to the FR mode.
5.1.1.3
Frequency reduction mode
The voltage across the FBCTRL pin in Frequency reduction mode no longer sets the peak
current. Instead it sets the operating frequency. The minimum peak current (Ipmin) through
the transformer is kept constant during the FR mode.
The ratio between Ipmin and Ipmax depends mainly on the value of the sense resistor
Rsense, assuming that the core is not saturated at Ipmax. The output power is reduced by
reducing the operating frequency and as a result more valleys are skipped.
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GreenChip III TEA1752 integrated PFC and flyback controller
The operating frequency of the flyback during FR mode determines if the PFC is turned on
or turned off. The turn-on operating frequency for enabling the PFC is selected at a higher
rate than the turn-off operating frequency. So the PFC is turned on at a higher output
power and turned off again at a lower output power.
In general the output voltage of an adapter is fixed, so a higher or lower output power of
the flyback results in a higher or lower output current.
The overall efficiency of the system is improved if the PFC is disabled at low output
currents. For this reason the PFC is turned off above 25 % of the nominal output current.
On the other hand, the PFC is turned on at larger output currents in order to improve the
power factor of the line current. This is often done below 50 % of the nominal output
current.
The hysteresis between turning on and turning off the PFC depends on the primary
inductance value, the output power and the line voltage. It is therefore important to select
the right inductance value to ensure enough PFC-on/PFC-off hysteresis. Section 5.1.2
describes how this is done.
5.1.2 The relationship between inductance value and the hysteresis of the PFC
The TEA1752 runs with a fixed minimum peak current (Ipmin) to control the output power
during the Frequency reduction mode, see Section 5.1 (the value of Ipmin is calculated in
Equation 17). Therefore the on-time (conducting time of the MOSFET) depends on the
selected inductance value and the input voltage, it is linearly related to the inductance
value and inversely proportional to the input voltage. The relationship between on-time
and off-time of the MOSFET is fixed via the turns ratio of the transformer and the output
voltage (neglecting the influence of the relatively short valley time). At lower line voltages
the operating frequency and output power decrease when a relatively large primary
inductance is selected, see also Section 5.1 and Figure 14.
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GreenChip III TEA1752 integrated PFC and flyback controller
Is
flyback driven at low line voltages,
assuming a relatively large primary
inductance for the flyback transformer
Ipmin (= fixed value)
tp
ts
tp
ts
tvalley
tx
T = 1 / fs
Is
flyback driven at very low line
voltages, assuming a relatively large
primary inductance for the flyback
transformer
Ipmin (= fixed value)
tp
ts
ts
tp
tvalley
T + tx = 1 / fs-low
019aaa040
Fig 14. Operating frequency as a function of (low) line voltages, assuming a relatively large selected primary
inductance value for the flyback transformer
The situation becomes worse when the primary inductance value is increased as well,
because this limits the maximum deliverable output power at low line voltages even more
(by default flyback runs at a lower operating frequency, assuming a fixed peak current). In
practice this means that the flyback supports a limited amount of power at low line
voltages. Asking more power activates the feedback loop and results in enabling the PFC
at lower output power than was originally intended. In other words, the hysteresis between
turning on and turning off the PFC becomes smaller at low line voltages in comparison
with typical line voltages, assuming that a relatively large primary inductance value for the
transformer is selected. When the selected primary inductance value is much too large,
unwanted system behavior occurs, because there is no hysteresis left. The maximum
inductance value should be limited to prevent this unwanted system behavior at low line
voltages.
Most customers prefer a certain minimum hysteresis between turning on and turning off
the PFC at low line voltages. So it is helpful to have an indication of the acceptable
maximum primary inductance value of the transformer at the start of the design. Note that
several assumptions have to be made to calculate these inductance values in Figure 15.
Therefore these values should only be thought of as indications.
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GreenChip III TEA1752 integrated PFC and flyback controller
019aaa041
800
Lp
(μH)
(5)
(4)
600
(3)
(2)
(1)
400
200
75
95
115
135
155
PO (W)
Lp = f(PO)
Assumptions: Minimum voltage across the buffer capacitor (C3) is approximately 100 V (DC) at
50 % of the nominal output power.
(1) N × (VO + Vf) = 80 V
(2) N × (VO + Vf) = 92 V
(3) N × (VO + Vf) = 104.3 V
(4) N × (VO + Vf) = 118 V
(5) N × (VO + Vf) = 130 V
Fig 15. Indication of the acceptable primary inductance value, related to output power
and N × (VO + Vf)
Figure 15 shows an indication value for the primary inductance value of the flyback at
different output powers and different turn ratios. Selecting a larger value than proposed
here can result in too much loss of hysteresis. Selecting a smaller value prevents that, but
causes more overall switching losses. The inductance values shown in Figure 15 results
in loss of some hysteresis below roughly 115 V (AC) line voltage. However, they are
usually still acceptable at 90 V (AC), assuming that the voltage across bulk elcap C3 does
not drop too much. A rule of thumb is that the value of the buffer capacitor C3 in
microfarads is usually selected equal to the output power in Watts. Applying this general
rule of thumb results in a minimum voltage across the buffer capacitor of approximately
100 V (DC) at 90 V (AC) line voltage at 50 % of the nominal output power.
Selecting the inductance value with the help of Figure 15 is one method. Another method
is using Equation 15:
N × ( VO + Vf )
–6
– 1.0005
L p = ⎛ ---------------------------------⎞ × 43061 × 10 × ( I O ( nom ) × ( V O + V f ) )
⎝
⎠
104.3
(15)
Where:
•
•
•
•
AN10861
Application note
IO(nom) stands for the nominal output current according to the type plate of the adapter
VO stands for the output voltage
Vf stands for forward voltage across the secondary diode
Lp stands for the primary inductances of the flyback transformer
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GreenChip III TEA1752 integrated PFC and flyback controller
• N is the turns ratio between the primary and secondary windings (Np/Ns)
Equation 15 gives some deviation at a low and a high value of the N × ( V O + V f ) product.
It is therefore recommended to keep this value between 80 V and 130 V.
Example:
• IO(nom) = 4.62 A
• VO = 19.5 V
• Vf = 0.05 V
• N × ( V O + V f ) = 104.3
104.3
–6
– 1.0005
–6
= 476 × 10 H
L p = ⎛ -------------⎞ × 43061 × 10 × ( 4.62 × ( 19.5 + 0.05 ) )
⎝ 104.3⎠
The final value used is 450 μH.
5.1.3 Relationship between Ipmin and the required PFC-on/off level
The PFC is usually turned on and turned off between 50 % and 25 % of the nominal
output current of the flyback. The PFC can only be turned on or turned off by the flyback
when it is running in FR mode. The typical internal operating frequency of the flyback for
turning on the PFC is 86 kHz and for turning off the PFC is 48 kHz. Using the average of
both values (percentage wise and frequency wise) in combination with Equation 12 results
in Equation 16:
1
2
0.375 × I O ( nom ) × ( V O + V f ) = --- × L p × I pmin × 67000 × η fb
2
(16)
Or:
I pmin =
2 × 0.375 × I O ( nom ) × ( V O + V f )
---------------------------------------------------------------------------L p × 67000 × η fb
(17)
Where:
•
•
•
•
•
•
0.375 is the average value of 50 % and 25 % of the nominal output current
VO is the output voltage
Vf is forward voltage across the secondary diode
Lp is the primary inductances of the flyback transformer
67000 is the average value of 86000 Hz and 48000 Hz
ηfb is the efficiency of the flyback (please use relatively high values, such as
0.97…0.98)
Example:
• IO(nom) = 4.62 A
• VO = 19.5 V
• Vf = 0.05 V
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• Lp = 450 μH
• ηfb = 0.98
I pmin =
2 × 0.375 × 4.62 × ( 19.5 + 0.05 )
------------------------------------------------------------------------------ = 1.514 A
–6
450 × 10 × 67000 × 0.98
5.1.4 The influence of Rsense and the series resistance R16 + R17
The sense resistor, Rsense, together with the series impedance R16 and R17, has four
functions:
• Prevent or minimize the risk of saturation of the flyback transformer.
• Allow enough power to the output (assuming the inductance is not going into
saturation).
• Allow some adjustment for enabling or disabling the PFC at a certain output power
level. Note that the value of Rsense is more dominant for this adjustment than the
values of R16 and R17, as their influence is much smaller.
• R17 and C23 prevent FBSENSE being charged negative because of disturbances
across Rsense.
The saturation level (Ip(sat)) of the transformer and the value of the sense resistor are
important design parameters. Section 5.1.4.1 shows the calculation for the saturation
level of the transformer. After that the maximum peak current (Ipmax) through the
transformer is determined. This value should preferably be below the saturation level of
the transformer.
5.1.4.1
Calculating the saturation current Ip(sat) of the flyback transformer
The saturation level of a transformer can be calculated with Equation 18.
N p × B max × A e
I p ( sat ) = -----------------------------------Lp
(18)
Example with the following assumptions:
•
•
•
•
Np = 32 turns
Bmax = 390 mT (PQ3220, material PC44, Bmax at 100 °C)
Ae = 170 × 10−6 m2 (from transformer supplier data sheet)
Lp = 450 × 10−6
–6
32 × 0.39 × 170 × 10
Result: I p ( sat ) = ------------------------------------------------------- = 4.71 A
–6
450 × 10
Values for Ae and Bmax can be found in the data sheet of the transformer supplier. The
Bmax value depends on temperature. It decreases rapidly at high operating temperatures.
Therefore the Bmax value should be selected at high operating temperatures. Saturation of
the core does not happen when the maximum peak current (Ipmax) is below the saturation
current (Ip(sat)). Section 5.1.4.2 shows the calculation of Ipmax. A saturated core does not
deliver more power to the output, but only deteriorates the overall performance of the
system (more stress and EMI and, worst case, a possible system failure).
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5.1.4.2
Calculation of Ipmax for flyback operating in Quasi-resonant mode
The flyback peak current operating in Quasi-resonant mode can be calculated with
Equation 19:
2
– b + (b – 4 × a × c)
I pmax = ------------------------------------------------------2×a
(19)
Where:
• a = N × Vi(DC)min × Lp
• b = −2 × IO × Lp × {N × (VO +Vf) + Vi(DC)min}
• c = −2 × IO × tvalley × N × Vi(DC)min × (VO + Vf)
For a, b and c:
•
•
•
•
VO is the output voltage
N is the turns ratio between the primary and secondary windings (Np/Ns)
Lp is the inductance value of the primary winding
tvalley is the valley time, sometimes also described as dead time. This time is usually
around the 1.1 μs
• Vi(DC)min is the minimum voltage across bulk elcap C3 at its nominal output load. In
this example this is 75 V (DC). The actual voltage depends on how fast the PFC is
enabled. It is therefore recommended to check this value in every application.
Examples:
• a = 5.3333 × 75 × 450 × 10−6 = 180 × 10−3
• b = −2 × 4.62 × 450 × 10−6 × {5.3333 × (19.5 + 0.05) + 75} = −745.39 × 10−3
• c = −2 × 4.62 × 1.1 × 10−6 × 5.3333 × 75 × (19.5 + 0.05) = −79.4824 × 10−3
I pmax ( at I O = 4.62 A ) =
–3
–3 2
–3
–3
745.39 × 10 + ( – 745.39 × 10 ) – 4 × 180 × 10 × – 79.4824 × 10
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- = 4.25 A
–3
2 × 180 × 10
The calculated peak current is below the saturation level of 4.71 A (see Section 5.1.4.1). It
is recommended to have some margin between this calculated value and the saturation
level of the core. For example, the system might still run into a problem during a peak
load. This is something that has to be checked as well for the final design. The calculation
below shows the results if the assumed peak output current is 5.7 A and the PFC has
been on for some time. It is assumed that the minimum voltage across buffer cap C3 is
240 V (DC).
• a1 = 5.3333 × 240 × 450 × 10−6 = 576 × 10−3
• b1 = −2 × 5.70 × 450 × 10−6 × {5.3333 × (19.5 + 0.05) + 240} = −1.7661
• c1 = −2 × 5.70 × 1.1 × 10−6 × 5.3333 × 240 × (19.5 + 0.05) = -313.8 × 10−3
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I pmax ( at I O = 5.7 A ) =
2
–3
–3
1.7661 + ( – 1.7661 ) – 4 × 576 × 10 × – 313.8 × 10
--------------------------------------------------------------------------------------------------------------------------------------- = 3.23 A
–3
2 × 576 × 10
Select the highest value of Ipmax (at IO = 4.62 A and at IO = 5.7 A) and compare this value
with Ip(sat). The value of Ipmax should preferably be lower than Ip(sat). If so, then use the
value of Ip(sat) for Ipmax, because this gives more margin to the deliverable maximum
output power.
5.1.4.3
Calculation of the current sense resistor Rsense
The next step is calculating the value for Rsense, see Equation 20:
V sense ( fb )max – V sense ( fb )min
0.63 – 0.3
0.33
R sense = ------------------------------------------------------------------- = ------------------------------- = ------------------------------I
–
I
I pmax – I pmin
I pmax – I pmin
pmax
pmin
(20)
Remarks:
• Vsense(fb)max and Vsense(fb)min: Measured at dV/dt = 0 mV/μs.
• Ipmax: Fill in the highest Ipmax level (see Section 5.1.4.2).
Using the saturation current Ip(sat) for Ipmax is often preferred (assuming that Ip(sat) > Ipmax)
because it generally allows for a slightly higher maximum output power for the design
(it gives some extra margin). Using the highest peak current of all (Ip(sat) = 4.715 A, see
Section 5.1.4) results in a value for Rsense as calculated in Equation 21:
0.33
R sense = --------------------------------- = 0.103 ≈ 0.100 Ω
4.715 – 1.514
5.1.4.4
(21)
Calculation of the series resistance R16 and R17
Equation 22 calculates the series resistance of R16 and R17:
I pmax × 0.3 – I pmin × 0.63
I pmax × V sense ( fb )min – V sense ( fb )max
R SERIES = -------------------------------------------------------------------------------------- = ------------------------------------------------------------–6
I adj ( FBSENSE ) × ( I pmax – I pmin )
3 × 10 × ( I pmax – I pmin )
(22)
Remarks:
• Vsense(fb)max and Vsense(fb)min: measured at dV/dt = 0 mV/μs
Example for a typical 90 W adapter:
4.715 × 0.3 – 1.514 × 0.63
- = 48504 Ω
R SERIES = --------------------------------------------------------------–6
3 × 10 × ( 4.715 – 1.514 )
The value of R17 is often a value roughly between 680 Ω and 1200 Ω. Its purpose is to
prevent C10 being charged in an unwanted way because of spikes across Rsense that may
trigger the ESD protection inside the IC. Selecting a value between these two limits allows
some freedom for trimming R16 or the delay compensation resistor R16A. The value of
R17 is chosen at 1000 Ω. The value of R16 then becomes: 48504 − 1000 = 47504 Ω.
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5.1.5 Calculation of the delay compensation resistors RCOMP and R16A
RCOMP and R16A are intended to compensate the sum of the following three delays:
• The internal delay time of the IC
• The switch-off time of the MOSFET
• The delay time related to R17 × C23 (filter in front of the FBSENSE pin).
The transformer is still conducting current at the primary side during the sum of all these
delay times. This delay can be translated into an extra current, IDELAY, through the
transformer (see Figure 16) and results in extra energy for the output. The amount of extra
energy depends on the input voltage.
The purpose of the resistors RCOMP and R16A is to compensate for the unwanted current
(IDELAY) with the corresponding delay time. The voltage across R16A can be translated to
a current IPRESET with the corresponding preset time. The system is compensated if the
preset values match the delay values.
IDELAY
IPRESET
IPREFERRED
tPRESET
tDELAY
tPREFERRED
019aaa042
Fig 16. Principle of delay compensation
The voltage across R16A depends on the current through this resistor. The main part of
this current flows via R5, R5A, and R6A. Note that the current through R5 and R5A is split
up into two parts afterwards and is therefore only partly flowing through R6. The other part
is flowing through R6A. One resistor can replace all these resistors. This resistor is called
RCOMP. The value of this resistor can be calculated with Equation 23 when the schematic
is built according to Figure 1:
R COMP = 2 × ⎛ R5 + R5A + R6A
-----------⎞⎠
⎝
2
(23)
Example calculation for a typical 90 W adapter:
2.7 MΩ
R COMP = 2 × ⎛ 2 MΩ + 1.3 MΩ + -------------------⎞ = 9.3 MΩ = 9300 kΩ
⎝
2 ⎠
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The final delay time is determined by the internal delay time of the IC, the response time
needed for switching off the MOSFET and the time-constant, R17 × C23. A minimum
RC time is required in order to filter out disturbances on pin FBSENSE. An RC time
selection that is too large cannot follow the ramping up input voltage properly. Therefore
all other delays are first subtracted from the conducting time of the flyback MOSFET. The
remaining time should be at least 5.5 times the minimum RC time required for filtering out
disturbances on the FBSENSE.
A common value for the internal delay time of the IC is 220 ns. Switching of the MOSFET
usually takes around 60 ns (but check this value in the final application, as the situation
might be different because of the use of different MOSFETs, gate resistors, etc). The
conduction time of the flyback MOSFET is shortest when the input voltage is at its highest.
The highest value is usually 390 V (DC). Equation 24 shows the calculation for
R17 × C23:
L p × I pmin
------------------------- – t int.delay – t MOSFET – off
–9
390 × 10
R17 × C23 ( ns ) ≤ ----------------------------------------------------------------------------------------5.5
(24)
Example calculation for a typical 90 W adapter:
–6
450 × 10 × 1.514
---------------------------------------------- – 220 – 60
–9
390 × 10
R17 × C23 ≤ ------------------------------------------------------------------------- ≤ 293 ns
5.5
A commonly used RC time for this filter is 220 ns at R17 = 1 kΩ and C23 = 220 pF. This
value is therefore used for the following equations. The output follows the input with a
delay of just one RC time after roughly five RC times. The total delay time can now be
calculated with Equation 25:
t delay = t int.delay + t MOSFET – off + R17 × C23
(25)
Example for a typical 90 W adapter:
t delay = 220 × 10
–9
+ 60 × 10
–9
3
+ 1 × 10 × 220 × 10
– 12
= 500 ns
The value of R16A can now be calculated with Equation 26:
⎛
R COMP ⎞ ⎛ R sense × R COMP × t delay⎞
R16A = ⎜ 1 – ------------------------------⎟ × ⎝ ----------------------------------------------------------⎠
6
Lp
⎝
83.333 × 10 ⎠
(26)
Example for a typical 90 W adapter:
6
–9
6
⎛
0.1000 × 9.3 × 1 × 10 × 500 × 10 ⎞
9.3 × 10 ⎞ ⎛ -------------------------------------------------------------------------------------R16A = ⎜ 1 – ------------------------------⎟ × ⎜
⎟ = 918 Ω
–6
6
⎝
⎠
450 × 10
83.333 × 10 ⎠ ⎝
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5.1.6 Calculation of the flyback soft start components
The soft start is implemented through the RC network at pin FBSENSE.
The sum of R16, R16A and R17 must be at least 16 kΩ (see TEA1752T_LT data sheet).
This ensures that the voltage Vstart(soft)fb (0.63 V) is reached and the start-up of the flyback
is enabled.
In general the values of R16A and R17 are much smaller than the value of R16.
Therefore the soft start time is: t softstart ≈ 3 × R16 × C10 .
It is recommended to make the soft start time for the flyback longer than the soft start time
of the PFC. It is also recommended to keep the soft start time within the range of 5 ms to
10 ms.
The total soft start time is approximately 8 ms when C10 = 56 nF and R16 = 49 kΩ.
5.2 Flyback control and PFC with delay options
The flyback controls the operation mode of the PFC. The PFC is turned on at an internal
flyback frequency of 86 kHz and it is turned off at an internal frequency of 48 kHz (see
Figure 12 and the TEA1752T_LT data sheet). PFC has a relatively fast turn-on, but its
turn-off is delayed via capacitor C24, which is connected to the PFCTIMER pin (see
Figure 17). In this way it is possible to prevent the PFC from entering a kind of burst mode
because of fast and substantial repetitive load changes at the output. Preventing this
results in a more stable input voltage for the flyback. The amount of time for ignoring the
shutting down signal of the PFC depends on the capacitance value connected to the
PFCTIMER pin. This time can be calculated with Equation 27:
t delay – PFC
off
≈ C24 × 36 × 10
4
(27)
Example: a capacitance value of 2.7 μF for C24 results in a delay of approximately 1 s. It
is recommended to use a minimum value of 1 nF for C24. It is also recommended to place
the 10 nF noise filter capacitor C15 as close as possible to the FBCTRL pin to guarantee
a smooth transition from PFC-off to PFC-on and to avoid audible noise in the flyback
transformer.
Note that the hysteresis between turning on and turning off the PFC can be influenced by
the inductance value (see Section 5.1.2). Also the valley time and other disturbances on
the FBCTRL pin makes the hysteresis smaller. It is therefore advised to use the layout
guidance (see Section 7) and keep the valley time short (usually a value close to 1.1 μs
leads to good results).
5.2.1 Improving start-up time of the PFC
The PFC in the TEA1752 is turned on when the flyback is suddenly heavily loaded by a
step load. It is in general turned on fast enough, but sometimes an even shorter start-up
time is required. This is especially valid at very low line voltages in combination with large
load changes. The flyback may enter the Safe restart mode when the maximum on-time
protection (ton(fb)max) is hit because of a voltage that has become too low across the bulk
elcap. Selecting a larger value for the bulk elcap and/or starting up the PFC as soon as
possible improves this situation. Figure 18 shows an example of how this can be done.
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R28
14
R29
15 kΩ
PFCTIMER
14
TEA1752
PFCTIMER
150 Ω
Q3
C25
TEA1752
2
C24
2
C24
GND
GND
019aaa048
Fig 17. Standard configuration for the
PFCTIMER pin
019aaa049
Fig 18. Improving the start-up time of the
PFC
The delay time of the PFC (described in Section 5.2) is no longer determined by the value
of C24 in Figure 18, but by C25. The value of capacitor C24 has to be very small, typically
1 nF. The start-up time of the PFC can be neglected. It is recommended to use a transistor
with a large DC current gain (= hFE).
The start-up time of the PFC in Figure 17 is determined by Equation 28:
t delay – PFC on = 6930 × C24
(28)
Example:
A capacitance value of 2.7 μF for C24 results in a delay of 18.7 ms before the PFC is
turned on. The ratio between the turning off and the turning on of the PFC (in Figure 17)
therefore equals 52.
5.3 Flyback protection mode
5.3.1 Short circuit on pin FBCTRL
If pin FBCTRL is shorted to ground, switching of the flyback controller is inhibited. This
situation equals the minimum or a no output power situation.
5.3.2 Open FBCTRL pin
As shown in Figure 19. the FBCTRL pin is connected to an internal voltage source of
3.5 V via an internal resistor of 3 kΩ. When the voltage on pin FBCTRL exceeds 2.5 V,
this connection is disabled and the FBCTRL pin is biased with an internal 30 μA current
source. When the voltage on the FBCTRL pin exceeds Vto(FBCTRL) (4.5 V) a fault is
assumed. Switching of the flyback (and also the PFC) is blocked and the controller enters
the Safe restart mode (TEA1752T) or triggers the latched protection (TEA1752LT).
An internal switch pulls the FBCTRL pin down when the flyback is disabled.
5.3.3 Time-out flyback control loop
A time-out function can be realized to protect against an output short circuit at initial
start-up or against an open control loop situation. This can be done by placing a resistor in
series with a capacitor between pin FBCTRL and ground. The triggering of the time-out
protection generates a safe restart for the TEA1752T and a latched protection for the
TEA1752LT.
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When the voltage on pin FBCTRL exceeds 2.5 V (see Figure 19) the switch in series with
the resistor of 3 kΩ is opened. Pin FBCTRL and therefore the RC combination is biased
with a 30 μA current source. When the voltage on pin FBCTRL exceeds 4.5 V, the
switching of the flyback (and also of the PFC) is blocked and the controller enters the Safe
restart mode (TEA1752T) or is latched (with TEA1752LT). The capacitor can be used to
set the time for reaching 4.5 V at the FBCTRL pin. The resistor is necessary to separate
the relatively large time-out capacitor from the control loop response. It is advised to use a
resistor of at least 30 kΩ. This resistor also influences the charge time of the capacitor.
The time-out time tto can be calculated with Equation 29:
C to ⋅ V to ( FBCTRL ) – ( I O ( FBCTRL ) ⋅ R to )
t to = -------------------------------------------------------------------------------------------I O ( FBCTRL )
(29)
The capacitor can be calculated with Equation 30:
I O ( FBCTRL ) ⋅ t to
C to = ------------------------------------------------------------------------------V to ( FBCTRL ) – ( I O ( FBCTRL ) ⋅ R to )
(30)
The resistor can be calculated with Equation 31:
V to ( FBCTRL ) t to
R to = ---------------------------- – -------I O ( FBCTRL ) C to
(31)
Example with the following assumptions:
• tto = 37 ms
• Cto = 330 nF
4.5 V 37 ms
R to = --------------- – ------------------ = 37.9 kΩ ≈ 39 kΩ
30 μA 330 nF
If time-out protection is not required, if can be disabled by placing a resistor of 100 kΩ
between pin FBCTRL and ground.
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2.5 V
3.5 V
30 μA
4.5 V
3 kΩ
3 FBCTRL
time-out
TEA1752
019aaa043
a. Circuit diagram
4.5 V
2.5 V
VFBCTRL
output
voltage
intended output
voltage not
reached within
time-out time.
restart
intended output voltage
reached within time-out
time.
019aaa044
b. Timing diagram
Fig 19. Time-out protection
5.3.4 Overvoltage protection flyback
The IC has an internal latched overvoltage protection circuit, which switches off both
controllers when an overvoltage is detected at the output of the flyback. The IC can detect
an overvoltage at a secondary winding of the flyback by measuring the voltage at the
auxiliary winding during the secondary stroke. A series resistor between the auxiliary
winding and the FBAUX pin converts this voltage to a current through the FBAUX pin.
D5
T1
primary
VCC
D23A
C13
1
D_output
TEA1752
2
4
R23
FBAUX
R23A
auxiliary
secondary
R-OVP = R23
GND
R-OPP = R23 + R23A
019aaa045
Fig 20. Flyback OVP and OPP circuit
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At a current, Iovp(FBAUX), of 300 μA into the FBAUX pin, the IC detects an overvoltage. An
internal integrator filters noise and voltage spikes. The output of the integrator is used as
an input for an up-down counter. The counter has been added as an extra filter to prevent
false OVP detection, which might occur during ESD or lightning events.
If the integrator detects an overvoltage, the counter increases its value by 1. If another
overvoltage is detected during the next switching cycle, the counter increases its value by
1 again. If no overvoltage is detected during the next switching cycle, the counter
subtracts its value by 2 (the minimum value is 0). If the value reaches 8, the IC assumes a
true overvoltage and activates the latched protection. Both converters are switched off
immediately and VCC starts cycling between Vth(UVLO) and Vstartup without a restart.
Switching off and then switching on the mains input voltage triggers the fast latch reset
circuit and resets the latch.
The OVP level can be set by the resistor Rovp:
R ovp
aux
⎛N
---------- × V ovp ( VOSENSE )⎞ – V clamp ( FBAUX ) – V f ( D23A )
⎝ Ns
⎠
= ------------------------------------------------------------------------------------------------------------------------------I ovp ( FBAUX )
(32)
aux
⎛N
---------- × V ovp ( VOSENSE )⎞ – 0.7 ( typical ) – V f ( D23A )
⎝ Ns
⎠
= ---------------------------------------------------------------------------------------------------------------------------300 μA ( typical )
Where:
•
•
•
•
Ns is the number of turns on the secondary winding.
Naux is the number of turns on the auxiliary winding of the flyback transformer.
Vclamp(FBAUX) is the positive clamp voltage of the FBAUX pin.
Vf(D23A) is the forward voltage of D23A at a current of 300 μA.
The tolerances on Iovp(FBAUX) have to taken into account for the calculation of the
Vovp(VOSENSE) level to avoid triggering of the OVP during normal operation.
5.3.5 OverPower Protection (OPP)
The maximum output power in a flyback in Quasi-resonance mode depends on the
(mains) input voltage. An OPP is implemented to compensate for this. During the primary
stroke of the flyback the mains voltage is sensed by measuring the current drawn from pin
FBAUX. With a resistor between the flyback auxiliary winding and pin FBAUX the voltage
at the auxiliary winding is converted to a current IFBAUX (see Figure 20). The IC uses the
current information to reduce the setting of the maximum flyback peak current measured
through pin FBSENSE. See Figure 21 for the limitation of the maximum VFBSENSE level as
a function of IFBAUX.
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VFBSENSE
(V)
0.65
0.46
−360
IFBAUX (μA)
−100
0
019aaa046
Fig 21. OPP maximum FBSENSE voltage
The total OPP resistance determining the IFBAUX current during the primary stroke of the
flyback exists of R23 + R23A (see Figure 20). The OVP resistor R23 has to be calculated
before the remaining part of the OPP resistor R23A can be calculated.
The value of R23A can be calculated with Equation 33:
N aux
----------- ⋅ V O ( PFC )low – V clamp ( FBAUX )
Np
R23A = ------------------------------------------------------------------------------------– R OVP =
I start ( OPP )FBAUX
N aux
---------- ⋅ 240 V – 0.8 V
Np
-------------------------------------------------- – R OVP
100 μA
(33)
The sum of R23 and R23A should be lower than 666 kΩ.
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6. Summary of calculations for adjustment of the flyback
See Figure 1 application schematic for component reference numbers.
T1
Vi (DC)
D_output
Lp
C_output
RCOMP
RSERIES = R17 + R16
FBSENSE
Iadj(FBSENSE)
R17
Q2
FBDRIVER
R16
R16A
Rsense
C23
019aaa039
C10
FBSENSE has two internal reference levels:
(1) Vstart(soft)fb = 0.630 V at dV/dt = 0 mV/μs
(2) Vsense(fb)min = 0.300 V at dV/dt 0 mV/μs
a. Most important components for adjusting the flyback in the application
019aaa041
800
Lp
(μH)
(5)
(4)
600
(3)
(2)
(1)
400
200
75
95
115
135
155
PO (W)
Lp = f(PO)
Assumptions: Minimum voltage across buffercap (C3) is approximately 100 V (DC) at 50 % of the
nominal output power.
(1) N × (VO + Vf) = 80 V
(2) N × (VO + Vf) = 92 V
(3) N × (VO + Vf) = 104.3 V
(4) N × (VO + Vf) = 118 V
(5) N × (VO + Vf) = 130 V
b. Indication of the acceptable inductance value, related to output power and N × (VO + Vf)
Fig 22. Most important components and inductance value for adjusting the flyback in the
application
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AN10861
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GreenChip III TEA1752 integrated PFC and flyback controller
Step 1: Use the graph in Figure 22 to determine an indication for the primary inductance
value or use Equation 34:
N × ( VO + Vf )
–6
– 1.0005
L p = ⎛ ---------------------------------⎞ × 43061 × 10 × ( I O ( nom ) × ( V O + V f ) )
⎝
⎠
104.3
(34)
Step 2: Select a transformer and calculate the saturation current:
N p × B max × A e
I p ( sat ) = -----------------------------------Lp
(35)
Step 3: Calculate the required peak current through the flyback transformer. Calculate this
value during nominal output current in combination with the minimum electrolytic buffer
capacitor voltage and at peak output current when the PFC is operating. Only the highest
value of these two needs to be taken into account. Name this value Ipmax.
2
– b + (b – 4 × a × c)
I pmax = -----------------------------------------------------2×a
(36)
Where:
• a = N × Vi(DC)min × Lp
• b = −2 × IO × Lp × {N × (VO + Vf) + Vi(DC)min}
• c = −2 × IO × tvalley × N × Vi(DC)min × (VO + Vf)
Common rule is that Ip(sat) > Ipmax. Selecting the higher Ip(sat) value for Ipmax prevents
saturation of the transformer and allows a power margin. Therefore in general the
calculation is continued with Ipmax = Ip(sat).
Step 4: Calculate Ipmin (related to the turning on or the turning off of the PFC):
I pmin =
2 × 0.375 × I O ( nom ) × ( V O + V f )
---------------------------------------------------------------------------L p × 67000 × η fb
(37)
ηfb stands for the efficiency of the flyback. Use relatively high values, e.g. close to
0.97…0.98.
Step 5: Calculating the value of Rsense:
0.33
R sense = -----------------------------I pmax – I pmin
(38)
Step 6: Calculating the value of RSERIES:
I pmax × 0.3 – I pmin × 0.63
R SERIES = ------------------------------------------------------------–6
3 × 10 × ( I pmax – I pmin )
(39)
Note that the RSERIES comprises two components, R16 and R17. The common value for
R17 is between 820 Ω and 1200 Ω. A typical value that is used often is 1000 Ω.
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AN10861
NXP Semiconductors
GreenChip III TEA1752 integrated PFC and flyback controller
Step 7: Checking/calculating the time constant R17 × C23:
L p × I pmin
------------------------- – t int.delay – t MOSFET – off
–9
390 × 10
R17 × C23 ( ns ) ≤ ----------------------------------------------------------------------------------------5.5
(40)
Where:
• tint.delay = 220 ns
• tMOSFET-off ≅ 60 ns (Note that the value can be different in other applications)
In general the calculation often shows that R17 × C23 ≥ 220 ns. If this is so then 220 ns
should be sufficient for R17 × C23. A slightly smaller value might be acceptable but is not
preferred (has to be checked on the application board).
Step 8: Calculate the delay time:
t delay = t int.delay + t MOSFET – off + R17 × C23
(41)
Remark: The commonly used value for R17 × C23 is 220 ns (see also step 7).
Step 9: Calculating the compensating resistor RCOMP:
R6A
R COMP = 2 × ⎛ R5 + R5A + -----------⎞
⎝
2 ⎠
(42)
Calculating the value of R16A:
⎛
R COMP ⎞ ⎛ R sense × R COMP × t delay⎞
R16A = ⎜ 1 – ------------------------------⎟ × ⎝ ----------------------------------------------------------⎠
6
Lp
⎝
83.333 × 10 ⎠
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Rev. 01 — 16 July 2010
(43)
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AN10861
NXP Semiconductors
GreenChip III TEA1752 integrated PFC and flyback controller
7. PCB layout considerations
A good layout is considered to be an important part of the final design. It minimizes all
kinds of disturbances and makes the overall performance more robust with less risk of
EMI. Guidelines for the improvement of the layout of the print-circuit board are given
below:
• Separate large signal grounds from small signal grounds (see Figure 23). Small signal
grounds can be easily recognized by their triangle shaped symbol. All other ground
symbols are related to large signal grounds.
• Try to make the print area that fits within the separate large signal loops
(see Figure 23) as small as possible. Each separate large signal loop has its own
color.
• The connection between both MOSFETs (PFC and flyback) and both driver outputs of
the IC should be as short as possible (green line in Figure 23). Try to minimize the
coupling between these two signals by increasing the distance between them and/or
preferably using a guided ground track for both connections.
• The power ground and small signal ground are only connected with one short copper
track (make this track as short and as wide as possible). Preferably it should become
one spot (connection between ground 4a and ground 6a).
• Use a ground shield underneath the IC, connect this ground shield to pin 2 of the IC.
• All resistors connected in series with an IC pin should be connected as close as
possible to that pin.
• Any heatsink connected to a component must be connected to that component's
nearest corresponding ground signal. Make this connection as short as possible.
Connect the heatsink of diode bridge BD1 to ground 1, Q1 to 4 and Q2 to 4b. In
typical applications all three components are often mounted on one single heatsink. If
this is indeed the case, just make one wide copper track that connects all three
grounds mentioned above to each other. Also combine in this copper track ground 2.
• Connect the grounds of 6b with each other.
• Make a so-called "star ground" from ground 6a, 6b, 6c, and 7. Ground 6a is the middle
of the star and is connected to pin 2 (this is the ground of the IC).
• Grounds marked with 7 do not have to be a so-called "star ground”.
• Place the y-cap across grounds 1 and 8. Preferably use one special copper track,
separated from all others for this connection (or use the connection copper track of
the heatsinks in a typical application setup for this purpose).
• C4, C15, C23 and C22 (in order of priority) should be placed as close as possible to
the IC. Reduce coupling between the PFC switching signals (PFC driver and
PFCAUX) and the flyback sense signals (FBSENSE and FBCTRL) as much as
possible, because this minimizes the risk of electromagnetic interference and audible
noise.
• Figure 23 shows an overview of the hierarchy of the different grounds at the bottom.
• Connect the anode of the TL431 (ground 8) to ground 9 with one special separate
connecting copper track. Minimize all other currents in this special track. The actual
place of connection should preferably be located as close as possible to the output.
AN10861
Application note
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Rev. 01 — 16 July 2010
© NXP B.V. 2010. All rights reserved.
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−
C2
2
12
1
3
BC1
T1
2
R5
C3
C8
R18
6c
LF2
4a
VCC
8
TEA1791
C30
4
GND
R5A
2 4
1
R6
D2
D4
Q1
R8
R9
U3
D30
D3
C5
1
11
1
DRIVER
C1
7
R6A
Q2
R14
R13
C9
CX1
R12
R2
C6
PFCAUX
C25
16
1
TEA1752
8
7
Q3
3
2
6
5
7
D23A
R20
C12 6
R34
R37
FBAUX
6b
FBCTRL
4
PFCCOMP
1
C34
R24
R35
C15
3
C35
2
R36
R25
RT2
NTC
C17
U4
6a
Θ
OPTIONAL
Vout −
R23
4
C29
8
U2
R29
C24
R23A
6b
VCC
6b
HV
FBSENSE
10
C13
C14
7
C28
C27
12
VINSENSE
R28
13
C23
11
R3
L3
C31
9, 10
D5
LATCH
R27
9
GND
PFCDRIVER
14 15
FBDRIVER
7
VOSENSE
7
BC2
R33
5
HVS
C4
U1
7, 8
R15
4b
R7
PFCTIMER
8
R32
R38
C22
R4
C21
C20
C19
R26
C18
7
7
7
7
7
7
7
C16
7
7
7
7
9
see section 5.2, 5.2.1
6c
7
large signal current loop
6b
43 of 46
© NXP B.V. 2010. All rights reserved.
large signal current loop
1
Fig 23. PCB layout considerations
2
3
4a
4b
8
9
019aaa047
AN10861
6a
4
large signal current loop
GreenChip III TEA1752 integrated PFC and flyback controller
Rev. 01 — 16 July 2010
All information provided in this document is subject to legal disclaimers.
RT1
NTC
1
n.c.
Q4
R17
PFCSENSE
CY1
R30
R16A
4
Θ
n.c.
7
Vout +
LF1
mains
inlet
n.c.
6
R10
C10
F1
n.c.
5
R11
R16
R1
3
SRSENSE
+
BD1
D1
L2
9
NXP Semiconductors
AN10861
Application note
L1
AN10861
NXP Semiconductors
GreenChip III TEA1752 integrated PFC and flyback controller
8. References
[1]
AN10861
Application note
IEC-60950 — Chapter 2.1.1.7 “discharge of capacitors in equipment”
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 16 July 2010
© NXP B.V. 2010. All rights reserved.
44 of 46
AN10861
NXP Semiconductors
GreenChip III TEA1752 integrated PFC and flyback controller
9. Legal information
9.1
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
9.2
Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
AN10861
Application note
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
9.3
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
GreenChip — is a trademark of NXP B.V.
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 16 July 2010
© NXP B.V. 2010. All rights reserved.
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AN10861
NXP Semiconductors
GreenChip III TEA1752 integrated PFC and flyback controller
10. Contents
1
1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.3
2
3
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.5
3.6
3.7
4
4.1
4.1.1
4.1.2
4.2
4.2.1
4.3
4.3.1
4.3.2
4.3.3
4.3.4
5
5.1
5.1.1
5.1.1.1
5.1.1.2
5.1.1.3
5.1.2
5.1.3
5.1.4
5.1.4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
The TEA1752 GreenChip III controller . . . . . . . 3
Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
System features . . . . . . . . . . . . . . . . . . . . . . . . 3
PFC features . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Flyback features . . . . . . . . . . . . . . . . . . . . . . . . 4
Application schematic . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 6
System description and calculation. . . . . . . . . 8
PFC and flyback start conditions . . . . . . . . . . . 8
Start-up sequence. . . . . . . . . . . . . . . . . . . . . . . 8
VCC cycle in safe restart protection mode. . . . 10
Mains voltage sensing and brownout . . . . . . . 11
Discharge of mains input capacitor. . . . . . . . . 11
Brownout voltage adjustment . . . . . . . . . . . . . 12
Internal Overtemperature Protection (OTP) . . 12
LATCH pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Fast latch reset . . . . . . . . . . . . . . . . . . . . . . . . 13
PFC description and calculation . . . . . . . . . . 13
PFC output power and voltage control . . . . . . 14
Setting the PFC output voltage. . . . . . . . . . . . 15
Calculation of the PFC soft start and soft
stop components . . . . . . . . . . . . . . . . . . . . . . 17
PFC demagnetizing and valley detection . . . . 17
Design of the PFCAUX winding and circuit . . 18
PFC protection modes . . . . . . . . . . . . . . . . . . 19
VOSENSE overvoltage protection . . . . . . . . . 19
VOSENSE open and short pin detection . . . . 19
VINSENSE open pin detection . . . . . . . . . . . . 20
Overcurrent protection . . . . . . . . . . . . . . . . . . 20
Flyback description and calculation . . . . . . . 20
Flyback output power control . . . . . . . . . . . . . 20
Three different operation modes of the
TEA1752. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Quasi-resonant mode . . . . . . . . . . . . . . . . . . . 22
Discontinuous conduction mode. . . . . . . . . . . 23
Frequency reduction mode . . . . . . . . . . . . . . . 23
The relationship between inductance value
and the hysteresis of the PFC . . . . . . . . . . . . 24
Relationship between Ipmin and the required
PFC-on/off level . . . . . . . . . . . . . . . . . . . . . . . 27
The influence of Rsense and the series
resistance R16 + R17 . . . . . . . . . . . . . . . . . . . 28
Calculating the saturation current Ip(sat)
of the flyback transformer . . . . . . . . . . . . . . . . 28
Calculation of Ipmax for flyback operating in
Quasi-resonant mode . . . . . . . . . . . . . . . . . .
5.1.4.3
Calculation of the current sense resistor
Rsense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.4.4
Calculation of the series resistance R16
and R17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.5
Calculation of the delay compensation
resistors RCOMP and R16A. . . . . . . . . . . . . . .
5.1.6
Calculation of the flyback soft start
components . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
Flyback control and PFC with delay
options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1
Improving start-up time of the PFC . . . . . . . .
5.3
Flyback protection mode . . . . . . . . . . . . . . . .
5.3.1
Short circuit on pin FBCTRL . . . . . . . . . . . . .
5.3.2
Open FBCTRL pin . . . . . . . . . . . . . . . . . . . . .
5.3.3
Time-out flyback control loop . . . . . . . . . . . . .
5.3.4
Overvoltage protection flyback. . . . . . . . . . . .
5.3.5
OverPower Protection (OPP). . . . . . . . . . . . .
6
Summary of calculations for adjustment
of the flyback . . . . . . . . . . . . . . . . . . . . . . . . . .
7
PCB layout considerations . . . . . . . . . . . . . .
8
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
Legal information . . . . . . . . . . . . . . . . . . . . . .
9.1
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.4.2
29
30
30
31
33
33
33
34
34
34
34
36
37
39
42
44
45
45
45
45
46
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 16 July 2010
Document identifier: AN10861
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