Data Sheet

TEA1752T
HV start-up DCM/QR flyback controller with integrated
DCM/QR PFC controller
Rev. 2 — 16 November 2012
Product data sheet
1. General description
The TEA1752T is the third generation of green Switched Mode Power Supply (SMPS)
controller ICs. The TEA1752T combines a controller for Power Factor Correction (PFC)
and a flyback controller. Its high level of integration allows the design of a cost-effective
power supply with a very low number of external components.
The special built-in green functions provide high efficiency at all power levels. This
efficiency applies to quasi-resonant operation at high-power levels, quasi-resonant
operation with valley skipping, as well as reduced frequency operation at lower power
levels. At low-power levels, the PFC switches off to maintain high efficiency.
During low-power conditions, the flyback controller switches to frequency reduction mode
and limits the peak current to an adjustable minimum value. This mode ensures high
efficiency at low-power and good standby power performance while minimizing audible
noise from the transformer.
The TEA1752T is a Multi-Chip Module, (MCM), containing 2 chips. The proprietary
high-voltage BCD800 process which makes direct start-up possible from the rectified
universal mains voltage in an effective and green way. The second low voltage
Silicon On Insulator (SOI) is used for accurate, high speed protection functions and
control.
The TEA1752T enables the design of highly efficient and reliable supplies with power
requirements of up to 250 W with a minimum number of external components.
Remark: All values provided throughout the running text, are typical values unless
otherwise stated.
TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
2. Features and benefits
2.1 Distinctive features




Integrated PFC and flyback controller
Universal mains supply operation (70 V AC to 276 V AC)
Dual boost PFC with accurate maximum output voltage (NXP patented)
High level of integration, resulting in a very low external component count and a
cost-effective design
 Adjustable PFC switch-off delay
2.2 Green features
 On-chip start-up current source
2.3 PFC green features
 Valley/zero voltage switching for minimum switching losses (NXP patented)
 Frequency limitation to reduce switching losses
 PFC is switched off when a low load is detected at the flyback output
2.4 Flyback green features
 Valley switching for minimum switching losses (NXP patented)
 Frequency reduction with adjustable minimum peak current at low-power operation to
maintain high efficiency at low output power levels
2.5 Protection features
 Safe restart mode for system fault conditions
 Continuous mode protection with demagnetization detection for both converters (NXP
patented)
 UnderVoltage Protection (UVP) (foldback during overload)
 Accurate OverVoltage Protection (OVP) for both converters (adjustable for flyback
converter)
 Mains voltage independent OverPower Protection (OPP)
 Open control loop protection for both converters. The open-loop protection on the
flyback converter is a safe restart
 OverTemperature Protection (OTP)
 Low and adjustable OverCurrent Protection (OCP) trip level for both converters
 General-purpose input for latched protection, for system OverTemperature Protection
(OTP) for example
3. Applications
 The device is used in all applications that require an efficient and cost-effective power
supply solution for up to 250 W. Notebook adapters in particular can benefit from the
high level of integration
TEA1752T
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 November 2012
© NXP B.V. 2012. All rights reserved.
2 of 33
TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
4. Ordering information
Table 1.
Ordering information
Type number
TEA1752T
TEA1752T
Product data sheet
Package
Name
Description
Version
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 November 2012
© NXP B.V. 2012. All rights reserved.
3 of 33
TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
5. Block diagram
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TEA1752T
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 November 2012
© NXP B.V. 2012. All rights reserved.
4 of 33
TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
6. Pinning information
6.1 Pinning
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Pin configuration: TEA1752T (SOT109-1)
6.2 Pin description
Table 2.
Pin description
Symbol
TEA1752T
Product data sheet
Pin
Description
VCC
1
supply voltage
GND
2
ground
FBCTRL
3
flyback control input
FBAUX
4
auxiliary winding input for demagnetization timing and flyback OVP
LATCH
5
general-purpose protection input
PFCCOMP
6
frequency compensation pin for PFC
VINSENSE
7
mains voltage sense input
PFCAUX
8
auxiliary winding input for demagnetization timing for PFC
VOSENSE
9
sense input for PFC output voltage
FBSENSE
10
flyback current sense input
PFCSENSE
11
PFC current sense input
PFCDRIVER
12
PFC gate-driver output
FBDRIVER
13
flyback gate-driver output
PFCTIMER
14
delay timer pin for PFC on/off control
HVS
15
high-voltage safety spacer, not connected
HV
16
high-voltage start-up / flyback valley sensing
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 November 2012
© NXP B.V. 2012. All rights reserved.
5 of 33
TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
7. Functional description
7.1 General control
The TEA1752T contains a controller for a power factor correction circuit as well as a
controller for a flyback circuit. A typical configuration is shown in Figure 3.
,&
DDD
Fig 3.
A typical configuration of the TEA1752T IC
7.1.1 Start-up and UnderVoltage LockOut (UVLO)
Initially the capacitor on the VCC pin is charged from the high-voltage mains from the HV
pin.
When VCC is less than Vtrip, the charge current is low. This low current protects the IC if
the VCC pin is shorted to ground. To ensure a short start-up time, the charge current
greater than Vtrip is increased until VCC reaches Vth(UVLO). When VCC is between Vth(UVLO)
and Vstartup, the charge current goes low again to ensure a low safe restart duty cycle
during fault conditions.
The control logic activates the internal circuitry and switches off the HV charge current
when the voltage on the VCC pin passes the Vstartup level. First, the LATCH pin current
source is activated and the soft-start capacitors on the PFCSENSE and FBSENSE pins
are charged. The clamp circuit on the PFCCOMP pin is also activated.
The PFC circuit is activated when the following conditions are met:
• the LATCH pin voltage exceeds the Ven(LATCH) voltage
• the PFCCOMP pin voltage reaches the Ven(PFCCOMP) voltage
• the soft-start capacitor on the PFCSENSE pin is charged
TEA1752T
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 November 2012
© NXP B.V. 2012. All rights reserved.
6 of 33
TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
If the soft-start capacitor on the FBSENSE pin is charged, the flyback converter is also
activated. The flyback converter output voltage is then regulated to its nominal output
voltage. The auxiliary winding of the flyback converter takes over the IC supply (see
Figure 4).
If during start-up the LATCH pin does not reach the Ven(LATCH) level before VCC reaches
Vth(UVLO), it is deactivated. The charge current is then switched on again.
When the flyback converter starts, VFBCTRL is monitored. If this output voltage does not
reach its intended regulation level within a specified time, the voltage on the FBCTRL pin
reaches the Vto(FBCTRL) level. An error is then assumed and a safe restart is initiated.
When one of the protection functions is activated, both converters stop switching and the
VCC voltage drops to Vth(UVLO). A latched protection recharges the capacitor CVCC using
the HV pin, but does not restart the converters. To provide safe restart protection, the
capacitor is recharged using the HV pin and the device restarts (see Figure 1).
If OVP of the PFC circuit (VVOSENSE > VOVP(VOSENSE)) occurs, the PFC controller stops
switching until the VOSENSE pin voltage drops to less than VOVP(VOSENSE). If a mains
undervoltage is detected VVINSENSE < Vstop(VINSENSE), the PFC controller stops switching
until VVINSENSE > Vstart(VINSENSE) again.
When the voltage on the VCC pin drops below the undervoltage lockout level, both
controllers stop switching and re-enter the safe restart mode. In the safe restart mode, the
driver outputs are disabled and the VCC pin voltage is recharged using the HV pin.
TEA1752T
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 November 2012
© NXP B.V. 2012. All rights reserved.
7 of 33
TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
IHV
Vstartup
Vth(UVLO)
Vtrip
VCC
Vstart(VINSENSE)
VINSENSE
Ven(PFCCOMP)
PFCCOMP
Ven(LA TCH)
LATCH
PROTECTION
soft start
PFCSENSE
PFCDRIVER
soft start
FBSENSE
FBDRIVER
Vto(FBCTRL)
FBCTRL
Vstart(fb)
VOSENSE
VO
charging VCC
capacitor
Fig 4.
starting
converters
normal
operation
protection
restart
014aaa744
Start-up sequence, normal operation and restart sequence
7.1.2 Supply management
All internal reference voltages are derived from a temperature compensated and trimmed
on-chip band gap circuit. Internal reference currents are derived from a temperature
compensated and trimmed on-chip current reference circuit.
7.1.3 Latch input
The LATCH pin is a general-purpose input pin, which is used to switch off both converters.
The pin sources a current IO(LATCH) of 80 A. Switching is stopped as soon as the voltage
on the latch pin drops below 1.25 V.
TEA1752T
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 November 2012
© NXP B.V. 2012. All rights reserved.
8 of 33
TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
At initial start-up, switching is stopped until the capacitor on the LATCH pin is charged
above 1.35 V. No internal filtering is done on this pin. An internal Zener clamp of 2.9 V
protects this pin from excessive voltages.
7.1.4 Fast latch reset
In a typical application, the mains is interrupted briefly to reset the latched protection. The
PFC bus capacitor, Cbus, does not have to discharge for this latched protection to reset.
When the VINSENSE voltage drops below 750 mV and is then raised to 870 mV, the
latched protection is reset.
The latched protection is also reset by removing both the voltage on the VCC and HV pins.
7.1.5 Overtemperature protection
An accurate internal temperature protection is provided in the circuit. When the junction
temperature exceeds the thermal shut-down temperature, the IC stops switching. While
OTP is active, the capacitor CVCC is not recharged from the HV mains. If the VCC supply
voltage is not sufficient, the OTP circuit is supplied from the HV pin.
OTP is a latched protection. It is reset by removing the voltage on the VCC and HV pins or
by the fast latch reset function (see Section 7.1.4).
7.2 Power factor correction circuit
The power factor correction circuit operates in quasi-resonant or Discontinuous
Conduction Mode (DCM) with valley switching. The next primary stroke is only started
when the previous secondary stroke has ended and the voltage across the PFC MOSFET
has reached a minimum value. VPFCAUX is used to detect transformer demagnetization
and the minimum voltage across the external PFC MOSFET switch.
7.2.1 ton control
The power factor correction circuit is operated in ton control. The resulting mains harmonic
reduction is well within the class-D requirements.
7.2.2 Valley switching and demagnetization (PFCAUX pin)
The PFC MOSFET is switched on after the transformer is demagnetized. Internal circuitry
connected to the PFCAUX pin detects the end of the secondary stroke. It also detects the
voltage across the PFC MOSFET. To reduce switching losses and electromagnetic
Interference (EMI), the next stroke is started if the voltage across the PFC MOSFET is at
its minimum (valley switching).
If a demagnetization signal is not detected on the PFCAUX pin, the controller generates a
Zero Current Signal (ZCS). This ZCS occurs 50 s after the last PFCGATE signal.
If a valley signal is not detected on the PFCAUX pin, the controller generates a valley
signal 4 s after demagnetization is detected.
To protect the internal circuitry during lightning events, for example, add a 5 k series
resistor to PFCAUX. To prevent incorrect switching due to external disturbance, place the
resistor close to the IC on the printed-circuit board.
TEA1752T
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 November 2012
© NXP B.V. 2012. All rights reserved.
9 of 33
TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
7.2.3 Frequency limitation
To optimize the transformer and minimize switching losses, the switching frequency is
limited to fsw(PFC)max. If the frequency for quasi-resonant operation is above the fsw(PFC)max
limit, the system switches over to DCM. The PFC MOSFET is only switched on at a
minimum voltage across the switch (valley switching).
7.2.4 Mains voltage compensation (VINSENSE pin)
The equation for the transfer function of a power factor corrector contains the square of
the mains input voltage. In a typical application this results in a low bandwidth for low
mains input voltages and a high bandwidth for high mains input voltages.
To compensate for the mains input voltage influence, the TEA1752T contains a correction
circuit. The average input voltage is measured using the VINSENSE pin and the
information is fed to an internal compensation circuit. Using this compensation, it is
possible to keep the regulation loop bandwidth constant over the mains input range. This
feature yields a fast transient response on load steps, while still complying with class-D
MHR requirements.
In a typical application, a resistor and two capacitors on the PFCCOMP pin set the
bandwidth of the regulation loop.
7.2.5 Soft start-up (PFCSENSE pin)
To prevent audible transformer noise at start-up or during hiccup, the soft-start function
slowly increases the transformer peak current. This increase is achieved by inserting RSS1
and CSS1 between the PFCSENSE pin and current sense resistor RSENSE1. An internal
current source charges the capacitor to:
V PFCSENSE = I start  soft PFC  R SS1
(1)
The voltage is limited to Vstart(soft)PFC.
The start level and the time constant of the increasing primary current level are adjusted
externally by changing the values of RSS1 and CSS1.
soft – s tart = 3  R SS1  C SS1
(2)
The charging current Istart(soft)PFC flows as long as VPFCSENSE is less than 0.5 V. If
VPFCSENSE exceeds 0.5 V, the soft-start current source starts limiting current Istart(soft)PFC.
When the PFC starts switching, the Istart(soft)PFC current source is switched off (see
Figure 5).
Resistor RSS1 and capacitor CSS1 are also used to prevent audible noise, when the PFC is
switched off by performing a soft stop.
TEA1752T
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 November 2012
© NXP B.V. 2012. All rights reserved.
10 of 33
TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
6
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Fig 5.
Soft start-up of PFC
7.2.6 Low-power mode
When the output power of the flyback converter (see Section 7.3) is low, the flyback
converter switches over to frequency reduction mode. When the maximum switching
frequency of the flyback drops below 48 kHz, the power factor correction circuit is
switched off to maintain high efficiency. Connect a capacitor to the PFCTIMER pin to delay
switching off (see Section 7.2.7).
During low-power mode operation, the PFCCOMP pin is clamped to a minimum voltage of
3.5 V and a maximum voltage of 3.9 V. The lower clamp voltage limits the maximum
power that is delivered when the PFC is switched on again. The upper clamp voltage
ensures that the PFC returns to its normal regulation point in a limited time when returning
from low-power mode.
When the flyback converter frequency exceeds 86 kHz, the power factor correction circuit
restores normal operation.
7.2.7 PFC off delay (PFCTIMER pin)
When the flyback converter maximum frequency drops below 48 kHz, the PFC is
switched off. The IC then outputs a 10 A current to the PFCTIMER pin. When the voltage
on the PFCTIMER pin reaches 3.6 V, the PFC is switched off by performing a soft-stop.
When the flyback converter frequency exceeds 86 kHz, a switch discharges the
PFCTIMER pin capacitor. When the voltage on the PFCTIMER pin drops below 1.27 V,
the PFC is switched on (see Figure 6).
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Fig 6. PFC start/stop via PPFCTIMER pin
TEA1752T
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 November 2012
© NXP B.V. 2012. All rights reserved.
11 of 33
TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
7.2.8 Dual-boost PFC
The mains input voltage modulates the PFC output voltage. The mains input voltage is
measured using the VINSENSE pin. If the voltage on the VINSENSE pin drops below
2.2 V, the current is sourced from the VOSENSE pin. To ensure stable switch-over, a
200 mV transition region is inserted around the 2.2 V (see Figure 7).
At low VINSENSE input voltages, the output current is 15 A. This output current, in
combination with the resistors on the VOSENSE pin, sets the lower PFC output voltage
level at low mains voltages. At high mains input voltages, the current switches to zero.
The PFC output voltage is then at its maximum. As this current is zero in this situation, it
does not affect the accuracy of the PFC output voltage.
To ensure proper switch-off, the VOSENSE current switches to its maximum value of
15 A when VVOSENSE drops below 2.1 V.
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Voltage to current transfer function for dual boost PFC
7.2.9 Overcurrent protection (PFCSENSE pin)
The maximum peak current is limited cycle-by-cycle by sensing the voltage across an
external sense resistor, RSENSE1, on the source of the external MOSFET. The voltage is
measured using the PFCSENSE pin.
7.2.10 Mains undervoltage lockout/brownout protection (VINSENSE pin)
To prevent the PFC from operating at very low mains input voltages, the voltage on the
VINSENSE pin is continuously sensed. When the voltage on this pin drops below the
Vstop(VINSENSE) level, switching of the PFC is stopped.
The voltage on the VINSENSE pin is clamped to a minimum value, Vstart(VINSENSE) 
Vpu(VINSENSE). This voltage clamping provides for a fast restart when the mains input
voltage is restored after a mains dropout.
7.2.11 Overvoltage protection (VOSENSE pin)
To prevent output overvoltage during load steps and mains transients, an overvoltage
protection circuit is built in.
When the voltage on the VOSENSE pin exceeds the VOVP(VOSENSE) level, switching of the
power factor correction circuit is stopped. Switching of the PFC recommences when the
VOSENSE pin voltage drops below the VOVP(VOSENSE) level again.
TEA1752T
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 November 2012
© NXP B.V. 2012. All rights reserved.
12 of 33
TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
When the resistor between the VOSENSE pin and ground is open, the overvoltage
protection is also triggered.
7.2.12 PFC open-loop protection (VOSENSE pin)
The power factor correction circuit does not start switching until the voltage on the
VOSENSE pin is greater than the Vth(ol)(VOSENSE) level. This feature protects the circuit
from open-loop and VOSENSE short-circuit.
7.2.13 Driver (PFCDRIVER pin)
The driver circuit to the gate of the power MOSFET has a current sourcing capability of
500 mA and a current sink capability of 1.2 A. These capabilities permit fast turn-on and
turn-off of of the power MOSFET for efficient operation.
7.3 Flyback controller
The TEA1752T includes a controller for a flyback converter. The flyback converter
operates in quasi-resonant or DCM with valley switching. The auxiliary winding of the
flyback transformer provides demagnetization detection and powers the IC after start-up.
7.3.1 Multimode operation
The TEA1752T flyback controller operates in several modes (see Figure 8).
flyback
switching
frequency
125 kHz
86 kHz
frequency
reduction
PFC off
PFC on
48 kHz
Ipmin
adjust
discontinuous
with valley
switching
quasi-resonant
output power
014aaa745
Fig 8.
Multimode operation flyback
At high output power the converter switches to quasi-resonant mode. The next converter
stroke starts after demagnetization of the transformer and detection of the valley. In
quasi-resonant mode switching losses are minimized. This minimization is achieved by
the converter only switching on when the voltage across the external MOSFET is at its
minimum (see Section 7.3.2).
TEA1752T
Product data sheet
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Rev. 2 — 16 November 2012
© NXP B.V. 2012. All rights reserved.
13 of 33
TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
To prevent high frequency operation at low loads, the maximum switching frequency is
limited to 125 kHz. When the frequency limit is reached, the quasi-resonant operation
changes to DCM with valley skipping. The frequency limit reduces the MOSFET switch-on
losses and conducted EMI.
A Voltage Controlled Oscillator (VCO) controls the frequency at very low power and
standby levels. The minimum frequency is reduced to zero. During frequency reduction
mode, the primary peak current is kept at an adjustable minimum level to maintain a high
efficiency. As the primary peak current is low in frequency reduction operation, no audible
noise is noticeable at switching frequencies in the audible range. Valley switching is also
active in this mode.
In frequency reduction mode, the PFC controller is switched off. The flyback maximum
frequency changes linearly with the control voltage on the FBCTRL pin (see Figure 9).
Hysteresis has been added for stable on and off switching of the PFC. At no-load
operation, the switching frequency is reduced to (almost) zero.
The input voltage of the flyback converter and the capacitance on the drain node of the
flyback power switch affect the frequency reduction slope. By choosing the proper
compensation, the frequency reduction slope for high input voltages are chosen as the
same as for low input voltages. This compensation yields an input voltage independent
PFC switch-on and switch-off power level (see the application information in Section 11).
PFC off
fsw(fb)max
PFC on
frequency
reduction
switching frequency
discontinuous
with valley
switching
1.5 V
Fig 9.
VFBCTRL
quasi resonant
014aaa159
Frequency control of flyback
7.3.2 Valley switching (HV pin)
A new cycle starts when the external MOSFET is switched on. VFBSENSE and VFBCTRL
determine the on-time. The MOSFET is then switched off and the secondary stroke starts.
After the secondary stroke, the drain voltage shows an oscillation with a frequency of
approximately:
1
f = -------------------------------------------------- 2     Lp  Cd  
TEA1752T
Product data sheet
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Rev. 2 — 16 November 2012
(3)
© NXP B.V. 2012. All rights reserved.
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TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
where Lp is the primary self-inductance of the flyback transformer and Cd is the
capacitance on the drain node.
When the internal oscillator voltage is high and the secondary stroke ended, the circuit
waits for the lowest drain voltage before starting a new primary stroke.
Figure 10 shows the drain voltage, valley signal, secondary stroke signal and the internal
oscillator signal.
Valley switching allows high frequency operation as capacitive switching losses are
reduced (see Equation 4). High frequency operation makes small and cost-effective
magnetic components possible.
2
1
P = ---  C d  V  f
2
(4)
primary
stroke
secondary
stroke
secondary
ringing
drain
valley
secondary
stroke
(2)
(1)
oscillator
014aaa027
(1) Start of new cycle at lowest drain voltage.
(2) Start of new cycle in a classical Pulse Width Modulation (PWM) system without valley detection.
Fig 10. Signals for valley switching
7.3.3 Current mode control (FBSENSE pin)
Current mode control is used for the flyback converter because of its good line regulation.
The FBSENSE pin senses the primary current across an external resistor and compares it
with an internal control voltage. The internal control voltage is proportional to the FBCTRL
pin voltage (see Figure 11).
TEA1752T
Product data sheet
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TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
The FBSENSE pin outputs a current of 3 A. This current runs through the resistors from
the FBSENSE pin to the sense resistor and creates an offset voltage. The minimum peak
current of the flyback is adjusted using this offset voltage. Adjusting the minimum peak
current level changes the frequency reduction slope (see Figure 8).
Vsense(fb)max
0.65 V
FBSENSE
offset voltage
PFC off
FBSENSE
peak voltage
PFC on
flyback
frequency
reduction
SENSE resistor
peak voltage
flyback
discontinuous
or QR
flyback
cycle skip
mode
0.325 V
1.5 V
2.0 V
VFBCTRL
014aaa747
Fig 11. Peak current control of flyback part
7.3.4 Demagnetization (FBAUX pin)
The system is always in QR or DCM mode. The internal oscillator does not start a new
primary stroke until the previous secondary stroke has ended.
Demagnetization features a cycle-by-cycle output short-circuit protection by immediately
lowering the frequency (longer off-time), thus reducing the power level.
Demagnetization recognition is suppressed during the first tsup(xfmr_ring) time of 2 s. This
suppression is necessary at low output voltages and at start-up. It can also be required in
applications where the transformer has a large leakage inductance.
If the FBAUX pin is open-circuit or not connected, a fault condition is assumed and the
converter immediately stops. Operation restarts as soon as the fault condition is removed.
7.3.5 Flyback control/time-out (FBCTRL pin)
The FBCTRL pin is connected to an internal voltage source of 3.5 V using an internal
resistor of 3 k. When the voltage on this pin exceeds 2.5 V, the connection is disabled
and the pin is biased with a small current. If the voltage on this pin exceeds 4.5 V, a fault is
assumed, switching is stopped and a restart is made.
If a capacitor and a resistor are connected in series to this pin, a time-out function is
created to protect against an open control loop. See Figure 12 and Figure 13. The
time-out function is disabled by connecting a resistor (100 k) to ground on the FBCTRL
pin.
If the pin is short-circuited to ground, switching of the flyback controller is prevented.
TEA1752T
Product data sheet
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TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
Under normal operating conditions, the converter regulates the output voltage. The
voltage on the FBCTRL pin then varies between 1.3 V for the minimum output power and
2 V for the maximum output power.
2.5 V
3.5 V
30 μA
4.5 V
3 kΩ
FBCTRL
time-out
014aaa049
Fig 12. Time-out protection circuit
4.5 V
2.5 V
VFBCTRL
output
voltage
intended output
voltage not
reached within
time-out time.
restart
intended output voltage
reached within time-out
time.
014aaa050
Fig 13. Time-out protection (signals), safe restart
7.3.6 Soft-start-up (FBSENSE pin)
To prevent audible transformer noise during start-up, the soft-start function slowly
increases the transformer peak current. This increase is achieved by inserting a resistor
and a capacitor between the FBSENSE and the current sense resistor.
An internal current source charges the capacitor to:
V = I start  soft fb  R SS2
(5)
with a maximum of approximately 0.63 V.
The start level and the time constant of the increasing primary current level are adjusted
externally by changing the values of RSS2 and CSS2.
soft – s tart = 3  R SS2  C SS2
TEA1752T
Product data sheet
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TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
The soft-start current Istart(soft)fb switches on as soon as VCC reaches Vstartup. When
VFBSENSE has reached 0.63 V, the flyback converter starts switching.
The charging current Istart(soft)(FB) flows as long as VFBSENSE is less than approximately
0.63 V. If VFBSENSE exceeds 0.63 V, the soft-start current source starts limiting the current.
After the flyback converter has started, the soft-start current source is switched off.
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Fig 14. Soft start-up of flyback.
7.3.7 Maximum on-time
The flyback controller limits the on-time of the external MOSFET to 40 s. When the
on-time is longer than 40 s, the IC stops switching and enters the safe restart mode.
7.3.8 Overvoltage protection (FBAUX pin)
An output overvoltage protection is implemented in the GreenChip III series. In the
TEA1752T, the auxiliary voltage is sensed using the current flowing into the FBAUX pin
during the secondary stroke. The auxiliary winding voltage is a well-defined replica of the
output voltage. An internal filter averages voltage spikes.
An internal up-down counter prevents false OVP detection which can occur during ESD or
lightning events. The internal counter counts up by one when the output voltage exceeds
the OVP trip level within one switching cycle. The internal counter counts down by two
when the output voltage has not exceeded the OVP trip level within one switching cycle.
When the counter has reached eight, the IC assumes a true OVP, sets the latched
protection and switches off both converters.
The converter only restarts after the OVP latch is reset. In a typical application, the
internal latch is reset when the VINSENSE voltage drops below 750 mV and is then raised
to 870 mV.
The latched protection is also reset by removing both the voltage on the VCC and HV
pins.
The demagnetization resistor, RFBAUX sets the output voltage Vo(OVP) at which the OVP
function trips:
Ns
V o  OVP  = -----------  I ovp  FBAUX   R FBAUX + V clamp  FBAUX  
N aux
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NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
where Ns is the number of secondary turns and Naux is the number of auxiliary turns of the
transformer. Current Iovp(FBAUX) is internally trimmed.
Accurate OVP detection is made possible by adjusting the value of RFBAUX to the turns
ratio of the transformer.
7.3.9 Overcurrent protection (FBSENSE pin)
The primary peak current in the transformer is measured accurately cycle-by-cycle using
the external sense resistor Rsense2. Vfbctrl sets the level to which the OCP circuit limits
VFBSENSE (see Section 7.3.3). The OCP detection is suppressed during the leading-edge
blanking period, tleb, to prevent false triggering due to switch-on spikes.
tleb
OCP level
VFBSENSE
t
014aaa022
Fig 15. OCP leading edge blanking
7.3.10 Overpower protection
During the primary stroke of the flyback converter, the input voltage is measured by
sensing the current drawn from the FBAUX pin.
The current information is used to limit the maximum peak current of the flyback converter,
measured from the FBSENSE pin. The internal compensation is such that a maximum
output power, which is almost independent of the input voltage, is realized.
The OPP curve is given in Figure 16.
VFBSENSE
(V)
0.65
0.46
−360
IFBAUX (μA)
−100
0
014aaa749
Fig 16. Overpower protection curve
TEA1752T
Product data sheet
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TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
7.3.11 Driver (FBDRIVER pin)
The driver circuit to the power MOSFET gate has a current sourcing capability of 500 mA
and a current sink capability of 1.2 A. These capabilities permit fast turn-on and turn-off of
the power MOSFET, thus ensuring efficient operation.
8. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
0.4
+38
V
0.4
+5
V
Voltages
VCC
supply voltage
VLATCH
voltage on the LATCH pin
VFBCTRL
voltage on the FBCTRL pin
0.4
+5
V
VPFCCOMP
voltage on pin PFCCOMP
pin
0.4
+5
V
VVINSENSE
voltage on the VINSENSE
pin
0.4
+5
V
VVOSENSE
voltage on the VOSENSE
pin
0.4
+5
V
VPFCAUX
voltage on the PFCAUX pin
25
+25
V
VFBSENSE
voltage on the FBSENSE pin current limited
0.4
+5
V
0.4
+5
V
0.4
+5.5
V
voltage on the HV pin
0.4
+650
V
IFBCTRL
current on the FBCTRL pin
3
0
mA
IFBAUX
current on the FBAUX pin
1
+1
mA
IPFCSENSE
current on the PFCSENSE
pin
1
+10
mA
IFBSENSE
current on the FBSENSE pin
1
+10
mA
IFBDRIVER
current on the FBDRIVER
pin
duty cycle < 10 %
0.8
+2
A
duty cycle < 10 %
0.8
+2
A
-
8
mA
-
0.6
W
VPFCSENSE voltage on the PFCSENSE
pin
current limited
current limited
VPFCTIMER voltage on the PFCTIMER
pin
VHV
Currents
IPFCDRIVER current on the PFCDRIVER
pin
IHV
current on the HV pin
General
TEA1752T
Product data sheet
Tamb < 75 C
Ptot
total power dissipation
Tstg
storage temperature
55
+150
C
Tj
junction temperature
40
+150
C
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TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
Table 3.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
electrostatic discharge
voltage
class 1
Min
Max
Unit
ESD
VESD
human body
model
pins 1 to 13
[1]
-
2000
V
pin 16 (HV)
[1]
-
1500
V
machine model
[2]
-
200
V
-
500
V
charged device
model
[1]
Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
[2]
Equivalent to discharging a 200 pF capacitor through a 0.75 H coil and a 10  resistor.
9. Thermal characteristics
Table 4.
Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from
junction to ambient
in free air; JEDEC test board
124
K/W
Rth(j-c)
thermal resistance from
junction to case
in free air; JEDEC test board
37
K/W
10. Characteristics
Table 5.
Characteristics
Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC < Vtrip;
Vth(UVLO) < VCC < Vstartup
-
1
-
mA
Vtrip < VCC < Vth(UVLO)
-
5.4
-
mA
Start-up current source (HV pin)
IHV
supply current drawn from
the HV pin
VHV > 80 V
with auxiliary supply
VBR
breakdown voltage
8
20
40
A
650
-
-
V
Supply voltage management (VCC pin)
Vtrip
trip voltage
0.55
0.65
0.75
V
Vstartup
start-up voltage
21
22
23
V
Vth(UVLO)
undervoltage lockout threshold
voltage
14
15
16
V
Vstart(hys)
hysteresis of start voltage
during start-up phase
-
300
-
mV
Vhys
hysteresis voltage
Vstartup  Vth(UVLO)
6.3
7
7.7
V
Ich(low)
low charging current
VHV > 80 V; VCC < Vtrip or
Vth(UVLO) < VCC < Vstartup
1.2
1.0
0.8
mA
TEA1752T
Product data sheet
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TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
Table 5.
Characteristics …continued
Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Ich(high)
high charging current
VHV > 80 V; Vtrip < VCC < Vth(UVLO)
4.6
5.4
6.3
mA
ICC(oper)
operating supply current
no-load on FBDRIVER and
PFCDRIVER pins
2.25
3
3.75
mA
Input Voltage Sensing PFC (VINSENSE pin)
Vstop(VINSENSE)
stop voltage on the VINSENSE
pin
0.86
0.89
0.92
V
Vstart(VINSENSE)
start voltage on the VINSENSE
pin
1.11
1.15
1.19
V
Vpu(VINSENSE)
pull-up voltage difference on
the VINSENSE pin
active after Vstop(VINSENSE) is
detected
-
100
-
mV
Ipu(VINSENSE)
pull-up current on the
VINSENSE pin
active after Vstop(VINSENSE) is
detected
55
47
40
A
4
-
-
V
-
0.75
-
V
Vmvc(VINSENSE)max maximum mains voltage
compensation voltage on the
VINSENSE pin
Vflr
fast latch reset voltage
active after Vth(UVLO) is detected
Vflr(hys)
hysteresis of fast latch reset
voltage
-
0.12
-
V
II(VINSENSE)
input current on the VINSENSE VVINSENSE > Vstop(VINSENSE) after
pin
Vstart(VINSENSE) is detected
5
33
100
nA
Vbst(dual)
dual boost voltage
current switch-over point
-
2.2
-
V
switch-over region
-
200
-
mV
Loop compensation PFC (PFCCOMP pin)
gm
transconductance
VVOSENSE to IO(PFCCOMP)
60
80
100
A/V
IO(PFCCOMP)
output current on the
PFCCOMP pin
VVOSENSE = 2 V
33
39
45
A
Ven(PFCCOMP)
enable voltage on pin
PFCCOMP
Vclamp(PFCCOMP)
clamp voltage on the
PFCCOMP pin
VVOSENSE = 3.3 V
Low-power mode; PFC off; lower
clamp voltage.
Upper clamp voltage
[1]
45
39
33
A
-
3.5
-
V
-
3.5
-
V
-
3.9
-
V
Vton(PFCCOMP)zero
zero on-time voltage on the
PFCCOMP pin
3.4
3.5
3.6
V
Vton(PFCCOMP)max
maximum on-time voltage on
the PFCCOMP pin
1.20
1.25
1.30
V
VVINSENSE = 3.3 V;
VPFCCOMP = Vton(PFCCOMP)max
3.6
4.5
5
s
VVINSENSE = 0.9 V;
VPFCCOMP = Vton(PFCCOMP)max
30
40
53
s
-
1.15
-
V
Pulse width modulator PFC
ton(PFC)
PFC on-time
Output voltage sensing PFC (VOSENSE pin)
Vth(ol)(VOSENSE)
TEA1752T
Product data sheet
open-loop threshold voltage on
the VOSENSE pin
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TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
Table 5.
Characteristics …continued
Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vreg(VOSENSE)
regulation voltage on the
VOSENSE pin
for IO(PFCCOMP) = 0
2.475 2.500 2.525 V
Vovp(VOSENSE)
overvoltage protection voltage
on the VOSENSE pin
Ibst(dual)
dual boost current
2.60
2.63
2.67
V
VVINSENSE < Vbst(dual) or
VVOSENSE < 2.1 V
-
15
-
A
VVINSENSE > Vbst(dual)
-
30
-
nA
V/t = 50 mV/s
0.49
0.52
0.55
V
V/t = 200 mV/s
Over current protection PFC (PFCSENSE pin)
Vsense(PFC)max
maximum PFC sense voltage
0.51
0.54
0.57
V
tleb(PFC)
PFC leading edge blanking
time
250
310
370
ns
Iprot(PFCSENSE)
protection current on the
PFCSENSE pin
50
-
5
nA
75
60
45
A
Soft-start PFC (PFCSENSE pin)
Istart(soft)PFC
PFC soft-start current
Vstart(soft)PFC
PFC soft-start voltage
enabling voltage
0.46
0.50
0.54
V
Vstop(soft)PFC
PFC soft-stop voltage
disabling voltage
0.42
0.45
0.48
V
-
250
-
kHz
0.8
1.1
1.4
s
-
-
1.7
V/s
Oscillator PFC
fsw(PFC)max
maximum PFC switching
frequency
toff(PFC)min
minimum PFC off-time
.
Valley switching PFC (PFCAUX pin)
(V/t)vrec(PFC)
PFC valley recognition voltage
change with time
tvrec(PFC)
PFC valley recognition time
tto(vrec)PFC
VPFCAUX = 1 V peak-to-peak
[2]
-
-
300
ns
demagnetization to V/t = 0
[3]
-
-
50
ns
3
4
6
s
PFC valley recognition time-out
time
Demagnetization management PFC (PFCAUX pin)
Vth(comp)PFCAUX
comparator threshold voltage
on the PFCAUX pin
150
100
50
mV
tto(demag)PFC
PFC demagnetization time-out
time
40
50
60
s
Iprot(PFCAUX)
protection current on the
PFCAUX pin
75
-
5
nA
VPFCAUX = 50 mV
PFC off delay (PFCTIMER pin)
Isource(PFCTIMER)
source current on the
PFCTIMER pin
-
10

A
Isink(PFCTIMER)
sink current on the PFCTIMER VPFCTIMER = 5 V
pin
-
0.95

mA
Vstart(PFCTIMER)
start voltage on the PFCTIMER
pin
-
1.27
-
V
TEA1752T
Product data sheet
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TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
Table 5.
Characteristics …continued
Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Vstop(PFCTIMER)
stop voltage on the PFCTIMER
pin
Min
Typ
Max
Unit
-
3.6
-
V
-
A
Driver (PFCDRIVER pin)
Isrc(PFCDRIVER)
source current on the
PFCDRIVER pin
VPFCDRIVER = 2 V
-
0.5
Isink(PFCDRIVER)
sink current on the
PFCDRIVER pin
VPFCDRIVER = 2 V
-
0.7
-
A
VPFCDRIVER = 10 V
-
1.2
-
A
9.5
10.8
12
V
A
VO(PFCDRIVER)max
maximum output voltage on the
PFCDRIVER pin
OverVoltage Protection flyback (FBAUX pin)
Iovp(FBAUX)
overvoltage protection current
on the FBAUX pin
279
300
321
Ncy(ovp)
number of overvoltage
protection cycles
6
8
12
60
80
110
mV
-
5
nA
Demagnetization management flyback (FBAUX pin)
Vth(comp)FBAUX
comparator threshold voltage
on the FBAUX pin
Iprot(FBAUX)
protection current on the
FBAUX pin
VFBAUX = 50 mV
75
Vclamp(FBAUX)
clamp voltage on the FBAUX
pin
IFBAUX = 100 A
0.85 0.7
0.55 V
IFBAUX = 300 A
0.79
0.94
1.09
V
1.5
2
2.5
s
tsup(xfmr_ring)
transformer ringing
suppression time
Pulse width modulator flyback
ton(fb)min
minimum flyback on-time
-
tleb
-
ns
ton(fb)max
maximum flyback on-time
32
40
48
s
fsw(fb)max
maximum flyback switching
frequency
100
125
150
kHz
Vstart(VCO)FBCTRL
VCO start voltage on the
FBCTRL pin
1.3
1.5
1.7
V
fsw(fb)swon(PFC)
PFC switch-on flyback
switching frequency
-
86
-
kHz
fsw(fb)swoff(PFC)
PFC switch-off flyback
switching frequency
-
48
-
kHz
VVCO(FBCTRL)
VCO voltage difference on the
FBCTRL pin
-
0.12 -
V
Oscillator flyback
Peak current control flyback (FBCTRL pin)
VFBCTRL
voltage on the FBCTRL pin
for maximum flyback peak current
1.85
2
2.15
V
Vto(FBCTRL)
time-out voltage on the
FBCTRL pin
enable voltage
-
2.5
-
V
trip voltage
4.2
4.5
4.8
V
-
3
-
k
Rint(FBCTRL)
TEA1752T
Product data sheet
internal resistance on the
FBCTRL pin
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TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
Table 5.
Characteristics …continued
Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IO(FBCTRL)
output current on the FBCTRL
pin
VFBCTRL = 0 V
1.4
1.19 0.93 mA
VFBCTRL = 2 V
0.6
0.5
0.4
mA
Ito(FBCTRL)
time-out current on the
FBCTRL pin
VFBCTRL = 2.6 V
36
30
24
A
VFBCTRL = 4.1 V
34.5 28.5 22.5 A
Valley switching flyback (HV pin)
(V/t)vrec(fb)
flyback valley recognition
voltage change with time
td(vrec-swon)
valley recognition to switch on
delay time
[4]
75
-
+75
V/s
-
150
-
ns
75
60
45
A
0.55
0.63
0.70
V
Soft-start flyback (FBSENSE pin)
Istart(soft)fb
flyback soft-start current
Vstart(soft)fb
flyback soft-start voltage
enable voltage
Overcurrent protection flyback (FBSENSE pin)
Vsense(fb)max
maximum flyback sense
voltage
V/t = 50 mV/s
0.61
0.65
0.69
V
V/t = 200 mV/s
0.64
0.68
0.72
V
Vsense(fb)min
minimum flyback sense voltage V/t = 50 mV/s
0.305 0.325 0.345 V
tleb(fb)
flyback leading edge blanking
time
255
305
355
ns
Iadj(FBSENSE)
adjust current on the
FBSENSE pin
3.2
3
2.8
A
IFBAUX = 80 A
0.61
0.65
0.69
V
IFBAUX = 120 A
0.57
0.62
0.67
V
IFBAUX = 240 A
0.47
0.52
0.57
V
IFBAUX = 360 A
0.41
0.46
0.51
V
VFBDRIVER = 2 V
-
0.5
-
A
Overpower protection flyback (FBSENSE pin)
Vsense(fb)max
V/t = 50 mV/s
maximum flyback sense
voltage
Driver (FBDRIVER pin)
Isrc(FBDRIVER)
source current on the
FBDRIVER pin
Isink(FBDRIVER)
sink current on the FBDRIVER VFBDRIVER = 2 V
pin
VFBDRIVER = 10 V
-
0.7
-
A
-
1.2
-
A
maximum output voltage on the
FBDRIVER pin
9.5
10.8
12
V
1.23
1.25
1.27
V
VO(FBDRIVER)(max)
LATCH input (LATCH pin)
Vprot(LATCH)
protection voltage on the
LATCH pin
IO(LATCH)
output current on the LATCH
pin
Vprot(LATCH) < VLATCH < Voc(LATCH)
85
80
75
A
Ven(LATCH)
enable voltage on the LATCH
pin
at start-up
1.30
1.35
1.40
V
Vhys(LATCH)
hysteresis voltage on the
LATCH pin
Ven(LATCH)  Vprot(LATCH)
80
100
140
mV
TEA1752T
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 November 2012
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TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
Table 5.
Characteristics …continued
Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Voc(LATCH)
open-circuit voltage on the
LATCH pin
Min
Typ
Max
Unit
2.65
2.9
3.15
V
Temperature protection
Tpl(IC)
IC protection level temperature
130
140
150
C
Tpl(IC)hys
hysteresis of IC protection level
temperature
-
10
-
C
[1]
For a typical application with a compensation network on pin PFCCOMP, like the example in Figure 3.
[2]
Minimum required voltage change time for valley recognition on pin PFCAUX.
[3]
Minimum time required between demagnetization detection and V/t = 0 on pin PFCAUX.
[4]
Guaranteed by design.
TEA1752T
Product data sheet
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Rev. 2 — 16 November 2012
© NXP B.V. 2012. All rights reserved.
26 of 33
TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
11. Application information
A power supply with the TEA1752T consists of a power factor correction circuit and a
flyback converter (see Figure 17).
Capacitor CVCC buffers the IC supply voltage. The IC is powered using the high voltage
rectified mains during start-up and the auxiliary winding of the flyback converter during
operation. Sense resistors RSENSE1 and RSENSE2 convert the current through the
MOSFETs S1 and S2 into a voltage at the PFCSENSE and FBSENSE pins. The values of
RSENSE1 and RSENSE2 define the maximum primary peak current in MOSFETs S1 and S2.
In the example given, the LATCH pin is connected to a Negative Temperature Coefficient
(NTC) resistor. The protection is activated when the resistance drops below a value
calculated as follows:
V prot  LATCH 
------------------------------- = 15.6 k
I O  LATCH 
(8)
A capacitor CTIMEOUT is connected to the FBCTRL pin. RLOOP is added so that the
time-out capacitor does not interfere with the normal regulation loop.
RS1 and RS2 are added to prevent the soft-start capacitors from being charged during
normal operation due to negative voltage spikes across the sense resistors.
Resistor RAUX1 is added to protect the IC from damage during lightning events.
RS3 and RCOMP are added to compensate for input voltage variations. The (stray)
capacitance on the drain node of MOSFET S3 affects the frequency reduction slope and
therefore the PFC switch-on and switch-off levels. Choosing the proper values for RS3
and RCOMP results in an input voltage independent PFC switch-on and switch-off power
level.
TEA1752T
Product data sheet
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Rev. 2 — 16 November 2012
© NXP B.V. 2012. All rights reserved.
27 of 33
TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
DDD
Fig 17. Typical application diagram for the TEA1752T IC
TEA1752T
Product data sheet
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Rev. 2 — 16 November 2012
© NXP B.V. 2012. All rights reserved.
28 of 33
TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 18. Package outline SOT109-1 (SO16)
TEA1752T
Product data sheet
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Rev. 2 — 16 November 2012
© NXP B.V. 2012. All rights reserved.
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TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
13. Revision history
Table 6.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TEA1752T v.2
20121116
Product data sheet
-
TEA1752T v.1
-
-
Modifications:
TEA1752T v.1
TEA1752T
Product data sheet
•
•
•
Multiple text changes
Multiple graphic updates
Updates to several characteristics
20090210
Objective data sheet
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Rev. 2 — 16 November 2012
© NXP B.V. 2012. All rights reserved.
30 of 33
TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
TEA1752T
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 November 2012
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TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
GreenChip — is a trademark of NXP B.V.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
TEA1752T
Product data sheet
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Rev. 2 — 16 November 2012
© NXP B.V. 2012. All rights reserved.
32 of 33
TEA1752T
NXP Semiconductors
HV start-up flyback controller with integrated PFC controller
16. Contents
1
2
2.1
2.2
2.3
2.4
2.5
3
4
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.2
7.2.1
7.2.2
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Distinctive features . . . . . . . . . . . . . . . . . . . . . . 2
Green features . . . . . . . . . . . . . . . . . . . . . . . . . 2
PFC green features . . . . . . . . . . . . . . . . . . . . . 2
Flyback green features . . . . . . . . . . . . . . . . . . . 2
Protection features . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 6
General control . . . . . . . . . . . . . . . . . . . . . . . . . 6
Start-up and UnderVoltage LockOut (UVLO) . . 6
Supply management. . . . . . . . . . . . . . . . . . . . . 8
Latch input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Fast latch reset . . . . . . . . . . . . . . . . . . . . . . . . . 9
Overtemperature protection . . . . . . . . . . . . . . . 9
Power factor correction circuit . . . . . . . . . . . . . 9
ton control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Valley switching and demagnetization
(PFCAUX pin) . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.2.3
Frequency limitation . . . . . . . . . . . . . . . . . . . . 10
7.2.4
Mains voltage compensation
(VINSENSE pin) . . . . . . . . . . . . . . . . . . . . . . . 10
7.2.5
Soft start-up (PFCSENSE pin) . . . . . . . . . . . . 10
7.2.6
Low-power mode . . . . . . . . . . . . . . . . . . . . . . 11
7.2.7
PFC off delay (PFCTIMER pin) . . . . . . . . . . . 11
7.2.8
Dual-boost PFC . . . . . . . . . . . . . . . . . . . . . . . 12
7.2.9
Overcurrent protection (PFCSENSE pin) . . . . 12
7.2.10
Mains undervoltage lockout/brownout
protection (VINSENSE pin) . . . . . . . . . . . . . . 12
7.2.11
Overvoltage protection (VOSENSE pin) . . . . . 12
7.2.12
PFC open-loop protection (VOSENSE pin) . . 13
7.2.13
Driver (PFCDRIVER pin) . . . . . . . . . . . . . . . . 13
7.3
Flyback controller . . . . . . . . . . . . . . . . . . . . . . 13
7.3.1
Multimode operation . . . . . . . . . . . . . . . . . . . . 13
7.3.2
Valley switching (HV pin) . . . . . . . . . . . . . . . . 14
7.3.3
Current mode control (FBSENSE pin) . . . . . . 15
7.3.4
Demagnetization (FBAUX pin) . . . . . . . . . . . . 16
7.3.5
Flyback control/time-out (FBCTRL pin) . . . . . 16
7.3.6
Soft-start-up (FBSENSE pin) . . . . . . . . . . . . . 17
7.3.7
Maximum on-time . . . . . . . . . . . . . . . . . . . . . . 18
7.3.8
Overvoltage protection (FBAUX pin) . . . . . . . 18
7.3.9
Overcurrent protection (FBSENSE pin) . . . . . 19
7.3.10
7.3.11
8
9
10
11
12
13
14
14.1
14.2
14.3
14.4
15
16
Overpower protection. . . . . . . . . . . . . . . . . . .
Driver (FBDRIVER pin) . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Thermal characteristics . . . . . . . . . . . . . . . . .
Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
20
20
21
21
27
29
30
31
31
31
31
32
32
33
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 16 November 2012
Document identifier: TEA1752T
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