TS61001 Datashet

TS61001
Full-bridge FET Driver
TRIUNE PRODUCTS
Features
Description
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The TS61001 is a high-voltage FET driver that can be used to
drive N-channel devices in full or half bridge configurations.
The TS61001 can support various power converter
applications, multiple standard and proprietary wireless power
applications, and motor driver systems.
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Supports Qi®, PMA, A4WP and proprietary wireless power
applications
Power outputs scalable based on FET size
Support for half and full-bridge power sections
Integrated comparator
Low external component count
Available in 28 pin 5x5 QFN
Specifications
Applications
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Multi-standard compliant and non-compliant wireless
chargers for:
ŒŒ Cell Phones and Smartphones
ŒŒ GPS Devices
ŒŒ Digital Cameras
ŒŒ Tablets and eReaders
ŒŒ Portable Lighting
Full and half-bridge power converters
Motor drive applications
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Drives both low side and high side N-channel MOSFETS
6Ω pull-up, 2Ω pull-down gate drivers
Independent TTL compatible inputs
Floating gate drive and bootstrap circuits for driving high
side devices – up to 85V for the bootstrap supply voltage
5 - 12V gate drive capability allows compatibility with a
wide range of FETs
Fast propagation delays (<50nS typical)
Matched channel to channel delays (<25nS mismatch)
Fast rise and fall times
Optional break before make detection to set minimum
dead time protection
Available comparator, amplifier and 3.3V linear regulator
(10mA capability) for supporting circuitry
Under voltage lock out protection
Over temperature shut down (TSD) protection
Typical Application Circuit
TS61001
Final Datasheet
March 19, 2015
Rev 1.2
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Pinout (Top View)
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Rev 1.2
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Pin Description
Pin #
Pin Name
Pin Function
Description
1
VS1
FET drive
High side MOSFET source #1
2
HO1
FET drive
High side MOSFET gate drive #1
3
LO1
FET drive
Low side MOSFET gate drive #1
4
VCCG
Input power
Input power supply (gate drive supply)
5
PGND
Power GND
Power GND
6
LO2
FET drive
Low side MOSFET gate drive #2
7
HO2
FET drive
High side MOSFET gate drive #2
8
VS2
FET drive
High side MOSFET source #2
9
VB2
Bootstrap
Bootstrap for gate drive #2
10
LS1ON
PWM1_L
Low-side gate control #1
11
HS1ON
PWM1_H
High-side gate control #1
12
LS2ON
PWM2_L
Low-side gate control #2
13
AGND
Analog GND
Analog GND
14
V5INT
Decoupling
Internal 5V regulator decoupling
15
SDATA
I2C Data
I2C data
16
SCLK
I2C Clock
I2C clock
17
V3P3
Decoupling
Internal 3.3V regulator decoupling
18
HS2ON
PWM2_H
High-side gate control #2
19
COMPOUT
Comparator
Comparator output
20
COMPN
Comparator
Comparator input (-)
21
COMPP
Comparator
Comparator input (+)
22
PGND
Power GND
Power GND
23
NC
No Connect
No Connect
24
PGND
Power GND
Power GND
25
VCC
Input power
Input power supply (main device supply)
26
/SLEEP
Disable
Disable Pin (active low)
27
NC
No Connect
No Connect
28
VB1
Bootstrap
Bootstrap for gate drive #1
TS61001
Final Datasheet
March 19, 2015
Rev 1.2
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Functional Block Diagram
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Final Datasheet
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Rev 1.2
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Absolute Maximum Rating
Over operating free–air temperature range unless otherwise noted(1, 2)
Parameter
Value
VCCG, VCC
Unit
13.2
V
13.2 (relative to VS1, VS2)
V
SDATA, SCLK
3.6
V
LS1ON, LS2ON, HS1ON, HS2ON
3.6
V
COMPN, COMPP, COMPOUT
3.6
V
Electrostatic Discharge – Human Body Model
+/-2k
V
Electrostatic Discharge – Charge Device Model
+/-500
V
260
°C
VB1, VB2
Lead Temperature (soldering, 10 seconds)
Notes:
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
Thermal Characteristics
Symbol
Parameter
Value
Units
ΘJA
Thermal Resistance Junction to Air (Note 1)
34.5
°C/W
ΘJC
Thermal Resistance Junction to Case (Note 1)
2.5
°C/W
TSTG
Storage Temperature Range
-65 to 150
°C
Maximum Junction Temperature
150
°C
Operating Junction Temperature Range
-40 to 125
°C
TJ MAX
TJ
Note 1: Assumes 16LD 3x3 QFN with hi-K JEDEC board and 13.5 inch2 of 1 oz Cu and 4 thermal vias connected to PAD
Recommended Operating Conditions
Symbol
VCCG / VCC
Parameter
Min
Input Operating Voltage
5
Rev 1.2
8
12.5
V
10
uF
Internal 3.3V Bypass Capacitor
4.7
uF
Internal 5V Bypass Capacitor
100
nF
Bootstrap Capacitor
47
nF
C3P3BYP
TS61001
Final Datasheet
March 19, 2015
Unit
nF
VCCG / VCC Bypass Capacitors
CBST
Max
100
CVCCBYP
CV5INTBYP
Typ
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Electrical Characteristics
Electrical Characteristics, TJ = -40C to 125C, VCC = 12V (unless otherwise noted)
Symbol
Parameter
Condition
Min
Typ
Max Unit
5
8
12.5
V
0.5
1.5
3
mA
VCC Supply Voltage
VCCG / VCC
Input Supply Voltage
Iq
Input Supply current
/SLEEP = Hi; No loads; Gate drivers off
Iq
Input Supply current
/SLEEP = Hi; Gate driver Fs = 200KHz (no load)
4
5
mA
Iqq_sleep
Stand by current
/SLEEP = 0V; Inputs driven Low
3
10
uA
Ron (pulldown)
HS,LS pull down device
VCCG/VCC = 12V
1.4
2
Ω
Ron (pullup)
HS, LS pull up device
VCCG/VCC = 12V
4.0
6.5
Ω
Ron Characteristics
Under Voltage Lock Out
UVLO (rise)
UV threshold (VCCG)
Rising threshold measurement
4.1
4.35
4.5
V
UVLO (fall)
UV threshold (VCCG)
Falling threshold measurement
3.8
4
4.3
V
UVLO (hyst)
UV hysteresis (VCCG)
Hysteresis
0.15
0.25
V
UVLO (rise)
UV threshold (VCC)
Rising threshold measurement
4.1
4.35
4.5
V
UVLO (fall)
UV threshold (VCC)
Falling threshold measurement
3.8
4
4.3
V
UVLO (hyst)
UV hysteresis (VCC)
Hysteresis
0.15
0.25
V
1.5
2.2
V
Input Pins VIH & VIL
VIH
Digital Input Pins
Gate driver inputs, I2C
VIL
Digital Input Pins
Gate driver inputs, I2C
0.8
1.3
V
Hyst
Digital Input Pins
Gate driver inputs, I2C
0.1
0.2
V
Propagation Delays & Rise/Fall times
TPLShl
Prop delay (LS) high to low
LSxON to LO1 (11V)
15
50
nS
TPLSlh
Prop delay (LS) low to high
LSxON to LO1(1V)
15
50
nS
TPHShl
Prop delay (HS) high to low
HSxON to HOx (HOx – VSx = 10V)
25
50
nS
TPHSlh
Prop delay (HS) low to high
HSxON to HOx (HOx – VSx = 1V)
25
50
nS
TPMMlshs
Prop delay mismatch (ls to hs)
LS off to HS on mismatch
10
40
nS
TPMMhsls
Prop delay mismatch (hs to ls)
HS off to LS on mismatch
10
40
nS
Minimum pulse width response
80
TPWmin
nS
Tr
Rise time (HS/LS)
1nF load; 20 – 80%
20
nS
Tp
Fall time (HS/LS)
1nF load; 80 – 20%
20
nS
3.45
V
V3P3 Regulator
Vout
Nominal Output voltage
Iout
External loading
Output Current capability
3.15
3.3
10
15
0
mA
Comparator
Voffset
Comparator Offset
-10
VCMin
Input Common Mode Range
0.2
Tcomp
Comparator detection time
TS61001
Final Datasheet
March 19, 2015
Rev 1.2
Input signal of 10mV
www.semtech.com
40
10
mV
1.8
V
80
nS
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Application Schematic
Figure 1: TS61001 Application Schematic
TS61001
Final Datasheet
March 19, 2015
Rev 1.2
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Package Dimensions
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Final Datasheet
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Ordering Information
Part Number
Description
TS61001-QFNR
Full-bridge FET Driver
RoHS and Reach Compliance
Triune Systems is fully committed to environmental quality.
All Triune Systems materials and suppliers are fully compliant
with RoHS (European Union Directive 2011/65/EU), REACH
SVHC Chemical Restrictions (EC 1907/2006), IPC-1752 Level
3 materials declarations, and their subsequent amendments.
Triune Systems maintains certified laboratory reports for
all product materials, from all suppliers, which show full
compliance to restrictions on the following:
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Cadmium (Cd)
Chlorofluorocarbons (CFCs)
Chlorinate Hydrocarbons (CHCs)
Halons (Halogen free)
Hexavalent Chromium (CrVI)
Hydrobromofluorocarbons (HBFCs)
Hydrochlorofluorocarbons (HCFCs)
Lead (Pb)
Mercury (Hg)
Perfluorocarbons (PFCs)
Polybrominated biphenyls (PBB)
Polybrominated Diphenyl Ethers (PBDEs)
TS61001
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Rev 1.2
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IMPORTANT NOTICE
Information relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a
guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein. Semtech reserves the right
to make changes to the product or this document at any time without notice. Buyers should obtain the latest relevant information before placing orders
and should verify that such information is current and complete. Semtech warrants performance of its products to the specifications applicable at the time
of sale, and all sales are made in accordance with Semtech’s standard terms and conditions of sale.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS, OR IN NUCLEAR APPLICATIONS IN WHICH THE FAILURE COULD BE REASONABLY EXPECTED TO RESULT IN PERSONAL INJURY, LOSS OF LIFE
OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN
SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall
indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney
fees which could arise.
The Semtech name and logo are registered trademarks of the Semtech Corporation. Triune Systems, L.L.C. is now a wholly-owned subsidiary of Semtech
Corporation. The Triune Systems® name and logo, MPPT-lite™, and nanoSmart® are trademarks of Triune Systems, LLC. in the U.S.A. All other trademarks
and trade names mentioned may be marks and names of Semtech or their respective companies. Semtech reserves the right to make changes to, or
discontinue any products described in this document without further notice. Semtech makes no warranty, representation or guarantee, express or
implied, regarding the suitability of its products for any particular purpose. All rights reserved.
© Semtech 2015
Contact Information
Semtech Corporation
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111, Fax: (805) 498-3804
www.semtech.com
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Final Datasheet
March 19, 2015
Rev 1.2
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