NX2715 SINGLE CHANNEL MOBILE PWM CONTROLLER WITH NMOS LDO CONTROLLER, PGOOD INDICATOR AND ENABLE ADVANCE DATA SHEET Pb Free Product DESCRIPTION The NX2715 controller IC is a compact synchronous Buck controller IC with 16 lead MLPQ package designed for step down DC to DC converter applications with feedforward functionality. Voltage feedforward provides fast response, good line regulation and nearly constant power stage gain under wide voltage input range. The NX2715 controller is optimized to convert single supply up to 24V bus voltage to as low as 0.8V output voltage. Internal UVLO keeps the controller off until the bus supply voltage exceeds 7V where internal digital soft starts get initiated to ramp up output. The NX2715 employs NMOS LDO controller, programmable current limiting and FB UVLO followed by latchout feature. Other features include: 5V gate drive, programmable frequency, over voltage protection, adaptive deadband control and Vcc under voltage lockout. FEATURES n n n Bus voltage operation from 7V to 24V Less than 1uA shutdown current with Enable low Excellent dynamic response with input voltage feed-forward and voltage mode control Programmable switching frequency Internal digital soft start function Programmable current limit triggers latch out FB UVLO followed by latch out feature NMOS LDO controller available Power Good indicator available Start into precharged output Pb-free and RoHS compliant n n n n n n n n APPLICATIONS n n n Notebook PC Graphic Card on board converters On board DC to DC such as 12V to 3.3V, 2.5V or 1.8V Set Top Box and LCD Display n TYPICAL APPLICATION VIN1 +7V to 20V MBR0530T1 33uF(25V POSCAP) 1uF 8 VIN BST 16 0.1uF HDRV 1 Q1 1.5uH VIN3 +5V 13 SW 15 PVCC OCP 10 10 14 VCC 1uF 9 NX2715 1uF 3.9nF LDRV 3 PGND 2 FB COMP VOUT1 +1.25V@10A 6k 2*2R5TPE330MC Q2 6.98k 1k 11 12 2.49k 18nF 12.4k 1nF EN 4 RT 100k 5 PGOOD (PAD) AGND LDO OUT 6 MTD3055 2.7nF 2.7k LDO FB 7 4.22k VOUT2 +1V@2A 1k 22uF ceramic Figure1 - Typical application of NX2715 ORDERING INFORMATION Device NX2715CMTR Rev. 1.4 01/08/08 Temperature 0 to 70o C Package MLPQ -16L Frequency 200kHz to 1MHz Pb-Free Yes 1 NX2715 ABSOLUTE MAXIMUM RATINGS VCC to GND & BST to SW voltage ...................... -0.3V to 6.5V VIN to GND ........................................................ -0.3V to 25V BST to GND Voltage ......................................... -0.3V to 35V SW to GND ....................................................... -2V to 35V All other pins ..................................................... -0.3V to 6.5V Storage Temperature Range ................................ -65oC to 150oC Operating Junction Temperature Range ................ -40oC to 125oC ESD Susceptibility ............................................ 2kV CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. PACKAGE INFORMATION BST SW VCC PVCC 16-LEAD PLASTIC MLPQ 16 15 14 13 HDRV 1 12 COMP PGND 2 11 FB 17 AGND LDRV 3 10 OCP 9 EN 5 6 7 8 LDO-OUT LDO-FB VIN 4 PGOOD RT θ JA ≈ 46o C/W ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc =5V, VIN=15V and TA = 0 to 70oC. Typical values refer to TA = 25oC. PARAMETER Reference Voltage Ref Voltage Ref Voltage line regulation Supply Voltage(Vcc) VCC Voltage Range Operating quiescent current Shut down current Vcc UVLO VCC-Threshold VCC-Hysteresis Rev. 1.4 01/08/08 SYM Test Condition Min VREF VCC IQ ISD TYP MAX 0.8 0.2 4.75 EN=HIGH EN=LOW VCC_UVLO VCC Rising VCC_Hyst VCC Falling 3 4.4 0.2 Units V % 5.25 5 1 V mA uA V V 2 NX2715 PARAMETER Supply Voltage(Vin) Vin Voltage Range Input Voltage Current Shut Down Current Vin UVLO Vin-Threshold Vin-Hysteresis Oscillator (Rt) Frequency Frequency Over Vin Ramp-Amplitude Voltage Ramp Offset Ramp/Vin Gain Max Duty Cycle Min on time Error Amplifiers Transconductance Input Bias Current Comp SD threshold Vref and Soft Start Soft Start time High Side Driver(CL=3300pF) Output Impedance , Sourcing Current Output Impedance , Sinking Current Rise Time Fall Time N Deadband Time Low Side Driver (CL=3300pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current Rise Time Fall Time Deadband Time OCP Adjust OCP current setting Enable Enable HI Threshold Enable LOW Threshold Rev. 1.4 01/08/08 SYM Test Condition TYP MAX Units Vin=24V EN=LOW 24 25 40 1 V uA uA Vin_UVLO Vin_Hyst Vin Rising Vin Falling 6 0.5 V V FS RT=open 200 VRAMP Vin=20V KHz % V V V/V % nS Vin Min 7 -5 5 2 0.8 0.1 88 150 2500 0.3 umho nA V 10 mS Ib Tss 100 RT=open Rsource(Hdrv) I=200mA 1 ohm Rsink(Hdrv) I=200mA 0.8 ohm THdrv(Rise) 10% to 90% THdrv(Fall) 90% to 10% Tdead(L to Ldrv going Low to Hdrv going H) High, 10% to 10% 50 50 30 ns ns ns Rsource(Ldrv) I=200mA 1 ohm Rsink(Ldrv) I=200mA 0.5 ohm 50 50 30 ns ns ns 32 uA TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv going L) High, 10% to 10% 1.4 0.4 V V 3 NX2715 PARAMETER Power Good(Pgood) Threshold Voltage as % of Vref Hysteresis FBUVLO Feedback UVLO threshold Over temperature Threshold Hysteresis LDO Controller FB Pin- Bias Current LDO FB Voltage LDO FB UVLO High Output Voltage Low Output Voltage High Output Source Current Over Voltage Protection Threshold Voltage as % of Vref Hysteresis Rev. 1.4 01/08/08 SYM Test Condition Min FB ramping up percent of nominal 65 TYP MAX 90 % 5 % 70 75 o 100 FB ramping up 65 0.8 70 10.2 0.2 3 % o 150 20 percent of nominal VIN=12V Units 75 C C nA V % V V mA 130 % 45 % 4 NX2715 PIN DESCRIPTIONS PIN SYMBOL PIN DESCRIPTION VCC This pin supplies the internal 5V bias circuit. . A high freq 1uF ceramic capacitor is placed as close as possible to and connected to this pin and ground pin. BST This pin supplies voltage to high side FET driver. A high freq minimum 0.1uF ceramic capacitor is placed as close as possible to and connected to this pin and SW pin. AGND Analog ground. FB This pin is the error amplifiers inverting input. This pin is connected via resistor divider to the output of the switching regulator to set the output DC voltage. COMP This pin is the output of the error amplifier and together with FB pin is used to compensate the voltage control feedback loop. SW This pin is connected to source of high side FETs and provide return path for the high side driver. HDRV High side gate driver output. LDRV Low side gate driver output. VIN Bus voltage input provides power supply to oscillator and VIN UVLO signal. EN Pull up this pin to Vcc for normal operation. Pulling this pin down below 0.4V shuts down the controller and resets the soft start. LDO FB LDO OUT PGOOD OCP LDO controller feedback input. If the LDOFB pin is pulled below 0.7*Vref, an internal comparator after certain delay and pulls down LDOOUT pin and initiates the HICCUP circuitry. LDO controller output. This pin is controlling the gate of an external NCH MOSFET. The maximum rating of this pin is 16V. An open drain output that requires a pull up resistor to Vcc or a voltage lower than Vcc. When FB pin reaches 90% of the reference voltage PGOOD transitions from LO to HI state. This pin is connected to the drain of the external low side MOSFET and is the input of the over current protection(OCP) comparator. An internal current source is flown to the external resistor which sets the OCP voltage across the Rdson of the low side MOSFET. Current limit point is this voltage divided by the Rds-on. PGND Power ground. PVCC Ldrv supply voltage. A 1uF high frequency cap must be connected from this pin to GND directly. RT Rev. 1.4 01/08/08 Oscillator's frequency can be set by using an external resistor from this pin to GND. When RT pin is open, the frequency is 200kHz. 5 NX2715 BLOCK DIAGRAM PGOOD FB 0.85Vref /0.90Vref 4.4/4.2 Bias 1.25V Generator 0.8V VCC VIN POR EN BST START 6/5.75 COMP START Reset dominant Hiccup DrvH 0.3V DISABLE RT Digital start Up FB 1.30Vref /0.85Vref VIN START SW OVP FET Drivers PWM SS_1/4_done OSC Dis_EA PVCC DRVL SS_half_done S R Vp Vp PGND Q SS_half_done 70%*Vp FB POR latch FB R Latchout logic OCP 0.6V CLAMP 32uA COMP VCC START Dis_EA EN AGND 0.6V 70%*Vp SS_1/4_done EN VpLDO DISABLE Vp LDO OUT LDO FB Figure 2 - Simplified block diagram of the NX2715 Rev. 1.4 01/08/08 6 NX2715 VIN1 +7V to 20V MBR0530T1 33uF(25V POSCAP) 1uF 8 VIN BST 16 0.1uF HDRV 1 VIN3 +5V 13 SW 15 PVCC OCP 10 1uF 14 NX2715 10 VCC 1uF 9 Q1 FDS8878 1.5uH 3.9nF LDRV 3 PGND 2 11 FB 12 COMP VOUT1 +1.25V@10A 6k 2*2R5TPE330MC Q2 FDS6676AS 6.98k 1k 2.49k 18nF 12.4k 1nF EN 4 RT 100k 5 PGOOD (PAD) AGND LDO OUT 6 LDO FB 7 MTD3055 2.7nF 2.7k 4.22k VOUT2 +1V@2A 1k 22uF ceramic Figure 3 - Simplified Demo board schematic Rev. 1.4 01/08/08 7 NX2715 5V 1 5V VIN 1 VIN 1 GNDIN L1 VDD BST 5 6 M1 R5 1 4 0 M3B open PGOOD JVOUT 1 C2 0.1u 100k SW 1 2 3 5 C12 open 5 4 3 2 HDRV R14 C9 25TQC33M 4 16 C11 1u 5V C7 0.1u 3 VIN D1 MBR0530T1 PVCC VIN VCC U1 8 C8 0.1u C5 1u F D S 8878 10 8 7 6 5 9 1u SHORT 13 R1 14 C1 C15 0.1u SW L2 EN 100k OUT R16 open C20 10u (cer) R17 M4 MTD3055 OCSET C13 C19 open M2 R6 3 4 0 LDO_OUT 7 8 C10 470p M3A open 7 LDO_FB 1k FB C18 22u (cer) GNDLDO R7 10 R10 6.98k R9 1k R4 2.7k R13 1 2 1 1V 0.1u LDO_OUT C16 3.9n 2 PGND R8 1k 2R5TPE330MC 2R5TPE330MC 1 2 3 C6 2.7n 2 3 4 5 C17 C14 GNDOUT 0 JLDO_OUT 1 VOUT 6k LDRV 6 10 DO5010P-152HC FDS6676AS VIN OUT R2 8 7 6 5 9 9 NX2715 SW R15 1.25V 15 11 R12 4.22k C4 18n 1 C3 1n R19 open RT COMP 12 PAD 4 open R3 2.49 17 R18 5V R11 12.4k Figure 4 - Demo board schematic based on ORCAD Rev. 1.4 01/08/08 8 NX2715 Bill of Materials Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Rev. 1.4 01/08/08 Quantity 3 5 1 1 1 1 1 2 1 1 1 1 1 1 1 1 2 1 1 1 3 3 1 1 1 2 1 Reference C1,C5,C11 C2,C7,C8,C15,C17 C3 C4 C6 C9 C10 C13,C14 C16 C18 C20 D1 L2 M1 M2 M4 R1,R7 R2 R3 R4 R5,R6,R17 R8,R9,R13 R10 R11 R12 R14,R15 U1 Part 1u 0.1u 1n 18n 2.7n 25TQC33M 470p 2R5TPE330MC 3.9n 22u 10u MBR0530T1 DO5010P-152HC FDS8878 FDS6676AS MTD3055 10 6k 2.49 2.7k 0 1k 6.98k 12.4k 4.22k 100k NX2715 9 NX2715 Demoboard waveforms Fig.5 Startup Fig.7 Voltage Ripple of 1.25V output Fig. 9 Dynamic response of 1.25V output Rev. 1.4 01/08/08 Fig.6 Startup with preload Fig.8 Output short into latch out Fig. 10 Dynamic response of LDO output 10 NX2715 APPLICATION INFORMATION IRIPPLE = Symbol Used In Application Information: VIN = - Input voltage VOUT - Output voltage IOUT - Output current VIN -VOUT VOUT 1 × × LOUT VIN FS ...(2) 20V-1.25V 1.25V 1 × × = 3.9A 1.5uH 20V 200kHz Output Capacitor Selection DVRIPPLE - Output voltage ripple Output capacitor is basically decided by the FS - Switching frequency amount of the output voltage ripple allowed during DIRIPPLE - Inductor current ripple steady state(DC) load condition as well as specification for the load transient. The optimum design may require a couple of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load Design Example Power stage design requirements: VIN=7-20V condition is determined by equation(3). VOUT=1.25V IOUT =10A ∆VRIPPLE = ESR × ∆IRIPPLE + DVRIPPLE <=25mV DVTRAN<=60mV @ 5A step ∆IRIPPLE 8 × FS × COUT ...(3) Where ESR is the output capacitors' equivalent FS=200kHz series resistance,COUT is the value of output capacitors. Typically when large value capacitors are selected Output Inductor Selection The selection of inductor value is based on in- such as Aluminum Electrolytic,POSCAP and OSCON ductor ripple current, power rating, working frequency types are used, the amount of the output voltage ripple and efficiency. Larger inductor value normally means is dominated by the first term in equation(3) and the smaller ripple current. However if the inductance is second term can be neglected. chosen too large, it brings slow response and lower For this example, POSCAP are chosen as output efficiency. Usually the ripple current ranges from 20% capacitors, the ESR and inductor current typically de- to 40% of the output current. This is a design freedom termines the output voltage ripple. which can be decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations: V -V V 1 L OUT = IN OUT × OUT × IRIPPLE VIN FS IRIPPLE =k × IOUTPUT ESR desire = ∆VRIPPLE 25mV = = 6.4m Ω ∆IRIPPLE 3.9A If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capaci- ...(1) tor. For example, for 25mV output ripple, POSCAP 2R5TPE330MCC2 with 12mΩ are chosen. E S R E × ∆ IR I P P L E ∆ VR IPPLE where k is between 0.2 to 0.4. Select k=0.3, then N = 20V-1.25V 1.25V 1 × × 0.4 ×10A 20V 200kHz LOUT =1.5uH Number of Capacitor is calculated as LOUT = Choose LOUT=1.5uH, then coilcraft inductor DO5010P-152HC is a good choice. Current Ripple is calculated as Rev. 1.4 01/08/08 ...(4) N= ...(5) 12mΩ × 3.9A 25mV N =1.9 The number of capacitor has to be round up to a integer. Choose N =2. 11 NX2715 If ceramic capacitors are chosen as output ca- output inductor is smaller than the critical inductance, pacitors, both terms in equation (3) need to be evalu- the voltage droop or overshoot is only dependent on ated to determine the overall ripple. Usually when this the ESR of output capacitor. type of capacitors are selected, the amount of capaci- pacitor such as electrolytic capacitor, the product of tance per single unit is not sufficient to meet the tran- ESR and capacitance is high and L ≤ L crit is true. In sient specification, which results in parallel configura- that case, the transient spec is mostly like to depen- tion of multiple capacitors. capacitor output ripple is : dent on the ESR of capacitor. The amount of ceramic ∆VRIPPLE = ESR × ∆IRIPPLE ∆IRIPPLE + 8 × 200kHz × COUT Using the above equations, although DC ripple spec can be met, however it needs to be studied for transient requirement. For low frequency ca- Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calculated by the following N= ESR E × ∆Istep ∆Vtran + VOUT × τ2 2 × L × C E × ∆Vtran ...(9) where Based On Transient Requirement Typically, the output voltage droop during transient is specified as ∆V droop < ∆V tran @step load DISTEP During the transient, the voltage droop during the transient is composed of two sections. One section is dependent on the ESR of capacitor, the other section is a function of the inductor, output capacitance as well 0 if L ≤ L crit τ = L × ∆Istep − ESR E × CE V OUT If the POSCAP Lcrit = where τ is the a function of capacitor,etc. 0 if L ≤ L crit τ = L × ∆Istep − ESR × COUT V OUT if L ≥ L crit ...(7) where L crit = ESR × COUT × VOUT ESR E × C E × VOUT = ...(8) ∆Istep ∆I step where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used in parallel. The above equation shows that if the selected Rev. 1.4 01/08/08 ESR E × CE × VOUT = ∆Istep 12mΩ× 330µF ×1.25V = 0.99µH 5A width of system is high enough, the overshoot can ...(6) 2R5TPE330MCC2(330uF, 12mohm ESR) is used, the crticial inductance is given as with a DISTEP transient load, if assuming the band- ∆Vovershoot ...(10) sient is 60mV for 5A load step. overshoot when load from high load to light load VOUT = ESR × ∆Istep + × τ2 2 × L × COUT L ≥ L crit For example, assume voltage droop during tran- as input, output voltage. For example, for the be estimated as the following equation. if The selected inductor is 1.5uH which is bigger than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance. number of capacitors is τ= = L × ∆Istep VOUT − ESR E × C E 1.5µH × 5A − 12mΩ × 330µF = 2.04us 1.25V N= ESR E × ∆Istep ∆Vtran + VOUT × τ2 2 × L × CE × ∆Vtran 12mΩ × 5A + 60mV 1.25V × 2.04us2 2 ×1.5µH × 330µF × 60mV = 1.74 = 12 NX2715 The number of capacitors has to satisfy both ripple and transient requirement. Overall, we choose N=2. It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters. Compensator Design Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response, compensator is employed to provide highest possible bandwidth and enough phase margin. Ideally, the Bode plot of the closed loop system has crossover frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain crossing 0dB with -20dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should be chosen. Voltage feedforward is used in NX2715 to compensate the output voltage variation caused by input voltage changing. The feedforward funtion is realized by using VIN pin voltage to program the oscillator ramp voltage VOSC at about 1/10 of VIN voltage, which provides nearly constant power stage gain under wide voltage input range. pensate the system with type III compensator. The following figures and equations show how to realize the type III compensator by transconductance amplifier. FZ1 = 1 2 × π × R 4 × C2 ...(11) FZ2 = 1 2 × π × (R 2 + R3 ) × C3 ...(12) FP1 = 1 2 × π × R3 × C3 ...(13) FP2 = 1 ...(14) C × C2 2 × π × R4 × 1 C1 + C2 where FZ1,FZ2,FP1 and FP2 are poles and zeros in the compensator. The transfer function of type III compensator for transconductance amplifier is given by: Ve 1 − gm × Z f = VOUT 1 + gm × Zin + Z in / R1 For the voltage amplifier, the transfer function of compensator is Ve −Z f = VOUT Zin To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R4>>2/gm. And it would be desirable if R1||R2||R3>>1/gm can be met at the same time. Zin Zf C1 Vout R3 R2 C3 C2 R4 Fb gm Ve R1 Vref A. Type III compensator design For low ESR output capacitors, typically such as Sanyo oscap and poscap, the frequency of ESR zero caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to comRev. 1.4 01/08/08 Figure 11 - Type III compensator using transconductance amplifier 13 NX2715 Case 1: FLC<FO<FESR(for most ceramic or low ESR POSCAP, OSCON) 2. Set R4 equal to 2.5kΩ. 3. Calculate C2 with zero Fz1 at 75% of the LC Gain(db) double pole by equation (11). 1 2 × π × FZ1 × R 4 C2 = power stage FLC 1 2 × π × 0.75 × 5.06kHz × 2.5k Ω = 17nF = 40dB/decade Choose C2=18nF. 4. Calculate C1 by equation (14) with pole Fp2 at loop gain FESR 20dB/decade one third of the switching frequency. 1 2 × π × R 4 × FP2 C1 = 1 2 × π × 2.5k Ω × 66.7kHz = 959pF = compensator Choose C1=1nF. FZ1 FZ2 FO FP1 FP2 5. Calculate C3 with the crossover frequency FO at 15kHz. Figure 12 - Bode plot of Type III compensator (FLC<FO<FESR) C3 = VOSC 2 × π × FO × L × COUT × VIN R4 1 2 × π × 15kHz × 1.5uH × 660uF × 10 2.5kΩ =3.7nF = Typical design example of type III compensator in which the crossover frequency is selected as FLC<FO<FESR and FO<=1/10~1/5Fs is shown as the following steps. In this example, output voltage is 1.25V, output inductor is 1.5uH, output capacitors are two POSCAP 2R5TPE330MCC2 (330uF, 12mohm ESR) 1. Calculate the location of LC double pole FLC and ESR zero FESR. FLC = = 1 2 × π × L OUT × COUT 1 2 × π × 1.5uH × 660uF = 5.06kHz FESR = 1 2 × π × ESR × C OUT 1 2 × π × 6m Ω × 660uF = 40kHz = Rev. 1.4 01/08/08 Choose C3=3.9nF. 6. Calculate R3 by equation (13) with Fp1 =FESR. R3 = 1 2 × π × FP1 × C3 1 2 × π × 40kHz × 3.9nF = 1kΩ = Choose R3 =1kΩ. 7. Calculate R2 by setting compensator zero FZ2 at the LC double pole. R2 = 1 1 1 ×( − ) 2 × π × C3 FZ2 FP1 1 1 1 ×( − ) 2 × π × 3.9nF 5.06kHz 40kHz = 7.05k Ω = Choose R2 =6.98kΩ. 14 NX2715 8. Calculate R1 . R × VREF 6.98kΩ × 0.8V R1 = 2 = = 12.41kΩ VOUT -VREF 1.25V-0.8V FESR = 1 2 × π × 9m Ω × 2000uF = 8.8kHz = Choose R1=12.4kΩ. Case 2: FLC<FESR<FO(for electrolytic capacitors) 1 2 × π × ESR × COUT 2. Set R4 equal to 2.5kΩ. 3. Calculate C2 with zero Fz1 at 75% of the LC Gain(db) double pole by equation (11). power stage C2 = FLC 40dB/decade FESR 1 2 × π × FZ1 × R 4 1 2 × π × 0.75 × 2.4kHz × 2.5k Ω = 35nF = Choose C2=33nF. loop gain 4. Calculate C1 by equation (14) with pole Fp2 at one third of the switching frequency. 20dB/decade C1 ≈ compensator 1 2 × π × R 4 × FP2 1 2 × π × 2.5k Ω × 66.7kHz ≈ 959pF ≈ FZ1 FZ2 FP1 FO FP2 Choose C1=1nF. 5. Calculate R3 with the crossover frequency FO at 15kHz. Figure 13 - Bode plot of Type III compensator (FLC<FESR<FO) If electrolytic capacitors are used as output capacitors, typical design example of type III compensator in which the crossover frequency is selected as FLC<FESR<FO and FO<1/10Fs is shown as the following steps. Here two SANYO MV-WF1000 with 18 mΩ is chosen as output capacitor, output inductor is 2.2uH, output voltage is 1.05V, switching frequency is 200kHz. 1. Calculate the location of LC double pole FLC and ESR zero FESR. FLC = = 1 2 × π × LOUT × COUT 1 2 × π × 2.2uH × 2000uF = 2.4kHz Rev. 1.4 01/08/08 R3 = VIN ESR × R 4 × VOSC 2 × π × FO × L 9mohm × 2.5kΩ 2 × π × 15kHz × 1uH =1.08kΩ =10 × Choose R3=1.2kΩ. 6. Calculate C3 by equation (13) with Fp1 =FESR. C3 = 1 2 × π × FP1 × R3 1 2 × π × 8.8kHz × 1.2k Ω = 14nF = Choose C3 =15nF. 7. Calculate R2 by setting compensator zero FZ2 at the LC double pole. 15 NX2715 R2 = 1 1 1 ×( − ) 2 × π × C3 FZ2 FP1 1 1 1 ×( − ) 2 × π × 15nF 2.4kHz 8.8kHz = 3.2k Ω = pole zero location and constant gain. Gain=gm × Fz = Choose R2 =4kΩ. 8. Calculate R1 The following equations show the compensator . R × VREF 4k Ω × 0.8V R1 = 2 = = 12.8k Ω VOUT -VREF 1.05V-0.8V Choose R1=12.7kΩ. R1 × R3 R1 +R 2 1 2 × π × R3 × C1 1 2 × π × R 3 × C2 Fp ≈ ...(15) ... (16) ... (17) Vout B. Type II compensator design If the electrolytic capacitors are chosen as R2 Fb power stage output capacitors, usually the Type II compensator can be used to compensate the sys- gm R1 tem. Ve R3 Vref C2 For this type of compensator, FO has to satisfy C1 FLC<FESR<<FO<1/10Fs. Gain(db) power stage Figure 15 - Type II compensator with transconductance amplifier 40dB/decade The following is parameters for type II compen- loop gain sator design. Input voltage is 12V, output voltage is 2.5V, output inductor is 2.2uH, output capacitors are 20dB/decade two 680uF with 41mΩ electrolytic capacitors. 1.Calculate the location of LC double pole FLC and ESR zero FESR. compensator Gain FLC = 1 2 × π × L OUT × COUT 1 = FZ FLC FESR FO FP Figure 14 - Bode plot of Type II compensator Type II compensator can also be realized by simple RC circuit without feedback as shown in figure 2 × π × 2.2uH × 1360uF = 2.9kHz FESR = 1 2 × π × ESR × COUT 1 2 × π × 20.5m Ω × 1360uF = 5.7kHz = 15. R3 and C1 introduce a zero to cancel the double pole effect. C2 introduces a pole to suppress the switching noise. Rev. 1.4 01/08/08 16 NX2715 1.Set R2 equal to10kΩ. Using equation 18, the final selection of R1 is 4.7kΩ. 2. Set crossover frequency at 1/20 of the swithing frequency, here FO=10kHz. Vout R2 Fb 3.Calculate R3 value by the following equation. V 2 × π × FO × L 1 VOUT × × R3 = OSC × Vin RESR gm VREF 1 2 × π × 10kHz × 2.2uH 1 × × 10 20.5mΩ 2.5mA/V 2.5V × 0.8V =0.8kΩ = R1 Vref Figure 16 - Voltage divider R 1= R 2 × VR E F V O U T -V R E F ...(18) where R2 is part of the compensator, and the value Choose R3 =1kΩ. of R1 value can be set by voltage divider. 4. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole. Input capacitors are usually a mix of high fre- 1 2 × π × R 3 × Fz C1 = quency ceramic capacitors and bulk capacitors. Ce- 1 2 × π × 1k Ω × 0.75 × 2.9kHz =70nF = 5. Calculate C2 by setting compensator pole Fp at half the swithing frequency. 2 = 1 π × R 3 ramic capacitors bypass the high frequency noise, and bulk capacitors supply switching current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the high frequency noise.The bulk input Choose C1=68nF. C Input Capacitor Selection × Fs 1 = π × 1k Ω × 3 0 0 k H z =530pF capacitors are decided by voltage rating and RMS current rating. The RMS current in the input capacitors can be calculated as: IRMS = IOUT × D × 1- D D= VOUT VINMIN ...(19) VINMIN = 7V, VOUT=1.05V, IOUT=10A, the result of Choose C2=560pF. Output Voltage Calculation Output voltage is set by reference voltage and input RMS current is 3.8A. For higher efficiency, low ESR capacitors are recommended. One Sanyo OSCON CAP 25SVP56M external voltage divider. The reference voltage is fixed 25V 56uF 28mΩ with 3.8A RMS rating are chosen at 0.8V. The divider consists of two ratioed resistors as input bulk capacitors. so that the output voltage applied at the Fb pin is 0.8V when the output voltage is at the desired value. The following equation applies to figure 16, which shows the relationship between VOUT , VREF and voltage di- vider. Rev. 1.4 01/08/08 17 NX2715 Power MOSFETs Selection The NX2715 requires two N-Channel power This power dissipation should not exceed maximum power dissipation of the driver device. MOSFETs. The selection of MOSFETs is based on maximum drain source voltage, gate source voltage, Over Current Limit Protection maximum current rating, MOSFET on resistance and Over current protection is achieved by sensing power dissipation. The main consideration is the power current through the low side MOSFET. An internal cur- loss contribution of MOSFETs to the overall converter efficiency. For example, two IRF7822 are used in application. They have the following parameters: VDS=30V, rent source of 32uA flows through an external resistor ID =18A,RDSON =6.5mΩ,QGATE =44nC. is on, the voltage at node SW is given as connected from OCP pin to SW node sets the over current protection threshold. When synchronous FET VSW =-IL × RDSON There are two factors causing the MOSFET power loss:conduction loss, switching loss. The voltage at pin OCP is given as Conduction loss is simply defined as: IOCP × ROCP +VSW PHCON =IOUT × D × RDS(ON) × K When OCP pin voltage is below zero, the over 2 PLCON =IOUT 2 × (1 − D) × RDS(ON) × K PTOTAL =PHCON + PLCON ...(20) current occurs after three cycles as shown in figure 17, both Hdrv and Ldrv will be shut down. where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature dependency. As a result, RDS(ON) should be selected for the worst case, in which K approximately equals to 1.4 at 125oC according to datasheet. Conduction loss should not exceed package rating or overall system thermal budget. Switching loss is mainly caused by crossover conduction at the switching transition. The total switching loss can be approximated. 1 × VIN × IOUT × TSW × FS ...(21) 2 where IOUT is output current, TSW is the sum of TR and TF which can be found in mosfet datasheet, and FS is switching frequency. Swithing loss PSW is frequency dependent. Also MOSFET gate driver loss should be considered when choosing the proper power MOSFET. MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits.It is proportional to frequency and is defined as: PSW = Pgate = (QHGATE × VHGS + QLGATE × VLGS ) × FS ...(22) where QHGATE is the high side MOSFETs gate charge,Q LGATE is the low side MOSFETs gate vbus I OCP 32uA OCP SW R OCP OCP comparator Figure 17 - Over Current Protection Waveform and Block Diagram charge,VHGS is the high side gate source voltage, and VLGS is the low side gate source voltage. Rev. 1.4 01/08/08 18 NX2715 The over current limit can be set by the following equation: where FO is the desired crossover frequency. Typically, in this LDO compensation, crossover IOCP × ROCP K × RDSON If MOSFET RDSON=6.5mΩ, the worst case thermal consideration K=1.5 and the current limit is set at 15A, then R OCP = ESR. FO is typically around several tens kHz to a few hundred kHz. For this example, we select Fo=100kHz. gm is the forward trans-conductance of MOSFET. LDO input ISET × K × RDSON 15A × 1.5 × 6.5m Ω = = 4.57kΩ IOCP 32uA + ISET = frequency FO has to be higher than zero caused by Vref Choose ROCP=4.64kΩ. For NX2715, if switching channel goes into OCP and latch up, the LDO will be latch up at the same time. Rf1 ESR Rf2 Rc Rload Cc Co LDO Selection Guide NX2715 offers a LDO controller. The selection of MOSFET to meet LDO is more straight forward. Figure 18 - NX2715 LDO controller. The selection is that the Rdson of MOSFET should meet the dropout requirement. For example. VLDOIN =3.3V VLDOOUT =2.5V ILoad =2A The maximum Rdson of MOSFET should be R RDSON = (VLDOIN − VLDOOUT ) × I LOAD = (3.3V − 2.5V) / 2A = 0.4Ω Most of MOSFETs can meet the requirement. More important is that MOSFET has to be selected right package to handle the thermal capability. For LDO, maximum power dissipation is given as PLOSS = (VLDOIN − VLDOOUT ) × I LOAD = (3.3V − 2.5V) × 2A = 1.6W Select IR MOSFET IRFR3706 with 9mΩ RDSON is sufficient. LDO Compensation The diagram of LDO controller including VCC regulator is shown in the following figure. For most low frequency capacitor such as elec- For IRFR3706, gm=53. Select Rf1=5kohm. Output capacitor is Sanyo POSCAP 4TPE150MI with 150uF, ESR=18mohm. CC = 1 53 × 18m Ω × =77pF 4 × π × 100kHz × 5k Ω 1+53 × 18m Ω Choose CC=82pF. For electrolytic or POSCAP, RC is typically selected to be zero. Rf2 is determined by the desired output voltage. R f2 = R f1 × VREF VLDOOUT − VREF 5kΩ × 0.8V 1.6V − 0.8V =5kΩ = Choose Rf2=5kΩ. When ceramic capacitors or some low ESR bulk capacitors are chosen as LDO output capacitors, the zero caused by output capacitor ESR is so high that trolytic, POSCAP, OSCON, etc, the compensation pa- crossover frequency FO has to be chosen much higher rameter can be calculated as follows. than zero caused by RC and CC and much lower than zero caused by ESR . For example, 22uF ceramic is CC = g × ESR 1 × m 4 × π × FO × R f1 1+gm × ESR used as output capacitor. We select Fo=100kHz, Rf1=1kohm and select MOSFET MTD3055(gm=5). R C and CC can be calculated as follows. Rev. 1.4 01/08/08 19 NX2715 RC =R f1 × Layout Considerations 2 × π × FO × CO 0.5 × gm =1kΩ × =5.4kΩ The layout is very important when designing high 2 × π × 100kHz × 22uF 0.5 × 5S frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. There are two sets of components considered in Choose RC=5.4kΩ. the layout which are power components and small sig- 10 × CO CC = RC × gm nal components. Power components usually consist of input capacitors, high-side MOSFET, low-side 10 × 22uF = 2 × π × 5.4kΩ × 5S =1.3nF MOSFET, inductor and output capacitors. A noisy environment is generated by the power components due to the switching power. Small signal components are connected to sensitive pins or nodes. A multilayer lay- Choose CC=1.2nF. out which includes power plane, ground plane and signal plane is recommended . Current Limit for LDO Current limit of LDO is achieved by sensing the LDO feedback voltage. When LDO_FB pin is below 70% of VREF, the IC goes into latch up. The IC will turn off all the channel and latch up. Layout guidelines: 1. First put all the power components in the top layer connected by wide, copper filled areas. The input capacitor, inductor, output capacitor and the MOSFETs should be close to each other as possible. This helps to reduce the EMI radiated by the power loop due to Over Voltage Protection When FB pin the high switching currents through them. exceeds 2. Low ESR capacitor which can handle input 1.04V(130%*VRE F) and be there for three cycles, over voltage RMS ripple current and a high frequency decoupling voltage protection will be triggered. Hdrv turns low ceramic cap which usually is 1uF and Ldrv turns high. Ldrv will be from high to low once need to be practically touching the drain pin of the upper MOSFET, a FB plane connection is a must. voltage falls below 0.68V(85%*V REF ). 3. The output capacitors should be placed as close as to the load as possible and plane connection is required. 4. Drain of the low-side MOSFET and source of the high-side MOSFET need to be connected thru a plane ans as close as possible. A snubber nedds to be placed as close to this junction as possible. 5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not enough. This is very important. The same applies to the output capacitors and input capacitors. 6. Hdrv and Ldrv pins should be as close to MOSFET gate as possible. The gate traces should be wide and short. A place for gate drv resistors is needed to fine tune noise if needed. Figure 19 - OVP trigger threshold. Rev. 1.4 01/08/08 7. Vcc capacitor, BST capacitor or any other by20 NX2715 passing capacitor needs to be placed first around the IC and as close as possible. The capacitor on comp to GND or comp back to FB needs to be place as close to the pin as well as resistor divider. 8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. All GNDs need to go directly thru via to GND plane. 10. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. 11. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. Rev. 1.4 01/08/08 21