Application Notes

AN11401
TEA1720/TEA1705 5 W to 12.5 W power supply/USB charger
Rev. 1 — 5 December 2013
Application note
Document information
Info
Content
Keywords
ultra low standby power, constant output voltage, constant output current,
primary sensing, Integrated emitter switch, low-cost NPN high-voltage
switch, integrated high voltage start-up, USB charger, standby supply,
5 W to 12.5 W supply, transient controller companion
Abstract
The TEA1720 is a primary sensing controller for power supplies up to
12.5 W. A low-cost NPN transistor is used as high-voltage switch.
The no-load power can be as low as 20 mW for a 10 W charger. It
surpasses the Energy Star 5 level (30 mW).
Excellent transient response can be achieved when using the transient
controller TEA1705 on secondary side.
When the maximum output power is exceeded, the IC changes from
constant voltage mode to constant current mode, which is suitable for
battery charging.
AN11401
NXP Semiconductors
TEA1720/TEA1705 5 W to 12.5 W power supply/USB charger
Revision history
Rev
Date
Description
v.1
20131205
first issue
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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1. Introduction
The TEA1720 is a flyback controller with primary sensing and an integrated emitter switch
for driving a low-cost NPN high-voltage switch.
An advanced burst mode and integrated high-voltage start-up circuit ensure a very low
no-load power consumption of 20 mW for a 10 W mobile charger.
Excellent transient response in burst mode can be achieved by using the (optional)
TEA1705 transient controller on secondary side. Using a wake-up pulse that travels
through the flyback transformer, the TEA1705 IC triggers the TEA1720 on the primary
side to recommence switching when the output voltage (Vout) drops to below 4.9 V.
When the maximum output power level is reached, the constant output voltage control
mechanism changes to a constant output current control mechanism, enabling the
TEA1720 to be used as a constant current charger.
Depending on the dimensioning of the mobile charger circuit, the output power range can
typically be 5 W to 12.5 W. Choose the NPN BJT switch accordingly.
The TEA1720 is assembled in an SO8 package. The (optional) TEA1705 comes in a
SOT23 package.
All values mentioned in the application note are typical values. For the
minimum/maximum values and spread figures, see the TEA1720 and TEA1705 data
sheets.
2. Scope
This application note describes application aspects of the TEA1720 SMPS controller IC.
The IC is typically used for low-power adapter or USB mobile charger applications. The
functionality, the control functions and the basic dimensioning of the circuit components of
an application circuit using the TEA1720 controller and optionally a TEA1705 transient
controller are explained.
Detailed transformer calculation is available in a separate calculation sheet.
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3. TEA1720/TEA1705 low-power adapter
The features of the TEA1720 enable power engineers to design a reliable, cost-effective,
and efficient adapter supplies with low no-load power consumption and a low component
count. The optional TEA1705 realizes excellent transient response in burst mode without
requiring an optocoupler or other additional mains isolation crossing components.
3.1 Key features TEA1720
3.1.1 Power features
• Low component count for cost-effective design
• Highly efficient > 80 %
• Primary sensing for control of the output voltage without optocoupler and secondary
feedback circuitry
•
•
•
•
•
•
•
Built-in emitter switch for driving a low-cost NPN high-voltage bipolar transistor
Minimizes audible noise in all operation modes
Energy Star 2.0 compliant
USB 1.1 and 1.2 compliant for mobile phone chargers
Jitter function for reduced EMI
Versions available with built-in cable compensation
Available in SO8 package
3.1.2 Green features
• No-load power consumption < 20 mW
• Very low supply current in no-load condition with energy save mode
• Incorporates a high-voltage start-up circuit with zero current consumption at normal
switching operation
3.1.3 Protection features
•
•
•
•
•
•
OverVoltage Protection (OVP) with auto-restart
UnderVoltage LockOut (UVLO) on the IC supply pin
OverTemperature Protection (OTP)
SENSE pin short circuit protection
Hiccup feature for automatic switch-off at output voltage that is continuously too low
Demagnetization protection for guaranteed Discontinuous Conduction Mode (DCM)
operation
• Open and short-circuit protection of the feedback control pin (FB)
• Short circuit protection of the charger output
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3.2 Key features TEA1705
3.2.1 Power features
• Excellent transient response in burst mode by constant monitoring of the output
voltage (Vout) and waking up the TEA1720 on primary side via the transformer when
Vout drops to below 4.9 V.
• Only two external components required
• No additional mains isolation crossing components required
• Available in SOT23 package
3.2.2 Protection features
• Preventing Vo to exceed 6.3 V in a no-load condition by drawing additional current (up
to 15 mA at 6.3 V) to protect the output capacitors when Vo exceeds 5.9 V when the
preload resistor provides insufficient load.
3.3 Applications
• Mobile communication
– Mobile phone battery charger
– Smart phone battery charger
– Tablet computer battery charger
• Major home appliances
– Washing machines and dryers
– Refrigerators and freezers
– Dish washers
– Induction cookers
– Room air conditioners
• Computing and consumer
– E-readers
– Portable audio/video
– Settop boxes
– PC peripherals
– Standby power supply for PC and TV
• Industrial and residential
– Smart metering
– Lighting
– Home and building automation
– Heating, Ventilation, and Air Conditioning (HVAC)
– Industrial automation and control
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AN11401
Application note
4. Basic application schematic
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Basic application schematic
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Fig 1.
TEA1720/TEA1705 5 W to 12.5 W power supply/USB charger
Rev. 1 — 5 December 2013
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&$3
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NXP Semiconductors
TEA1720/TEA1705 5 W to 12.5 W power supply/USB charger
5. Pinning
5.1 TEA1720
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Fig 2.
TEA1720 pinning diagram (S08)
Table 1.
Pin description
Pin
Pin name
Description
1
HV
input high voltage startup current source; breakdown voltage is 500 V
2
n.c.
not connected; high-voltage spacer pin
3
FB
feedback input; senses the voltage on the aux winding during secondary
stroke (which represents the voltage on the output winding) via a resistive
divider
at constant output voltage the sensed voltage is regulated on 2.5 V
when the sensed voltage drops to below 2.5 V, the regulation changes to
constant current mode
under 1.1 V, the controller enters hiccup mode (short circuit protection)
the OVP protection level is 3.2 V
demagnetization detection (which releases the next stroke and guarantees
discontinuous operation) checks that the voltage on the auxiliary winding
drops to below 50 mV after the secondary stroke
4; 5
GND
ground connection
6
SENSE
connected to the source of the internal MOSFET which is used as emitter
switch; the current through the MOSFET and the serially connected NPN
transistor is monitored using a resistor from the SENSE pin to ground
the peak level in burst mode is approximately 120 mV; the peak level in
other modes ranges from 120 mV and 530 mV (exact values are
depending on the dV/dt on the source pin)
7
VCC
supply voltage
at start-up, an internal current source charges the connected VCC
capacitor until the Vstart level (17 V) is reached
the device starts switching and the auxiliary winding takes over the supply
The UnderVoltage LockOut level (UVLO) on the VCC pin is 8.5 V
8
AN11401
Application note
EMITTER
drain connection of the internal MOSFET used as emitter switch; the
breakdown voltage is 40 V. RDSon is 0.9 
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*1'
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Fig 3.
TEA1705 pinning diagram (S0T23)
Table 2.
Pin description
Pin
Pin name
Description
1
VCC
supply voltage and level monitoring of Vout
when VCC drops to below 4.9 V and no switching occurs, a pulse is
generated to wake-up the TEA1720 on primary side
to protect polymer electrolytic capacitors with 6.3 V rating when no preload
resistor is connected or the preload resistor provides insufficient load, the
supply current increases linearly to 15 mA at 6.3 V when VCC exceeds
5.9 V
2
CAP
connection communication capacitor
the communication capacitor is discharged when VCC drops to below 4.9 V
while no switching occurs
during switching, the communication capacitor is (re)charged via this pin
3
AN11401
Application note
GND
ground connection
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6. System description
This section describes the system. Use Figure 1 as reference throughout this section.
6.1 Supply
At start-up, an internal current source, connected to the HV pin, charges the capacitor
connected to the VCC pin (see Figure 4).
When the voltage level on the VCC pin reaches 17 V (VCC(startup)), the internal current
source is switched off. The IC starts switching. The internal MOSFET drives the external
NPN via emitter switching. Both the IC supply current and the base current for the NPN
are delivered by the charge stored in the capacitor connected to the VCC pin.
When switching starts, the voltage generated at the auxiliary supply winding of the
transformer provides the supply (see Figure 5 and Figure 6).
When the IC does not start switching (due to protection) or when the auxiliary winding
does not take over the supply voltage, the voltage on the capacitor on the VCC pin drops
to 8.5 V (VCC(stop)). The internal current source is enabled again. It charges the capacitor
to 17 V (VCC(start)). This sequence is repeated (see Figure 6).
It is also possible to supply the IC externally. But the supply voltage must exceed 17 V
(VCC(startup)) with some margin to guarantee a start-up.
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Fig 4.
Charging the VCC capacitor
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Fig 5.
Rectified voltage of auxiliary winding takes over the VCC supply
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(1) HV current source on
(2) HV current source off
(3) Switching start; Vaux builds up
(4) Vaux takes over VCC supply
Fig 6.
AN11401
Application note
Voltage on the VCC pin
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6.2 Operating modes
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Basic circuit with relevant parameters
From no-load to maximum load and in Constant Current (CC) mode, the TEA172x uses
different operating modes, which are explained below.
A simplified model is used to explain the different modes (see Figure 14). The assumption
is that the current ISENSE in the sense resistor RSENSE equals the collector current (Ic) of
the NPN. In reality, ISENSE deviates from Ic because of the additional base current flowing
through resistor RSENSE. Moreover, the peak value of Ic exceeds ISENSE due to delayed
switch-off of the NPN transistor (caused by storage time).
For all these items compensations are built in the TEA1720. Details of the emitter drive
are explained in Section 6.3.
The regulation of a flyback converter is based on regulating the transferred energy
according to Equation 1:
2
P out = 0.5  L p  I pk  f sw  
(1)
Where:
• Pout = output power
• Lp = transformer primary inductance
• Ipk = peak value of the primary current at NPN switch-off time
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• fsw = switching frequency
•  = converter efficiency
The output power equals the energy, stored per stroke in the transformer (0.5  Lp  Ipk2)
times the number of strokes per second (fsw) minus the losses (efficiency ).
Though not completely accurate, this basic formula is sufficient to understand the control
modes.
The different operating modes are:
•
•
•
•
Burst mode
CVC mode: Constant Voltage peak Current regulation control
CVF mode: Constant Voltage Frequency regulation control
CCF mode: Constant Current Frequency regulation control
6.2.1 Burst mode
At fixed time intervals, the burst period is started. Each burst period starts with one stroke
at a fixed Ipk level. After the stroke the voltage is sensed at the FB pin near the end of the
secondary stroke. If the sensed voltage equals or exceeds 2.5 V, no additional strokes are
made. The IC enters energy save mode until the next burst period. If the sensed voltage
at the FB pin is < 2.5 V, additional strokes are made until the sensed voltage level at the
FB pin exceeds 2.5 V. Then the IC enters energy save mode until the next burst period.
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(1) Start of burst
(2) End of burst
(3) Minimum supply current for energy save; Only the oscillator is active
(4) Vout(pk) reaches control value in 1 or 2 cycles
(5) IC switches to minimum supply current, energy save
(6) IC switches to nominal supply just before new burst start
Timing and currents given are for TEA1720 version with fburst = 400 Hz
Fig 8.
AN11401
Application note
Burst mode with energy save mode
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The low no-load power is achieved by:
• Low burst period repetition rate (400 Hz)
• The IC enters energy save mode between burst periods, reducing current
consumption by a factor of 4.5
Audible noise is limited by:
• Selecting the minimal Ipk (Ipk(min)) for burst mode
• Repetition rate of strokes within the burst period is 22.5 kHz; well above the audible
limit
The no-load power is < 20 mW for a 10 W charger. At lower output power, lower no-load
power can be achieved.
The fixed time interval between burst periods determines the no-load power but also the
size of the required output capacitors. For more information about the size of the output
capacitor related to output power, ripple and load step performance (see Section 6.5).
When the output load increases, more strokes per burst period are added to transfer
enough energy.
Finally, the whole burst period is filled with strokes and the IC is switching continuously.
When the load increases further, the IC enters the CVC (Constant Voltage peak Current
control) mode.
To reduce the ripple in burst mode, slope compensation is added when the number of
strokes exceeds 50 % of the burst period.
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Fig 9.
AN11401
Application note
Slope compensation
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For duty cycles > 50 %, the reference level of Vout is linearly decreased. This ensures that
the regulation converges and the duty cycle remains constant. Figure 10 shows a
graphical explanation.
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Fig 10. Slope compensation regulation
In all graphs the black line represents the output voltage when the regulation is stable.
The red line represents the output voltage when there is a disturbance and the loop has to
regulate back to the stable state.
In burst mode, strokes are made and Vout increases until the reference level of Vout is
reached. Switching stops and the load discharges the output capacitor until the next burst
period starts.
When  < 50 % (Figure 10 top graph), the regulation converges to the stable state after a
disturbance.
When  > 50 % and no slope compensation is present (Figure 10 middle graph), the loop
does not converge and the  varies between minimum and maximum (1 stroke/burst and
31 strokes/burst). The long idle time after a burst period with 1 stroke causes increased
ripple at higher loads due to the longer discharge time of the output capacitor.
When  > 50 % and slope compensation is present (Figure 10 bottom graph), the
reference level for Vout drops linearly for 50 % <  < 100 %.The regulation converges and
the ripple of Vout remains minimal.
Pout in burst mode can be calculated with Equation 2:
P out = 0.5  L p  I pk  min   f burst  average_no_of_strokes_per_burst  
(2)
Where:
• fburst = fixed burst frequency, which determines the fixed time interval between bursts
• Ipk(min) = fixed minimum Ipk level in burst mode
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Measuring the voltage over the resistor from the SENSE pin to ground determines the
level of Ipk. The peak level voltage is around 120 mV in the application.
6.2.2 CVC mode
The CVC mode (Constant Voltage peak Current regulation mode) starts where the burst
mode ends. The IC is continuously switching at the repetition rate of strokes within the
burst period (= 22.5 kHz = fmin, the minimum switching frequency in continuous mode).
the peak current equals Ipk(min).
When more output power is required, the switching frequency is kept constant on fmin
(22.5 kHz). The Ipk level is increased to deliver the required power.
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Fig 11. CVC mode with Ipk control
Remark: The on-time (ton) increases with the amplitude of Ipk. This is not shown in
simplified graphics like Figure 11.
In this mode, the peak voltage level on the SENSE pin increases from 120 mV to 530 mV.
Pout in the CVC mode is described with Equation 3:
2
P out = 0.5  L p  I pk  f min  
(3)
Where:
• Ipk = Varying from Ipk(min) to Ipk(max) (determined by Vpk on the SENSE pin)
• fmin = Minimum switching frequency in continuous mode (22.5 kHz)
When Ipk(max) is reached, the IC enters the CVF mode.
6.2.3 CVF mode
The CVF mode (Constant Voltage Frequency regulation mode) takes over seamlessly
where the CVC mode ends.
In this mode, the Ipk is kept constant on Ipk(max). The frequency is increased to deliver the
additional required power.
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Fig 12. CVF mode with frequency regulation
The switching frequency is increased in this mode from fmin (22.5 kHz) to fmax (52 kHz).
The output power can be calculated with Equation 4:
2
P out = 0.5  L p  I pk  max   f sw  
(4)
Where:
• Ipk(max) = Fixed maximum Ipk (Vpk = 530 mV on the SOURCE pin)
• fsw = Switching frequency varies from fmin (22.5 kHz) to fmax (52 kHz)
The maximum output power is calculated using Equation 5:
2
P out  max  = 0.5  L p  I pk  max   f max  
(5)
This formula is useful for dimensioning the circuit. It is used in chapter 6.3 Transformer to
calculate a practical circuit.
When the maximum power is exceeded, the IC switches to Constant Power mode.
6.2.4 Constant Power (CP) mode
The CP mode is the short transition between Constant Voltage mode and Constant
Current mode.
In Constant Power mode the IC runs on maximum power (Equation 6).
2
P out  max  = 0.5  L p  I pk  max   f max  
(6)
The transition area is kept as small as possible.
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6.2.5 CCF mode
To enter Constant Current mode, initially the maximum output power must be exceeded.
This forces the IC to enter Constant Power mode. After that, the IC enters the CCF mode
(Constant Current Frequency regulated mode).
When the load further increases, Iout is kept constant on Iout(max), while Vout becomes the
voltage, present over the load at Iout(max).
It is the easiest to imagine the load as a resistive load. Increasing the load means
decreasing the load resistance. A linear decreasing load resistance leads to a linear
decrease of Vout over the load resistance at constant current Iout(max).
To regulate to a fixed value Iout(max), Ipk is kept constant and fsw is reduced in CCF mode.
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Fig 13. CCF mode regulation by frequency
The output power formula is the same as for CVF mode:
2
P out = 0.5  L p  I pk  max   f sw  
(7)
However, now fsw is used to keep Iout constant, while Vout becomes the voltage over the
load at Iout(max).
The switching frequency (fsw) drops from fmax (52 kHz) to fmin (22.5 kHz).
Remark: The transition from CVF mode to CP mode to CCF mode is seamless.
When the output voltage drops to below the Vout(hiccup) level for longer than 20.9 ms
(tblank(hiccup)), the overload protection becomes active. The IC stops switching and attemps
to restart. As long as the overload condition is present the IC makes repetitive restart
attempts. When the overload is removed, the IC restarts and resumes normal operation.
See Section 6.12.6 for a detailed description of the hiccup mode protection.
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6.2.6 Overview control modes
Figure 14 shows the control modes.
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CVB = Constant voltage with burst mode
CVC = Constant voltage with current mode
CVF = Constant voltage with frequency mode
CP = Constant Power
CCF = Constant current with frequency mode
Hiccup mode: When below Vth(hiccup) the IC restarts
Fig 14. Overview control modes
On the left Vout is kept constant, while on the right Iout is kept constant until Vout reaches
the Vth(hiccup) level.
6.3 Emitter drive NPN switch
The TEA1720 uses an emitter drive to control the external NPN switch. The advantages of
the emitter drive are:
• Fast switch-on of the NPN switch
• Guaranteed switch-off of the NPN switch
• The reverse base current that is a result of the NPN BJT switching off is used to
charge the VCC capacitor, preventing excessive switching losses
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6.3.1 Emitter drive switch-on
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Fig 15. Emitter drive switch-on
When the internal MOSFET of the TEA1720 switches on, the emitter of the NPN is pulled
low. The charge of the injection boost capacitor CBASE is transferred directly to the base,
ensuring an immediate switch-on of the NPN (NXP patent, patent pending). The
sustaining base drive is delivered by capacitor CVCC through RBASE.
6.3.2 Emitter drive switch-off
When the NPN switch is on, the collector current increases linearly. The collector current
and the base current are summed up. The resulting current exits through the emitter. The
current flows from the emitter via the internal MOSFET through RSENSE. Measuring the
voltage level across RSENSE (Vpk) determines the moment of switch-off. To compensate
for the base current, a constant offset of 60 mV is subtracted from the measured level.
This offset is equal to 12 % of the peak voltage for maximum Ipk (530 mV).
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Fig 16. Emitter drive switch-off
When the Vpk level on the SENSE pin is reached, the internal MOSFET is switched off.
The emitter current flow is blocked and the collector current exits through the base. The
(negative) base current drains off the charge built-up in the collector. Once all charge is
removed, it switches off the NPN. At the same time the negative base current charges
capacitor CBASE and capacitor CVCC (via diode DBASE) recovering part of the energy,
involved in the base drive during on-time. The switch-off time is often called storage time,
because it is the time required to drain off the stored charge, built-up in the collector
region.
During the storage time, the collector current still continues to increase. The final collector
peak current is therefore higher than the current measured at the SENSE pin at the
moment of switch-off.
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6.3.3 Waveforms
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Fig 17. Waveforms emitter switching
Figure 17 shows the waveforms of the SENSE pin voltage, the collector current, and the
collector voltage. At switch-on, the collector voltage drops to almost zero. The collector
current starts to increase from zero. The initial charge injection provided by capacitor
CBASE is clearly visible in the SENSE pin voltage. After the spike, the SENSE pin voltage
starts with a DC offset due to the base current injected via resistor RBASE. From there the
SENSE voltage follows the increasing collector current and increases more or less
linearly.
When the voltage on the SENSE pin reaches Vpk, the internal MOSFET is switched off.
The voltage on the SENSE pin immediately falls back to zero. The collector current
continues but flows through the base, charging capacitor CBASE and CVCC. The collector
voltage increases immediately to VCC (+ voltage drop over diode DBASE).
When all charge in the collector is removed, the NPN switches off. The collector current
decreases to zero and the collector voltage increases for the start of the secondary stroke.
During the time the charge of the collector is drained off (storage time), the collector
current continues to increase.
Remark: The storage time is not fixed. It changes roughly with a factor 1.7 from the high
mains (264 V) to the low mains (85 V). The higher the mains voltage, the shorter the
storage time.
6.3.4 Built-in compensations for emitter drive
The voltage, measured at resistor RSENSE, does not reflect the peak collector current
exactly. The actual power, however, is related to this peak collector current.
The TEA1720 comprises the following compensations for a controlled drive:
• DC offset compensation on the SENSE pin to compensate for the DC base current
• Vin compensation for Vpk, compensating for the change in storage time
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6.3.4.1
DC offset compensation
The implementation is quite straight forward. A fixed offset of 60 mV is deducted from the
level, measured on the SENSE pin. This offset is optimized for an NPN transistor with a
hFE of 9 to 10. Many low-power NPN transistors that are commonly used fall into this
category.
6.3.4.2
Vin compensation
The collector current continues to increase during storage time. The final peak collector
current is depending on:
• The steepness of the collector current, which is related to the rectified Vin (AC)
• The storage time, which is also related to the rectified Vin (AC)
Table 3 shows typical values for the storage time variation versus input voltage.
Table 3.
Storage time BUJ100 at 0.8 A (peak)
Input voltage (V (RMS/AC))
85
264
Storage time (s)
600
360
To cope with the variation, the peak collector current due to the variation of steepness of
the collector current, and the storage time versus input voltage, Vpk is adapted in
accordance with the input voltage.
To sense the input voltage, the level on the FB pin is measured during the primary stroke.
This level is proportional to the input voltage.
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Fig 18. Sensing Vin on the FB pin
The Vin compensation enables the limiting of the variation of the maximum output power
for all input voltages.
The built-in Vin compensation is designed for typical high-voltage low-power NPN
transistors like the BUJ100 from NXP Semiconductors.
If NPN transistors are used with major deviations in hFE and/or storage time, it is possible
to adapt the Vin compensation externally.
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Fig 19. Adapting Vin compensation externally
During primary stroke, the measured level on the FB pin can be tuned by adding a resistor
in series with a diode parallel to one of the FB sense resistors.
Placing the circuit to ground in parallel with the divider resistor, decreases the Vin
compensation, because the circuit is parallel to ground for negative voltages on the
auxiliary winding, reducing the measured level on the FB pin.
Placing the circuit in parallel with the divider resistor from the FB pin to the auxiliary
winding increases the Vin compensation because the circuit reduces the impedance of the
top resistor for negative voltages.
6.3.5 Base drive dimensioning
Correct dimensioning of the NPN transistor base drive is vital for proper operation of the
application. The components that are dimensioned are resistor RBASE and capacitor
CBASE.
Aspects that play a critical role in the dimensioning process are:
• The peak collector current (Ipk)
Equals the peak current in the primary inductance of the transformer.
• The AC input voltage level
The mains voltage that is supplied to the D1 to D4 rectifier bridge.
• The (quasi DC) voltage level that supplies the base current for the BJT (Q1)
This voltage is referred to as the base drive voltage. In the diagram of Figure 16 it is
the CVCC//CBASE voltage that is also used to supply the VCC for the TEA1720A IC, so
in our example the base drive voltage is VCC.
• The current gain (hFE) of the BJT (Q1)
Especially the current gain at Ipk is important.
• The storage time (ts) of the BJT (Q1)
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6.3.5.1
Initial base drive dimensioning - the base resistor
For initial dimensioning of the base drive resistor, the following information is required:
• The peak current in the primary winding of the transformer (Ipk)
• The hFE of the BJT at the peak current (Ipk)
• The base drive voltage (VCC)
The peak primary winding current (Ipk) results from Vref(pk)high (typically 0.53 V) and the
sense resistor value (Rsense).
V ref  pk high
I pk = --------------------------R sense
(8)
An initial estimate for the BJT hFE is read from the data sheet of the transistor used.
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(1) +125 C
(2) +25 C
(3) 40 C
Fig 20. Typical DC current gain (hFE = f(Ic); parameter VCE)
In a 10 W to 12 W flyback SMPS application, the peak primary winding current is usually
programmed to be between 700 mA and 800 mA. At that current level the hFE for a
BUJ100 transistor is approximately 10.
In the application (see Figure 16) the auxiliary winding of the transformer generates the
voltage (VCC) for the BJT base drive. It equals the TEA1720A VCC voltage. When a
'perfect transformer' is used, VCC is clearly defined and is constant with the AC input
voltage and the output power as long as the application is operating in constant voltage
(CV) mode.
In reality, depending on the quality of the transformer (coupling between secondary and
auxiliary winding), the generated VCC voltage varies with the output power/output voltage
produced by the flyback SMPS application. Furthermore, the output voltage also varies
with the AC input voltage (mains voltage) the SMPS is connected to.
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To calculate the initial value for RBASE, an estimated value for the base-emitter voltage of
the BJT is required under the condition that the BJT is on and saturated. Normally, that
VBE value is between 0.7 V and 1.0 V.
V CC – V ref  pk high – V BE
R BASE = -----------------------------------------------------------  h FE
I pk
(9)
Although it is not very likely that this initial dimensioning of the base drive resistor is fully
optimal, it does result in a perfectly safe starting point for further optimization
(see Section 6.3.5.2).
Example:
•
•
•
•
•
Ipk = 800 mA
hFE = 10
VCC = 17.5 V
Vref(pk)high = 0.53 V
VBE = 0.95 V
V CC – V ref  pk high – V BE
17.5 – 0.53 – 0.95
R BASE = -----------------------------------------------------------  h FE = -------------------------------------------  10  200 
0.8
I pk
6.3.5.2
Initial base drive dimensioning; the base capacitor
The base capacitor (CBASE) delivers a charge carrier injection boost into the BJT
BE-junction at the start of the primary stroke. This injection helps the BJT to reach an
acceptably low VCE(sat) at the end of the primary stroke without requiring a high stationary
injection that must be delivered through the base resistor (and would cause additional
ohmic losses in the base resistor).
A low capacitor value has no significant contribution to charge carrier injection and
therefore does not have a positive effect on the flyback SMPS operation. A very high base
capacitor value results in a tremendous initial charge injection which can result in
overdriving the BJT base, with corresponding increase of the switching losses.
As an initial value for CBASE, we use a capacitor that can store all of the charge that is
recovered from the BJT collector-base junction at the time of switch-off. The charge must
be stored in the CBASE capacitor at the VCC level. This results in the following initial value
for CBASE:
I pk  t s
C BASE = -------------V CC
(10)
Unfortunately, Ipk, ts and VCC substantially vary depending on the operating conditions of
the flyback SMPS. An appropriate CBASE value for full load operation, can be (much) too
large when the SMPS delivers low-power or no power. The result, higher/unacceptable
losses in low load or a power consumption that is too high in a no-load condition.
Therefore the CBASE capacitor value is a subject for careful optimization
(see Section 6.3.5.3).
For four relevant operating conditions we determine Ipk, ts and VCC. From those values we
can calculate the optimum CBASE for that condition (see Table 4).
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Table 4.
[1]
Suggested CBASE values depending on the operating condition
Mains (V
(AC))
Load
Ipk (mA)
115
full load
650
115
no-load
150
230
full load
600
230
no-load
120
VCC (V)
CBASE (nF)[1]
330
20
10.7
250
12
3.1
220
26
5.1
160
12
1.6
ts (ns)
Suggested initial values for CBASE are dependent on the operating condition.
As can be seen from Table 4 the suggested values for the CBASE capacitor differ
significantly depending on the operating condition of the flyback SMPS. A good starting
point for a CBASE capacitor is to take the logarithmic average of the suggested
capacitance values belonging to all relevant operating conditions. If we qualify all the
operating conditions in Table 4 as relevant, then the initial CBASE value is:
C BASE  init 
1
= exp  --- 
n
n

 1n  CBASEinit   4.1 nF
(11)
i=1
A practical choice to start with is 3.9 nF.
6.3.5.3
Base drive dimensioning optimization
In the optimization process an attempt is made to achieve one general objective:
Optimum overall efficiency of the flyback converter. However, while trying to realize that
objective we have to take into account a number of limiting constraints for all other
possible operating conditions:
• Keep the no-load power consumption of the flyback converter below a customer
specified maximum value (for example, 20 mW or < 30 mW to fulfill
Energy Star level 5)
• Keep the CV mode operation within the boundaries of 4.75 V and 5.25 V
• Keep the temperature of the BJT below a customer specified value (for example
< 90  at room temperature at minimal input voltage and maximum load
• Keep the CC mode operation within the ±12 % variation limits
• Keep the conducted and radiated EMI below the levels as defined in CISPR 55022.
• Especially the variation of (ambient) temperature can be a severe constraint for
proper operation
We must also pay attention to other aspects in the flyback converter application. However,
the influence the base drive dimensioning has on these is negligible. For example, the
maximum secondary diode temperature and the flyback transformer temperature must be
below a customer specified maximum value (for example < 85 at room temperature at
minimum input voltage and maximum load). But the base drive has no direct influence on
that. These aspects must be considered in another phase of the flyback converter
dimensioning process.
The optimization process
The base drive optimization process is time-consuming. Performance assessment
sessions are required for a matrix of RBASE/CBASE values.
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Performance assessment session
Basically, one performance assessment session (for one combination of RBASE and
CBASE) consists of:
1. Measurement of the efficiency in the following (4  4) matrix:
– At minimum mains (85 V (AC)/60 Hz), low mains (115 V (AC)/60 Hz),
high mains (230 V (AC)/50 Hz), and maximum mains (265 V (AC)/50 Hz)
– At 25 % load, 50 % load, 75 % load, and 100 % load
2. Measurement of no-load power consumption under the following conditions:
– At minimum mains (85 V (AC)/60 Hz), low mains (115 V (AC)/60 Hz),
high mains (230 V (AC)/50 Hz), and maximum mains (265 V (AC)/50 Hz)
3. Measurement of the output voltage in the following (4  5) matrix:
– At minimum mains (85 V (AC)/60 Hz), low mains (115 V (AC)/60 Hz),
high mains (230 V (AC)/50 Hz), and maximum mains (265 V (AC)/50 Hz)
– At 0 % load (no-load), 25 % load, 50 % load, 75 % load, 100 % load.
4. Measurement of the RBASE temperature at load (100 % load) and the following AC
input voltage conditions:
– At minimum mains (85 V (AC)/60 Hz), low mains (115 V (AC)60 Hz),
high mains (230 V (AC)/50 Hz), and maximum mains (265 V (AC)/50 Hz)
5. Measurement of the BJT temperature under full load (100 % load) and the following
AC input voltage conditions:
– At minimum mains (85 V (AC)/60 Hz), low mains (115 V (AC)/60 Hz),
high mains (230 V (AC)/50 Hz), and maximum mains (265 V (AC)50 Hz)
6. Measurement of the output current (in CC mode) in the following (4  5) matrix:
– At minimum mains (85 V (AC)/60 Hz), low mains (115 V (AC)/60 Hz),
high mains (230 V (AC)/50 Hz), and maximum mains (265 V (AC), 50 Hz)
– At 95 %, 90 %, 80 %, 70 %, and 60 % of the nominal rated (CV) output voltage
7. Evaluation of conducted and radiated EMI under relevant conditions
8. Verification of proper operation under relevant conditions (e.g. temperature range)
In applications where, for example, CC mode is not relevant or where EMI is not
important, the respective corresponding measurements can be skipped.
Varying RBASE and CBASE; filling the performance assessment session matrix
Start with the performance assessment session where RBASE = RBASE(init) and
CBASE = CBASE(init) (the middle value in the matrix).
Table 5.
Performance assessment session matrix
room for extension
.................
.................
.................
room for extension
RBASE = RBASE(nit) * 0.67 RBASE = RBASE(nit) * 0.67 RBASE = RBASE(nit) * 0.67
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CBASE = CBASE(init) * 0.5
CBASE = CBASE(init) * 1.0
CBASE = CBASE(init) * 2.0
RBASE = RBASE(nit) * 0.8
RBASE = RBASE(nit) * 0.8
RBASE = RBASE(nit) * 0.67
CBASE = CBASE(init) * 0.5
CBASE = CBASE(init) * 1.0
CBASE = CBASE(init) * 2.0
RBASE = RBASE(nit) * 1.0
RBASE = RBASE(nit) * 1.0
RBASE = RBASE(nit) * 1.0
CBASE = CBASE(init) * 0.5
CBASE = CBASE(init) * 1.0
CBASE = CBASE(init) * 2.0
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Table 5.
Performance assessment session matrix …continued
RBASE = RBASE(nit) * 1.2
RBASE = RBASE(nit) * 1.2
RBASE = RBASE(nit) * 1.2
CBASE = CBASE(init) * 0.5
CBASE = CBASE(init) * 1.0
CBASE = CBASE(init) * 2.0
RBASE = RBASE(nit) * 1.5
RBASE = RBASE(nit) * 1.5
RBASE = RBASE(nit) * 1.5
CBASE = CBASE(init) * 0.5
CBASE = CBASE(init) * 1.0
CBASE = CBASE(init) * 2.0
.................
.................
.................
Plot the tendency in the efficiency figures in a 3-dimensional graph (efficiency as a
function of RBASE and CBASE). If the efficiency has not reached a maximum, extend the
RBASE range in steps of a factor ~1.2 (higher or lower) and/or the CBASE range in steps of
a factor of ~2 (higher or lower) until a maximum efficiency value is found.
Provided that there is no conflict with the constraints listed above, the optimum for the
RBASE/CBASE combination is found. Fine-tuning of the RBASE/CBASE combination using
finer variation steps is an option.
A word of caution - overdriving and underdriving
Overdriving the base oversaturates the BJT which usually results in (much) higher than
necessary switching losses. It is inefficient but not immediately catastrophical.
On the other hand underdriving the base causes an undersaturated situation in the BJT
which leads to a high VCE voltage drop during on-state and consequently (very) high
conduction losses. Significant underdriving can rapidly lead to a thermally unstable
situation and thermal runaway, destroying the BJT.
The maximum efficiency is achieved under so-called "lean driving" conditions. Lean
driving conditions set the best balance between switching losses and conduction losses.
To be on the safe side, a BJT can be slightly overdriven, but preferably not underdriven.
Underdriven BJTs are much more prone to failure.
Finally, there can be (application specific) constraints that can impose minimum or
maximum value requirements on RBASE and CBASE.
6.3.5.4
Verification of RBASE at low temperatures
After optimizing RBASE, it is important to check the drive under all operating conditions.
This requirement is the most critical at start-up at low temperatures.
Check the start-up of the application at the lowest Vin (AC) and at the lowest specified
ambient temperature. The voltage at the SENSE pin must reach Vpk at start-up until VCC
reaches 8.5 V (VCC(stop)).
This check can be done by disconnecting the diode (DVCC) from the auxiliary winding to
the VCC capacitor. After the VCC capacitor is charged to 17 V (VCC(start)), switching starts
and continues until VCC reaches 8.5 V (VCC(stop)) because the VCC supply is not taken
over by the auxiliary winding.
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Fig 21. Setup for checking base current
Put the application in a temperature chamber and bring the temperature to the lowest
ambient temperature specified.
Measure the voltage on the VCC and SENSE pins. Especially monitor the last strokes
before VCC reaches 8.5 V and switching stops. Vpk must be reached.
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Green = VCC
Purple = Vout
Blue = Vsense
Fig 22. Base current high enough
For checking the voltage on the SENSE pin, zoom in on the part where switching stops. It
is clear the voltage at the SENSE pin remains correct until 8.5 V is reached (VCC(stop)).
The last stroke is ended as soon as VCC(stop) is reached.
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Figure 23 shows an example of the waveform on the SENSE pin when Vpk is not reached.
Green = VCC
Purple = Vout
Blue = Vsense
Fig 23. Base current too low to reach Vpk
Zooming in on the last strokes before switching stops, Vpk is not reached in the last full
stroke. The current keeps flowing until the maximum duty cycle is reached (75 %). RBASE
must be lowered to prevent that this condition occurs.
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6.4 Total input power at no-load
The input power at no-load consists of several components. An overview is given below:
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For a 10 W charger, the no load losses are:
(1) Leakage rectifier: 2  0.1 A at 375 V = 0.1 mW
(2) Leakage mains electrolytic capacitors: 5 A at 375 V = 2 mW (estimated)
(3) FB sensing resistive divider: Only dissipating during primary and secondary stroke = 0.1 mW
(4) Leakage HV current source: 1 A at 375 V = 0.4 mW
(5) Supply current IC: 130 A at 15 V = 2 mW
(6) Base drive losses = 4 mW
(7) Snubber losses = 2 mW
(8) The stored energy (0.5  Lp  Ipk2) is divided between the VCC (basedrive + IC supply current) and the secondary load
(transient detector and preload)
(9) Supply current transient detector: 0.1 mA at 5 V = 0.5 mW; influence on no-load power negligible; can be compensated by
adapting the preload resistor value.
(10) Preload resistor: 3.6 k; tuned to prevent Vout rises at maximum Vin (264 V (AC)); dissipation = 7.5 mW
Fig 24. Overview of no load losses
Adding up all numbers the result for a 10 W charger is:
P noload = 0.1 + 2 + 0.1 + 0.4 + 2 + 4 + 0.5 + 7.5 = 18.6 mW
(12)
For a 5 W charger, the P no-load is roughly half (< 10 mW). For a 12.5 W charger, the P
no-load remains < 30 mW.
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6.5 Value output capacitor, ripple, load step, transient controller
The value of the output capacitor is key in determining properties, like ripple and load step
behavior.
6.5.1 Ripple
For minimal ripple at full load, use two capacitors with a low ESR, like aluminum polymer
electrolytic capacitors, in parallel.
Due to the low burst frequency, ripple also occurs in burst mode. This ripple is highest
when the duty cycle in burst mode is around 50 % which is 50 % switching including the
recharging of the output capacitors and 50 % non-switching including the discharging of
the output capacitors. Because the peak current is highest at the highest input voltage, the
ripple is also highest at the maximum input voltage (Vin).
Vin (AC) = 264 V; Iload = 72 mA; Vout(ripple) (peak-to-peak) = 134 mV
Orange = Vout (DC; 1 V/div)
Green = FB pin; indicating the switching of the controller
Purple = Ripple Vout enlarged (AC; 50 mV/div)
Fig 25. Vout ripple at 50 % switching in burst mode
Practical example
• For a 10 W charger, the load current at 264 V (AC)/50 % duty cycle in burst mode is
72 mA.
• fburst = 400 Hz; tburst = 2.5 ms, 50%; tburst = tch = tdch = 1.25 ms.
• Take two 470 F output capacitors
The actual value of the output capacitors can be 80 %. So in practice the output capacitor
value becomes: C out = 0.8   2  470 F  = 750 F .
The discharge voltage (Vdch) during non-switching (which is equal to the charge voltage
(Vch) during switching) can be calculated with Equation 13.
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t dch
0.00125
- = 120 mV
V dch = I load  ---------- = 0.072  -----------------6
C out
750
(13)
With an additional 20 mV ripple, the resulting peak-to-peak ripple is 140 mV
Use the values in Table 6 when the ripple < 150 mV.
Table 6.
Cout for peak-to-peak ripple <150 mV
fburst
Pout(nom)
Cout(nom)
400 Hz
10 W
2  470 F
400 Hz
5W
2  270 F
6.5.2 Load step without transient control
When a load step occurs while the TEA1720 is switching, the loop responds immediately
and Vout remain within the USB 1.1 specification limits.
The situation is different when the load step occurs during the non-switching time in burst
mode because the primary sensing concept is "blind" to what happens on the secondary
side when the IC is in energy save mode between burst periods.
For load steps without transient controller, the USB 1.1 specification (see Section 8.1.1) is
followed in most cases.
USB 1.1 requires that Vout remains above 4.1 V for a 0 A to 0.5 A load step.
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Fig 26. Load step without transient controller
The worst case is when the load step occurs as the IC enters energy save mode. The
maximum time the capacitor has to maintain the output voltage is 1/fburst.
The capacitor value can be calculated with Equation 14:
I load
C out = ------------------------------------ f burst  V drop 
(14)
Where:
• Iload is the current after load step
• Vdrop is the output voltage (Vout) at the beginning of load step 4.1 V
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Equation 14 clearly indicates the relation between the output capacitor (Cout) and the
burst frequency (fburst).
Example:
Due to the internal load line of 250 mV, Vout at no-load is at least 5.00 V. As a result, the
voltage on the output capacitor can drop from 5.00 V to 4.10 V.
• Vdrop = 0.9 V
• Iload = 0.5 A
• fburst = 400 Hz
0.5
–6
C out  min  = --------------------------- = 1388  10
 400  0.9 
The result is the minimal required value for the capacitor (Cout). Most electrolytic
capacitors have a 20 % tolerance on the low-side. Divide the calculated value by 0.8 to
obtain the nominal value.
–6
1388
–6
C out  nom  = ---------------- = 1736
0.8
(15)
This is one 1000 F capacitor and one 820 F capacitor in parallel (or two 820 F
capacitors in parallel at a maximum negative tolerance of 15 %.
Table 7 shows the results.
Table 7.
Cout for USB 1.1 without transient controller
fburst
Cout(nom)
Maximum negative tolerance
400 Hz
1000 F + 820 F
20 %
400 Hz
2  820 F
15 %
Remark: The USB 1.1 specification specifies only one load step current (0 A to 0.5 A). It
is not related to the available maximum output power.
6.5.3 Transient controller (TEA1705)
To improve the load step performance in burst mode, the transient controller TEA1705
can be added.
The TEA1705 is placed on secondary side. It monitors continuous Vout via the VCC pin.
When Vout drops to below 4.9 V, when the TEA1720 is in burst mode and not switching
(energy save mode), the TEA1705 generates a wake-up pulse via the transformer to
trigger the TEA1720 to immediately start switching.
Using the TEA1705 in a 10 W charger with 2  470 F output capacitor, the 0 A to 2 A
load steps can be handled while Vout remains > 4.5 V.
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6.5.3.1
Circuit diagram
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Fig 27. Schematic diagram showing TEA1705
The VCC pin serves as supply pin and to monitor Vout. The supply current of the TEA1705
is only 100 A. This current does not affect the no-load power. It can be compensated by
adapting resistor RPRELAOD if required.
Only two additional components are required in the application, RCAP and CCAP. Typical
values are:
• RCAP = 4.7 
• CCAP = 47 nF
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6.5.3.2
Transient controller mechanism
Figure 28 shows how the transient controller mechanism operates.
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(1) The burst switching ends and the TEA1720 enters energy save mode. The transient detector on
the FB pin is enabled. The TEA1705 detects that no switching occurs and becomes active after
70 s.
(2) A load step of 0 A to 2 A occurs causing Vout to drop.
(3) When Vout reaches 4.9 V, the internal MOSFET between the capacitor CCAP and GND switches on
for 1.2 s and discharges CCAP over the secondary winding.
(4) The discharging of CCAP causes ringing in the transformer windings and generates a wake-up
pulse at the FB pin.
(5) The wake-up pulse is detected by the FB pin. The TEA1720 wakes up from energy save mode.
After 16 s switching starts at full power. Vout start to rise.
(6) During the first primary stroke, CCAP recharges and is ready for the next load step.
Fig 28. Load step during burst with transient controller
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6.5.3.3
TEA1705 generation wake-up pulse
Figure 29 shows the generation of the wake-up pulse.
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Fig 29. Wake-up pulse generation, CCAP discharge
When the internal MOSFET of the TEA1705 is on for 1.2 s, CCAP is discharged. The
discharge causes a step response on the secondary winding (and all other windings).
After the step the transformer starts a damped ringing with the same frequency and
damping as after the secondary stroke.
6.5.3.4
TEA1720 transient detector
Figure 30 shows the detection of the wake-up pulse.
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Fig 30. TEA1720 transient detector
The transient detector in the TEA1720 is a comparator with a detection level of 0.5 V. To
prevent false detection, the transient detector in the TEA1720 is only enabled during the
energy save mode where no switching occurs and the level on the FB pin is 0 V.
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6.5.3.5
TEA1705 charging CCAP
Figure 31 shows the charging of CCAP.
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Fig 31. Charging CCAP during primary stroke
When switching starts, the voltage on the secondary winding is negative. This negative
voltage charges CCAP via the backgate diode of the TEA1705 internal MOSFET. RCAP is
added to limit the charge current to safe values (< 3 A).
The amplitude of the negative voltage is proportional to Vin (AC). The charge on CCAP is
always high enough, even at the lowest AC input voltage, when the values CCAP = 47 nF
and RCAP = 4.7  are used.
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6.5.3.6
TEA1720 switching detector and wake-up pulse disable timer
To prevent unnecessary discharge of CCAP, the TEA1705 also contains a switching
detector (see Figure 32).
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Fig 32. Switching detector with disable timer wake-up pulse
The switching detector monitors the voltage on the CAP pin. When an AC signal is
present it detects the lowest level, which is during primary stroke.
The detection resets the internal 70 s timer. As long as the timer is active (as long as
switching occurs), the generation of the wake-up pulse is disabled. 70 s after the last
stroke detection the generation of wake-up pulses is enabled. Only when the TEA1720
enters energy save mode this condition occurs.
Remark: The TEA1705 can only generate a wake-up pulse and the TEA1720 can only
detect a wake-up pulse during energy save mode.
6.5.3.7
TEA1705 no-load Vout protection
When Vout exceeds 5.9 V, the VCC pin of the TEA1705 starts to draw current
(see Figure 33).
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The VCC current increases linearly from 0 mA at 5.9 V to 40 mA at 7.0 V. At 6.3 V, the
current is 15 mA, which corresponds with a secondary load of 95 mW.
This protection prevents Vout rises above 6.3 V, causing leakage of the often used
polymer output electrolytic capacitors with a 6.3 V rating when the preload resistor
provides insufficient load or no preload resistor is mounted.
6.6 Feedback
In a primary sensed system, the output voltage is regulated by measuring the voltage of
an auxiliary winding on primary side.
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Fig 34. Feedback from auxiliary winding
For optimal matching of the auxiliary winding and the output voltage, couple the
transformer auxiliary winding to the secondary winding tightly.
Due to the primary sensing concept, the secondary voltage is regulated before the
secondary diode. Changes in voltage drop over the diode are not corrected and are
reflected in the Vout level.
Figure 35 shows the waveform on the auxiliary winding.
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(1) No accurate measurement possible during ringing.
(2) Voltage drops due to decreasing voltage over the secondary diode with decreasing current.
(3) Measurements done towards the end of the secondary stroke at minimal secondary current to
increase accuracy and avoid ringing.
Fig 35. Waveform auxiliary winding
Vout is measured during the secondary stroke. To increase the accuracy, Vout is sampled
near the end of the secondary stroke. This timing minimizes the influence of the voltage
drop over the secondary diode because the diode current is close to zero. It also
minimizes errors because of ringing.
As the secondary stroke time varies with the value of Ipk (the higher Ipk, the longer the
secondary stroke time), the sample time is adapted accordingly.
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(1) To increase measurement accuracy, the position of the measurement pulse is adapted to the
duration of the secondary current. A measurement is done near the end of the stroke where the
secondary stroke is close to zero and ringing is minimal.
Fig 36. Adaptive sample time
Configure the resistive divider on the FB pin to deliver 2.5 V at the FB pin near the end of
the secondary stroke (burst mode). Take into account that the voltage near the end of the
secondary winding is V out + V diode .
6.7 Demagnetization protection
The signal of the auxiliary winding on the FB pin is also used for demagnetization
protection. That is, to determine if the secondary stroke has ended and all stored energy
in the transformer is transferred to secondary side.
To release the demagnetization protection, the voltage on the FB pin must drop to
< 50 mV after the secondary stroke has started. When no demagnetization is detected,
the next primary stroke is prohibited until demagnetization detection is true. This condition
ensures discontinuous operation.
6.8 Supply from auxiliary winding
The IC and the base drive are supplied from an auxiliary winding. It is possible to use the
feedback auxiliary winding or a separate winding.
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Fig 37. Supply from auxiliary winding
When designing the auxiliary winding, consider the waveforms on the winding as shown in
Figure 38.
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(1) Actual VCC, resulting from peak rectification of the ringing
(2) VCC, expected from the transformer calculations using winding ratios
Fig 38. VCC higher than anticipated due to ringing
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Depending on the power consumption of the IC plus base drive and the power, delivered
by the collector current of the NPN when switched off at the emitter, the rectified voltage of
the auxiliary winding follows the average or the peak of the ringing (peak rectification).
Therefore, the supply voltage can be higher than anticipated. The amount of ringing is
depending on the coupling of the auxiliary winding with the primary and secondary
winding. It may be necessary to adapt the number of auxiliary windings to get the correct
supply voltage.
The supply voltage range is rather large (8 V to 40 V). For optimum efficiency and no-load
input power design VCC on 10 V to 12 V at no-load at the minimum Vin (85 V (AC)).
Because the ringing and the charge, delivered by the collector current at switch-off
increases for higher load, the supply rises to 20 V to 22 V at full load.
6.9 Load line compensation
For a stable regulation, it is required that the voltage on the FB pin drops for higher loads.
This leads to a load line from zero load to full load of 500 mV. The IC has a built-in load
line compensation that limits the load line from zero to full load to 250 mV.
6.10 Cable compensation
Standard cables with a specified fixed resistance are often used with smartphone
chargers.
IC versions with cable compensation increase the output voltage (Vout) depending on the
delivered output power to compensate the voltage drop over the cable.
Figure 39 shows the effect of cable compensation for a compensation voltage of 0.3 V.
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Fig 39. Cable compensation
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Cable compensation uses positive feedback. The regulation loop has to be slow to
prevent instability. For load steps, an additional drop of the output voltage (Vout) at the end
of the cable occurs because of the voltage drop over the cable.
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Fig 40. Additional voltage step due to cable compensation
The slow cable compensation loop causes an additional voltage step at the end of the
cable of Iload  Rcable = cable compensation voltage both for positive as negative load
steps.
When using cable compensation the output capacitors must to be enlarged to
compensate for the extra voltage drop after a load step at the end of the cable.
Different cable compensation voltages are available (no compensation, 0.2 V, 0.3 V,
0.44 V).
6.11 Jitter
To improve ElectroMagnetic Interference (EMI), the switching frequency varies around the
center value, resulting in reduced peak levels around the switching frequency. Jitter of
approximately 8 % is present in all modes. The jitter frequency is between 100 Hz and
400 Hz. To keep Pout constant while varying fsw, Ipk is adapted accordingly as can be
derived from Equation 16.
2
P out = 0.5  L p  I pk  f sw  
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6.12 Protective features
The following protections are implemented:
•
•
•
•
•
•
•
UnderVoltage Protection (UVP) on the VCC pin
OverVoltage Protection (OVP) on Vout (via the FB pin)
OverTemperature Protection (OTP)
Demagnetization protection
Open/short circuit protection on the FB pin
Hiccup mode for overload/short circuit protection of the output
Short circuit protection on the SENSE pin
6.12.1 Undervoltage protection on the VCC pin
The UVP on the VCC pin prevents unpredictable behavior when the supply voltage drops
to below the minimum level required for operation. When the voltage on the VCC pin
drops to below 8.5 V (VCC(stop)) the IC restarts.
Restarting the IC causes switching to stop. The high-voltage current source is enabled to
charge the VCC capacitor. When VCC exceeds 17 V (VCC(startup)), the high-voltage current
source is disabled and switching restarts.
If the error persists, the sequence repeats itself. This condition is known as the hiccup
mode.
6.12.2 Overvoltage protection on Vout
The voltage on secondary side is monitored using VFB (measured on the FB pin). During
normal operation, VFB  2.5 V when sampled during the secondary stroke. If VFB > 3.2 V,
a forced restart is performed.
When the sampled voltage on pin FB > 3.2 V, switching stops. The auxiliary winding no
longer provides the VCC supply and VCC drops. If required, the IC waits until the VCC
supply < 8.5 V before enabling the high-voltage current source to charge the VCC
capacitor.
When VCC(startup) > 17 V, the high-voltage current source is switched off and the switching
is reenabled. If the error persists and the sampled voltage on pin FB exceeds 3.2 V,
switching stops, the sequence repeats itself. This condition is known as the hiccup mode.
The overvoltage level is determined as follows:
• Sampled voltage on the FB pin for Vout = 5 V: 2.5 V
• The voltage on the secondary winding before the diode: 5.3 V
• The secondary winding voltage ratio divided by the sampled voltage on the FB pin is
5.3 V / 2.5 V = 2.12
• The secondary winding voltage at a sampled voltage on the FB pin of 3.2 V:
3.2 V  2.12 = 6.8 V
• Vout after the diode becomes: 6.8 V  0.3 V = 6.5 V
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The output voltage must exceed 6.5 V before OVP is triggered. In practice, OVP triggers
when the output voltage is between 6.5 V and 6.8 V, depending on the steepness of the
Vout increase.
6.12.3 Overtemperature protection
When the temperature of the IC exceeds 150 C, OTP is activated. The IC stops switching
and VCC drops. When VCC drops to below VCC(stop) (8.5 V), the high-voltage current
source charges the VCC capacitor until 17 V (VCC(startup)) is reached. The IC does not start
switching until the die temperature drops to below 100 C. During the waiting time, VCC
cycles between charging to VCC(startup) and discharging of the non-switching TEA1720 to
VCC(stop) by the quiescent current.
The hysteresis from 150 C to 100 C ensures that no dangerous situations occur.
6.12.4 Demagnetization protection
Demagnetization protection is implemented to check that the secondary stroke has ended
before enabling the next primary stroke. This condition ensures discontinuous operation.
It prevents stress in overload conditions.
Demagnetization monitors the level on the FB pin after the secondary stroke is started.
The level must drop to below 50 mV before the next primary stroke is allowed. When no
demagnetization is detected at the start of the next primary stroke, this stroke is skipped
and the controller retries at the next primary stroke (cycle skipping).
6.12.5 Open/short protection on the FB pin
The FB pin detects if an AC voltage is present on the pin. When the voltage on the pin
does not alternate below and above 50 mV, indicating the pin is not connected to the
resistive feedback divider but open or shorted to ground, switching stops. Consequently,
VCC drops to below VCC(stop) and the IC restarts. When VCC reaches 17 V (VCC(startup)) at
the first stroke, the level at the FB pin is checked again to see if it alternates below and
above 50 mV. If not, the sequence repeats (hiccup mode). This action prevents the
presence of an uncontrolled output voltage when the FB pin is open or shorted to ground.
6.12.6 Hiccup mode for overload/short circuit protection of the output
To limit the input power in case of overload and/or short circuit, the controller enters
hiccup mode when Vout becomes too low.
The Vout level is monitored by the FB pin. When due to overload or a short circuit the
sampled voltage on the FB pin drops to below 1.10 V (Vth(hiccup)) for longer than 20.9 ms
(tblank(hiccup)), the switching stops and the IC restarts.
When during a restart the sampled voltage on the FB pin does not exceed 1.40 V
(Vth(rel)(hiccup)) within 20.9 ms (tblank(hiccup)), the sequence is repeated until the fault
condition is removed. When the fault condition is removed, normal operation is resumed.
Table 8 show the two levels for Vth(hiccup).
Table 8.
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Overview hiccup levels
Version
Vth(hiccup)
Vout(hiccup)
Vth(rel)(hiccup)
Vout(rel)
tblank(hiccup)
1. USB standard
1.10 V
2.00 V
1.40 V
2.7 V
20.9 ms
2
1.47 V
2.7 V
1.70 V
3.1 V
20.9 ms
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The values of Vout(hiccup) and Vout(rel) are given as guideline. The exact value depends on
the used divider for the FB pin.
The first version is USB compliant (Vout remains in regulation until 2 V before the
protection starts). The second version is meant for those who prefer protection to come in
early.
The sequence is explained in the picture below.
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(1) High-voltage current source charges VCC capacitor until VCC(startup) is reached.
(2) Switching starts. Vout rises to 5 V; Iload = 2 A.
(3) Short circuit occurs at end of the cable. Iload exceeds the Constant Current (CC) level. Vout drops to
below Vout(hiccup). VCC also drops (VCC is proportional to Vout).
(4) Switching continues for 20.9 ms (tblank(hiccup))
(5) After 20.9 ms, switching stops. VCC drops to 8.5 V (VCC(stop)). The hig-voltage current source is
enabled and charges the VCC capacitor to 17 V (VCC(startup)).The high-voltage current source is
switched off.
(6) Switching starts. Due to the short, Vout does not exceed Vout(rel). Switching continues for 20.9 ms
(tblank(hiccup)).
(7) After 20.9 ms, switching stops. The drop of VCC continues but more slowly, because only the
quiescent current for the TEA1720 is drawn (no base current).
(8) VCC drops until 8.5 V (VCC(stop)) is reached. The VCC capacitor is recharged.
(9) When VCC reaches 17 V (VCC(startup)) the sequence is repeated.
(10) When the short circuit is removed and switching starts, Vout will rise to exceed Vout(rel) within
20.9 ms (tblank(hiccup)). Normal operation is resumed.
Fig 41. Hiccup mode
The protection works the same for both overload and short circuit.
The input power Pin during protection is depending on the ratio between the time the IC is
switching (tblank(hiccup)) and the time no switching occurs (the VCC capacitor charging time,
with roughly 1 mA from 8.5 V (VCC(stop)) to 17 V (VCC(startup)), and the time VCC drops after
switching has stopped; see (6) to (9) in Figure 41). The charge time for a 10 F VCC
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capacitor is approximately:
 V CC  startup  – V CC  stop  
– 5  17 – 8.5 
- = 71 ms
VCC capacitor   -------------------------------------------------------------- = 10  ----------------------–3


I CC  startup 
1.2
(17)
To keep Pin for a 10 W charger below 1 W, a VCC capacitor of 10 F is required. When
the input power is too high, the VCC capacitor can be increased until the required input
power is met.
Remark: The actual value of ceramic capacitors of that size (10 F at 50 V) is often much
lower when used at a 20 V supply voltage. The lower capacitance value causes Pin to
increase.
6.12.7 Short circuit protection on the SENSE pin
The TEA1720 has a built-in protection for faults, caused by a short circuit of the SENSE
pin to ground or a shorted RSENSE resistor.
From the start of the primary stroke the voltage level on the SENSE pin is monitored. If the
level has not increased to 125 mV (Vscp(high)) within 1.35 s (tblank(scp)SENSE), a short
circuit is suspected and switching is stopped. VCC drops to 8.5 V (VCC(stop)) and the IC
restarts. If the fault condition persists, the sequence is repeated (hiccup mode). Once the
fault condition is removed, the IC restarts and normal operation is resumed.
The steepness of the primary current increase depends on the mains voltage. To
compensate for the steepness variation, tblank(scp)SENSE is adapted according the mains
voltage.
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Fig 42. Short circuit protection on the SENSE pin; adaptive tblank(scp)SENSE
Vin is the rectified mains voltage. The higher Vmains (and Vin), the shorter tblank(scp)SENSE.
An additional protection is implemented when the short circuit on the SENSE pin occurs
after the level of the SENSE pin passed 125 mV.
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Fig 43. Short circuit protection on the SENSE pin for Vsense > 125 mV
The left hand side shows a normal stroke. Vsense exceeds 125 mV (Vscp(high)) within the
required time (tblank(scp)SENSE). The level on the SENSE pin reaches Vpk and the gate drive
of the emitter switch is switched off.
At the next stroke Vsense exceeds 125 mV within tblank(scp)SENSE as well, but now a short
circuit occurs before Vpk is reached. The voltage on the SENSE pin drops to below
105 mV (Vscp(low)). The gate drive immediately switches off. The hysteresis between the
two detection levels (125 mV (Vscp(high)) and 105 mV (Vscp(low)) ensures stable behavior.
The conditions for SENSE pin short protection are listed below. The protection is only
triggered when the following criteria are all met:
• The gate drive must still be active
• tblank(scp)SENSE has passed
• The Vsense level is still below 125 mV (Vscp(high))
or
• The gate drive is still active
• tblank(scp)SENSE has passed
• The Vsense level drops to below 105 mV (Vscp(low))
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6.12.8 Protection overview table
Table 9.
Overview protections
Protection
Level
Action
UVP on pin VCC
(UnderVoltage LockOut
(UVLO))
8.5 V (VCC(stop))
stop switching; restart
OVP on output voltage (Vout)
VFB > 3.2 V
stop switching; restart
OTP
die temperature > 150
stop switching until T < 100 C
demagnetization
VFB < 50 mV
hold next primary stroke until
demagnetization has occurred
short/open circuit protection on AC detection on the FB pin
the FB pin
stop switching; restart
hiccup mode
VFB < 1.1 V or VFB < 1.47 V
Continues operation for 20.9
ms. If the condition still exists,
stops switching, restarts.
Otherwise the timer resets and
operation is continued.
short circuit protection on the
SENSE pin
Vsense < 125 mV at
t < tblank(scp)SENSE
stop switching; restart
7. Application
This chapter describes the following topics:
•
•
•
•
AN11401
Application note
Application diagram
Transformer considerations
ElectroMagnetic Interference (EMI)
Tolerances
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Application note
7.1 Application diagram
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AN11401
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Fig 44. Schematic demo board
TEA1720/TEA1705 5 W to 12.5 W power supply/USB charger
Rev. 1 — 5 December 2013
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5)
$7
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For the schematic, a 10 W charger application has been used. The following sections
describe the various components, going from the AC input to the output.
7.1.1 Input part and EMI filter
RF1 is a 2 A fuse for short circuit protection on the primary side. The inrush current is
limited by RT1, a 10  NTC resistor. Using an NTC on this position limits the efficiency
loss due to the series resistance.
For mains rectification, standard diodes are used. However using a diode bridge is also
possible.
Capacitors C1 and C2 form the main electrolytic capacitor. Capacitors C1 and C2,
inductors L101, L102, and resistor R102 form a damping filter for conducted EMI.
7.1.2 Connecting pin HV to the bus voltage
The HV pin of the TEA1720 is connected via resistor R1 and zener diode D1 to the
rectified mains voltage. Resistor R1 is added to increase the protection for surge tests.
Zener diode D1 prevents a restart after disconnecting the charger from the mains at high
input voltage and full load. In this condition, the voltage on the VCC capacitor drops to
below 8.5 V (VCC(stop)) while the mains electrolytic capacitors are only discharged to 50 V.
The remaining 50 V is high enough to enable audible repetitive restarts of the TEA1720
via the HV pin.
To disable the restart option via the HV pin, the voltage must be lower than 20 V. The
applied zener of 43 V in series together with the HV pin fulfills this requirement for
voltages on the electrolytic capacitors up to 63 V. Tests show that zener values between
36 V and 75 V prevent the repetitive restarts and enable start-ups from 75 V (AC).
7.1.3 Clamp
Diode D8, resistors R8 and R9, and capacitor C8 are designed to dampen the ringing after
switch-off of the NPN switch. D8 must be a slow diode for ringing damping. Figure 45 and
Figure 46 show damping using a fast and a slow diode.
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(1) Drain primary switch
(2) Cathode clamp diode
Fig 45. Damping using a slow diode (S1JL)
When using a slow diode, the diode conducts after the drain signal reaches its peak. The
clamping circuit remains parallel to the primary. This action leads to the fast damping of
the ringing. The ringing frequency is 1.1 MHz. The damping time is 2 s.
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(1) Drain primary switch
(2) Cathode clamp diode
Fig 46. Damping using fast diode (BYW26CV)
Using a fast diode, the clamping capacitor remains charged after reaching a peak. The
clamping circuit is not active and does not provide further damping. The oscillation
frequency is 2.2 MHz. The damping time increases to 4 s. Quick damping of the
oscillation is important to ensure proper measurement of the voltage on the FB pin at the
end of the secondary stroke.
The value of R9 controls the damping. It is a compromise of damping speed and
additional dissipation of the clamp. The values shown are a good starting point for a 10 W
application.
7.1.4 Sense resistor
The sense resistor between the SENSE pin and ground incorporates two SMD resistors in
parallel. Parallel configuration allows the use of standard SMD resistors for accurate
tuning.
Tune the value of the source resistor in the real application. Exact calculation is hardly
possible because of the influence of the used NPN switch (base current setting, storage
time) on the actual Ipk(p)max reached in the primary of the transformer.
For a first indication, the assumption is that the base current in the sense resistor
compensates the increase of the collector current at switch-off. Rsense can be calculated
with :
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V sense  pk max
R sense = -------------------------------I pk  p max
(18)
VSENSE(pk)max = 0.530 V. Ipk(p)max is the peak current required to deliver full power as in the
following calculation:
2
P in  max  = 0.5  L p  I pk  max   f max , where Pin(max) = Pout(max) / , and  = 80 % for 10 W.
In practice, Rsense can deviate due to the difference between the base current and the
increase of the collector current after switch-off of the NPN.
7.1.5 Auxiliary winding: Supply
One auxiliary winding of the transformer supplies the IC VCC voltage via R5, D5 and C70.
The actual VCC level is depending on:
• The amount of ringing on the winding, which is related to the Ipk level and the coupling
of the auxiliary winding to the primary. Ringing can cause the resulting VCC to be
higher than the average level during secondary stroke.
• Charge by the collector current flowing via D7 when the emitter of the NPN is
switched off. This additional charging increases for higher input voltages.
Check that VCC remains above 8.5 V (VCC(stop)) until Vout reaches 2.0 V or 2.7 V
(Vout(hiccup)). Resistor R5 is added to prevent a short load of the auxiliary winding under
no-load conditions that is too high. A short load can disturb the waveform at the FB pin.
The value of C70 must be at least 10 F because it also supplies the base current from
the NPN switch.
Remark: Install capacitor C70 as close to the IC as possible to suppress disturbances.
7.1.6 Base drive NPN
The supply voltage (VCC) also provides the base drive of the NPN.
When the internal MOSFET of the TEA1720 switches on, the emitter of the NPN is pulled
low. Capacitor C7 delivers the base charge at switch-on (NXP patent, patent pending).
The base resistor which determines the sustaining base drive during on-time, is split into
three parallel resistors (R70, R71 and R72) to handle the dissipation and the temperature.
Switching off the internal MOSFET directs the collector current through the base of the
NPN which charges the VCC capacitor (C70) via diode D5.
To ensure the emitter current is always high enough to reach the maximum Vpk (530 mV),
it is important that the sustaining base current is high enough.
Tests have shown that this condition is the most critical at low temperatures. The base
drive must be checked at the minimal operation temperature with minimal VCC
(8.5 V (VCC(stop)); see Section 6.3.5).
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7.1.7 Auxiliary winding: Feedback
To minimize disturbance on the signal for the FB pin, a separate auxiliary winding with a
maximum coupling to the secondary winding is used for feedback. The resistive divider
consists of resistors R3, R30, R31. Using two resistors in parallel enables the setting of an
accurate division factor. Capacitor C3 is added for spike suppression.
Remark: Capacitor C3 must not be too large, because it disturbs the waveform at the FB
pin and no accurate sampling of the voltage is possible. A value of 33 pF close to the pin
is a good value to use.
7.1.8 Secondary side
To improve efficiency, two Schottky diodes (D50 and D51) are used in parallel for
rectification on the secondary side,. Despite a 2 A rated output current, the peak current
can be higher than 9 A. The diodes must be capable to handle a current higher than 9 A.
From rating point of view one diode can handle the current, but in that case, check the
efficiency and the temperature of the diode. Capacitor C11 improves efficiency by starting
an immediate conduction at the start of the secondary stroke.
To avoid disturbance by switching spikes, connect the VCC and GND of the transient
controller TEA1705 as close as possible to the output. Capacitor C10 carries the charge
to generate the wake-up pulse. Resistor R10 limits the charge current to safe values. For
both components we applied 0603 parts successfully.
The output capacitors C51 and C52 manage the output ripple in burst mode at full load.
For the output ripple and load step behavior, use capacitors with low Equivalent Series
Resistance (ESR) like aluminum polymer electrolytic capacitors. Capacitor C53, a
ceramic capacitor of 22 F, is added for improved switching spike suppression.
Resistor R50 is the preload resistor. It serves two purposes:
• A small load on the secondary side ensures proper regulation of the output voltage at
a no-load condition.
• The preload resistor dissipates any excess of energy above the IC supply, base
current of the NPN switch, and the auxiliary divider generated in a no-load condition
by the fixed burst frequency and fixed Ipk. If excess energy is not dissipated, the
output voltage increases to the OVP level.
7.2 Layout considerations
A careful layout of the board is important to enable stable behavior under all conditions
and to meet the input/output, EMC, and thermal requirements. For the best result the
following items should be taken into account:
•
•
•
•
•
AN11401
Application note
Small power current loops to achieve a low radiated EMI level
Separation of large and small signal path
Secondary side routing to optimize ripple and noise
Routing input filter part
Thermal considerations
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Figure 47 to Figure 49 show the layout of the demo board. Figure 44 shows schematic
diagram.
a. Top
b. Bottom
Fig 47. Copper
a. Top
b. Bottom
Fig 48. Silk screen
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a. Top
b. Bottom
Fig 49. Demo board
7.2.1 Small power current loops to achieve a low radiated EMI level
To achieve a low radiated EMI level, the loop surface areas of the main power current
loops must be kept as small as possible during the primary and the secondary stroke. At
switch-off of the NPN and switch-on of the diodes D50 and D51 high dI/dt's are present at
the main current loops. Those dI/dt's induce Electromagnetic fields in these power current
loops. This can cause radiated EMI when the loop surface areas are too large.
During the primary stroke, the power current flows from the + terminal of capacitor C2
through the primary winding, the NPN, the IC internal emitter switch, and the current
sense resistors, back to the ground of capacitor C2 (the star ground). To keep the surface
area of this current loop small, place the peak-clamp outside the main current loop.
During the secondary stroke, the power current flows from the transformer winding (FL1)
through the output diodes (D50 and D51) to the output capacitors C51 and C52 and back
to the transformer winding (FL2).
Always keep the loop surface area of the peak-clamp as small as possible. The charge
current of peak clamp flows from the transformer collector connection (pin 6 of the
tranformer; see Figure 44 for the transformer pin arrangement) through the diode D8,
resistor R9 and capacitor C8 back to transformer bus voltage connection (pin 5 of the
transformer; see Figure 44 for the transformer pin arrangement).
7.2.2 Separation of large and small signal path
The ground connection of bulk electrolytic capacitor C2 acts as star ground. Here all
grounds (large signal, small signal) come together.
Connect all power grounds with a star grounding pattern to the ground connection of
capacitor C2.
Connect all small signal grounds with a star grounding pattern to the IC GND pins.
Connect the two IC GND pins together at the PCB with a PCB trace that is as short as
possible.
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The PCB trace between the IC GND pins and the ground connection of capacitor C2 must
be as short and as wide as possible.
At switch-off of the NPN a steeply increasing voltage with a high dV/dt is present at the
collector connection (pin 6 of the transformer; see Figure 44 for the transformer pin
arrangement) of the transformer. This dV/dt causes a capacitive current to flow from the
primary winding to the auxilliary winding or the shield in the transformer, connected to the
transformer auxilliary winding ground (pin 7 and 8 of the transformer; see Figure 44 for the
transformer pin arrangement). This current flows from the transformer winding ground to
the IC ground. From the IC ground it flows to the ground connection of the bulk electrolytic
capacitor C2, through the current sense resistors (R60 and R61) and the parasitic
capacitance of the NPN back to the transformer. This current may disturb the small signal
measurements of the IC. Use the IC ground as star ground for the small signals and the
parasitic current in the auxilliary winding ground.
Place resistors R3, R30, R31 and capacitor C3, connected to the IC FB pin, as close as
possible to the IC to avoid that power current loops, mains transients, and ESD events
disturb the FB pin.
At the secondary side, connect Y-cap C100 as close as possible to the USB-A metal
frame (S1 to S4). At the primary side, connect Y-cap C100 as close as possible to the
anodes of bridge rectifier diodes D101 and D102.
When using ground planes, in case of double layer board, connect them to the power or
small signal star ground at one point only.
7.2.3 Secondary side routing to optimize ripple and noise
To divide the current distribution through both diodes equally, design the layout as
symmetrical as possible, when using two diodes at the output.
To minimize the output ripple and noise, a proper PCB trace from the cathode of diodes
D50/D51 to the USB-A (J3) +5 V and from transformer ground (T1 FL2) to the USB-A (J3)
GND is required. Trace the PCB from the cathode of D50/D51 to the + connection of
capacitor C51 first, then to the + connection of capacitor C52, and finally to the USB +5 V.
Trace the transformer ground must to the ground connection of capacitor C51 first, then to
the ground connection of capacitor C52, and finally to the USB-A GND. Place capacitor
C53 as close as possible to the USB connector. Capacitor C11 is added to suppress
switching spikes. The position of preload resistor R50 is not critical.
7.2.4 Organizing the input part
The input part is organized so that interference from switching cannot reach the mains
connection without passing through the filter L1, L2 and C1. Create enough distance so
that crosstalk directly to the mains connections is avoided.
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7.2.5 Thermal considerations
Make sure that in this application the component temperatures do not exceed
requirements. Most critical components are the NPN, the output diodes and the NPN base
resistors. If the NPN case temperature is higher than the transformer core temperature,
the NPN can be glued to the transformer with thermal compound.
Because of the dissipation in the output diodes (D50, D51) and the base resistors (R70,
R71 and R72), place them at a copper area of sufficient size. In the demo board three
1206 base resistors are placed in parallel to keep the temperature of every single resistor
within the requirements. Provide as much copper area as possible at the diode
connections and base resistor connections for cooling. When using a double sided PCB,
put copper areas at both sides of the PCB, thermally connected using via's.
7.3 Transformer
A proper construction of the transformer is required for the primary sensing concept.
Topics are:
•
•
•
•
Lp and Ipk in relation to input voltage and power
For proper Vout sampling, the secondary stroke must be long enough
Transformer construction of windings
Safety
This chapter describes the basics, including the calculation of the main parameters which
can be used when dealing with a transformer manufacturer.
7.3.1 Calculating Lp and Ipk
Table 10 shows a calculation example for a 10 W application.
Only the main items, which determine the transformer are calculated, the primary
inductance Lp and the peak current Ipk at maximum output power.
Table 10.
Calculation Lp and Ipk
Definition
Values
Unit
Description
Values depending on design
VO
5.00
V (DC)
output voltage converter at maximum load (at PCB end)
Io(max)
2.20
A
maximum output current at border of CV/CC mode
Vth(hiccup)
2.70
V
output voltage in CC mode where the hiccup/safe restart is entered
VF(sec)
0.40
V
forward voltage secondary diode (Schottky)
Cmains
17.4
F
total bulk electrolytic capacitor value. Use approximately 2 F per Watt output
power (take into account the lower limit of the capacitor tolerance)
Vmains(min)
85
V (AC)
lowest specified mains input voltage for full performance
Vmains(max)
265
V (AC)
highest specified mains input voltage for full performance
fmains
60
Hz
frequency mains voltage at Vmains(min)
nVout_select
84
V
select the highest value for which tsec(min)  1.9 s

0.77
-
converter efficiency at maximum load (= border of CV/CC mode) and Vmains(min)
Calculation of minimum DC voltage at the bulk electrolytic capacitor
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Table 10.
Calculation Lp and Ipk …continued
Definition
Values
Unit
Description
Pin
14.29
W
Pin = VO * IO(max) / 
Vpk(elcap)
118.81
V
Vpk(elcap) = Vmains(min) * 2  2 * drop over mains rectifier diodes (0.7 V/diode)
Vmin(elcap)
67.56
V
Vmin(elcap) is where the dropping voltage of the electrolytic capacitor meets the
increasing mains voltage
kHz
data sheet value, maximum limit
Calculation Ipk(max) and Lp
fosc(high)
54
tdead(min)perc
0.02
tdead(min)
370
ns
tdead(min) = 1 / fsw * tdead(min)perc
1 / fsw = tprim + tsec + tdead(min); tdead(min) to ensure discontinuous operation
Ipk(max)
0.779
A
Ipk(max) = (2 * Pin * (Vmin(elcap) + nVout)) / ((Vmin(elcap) * nVout) * (1  tdead(min)perc))
Lp(max)
873
H
Lp = (1 / fosc(max) - tdead(min)) * 1 / (1 / Vmin(elcap) + 1 / nVout) * 1 / Ipk(max)
The calculation is done using an Excel spreadsheet. The used equations are explained in
the Description column of Table 10.
Remarks:
• The frequency, selected for the lowest mains, is 60 Hz. All 50 Hz mains have nominal
voltages of 220 V or higher. It is not realistic these drop to 85 V.
• The value of nVout (the output voltage multiplied by the ratio of the number of primary
windings and number of secondary windings) influences two design parameters:
– The peak voltage on the primary switch
– The secondary stroke time
The peak voltage on the primary switch when switched off can be cacluated with
Equation 19:
(19)
V pk  prim  = V elcap  max  + nV out + V pk  ringing 
Where:
• Vpk(prim) must remain below the maximum breakdown voltage of the switch
• Velcap(max) is reached for the maximum AC input voltage (264 V (AC)). It is
approximately 375 V (DC).
• Vpk(ringing) can go up to approximately 100 V.
Using nVout can keep Vpk(prim) at safe levels.
7.3.2 Secondary stroke time
This section describes the relation between nVout and the secondary stroke time.
The sampling time during the secondary stroke time and the secondary stroke time itself
are related to the output power. The sampling timing must fit within the secondary stroke
time.
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Figure 50 shows some basic signals. they help understand the relation between the
secondary stroke time and the transformer.
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Condition: discontinuous conduction mode.
Ipkp = primary peak current; Ipks = secondary peak current.
Remark: Secondary diode drop is neglected.
a. Schematic
b. Waveform
Fig 50. Calculating the secondary stroke time
During primary stroke time, the primary peak current increases linearly with a slope of the
DC voltage over the primary VDC divided by the inductance Lp.
The current on secondary side (Is) starts with the transformed current to the secondary
side: Ipk(prim) * n. It decreases linearly to zero with a slope proportional to the output
voltage Vout, and inversely proportional to Lp/n2.
From the equation for the secondary current we can derive an equation for the secondary
stroke time (ts).




 V out 
I s = n  I pkp –  -----------  t
  L p 
  ----2- 
 n 
(20)
The secondary stroke time (ts) is reached when Is becomes zero:
I pkp
t s = L p  ----------------------- n  V out 
(21)
For correct sampling the minimum secondary stroke time (ts(min) for Ipk = Ipk(min) is 1.9 s.
The ratio between Ipk(min) and Ipk(max) is approximately 4.9.
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When the calculated ts(min) is too short, the time can be increased by lowering nVout in the
calculation of Section 7.3.1 and recalculate Lp and Ipk.
7.3.3 Construction of windings
A suitable setup of the winding scheme as used in our demo board.
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The black dot shows the winding direction.
Fig 52. EVD15 construction and winding configuration
AN11401
Application note
Table 11.
Winding data
Layer
number
Color
Winding
Wires
Number of turns
parallel
Wire diameter
1
17
150 m
1
46 to 48
200 m
11
amber
aux winding
10
purple
isolation tape
9
blue
primary (sandwich)
8
purple
isolation tape
7
green
shield
6
purple
isolation tape
1
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Table 11.
Winding data …continued
Layer
number
Color
Winding
Wires
Number of turns
parallel
Wire diameter
5
yellow
secondary winding
3
2  350 m TIW
4
purple
isolation tape
3
red
FB winding
2
purple
isolation tape
1
blue
primary (sandwich)
6
1  300 m TIW
6
11
130 m
1
46 to 48
200 m
The primary inductance for a typical 10 W transformer is 880 H. The secondary winding
must be Triple Isolated Wire (TIW) to meet the safety standards.
7.3.4 Safety requirements
Because the output power is rather low, it is possible to use cores that are quite small for
the transformer (EEM12.4 for 5 W; EVD15 for 10 W). With these transformer sizes, make
sure that the safety requirements for mains isolation are met.
Using TIW for the secondary winding enables to keep the construction still small.
The pins of the bobbins for EE12.4 and EVD14 cores are often not spaced far enough
apart to fulfill the safety distance between hot and cold. The only solution is to use flying
leads to connect the secondary windings far enough from the primary pins at the bobbin.
However, flying leads are not convenient for production.
Some bobbin manufacturers can supply bobbins with the required safety distances.
These bobbins incorporate an extended secondary side footprint. They increase the
footprint but ensure easy production.
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8. Appendix
8.1 USB specification
The TEA172X is designed to fulfill the USB specification for chargers. Currently, USB 1.1
is used. However, USB 1.2 is advancing. The most important requirements are described
below.
8.1.1 USB 1.1
Figure 53 shows a graph of the static voltage versus current requirement for a USB 1.1
charger.
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The graph is valid for a quasi-stationary load without jitter and without spread.
(1) CVB; burst mode with energy saving; no-load = 10 mW to low load = 120 mW.
(2) CVC: 120 mW up to 2 W.
(3) CVF: 2 W up to 5 W.
(4) CP: 5 W with transition from CV to CC.
(5) CCF: 5 W down to 2.5 W.
(6) CCC: Constant voltage with burst mode. 2.5 W down to 1 W.
(7) Start-up and UVLO. No power conversion.
Fig 53. USB 1.1 static behavior and TEA172X operation modes
Figure 53 shows the voltage versus current for a 5 W USB charger using the TEA172X.
The USB 1.1 specification requires precise voltage regulation (5 V 5 % or
4.75 V to 5.25 V) and an output current up to 0.5 A. When higher than 0.5 A, the output
current must remain between 0.5 A and 1.5 A. The output voltage must remain < 5.25 V.
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If Vout drops to below 2 V, the power supply is allowed to shut down. It starts to "hiccup".
The power supply can also continue to deliver current for as long as the output current
remains < 1.5 A. The characteristic of most chargers is to keep the output voltage
between 4.75 V and 5.25 V until maximum output power is reached. When maximum
output power is reached, the chargers switch to current mode for charging.
The current mode has to work at least until an output voltage of 2 V is reached. When the
output voltage is < 2 V, behavior is not critical unless the output current increases to
exceed 1.5 A. For the USB 1.1 characteristic, the different operating modes of the
TEA172X are indicated.
Figure 54 shows the dynamic behavior requirements of USB 1.1 for a 5 W charger.
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(1) Load step 0 A  0.5 A. Requirements:
- Vout must remain > 4.1 V
- Vout average (over 1 s) must remain between 4.75 V and 5.25 V
No time limits for recovery.
(2) Load step Imax  0 A. Requirement:
- Vout must remain < 6 V
- Vout average (over 1 s) must remain between 4.75 V and 5.25 V
No time limit for recovery.
Fig 54. USB 1.1 dynamic behavior
For any load step between 0 A and 0.5 A, Vout must not drop to below 4.1 V. This
requirement is used to calculate the size of the output capacitors.
For any load step between Iout(max) and 0 A, the output voltage must not exceed 6 V. The
output voltage must remain between 4.75 V and 5.25 V when averaged over 1 s.
8.1.2 USB 1.2
Figure 55 shows the static behavior for USB 1.2, which is less demanding on a number of
aspects when compared to USB 1.1.
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The specification for the output voltage remains narrow until the output current reaches 0.5 A
(4.75 V to 5.25 V). No requirement for current limitation or minimal required Vout (VBUS).
(1) Charging port operation not allowed.
(2) Required operating range for Dedicated Charging Port (DCP).
(3) Valid load curve must cross both lines.
(4) Continuous current regulation allowed. Current limit trip operation allowed.
Fig 55. USB 1.2 static behavior
The USB 1.2 specification is identical to USB 1.1 up to an 0.5 A output current. At 0.5 A,
Vout must remain between 4.75 V and 5.25 V. When the output current exceeds 0.5 A,
there are no requirements except that the output voltage must remain < 5.25 V and the
output current must remain < 5 A.
At output currents < 1.5 A, the device must operate until the output voltage is 2 V. When
the output voltage is < 2 V or the output current is > 1.5 A, the device can shut down,
enter hiccup mode, or deliver any current < 5 A. In practice, most customers do not allow
currents in this mode above the nominal charge current to avoid excessive dissipation.
A major relaxation of USB 1.2 related to dynamic behavior are load steps. Load steps
have been divided into two ranges and three current levels. Table 12 shows an overview
of the load steps.
Table 12.
Load steps
IDCP
Min
Max
Unit
low
0
0.03
A
mid
0.03
0.1
A
high
0.5
-
A
Load steps are divided into the three Dedicated Charging Port (DCP) current ranges:
• IDCP low to IDCP mid
• IDCP mid to IDCP high
• IDCP low to IDCP high
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The additional IDCP mid level allows a relaxation of the undershoot requirements for
primary sensed chargers with low standby power, provided the USB device is designed
for USB 1.2. Figure 56 shows the requirements for undershoot during current steps from
low to mid and mid to high.
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Fig 56. USB dynamic undershoot 1
For load steps from IDCP low to IDCP mid (0 A to 0.03 A and up to 0.10 A) and from IDCP
mid to IDCP high (0.03 A to 0.10 A and up to 0.5 A), the following requirements apply:
• Vout must remain > 4.1 V
• The duration of the undershoot at Vout < 4.75 V must be < 10 ms
• The minimum time between load step 0 A to 0.03 A and up to 0.10 A and load step
0.03 A to 0.10 A and up to 0.5 A is 20 ms.
Figure 57 shows the requirements for undershoot during current steps from low to high.
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Fig 57. USB dynamic undershoot 2
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For any load step between IDCP low to IDCP high (0 A to 0.03 A and up to 0.5 A) the
following requirements apply:
• Vout can drop to the battery voltage of the attached Portable Device (PD)
• The undershoot (Vout < 4.75 V) must be < 10 ms
Figure 58 shows the requirement for load steps from high to low. They are the same
requirements as for USB 1.1.
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(1) Load step 1 A to 0 A (or any other load step down). Requirement, Vout must not exceed 6 V.
Fig 58. USB 1.2 dynamic overshoot
In general, the output voltage must not exceed 6 V for any load step during switch-on or
during switch-off.
9. Abbreviations
Table 13.
AN11401
Application note
Abbreviations
Acronym
Description
USB
Universal Serial Bus
IC
Integrated circuit
BJT
Bipolar Junction Transistor
SMPS
Switched Mode Power Supply
EMI
ElectroMagnetic Interference
OVP
OverVoltage Protection
UVLO
UnderVoltage LockOut
OTP
OverTemperature Protection
PCB
Printed-Circuit Board
TIW
Triple Insulated Wire
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10. Legal information
10.1 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
10.2 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Evaluation products — This product is provided on an “as is” and “with all
faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates
and their suppliers expressly disclaim all warranties, whether express, implied
or statutory, including but not limited to the implied warranties of
non-infringement, merchantability and fitness for a particular purpose. The
entire risk as to the quality, or arising out of the use or performance, of this
product remains with customer.
In no event shall NXP Semiconductors, its affiliates or their suppliers be liable
to customer for any special, indirect, consequential, punitive or incidental
damages (including without limitation damages for loss of business, business
interruption, loss of use, loss of data or information, and the like) arising out
the use of or inability to use the product, whether or not based on tort
(including negligence), strict liability, breach of contract, breach of warranty or
any other theory, even if advised of the possibility of such damages.
Notwithstanding any damages that customer might incur for any reason
whatsoever (including without limitation, all damages referenced above and
all direct or general damages), the entire liability of NXP Semiconductors, its
affiliates and their suppliers and customer’s exclusive remedy for all of the
foregoing shall be limited to actual damages incurred by customer based on
reasonable reliance up to the greater of the amount actually paid by customer
for the product or five dollars (US$5.00). The foregoing limitations, exclusions
and disclaimers shall apply to the maximum extent permitted by applicable
law, even if any remedy fails of its essential purpose.
Safety of high-voltage evaluation products — The non-insulated high
voltages that are present when operating this product, constitute a risk of
electric shock, personal injury, death and/or ignition of fire. This product is
intended for evaluation purposes only. It shall be operated in a designated
test area by personnel that is qualified according to local requirements and
labor laws to work with non-insulated mains voltages and high-voltage
circuits.
The product does not comply with IEC 60950 based national or regional
safety standards. NXP Semiconductors does not accept any liability for
damages incurred due to inappropriate use of this product or related to
non-insulated high voltages. Any use of this product is at customer’s own risk
and liability. The customer shall fully indemnify and hold harmless NXP
Semiconductors from any liability, damages and claims resulting from the use
of the product.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
10.3 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
GreenChip — is a trademark of NXP B.V.
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11. Contents
1
2
3
3.1
3.1.1
3.1.2
3.1.3
3.2
3.2.1
3.2.2
3.3
4
5
5.1
5.2
6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.4.1
6.3.4.2
6.3.5
6.3.5.1
6.3.5.2
6.3.5.3
6.3.5.4
6.4
6.5
6.5.1
6.5.2
6.5.3
6.5.3.1
6.5.3.2
6.5.3.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
TEA1720/TEA1705 low-power adapter. . . . . . . 4
Key features TEA1720 . . . . . . . . . . . . . . . . . . . 4
Power features . . . . . . . . . . . . . . . . . . . . . . . . . 4
Green features . . . . . . . . . . . . . . . . . . . . . . . . . 4
Protection features . . . . . . . . . . . . . . . . . . . . . . 4
Key features TEA1705 . . . . . . . . . . . . . . . . . . . 5
Power features . . . . . . . . . . . . . . . . . . . . . . . . . 5
Protection features . . . . . . . . . . . . . . . . . . . . . . 5
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Basic application schematic. . . . . . . . . . . . . . . 6
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TEA1720. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TEA1705. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
System description . . . . . . . . . . . . . . . . . . . . . . 9
Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Operating modes . . . . . . . . . . . . . . . . . . . . . . 11
Burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CVC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CVF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Constant Power (CP) mode . . . . . . . . . . . . . . 16
CCF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Overview control modes . . . . . . . . . . . . . . . . . 18
Emitter drive NPN switch . . . . . . . . . . . . . . . . 18
Emitter drive switch-on . . . . . . . . . . . . . . . . . . 19
Emitter drive switch-off . . . . . . . . . . . . . . . . . . 19
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Built-in compensations for emitter drive . . . . . 21
DC offset compensation . . . . . . . . . . . . . . . . . 22
Vin compensation . . . . . . . . . . . . . . . . . . . . . . 22
Base drive dimensioning . . . . . . . . . . . . . . . . 23
Initial base drive dimensioning
- the base resistor . . . . . . . . . . . . . . . . . . . . . . 24
Initial base drive dimensioning;
the base capacitor . . . . . . . . . . . . . . . . . . . . . 25
Base drive dimensioning optimization . . . . . . 26
Verification of RBASE at low temperatures. . . . 28
Total input power at no-load . . . . . . . . . . . . . . 32
Value output capacitor, ripple, load step,
transient controller . . . . . . . . . . . . . . . . . . . . . 33
Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Load step without transient control . . . . . . . . . 34
Transient controller (TEA1705). . . . . . . . . . . . 35
Circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . 36
Transient controller mechanism . . . . . . . . . . . 37
TEA1705 generation wake-up pulse . . . . . . . 38
6.5.3.4
6.5.3.5
6.5.3.6
6.5.3.7
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.12.1
6.12.2
6.12.3
6.12.4
6.12.5
6.12.6
6.12.7
6.12.8
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.3
7.3.1
7.3.2
7.3.3
7.3.4
8
8.1
8.1.1
TEA1720 transient detector . . . . . . . . . . . . . .
TEA1705 charging CCAP . . . . . . . . . . . . . . . .
TEA1720 switching detector and wake-up
pulse disable timer . . . . . . . . . . . . . . . . . . . . .
TEA1705 no-load Vout protection . . . . . . . . . .
Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Demagnetization protection . . . . . . . . . . . . . .
Supply from auxiliary winding . . . . . . . . . . . .
Load line compensation . . . . . . . . . . . . . . . . .
Cable compensation . . . . . . . . . . . . . . . . . . .
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protective features . . . . . . . . . . . . . . . . . . . . .
Undervoltage protection on the VCC pin . . . .
Overvoltage protection on Vout . . . . . . . . . . . .
Overtemperature protection . . . . . . . . . . . . . .
Demagnetization protection . . . . . . . . . . . . . .
Open/short protection on the FB pin . . . . . . .
Hiccup mode for overload/short circuit
protection of the output . . . . . . . . . . . . . . . . .
Short circuit protection on the SENSE pin . . .
Protection overview table . . . . . . . . . . . . . . . .
Application. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application diagram . . . . . . . . . . . . . . . . . . . .
Input part and EMI filter . . . . . . . . . . . . . . . . .
Connecting pin HV to the bus voltage . . . . . .
Clamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sense resistor . . . . . . . . . . . . . . . . . . . . . . . .
Auxiliary winding: Supply . . . . . . . . . . . . . . . .
Base drive NPN . . . . . . . . . . . . . . . . . . . . . . .
Auxiliary winding: Feedback . . . . . . . . . . . . .
Secondary side . . . . . . . . . . . . . . . . . . . . . . .
Layout considerations . . . . . . . . . . . . . . . . . .
Small power current loops to achieve a low
radiated EMI level . . . . . . . . . . . . . . . . . . . . .
Separation of large and small signal path . . .
Secondary side routing to optimize ripple
and noise . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Organizing the input part . . . . . . . . . . . . . . . .
Thermal considerations . . . . . . . . . . . . . . . . .
Transformer . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculating Lp and Ipk . . . . . . . . . . . . . . . . . . .
Secondary stroke time . . . . . . . . . . . . . . . . . .
Construction of windings . . . . . . . . . . . . . . . .
Safety requirements . . . . . . . . . . . . . . . . . . . .
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB specification. . . . . . . . . . . . . . . . . . . . . .
USB 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
39
40
40
41
43
43
45
45
46
47
47
47
48
48
48
48
50
52
52
53
54
54
54
56
57
57
58
58
58
60
60
61
61
62
62
62
63
65
66
67
67
67
continued >>
AN11401
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 December 2013
© NXP B.V. 2013. All rights reserved.
73 of 74
AN11401
NXP Semiconductors
TEA1720/TEA1705 5 W to 12.5 W power supply/USB charger
8.1.2
9
10
10.1
10.2
10.3
11
USB 1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .
Legal information. . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
71
72
72
72
72
73
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 5 December 2013
Document identifier: AN11401
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