Application Notes

AN10954
GreenChip SR TEA1795T dual synchronous rectification
driver IC
Rev. 1 — 14 December 2010
Application note
Document information
Info
Content
Keywords
TEA1795T, MOSFET, driver IC, synchronous, rectifier, resonant,
converter
Abstract
The TEA1795T is a dual synchronous rectifier driver IC for a resonant
converter, which can be used to control the gates of two separated
MOSFETs configured as diodes on the secondary side of a resonant
converter.
AN10954
NXP Semiconductors
GreenChip SR TEA1795T dual synchronous rectification driver IC
Revision history
Rev
Date
Description
v.1
20101214
First issue
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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1. Introduction
The TEA1795T is a dual synchronous rectifier driver IC for a resonant converter. Using
this IC the gates of two separated MOSFETs, configured as diodes on the secondary side
of a resonant converter, can be controlled. Figure 1 shows the basic configuration of a
resonant converter with two SR MOSFETs on the secondary side. The MOSFETs are
placed in the ground path of the circuit, making the supply of the driver IC easier.
Q1
MOSFET Cr
Vin
Q2
MOSFET
TR1
resonant
transformer
1
3
2
4
Cout
5
6
IC1
1/2 TEA1795
Q3
SR_MOSFET
IC1
1/2 TEA1795
Q4
SR_MOSFET
019aaa448
Fig 1.
Basic schematic of a resonant converter
2. Quick start-up
This section describes how to start the device quickly. The IC is suitable in a resonant
converter and can drive two SR MOSFETs on secondary side (see Figure 1). The
MOSFETs have to be placed with their source at ground level. The IC can drive two
MOSFETS independently because there are two drivers in the package.
The drain-source voltage (VDS) is measured separately for each driver to determine what
the status of the MOSFET should be (on or off). When a negative current is flowing
through the MOSFET or, in other words, the anti-parallel diode is conducting, the
MOSFET is turned on. The negative current is detected by a voltage drop over the
MOSFET of at least 0.6 V. A comparator with a threshold level of 220 mV becomes
HIGH and causes the MOSFET to turn on.
A timer is triggered, which stops the output from changing for a period of 520 ns in order
to prevent any form of oscillation. After the blanking time the MOSFET can either be
turned off or stay turned on, depending on the value of VDS.
The drain-source voltage must be higher than 12 mV for the MOSFET to turn off. After
the MOSFET has been turned off a second timer is triggered and the MOSFET status
does not change for a period of 400 ns. Then the MOSFET can be turned on again.
In addition to the levels of 12 mV and 220 mV, a third level is used which regulates the
drain-source voltage to 25 mV. This third level is active when VDS is between 25 mV
and 12 mV. It was added to speed up the turn-off of the MOSFET (see Section 7.1.1).
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Figure 2 shows the pinning diagram of the TEA1795T. The DSA and SSA pins or the DSB
and SSB pins must be connected to the drain and the source of the MOSFET to measure
the drain-source voltage. The SSA and SSB pins must be connected as close as possible
to the source pins. The DSA and DSB pins must be connected as close as possible to the
drain pins. This prevents wrong measurement values being obtained because of the
voltage drop over the tracks and the layout of the Printed-Circuit Board (PCB). The
outputs of the drivers are pins GDA and GDB, which have to be connected to the gates of
the MOSFETs.
The supply pin of the IC is VCC. It can be connected to an output voltage of the resonant
converter because of its wide supply voltage range (8.5 V to 38 V).
SSA
1
GND
2
8
SSB
7
VCC
TEA1795T
GDA
3
6
GDB
DSA
4
5
DSB
014aaa976
Fig 2.
Pinning diagram
Table 1.
Pin descriptions
Symbol
Pin
Description
SSA
1
source sense input MOSFET A
GND
2
ground
GDA
3
gate driver output MOSFET A
DSA
4
drain sense input for synchronous timing MOSFET A
DSB
5
drain sense input for synchronous timing MOSFET B
GDB
6
gate driver output MOSFET B
VCC
7
supply voltage
SSB
8
source sense input MOSFET B
Careful attention must be paid to the layout of the PCB to get the best possible results.
Tracks from drain to DSA (or DSB) and from source to SSA (or SSB) form a loop which
must be as short as possible. This can be achieved by routing them as closely as possible
and parallel to each other. Alternatively, they can be put above each other in a dual-layer
PCB (see Figure 23). A filter can be added to the system to improve the design,
depending on the MOSFET used and the mode of operation (CCM or DCM)
(see Section 7.1.2 and Section 7.2.1).
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3. Resonant converter versus flyback
The TEA1795T has been developed for a resonant converter supply. It is derived from the
TEA1761, a MOSFET driver IC for flyback SR. The main difference is the blanking time
after turn-on.
The differences between a resonant converter supply and a flyback supply are:
• The secondary current does not have to start at the beginning of a primary switching
transition
• The current increases and decreases (sinusoidally)
• The switching frequency can be much higher
• The dI/dt of the current is much higher
In a flyback converter the secondary phase starts when the current through the switch
(diode, MOSFET) is at its maximum. This is not the case in a resonant converter, where
the current starts at 0 A and rises until it has reached its maximum. Then it decreases
again. The overall shape of the current is more or less sinusoidal (see Figure 3).
start secondary current coincide with a primary switching transition
flyback
timing primary MOSFET
start with maximum current
secondary current
DI/dt
resonant
timing primary MOSFETS
secondary current
t
start at zero current
DI/dt
primary switching transitions
start secondary current doesn't have to coincide with a primary switching transition
Fig 3.
019aaa729
The difference between the secondary current in a flyback and a resonant converter
The current does not have to start at the beginning of a primary switching transition. This
makes the timing more vulnerable to incorrect sensing, causing the SR-MOSFET to
switch at the wrong moment.
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4. Diodes as rectifiers
In older designs, Schottky diodes were used to rectify the current on the secondary side.
The advantages of Schottky diodes compared to PN-diodes are:
• Lower voltage drop
• Less reverse recovery
The Schottky diodes also have a few disadvantages:
• Higher parasitic capacitance
• Reverse leakage current
• Not available for higher output voltages
Two modes can be distinguished in a resonant converter:
• Continuous Conduction Mode (CCM)
• Discontinuous Conduction Mode (DCM)
For DCM the secondary current can be modeled using Equation 1:
k + 1  
k
I sec = I amp  sin   1   t – t no    ------------  t  --------------------------  k  N
1
1
I sec
k + 1  
k + 1  
= 0  --------------------------  t  -------------------------- + t no
1
1
(1)
Where:
•
•
•
•
AN10954
Application note
Iamp is amplitude of the current
1 is the radial frequency
Isec is the secondary current
tno is the time that the secondary current is zero (see Figure 4)
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50
Isec
(A)
40
Tpr / 2
Tpr / 2
30
tno
tno
20
10
0
2 × 10−6
0
4 × 10−6
6 × 10−6
π
+t
ω1 no
Fig 4.
8 × 10−6
1 × 10−5
t (s)
×2
019aaa449
Approximation of the secondary current of the resonant converter in DCM
For Iamp Equation 2 and Equation 3 can also be written:
t pr
-----2
1
P O = V O  ------------------- 
t pr
------ + t no
2
 Iamp  sin   1  t 
0
(2)
1
2
= ---  V O  I amp  ------------------------t no

1 + 2  -----t pr
or
t no
 PO
I amp =  1 + 2  ------  ---  ------t pr
2 VO
(3)
Where:
• tpr = 2   / 1
• PO is the output power
• VO is the output voltage
The voltage drop of a Schottky diode can be calculated with Equation 4:
V f  I d  = V f0 + R d  I d
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(4)
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GreenChip SR TEA1795T dual synchronous rectification driver IC
Finally, the total dissipation in the secondary rectifiers taking the current as shown in
Figure 4 can be calculated with Equation 5:
2
1
1
2
P tot =  ---  V F  I amp + ---  R d  I amp   ------------------------

2
t no
1 + 2  -----t pr
(5)
By replacing Iamp with Equation 3 the power dissipation changes to Equation 6:
2
PO 2
t no 
pO

P tot =  V F  ------- + -----  R d  --------2-   1 + 2  ------ 

VO 8
t pr 

VO
(6)
Equations for the CCM case can be created as equivalents of the DCM case equations. In
Section 11.2 the CCM case is presented in detail. Here only the results are shown.
Example:
•
•
•
•
•
•
tno = 500 ns
ttill0 = 500 ns
PO = 240 W
VO = 12 V
Rd = 5 m
VF = 280 mV
For CCM the dissipation in the diodes equals: 7.925 W. For DCM the dissipation equals:
8.314 W.
5. MOSFETs as rectifiers
Ideally if the diodes are replaced by SR-MOSFETs the dissipation in the DCM case is
reduced to:
2
2
t no
PO

1
1
2
P tot = ---  R DSon  I amp  ------------------------- = -----  R DSon  --------2-   1 + 2  ------

8
t pr 
2
t no
VO
1 + 2  -----t pr
(7)
Example for DCM mode:
•
•
•
•
•
•
•
AN10954
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VF = 280 mV
Rd = 5 m
PO = 240 W
tno = 500 ns
tpr = 10 s (keeping in mind that tpr is not the period time but tpr + 2  tno is)
VO = 12 V
RDSon = 4 m
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With Schottky diodes, the dissipation will be 8.314 W and with MOSFETS 2.171 W.
Compared to the 240 W output power this is an improvement of approximately 2.6 %
(going from 3.5 % to 0.91 %). For CCM mode with ttill0 = 500 ns and tsw = 10 s, the
values are respectively 7.925 W (3.3 %) and 1.86 W (0.78 %). This is an improvement of
2.5 %.
Remark: An additional control IC is needed to turn on and turn off the MOSFET at the
right time (see Section 6).
Remark: When the MOSFET is not conducting, it behaves like a diode, so losses are
higher (see Equation 28).
6. Basic functionality of the TEA1795T
When using MOSFETs instead of diodes, the MOSFET has to be turned on when current
is flowing through it. It has to be turned off when there is no current flowing through it. The
TEA1795T IC has been developed to realize these functions. Section 6.1 describes the
turn-on function. Section 6.2 describes the turn-off function.
6.1 The turn-on function
It is easy to detect if current is flowing through the MOSFET. A MOSFET that is not
conducting (turned on) behaves like a diode. When current is flowing through the diode
the voltage drop is above 0.5 V. A level of 220 mV has been built in in the IC to which this
voltage can be compared. When this level is exceeded the TEA1795 charges the gate of
the MOSFET and turns it on. Depending on the current flowing through the diode, the
voltage drops to V DS = I DS  R DSon .
6.2 The turn-off function
A second level has been built in to turn the MOSFET off again. When the drain-source
voltage drop is less than 12 mV, meaning that the current through the MOSFET is below a
certain level (see Equation 8, the MOSFET is turned off again.
12 mV
I DS_off  ---------------R DSon
(8)
Example: if the current is behaving as described in Equation 2 and RDSon = 4 m, then
IDS_off = 3 A.
Summary: The MOSFET is turned on at VDS < 220 mV. The MOSFET is turned off at
VDS > 12 mV.
The pin connections are shown in Figure 2. The voltage drop over the MOSFET is
measured differentially (driver A: DSA (pin 4)  SSA (pin 1); driver B
DSB (pin 5)  SSB (pin 8)). The outputs of the drivers are GDA for driver A and GDB for
driver B. Finally, two pins are left, the GND (pin 2) and the positive connection of the
power supply (VCC, pin 7). In Table 1 the pinning information is listed.
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7. Improving the system
The following improvements have to do with the turn-on and turn-off moments of the
MOSFETs:
• Turn-on:
– Immediate turn-off after turn-on
– false turn-on
– parasitic turn-on
• Turn-off:
– premature turn-off
– turn-off is too late
– false turn-off
7.1 Turn-on
7.1.1 Immediate turn-off after turn-on
A blanking time has been built in to prevent the MOSFET from turning off immediately
after it has been turned on, because the drain-source voltage is still above the turn-off
level (12 mV). This blanking time is typically 520 ns. If, after 520 ns the value is above
the regulation level (25 mV) or the turn-off level, the gate is discharged until the
regulation level is reached or the MOSFET is turned off.
The disadvantage of the blanking time feature is that if the current becomes zero during
this blanking time it reverses and causes additional losses. If, after the blanking time, the
drain-source voltage is still below the regulation level, the gate voltage is lowered until the
drain-source voltage equals regulation level.
The regulation level mentioned above is added to the IC. When the input voltage is higher
than this regulation level but lower than the turn-off level the IC regulates the drain-source
voltage to 25 mV by controlling the gate voltage of the MOSFET. The MOSFET is
normally used in its linear region, but by lowering the gate voltage to just above the
threshold level the MOSFET enters its saturation region. This prevents the MOSFET
turning off too late when the turn-off level is reached. To turn off the MOSFET, the gate
voltage only needs to decrease slightly, instead of requiring a discharge from a high gate
voltage to the threshold voltage. Figure 5 shows the decision levels of the TEA1795T.
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0
VDS
(mV)
−12
−25
regulation region
IDS
VDS
(mV)
−25
turn-off level
regulation level
−220
turn-on level
−600
diode forward voltage
−12
IDS × RDSon
019aaa452
019aaa509
a. turn-off, regulation and turn-on levels[1]
b. Drain-source voltage[2]
VDS > −220 mV
off mode 2
t
blanking time (400 ns)
VDS < −220 mV
000
001
on mode
blanking time (520 ns)
blanking time over
off mode 1
101
blanking time over
VDS > −12 mV
VDS > −12 mV
regulation mode
charge gate
−25 mV < VDS < −12 mV
011
010
VDS < −25 mV
VDS < −25 mV
regulation mode
discharge gate
−25 mV < VDS < −12 mV
019aaa510
c. TEA1795T state diagram[3]
(1) Three levels are built in: turn-on level (220 mV), turn-off level (12 mV) and regulation level (25 mV).
(2) If the drain-source voltage is lower than 25 mV the gate is totally charged (Linear mode). As soon as the drain-source voltage
increases to above 25 mV the gate is discharged until the drain-source voltage is 25 mV again (Saturation mode). Above 12
mV the gate is fully discharged (off mode)
(3) 000, 001, 010, 011, and 101 are the five states.
Fig 5.
The decision matrix of the TEA1795
The regulation level means that between this level (25 mV) and the turn-off level
(12 mV) the IC stabilizes VDS to 25 mV by charging or discharging the gate. When the
current becomes too low to keep VDS at 25 mV the drain voltage exceeds 12 mV and
the MOSFET is turned off very quickly. If current is still present, the MOSFET behaves like
a diode again and the voltage decreases to below 0.5 V.
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7.1.2 False turn-on
Ideally, the MOSFET is turned on and off at the zero crossing of the current. However,
some parasitic components have a negative impact on the behavior of the synchronous
rectifier. The secondary inductance and the drain-source capacitance form a resonant
network which causes some oscillation of the drain-source voltage during the switching of
one of the MOSFETs (primary or secondary). Figure 6 shows the schematic.
TR1
1
3
2
4
5
1
TR2
Lpar
8
4
Lpar2
Cout
5
Vout
6
Q1
CDS1
Q2
CDS2
019aaa453
Fig 6.
Parasitic components causing oscillation
Figure 7 shows examples of oscillations. When the voltage of the drain-source decreases
below 220 mV false triggering of the MOSFET occurs, causing unstable behavior.
(2)
(1)
(3)
(4)
oscillation by zero
crossing secondary
current
half bridge switching
oscillation by half
bridge switching
019aaa730
(1) Half-bridge point
(2) VDS of one of the SR MOSFETs
(3) Secundary current
(4) Primary current
Fig 7.
Example of oscillation
An RC-filter is placed in front of the input of the driver IC to filter out the high frequency
component in the drain-source voltage (see Figure 11). This prevents false triggering of
the MOSFET.
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The voltage difference between pin 1 and pin 4 (and also between pin 5 and pin 8) for a
step from VI to 0 V can be calculated with Equation 9:
t
V C1  t  = V I  exp  – -------------
 R  C
(9)
Where:
• VC1 (t) = 0.1 VI (= 10 % of the end value)
• t = 100 ns
• R = 3.9 k
The result is a capacitor value (C) of 10 pF.
7.1.3 Parasitic turn-on
When the drain-source voltage (Figure 8, line 3) rapidly increases, the gate voltage
(Figure 8, line 1) is lifted to the threshold level of the MOSFET, causing it to turn on. This is
caused by the weak sinking capability of the driver output during the transition from
Regulation mode to the Off mode of the IC (see Figure 5). During the regulation mode the
sinking capability is taken care by a 24  MOSFET. The 1  MOSFET is only available in
the off-mode. It takes time to turn on this 1  MOSFET, because of the internal delay.
When this MOSFET is conducting, the gate of the SR MOSFET is discharged again.
Therefore a spike is visible on the gate during the transition.
Iprim
(2)
VGS
(1)
(1)
identical
VDS
(3)
019aaa885
The gate voltage of one of the SR MOSFETs (left). It shows a small pulse after the MOSFET is turned off. The small pulse is
caused by fast rising of the drain-source voltage (right).
(1) Gate source voltage.
(2) Primary current.
(3) Drain-source voltage over the primary MOSFET.
Fig 8.
Parasitic turn-on
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7.2 Turn-off
7.2.1 Premature turn-off
The drain-source voltage is measured between two points of the PCB. The impedance
between these points incorporates the resistance of the track, the MOSFET and
inductance Lpar. Lpar2 is also part of the parasitic inductance, but it does not have any
impact on the measurement (see Figure 9).
1 TR1 3
2
4
5
CO1
6
Lpar2
VO
Lpar
+
RDS0n + Rtrack
VDS_sense
−
Lpar
Lpar2
019aaa886
Fig 9.
Parasitic inductance
Equation 10 calculates the voltage over the inductance:
V L  t  = L par 
dI ds
dt
(10)
If the secondary current can be modeled using Equation 11:
I DS  t  = I amp  sin   1  t 
(11)
Then the induced voltage equals:
V L  t  = L par 
d
I
 sin   1  t  
d t amp
(12)
Combined with the resistance between the measuring points the voltage drop equals:
V DS  t  = I amp  L par   1  cos   1  t  + R DSon  I amp  sin   1  t 
2
2
2
= I amp   L par   1 + R DSon   cos   1  t –  
(13)
R DSon
 = atan  -----------------------
 L par   1
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Figure 10 shows an example, where:
• Lpar = 10 nH
• RDSon = 4 m
• IDS(t) = 34.558  sin(1  t)
V
VDS
0.2
RDSon × IDS
0
2 × 10−6
0
t
4 × 10−6
019aaa454
Fig 10. Example of phase shift caused by parasitic inductance of 10 nH. RDSon = 4 m;
fs = 100 kHz (= 2   / 1 + 2  tno); IDS = 34.558 sin(1  t)
The time (t1) of the early turn-off of the MOSFET can be calculated with Equation 14:
t pr
V th



------ – t 1 = acos   ------------------------------------------------------------------------ + 
2
2
2
2
I

amp  L par   1 + R DSon
(14)
In this case it is approximately 1.627 s, giving an additional loss of
3.686 W  2.171 W = 1.515 W. The result of this inductance is that the losses are almost
doubled. Therefore a solution to decrease these losses is required. One solution is to use
an RC filter as a compensation network (see Figure 11).
Isec
TR1
1
3
2
4
5
6
R1
DSA
D1
C1
SSA
R3
7
1
2
3
GND
IRC
IDS
VCC
4
R2
DSB
MOSFET
GDA
Q1
C3
IC1-1
TEA1795
C2
SSB
5
6
8
GDB
Q2
IC1-2
TEA1795
RC-filter
two different clamping network
019aaa455
Fig 11. RC-filter as compensation network
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The associated equations are:
I sec  s  = I DS  s  + I RC  s 
R 1  I RC + V C1 = L par 
I RC = C 1 
dI ds
+ R DSon  I DS
dt
(15)
dV C1
dt
The solution for this system in the time domain is given in Section 11. In the s-domain the
system can be written as:
I sec  s  = I DS  s  + I RC  s   I DS  s 
I sec  s   I DS  s 
1 
 R + --------------  I RC =  s  L par  R DSon + 1   I DS 
 1 C 1  s
V C1
par  s
L
------------------ + 1
 R DSon

(16)
= -----------------------------------------  R DSon  I DS
 R1  C1  s + 1 
I RC
V C1 = --------------C1  s
If:
L par
-------------= R1  C1
R DSon
(17)
the last part of Equation 16 changes to:
V C1 = R DSon  I DS
(18)
Example:
• Lpar = 10 nH
• RDSon = 4 m
• R1 = 3.9 k
Results in: C1 = 641 pF.
Figure 12 shows the result of the compensation. Ideally, the capacitor voltage follows the
drain-source voltage very accurately. In reality, however, this is very often not the case.
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V
(2)
VDS
0.2
RDSon × IDS
(1)
(3)
VC1
(= VDS compensation)
0
0
2 × 10−6
t
4 × 10−6
019aaa456
(1) The ideal voltage drop over the MOSFET.
(2) The voltage drop over the MOSFET including the inductance.
(3) The compensated voltage.
Fig 12. Compensation of the voltage drop over the MOSFET
When one of the secondary MOSFET is conducting, the other MOSFET has a voltage
drop of approximately twice the output voltage. The compensation capacitor C1 is also
charged to this voltage. When the voltage drops to below zero because the voltage over
the transformer reverses, the capacitor is also discharged to 220 mV. If the built-in diode
of the MOSFET conducts this is approximately 0.6 V. Figure 13 shows the voltage of the
capacitor as a function of time. It takes 10.3 s to discharge the capacitor.
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20
V
10
VC1
0
0
5 × 10−6
1 × 10−5
t
019aaa457
a. The discharge time of the compensation capacitor equals 10.3 s. This time can also be
calculated with Equation 9 (R1 = 3.9 k; C1 = 641 pF; VC1 = 0.2 V, Vin = 24 V).
0
VC1
V
−0.5
0
1 × 10−6
t
019aaa511
b. The capacitor voltage is clamped down to 0 V:
The discharge time compensation capacitor equals 1.02 s
Fig 13. The discharge time of the compensation capacitor from 24 V to 0.22 V when the
MOSFET is turned on
Without further adaptations this compensation circuit does not work. The first one is to
clamp the voltage to 0 V (MOSFET) or 250 mV (RF Schottky diode). This reduces the
discharge time (from 0 V to 220 mV) to 1.02 s. The second one to compromise
between the delay caused by capacitor C1 and to what extent the induction (Lpar) is
compensated, expressed by the function "Early" (see Figure 14). A larger compensation
capacitor results in a larger turn-on delay, which again results in a better compensation.
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turn-off level reached
turn-on level reached
IDS
−0.22
VC1
V
0
2 × 10−6
0
4 × 10−6
t
t_till0 = early (C1)
C1 = 100 pF
t_delay = delay (C1)
C1 = 100 pF
019aaa458
a. Presentation of tdelay and ttill0-labels in diagram
(1)
s
tdelay
510 × 10−9
(2)
ttill0
0
0
322
C1
pF
019aaa512
b. Minimal dissipation when tdelay = ttill0
Fig 14. The compromise between delay in turn-on time (tdelay) and premature turn-off
time (ttill0)
The calculation of the function ttill0 = Early(C1) is explained in Section 11. Here only the
result for an amplitude of a current of 34.6 A and a parasitic inductance of 10 nH is given.
Figure 15 shows how the total dissipation (Ptot) depends on the C1 value of 322 pF. The
minimum dissipation approximately coincides with a C1 value of 322 pF, where tdelay = ttill0
is valid (see Figure 14). The delay time and the early time are around 510 ns.
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3
(1)
P
(W)
Ptot (C1)
(2)
PMOSFET (C1)
(3)
Pdiode (C1)
2
1
5 × 10−10
0
C1
F
minimum dissipation for C1 is 322 pF
019aaa459
The dissipation can be divided in the diode phase (MOSFET off) and the RDSon phase
(MOSFET on). The chosen value is not exactly the minimum dissipation because of the different
derivatives of the delay function and the early function. (see Figure 14).
Fig 15. The total dissipation in the MOSFETs as a function of the capacitor value (line 1)
In Figure 15 the minimum dissipation does not coincide with the chosen value. This is
caused by different values with which the delay function increases and the early function
decreases.
The dissipation is increased from 2.171 W (optimal switching) to 2.751 W (with
compensation R1 = 3.9 k, and C1 = 322 pF). These values are calculated without taking
into account the delay in the IC and with a MOSFET used to clamp the filter capacitor
voltage to 0 V. If instead of a MOSFET a diode is used, the voltage is clamped to 250 mV.
The new optimal value of C1 changes to 247.14 pF; tdelay = ttill0 = 726.5 ns);
Ptot = 3.316 W.
R1 is dimensioned as R1 = 3.9 k because the maximum current coming out of the DSA
and DSB pins is 1 A, giving a voltage drop of approximately 4 mV. In the worst case the
turn-off threshold level is lowered to 8 mV instead of 12 mV.
The dissipation in the resistor cannot be ignored, because of the relatively low value of R1
(3.9 k). E.g., when the output voltage is 12 V one of the two resistors will always have a
24 V voltage drop, while the other resistor is at approximately ground level. 24 V means a
dissipation of around 150 mW. This can be a problem for very low load specifications. Two
options are possible to improve the low load dissipation.
• A switch Q3 is added in series with R1 (see Figure 16). The sense is connected to the
source of Q3
• In the second option the source (Q3) is not connected to the sense input, but the drain
(Q5) is.
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Isec
TR3
1
3
2
4
5
6
R2
R3
R1
Q5
DSA
Q6
C2
SSA
7
3
1
2
GND
IDS
Q3
VCC
4
IRC
DSB
GDA
Q2
C3
Q4
IC2-1
TEA1795
C1
SSB
5
GDB
6
Q1
IC2-2
TEA1795
8
Q3 and Q5 placed on two different positions
to decrease the low load losses
019aaa460
Two options: Q3 and Q5
Fig 16. Additional switches to decrease the low power losses by adding a circuit
It is important to know how large the compensation capacitor has to be, so the correct
MOSFET (Q3 or Q5) can be selected. The drain-source capacitance of Q4 and Q6 are
placed parallel to the compensation capacitance.
Table 2.
Compensation capacitance
VDS
100 mV (Typical)
10 V (Typical)
10 V (Maximum)
2N7002
41 pF
31 pF
50 pF
BSN20
21 pF
17 pF
27 pF
BSS123
110 pF
55 pF
-
2N7002
25 pF
6.8 pF
30 pF
BSN20
17 pF
7 pF
15 pF
BSS123
100 pF
12 pF
-
Ciss
Coss
The timing of the switches (Q3, Q4, Q5, and Q6) is set in the following way: When the
voltage of Q1 is low, Q5 has to be off and Q6 has to be on. On the other hand when the
voltage of Q1 is high Q5 has to be on and Q6 has to be off. The same can be said about
the state of Q3 and Q4 (see Table 3).
Table 3.
The states of Q3, Q4, Q5, and Q6
State
Q3
Q4
Q5
Q6
Q1 = LOW;
Q2 = HIGH
off
on
on
off
Q1 = HIGH;
Q2 = LOW
on
off
off
on
The next step is to find the right driver signals to meet the states in Table 3. There are two
options:
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• To derive the signal from the transformer winding
(see Figure 17, Q3  Q4 configuration)
• To derive the signal from the driver output (see Figure 17, Q5  Q6 configuration)
If transformer winding is used the gate of Q3 is connected via a resistance division to the
drain of Q2. Q4 is connected to the drain of Q1. The gate of Q5 is connected to the drain of
Q1 (see Figure 17). The gate of Q6 is connected to the drain of Q2.
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TR3
1
3
2
4
5
6
R6
R4
R2
R1
Q5
DSA
C2
Q6
SSA
Q3
VCC
DSB
7
4
GDA
3
1
2
GND
Q2
Q4
IC2-1
TEA1795
C1
SSB
5
GDB
6
Q1
IC2-2
TEA1795
8
R3
R5
019aaa461
a. Q3  Q4 configuration
TR1
1
3
2
4
5
6
R2
R1
Q5
Q3
DSB
Q6
C2
SSB
DSA
5
6
GDB
Q2
IC1-2
TEA1795
8
Q4
C1
SSA
3
GDA
Q1
IC1-1
TEA1795
1
IC2B
IC2A
2
4
3
4
5
019aaa513
b. Q5  Q6 configuration
Fig 17. The drive of MOSFETs Q3, Q4, Q5 and Q6
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Figure 18 to Figure 20 show the measurement results for the first schematic
(Q3  Q4 configuration).
(1)
(2)
(2)
(5)
(4)
(3)
(3)
(1)
(4)
019aaa733
(5)
019aaa734
C1 = 33 pF; R1 = 3.9 k; Iload = 15 A
(1) Voltage on the DSA pin
(2) Half-bridge point
(3) Drain-source voltage on MOSFET
(4) Gate source voltage
(5) Primary transformer current
a. The total delay before MOSFET is turned on
(C1 = 33 pF)
b. The delay caused by the charge of the
compensation capacitor (C1 = 33 pF)
Fig 18. Measurement results of the TEA1795 with compensation network
The delay between the current starting to flow through the MOSFET and the turn-on of the
MOSFET is 597 ns. 259 ns is caused by charging the capacitor and 338 ns by the delay
of switching Q3 and Q4. The premature turn-off is approximately 1 s.
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(1)
(2)
(2)
(4)
(4)
(3)
(3)
(1)
(5)
019aaa769
(5)
019aaa774
C1 = 100 pF; R1 = 3.9 k; Iload = 15 A
(1) Voltage on the DSA pin
(2) Half-bridge point
(3) Drain-source voltage on MOSFET
(4) Gate source voltage
(5) Primary transformer current
a. The capacitance is increased to 100 pF. The delay
is increased with 100 ns (see Figure 18)
b. Increasing the compensation capacitor from 33 pF
to 100 pF prematurely causes switching to
decrease from 1 s to 759 ns
Fig 19. Measurement results of the TEA1795 with compensation network
The delay between the current starting to flowing through MOSFET and the turn-on the
MOSFET is 697 ns. 359 ns is caused by charging the capacitor and 338 ns is caused by
the delay of switching Q3 and Q4. The premature turn-off is approximately 759 ns.
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8. DCM versus CCM
It does not matter whether the converter is working in CCM mode or DCM mode. There is,
however, one exception: the dimensioning of the RC filter is different for DCM and CCM.
The MOSFETs have to turn off at the right time to prevent current flowing in the wrong
direction (see Figure 20). In Continuous Conductance Mode (CCM) the dI/dt during
commutation (going to zero) is much higher than the dI/dt in Discontinuous Conduction
Mode (DCM). Therefore, in CCM, the input filter of the IC has to be dimensioned in such a
way that only the high frequency oscillation is filtered out and compensation for parasitic
inductance is not necessary.
(5)
(4)
(1)
(2)
(3)
019aaa770
019aaa771
Capacitance = 100 pF; Resistance = 3.9 k; Iload = 15 A
(1) Voltage on the DSA pin
(2) Half-bridge point
(3) Drain-source voltage on MOSFET
(4) Gate source voltage
(5) Primary transformer current
a. High reverse current causes a lot of ringing
b. Low reverse current causes much less ringing
Fig 20. Measurement results of the TEA1795 with compensation network
9. Issues
9.1 Unstable behavior of the control voltage at low output power
The TEA1795 only turns on the MOSFET if the voltage drop over of the MOSFET is at
least 220 mV (see Section 6.1). When the MOSFET is conducting the voltage drops to a
few millivolts. This difference in voltage causes a high current dump which again causes a
large power transfer per cycle. The transfer can only be changed by changing the control
signal. When the voltage drop over of the MOSFET is less than 220 mV no power is
delivered to the output. Therefore a small change in the control signal leads to a major
difference in power transfer, which causes an oscillation.
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9.2 Fast discharging of the gate in Regulation mode
When the blanking time following the turn-on of the SR-MOSFET is passed, the IC
changes from On mode to Regulation mode. When the measured drain-source voltage is
higher than 25 mV the IC regulates the drain-source voltage to 25 mV. The gate is fully
discharged, because the turn-off circuit is also active at that moment. The IC
compensates this behavior again by charging the gate voltage. This charge current is only
5 mA so that the charging is very slow. Figure 21 shows the result of this behavior.
(3)
fast discharge
(4)
fast discharge
(2)
(5)
(1)
019aaa772
(1) Midpoint half-bridge
(2) Gate source voltage on MOSFET A
(3) Drain-source voltage of MOSFET A
(4) Gate source voltage on MOSFET B
(5) Primary transformer current
Fig 21. Fast discharging in Regulation mode
9.3 Power supply in Off mode
If the power supply is in the Off mode, the IC gets no supply. Despite the absence of
power the output of the driver is low ohmic. This is caused by an internal charge on a gate
of the output MOSFET of the driver. This charge cannot flow away and causes the output
of the IC to stay low ohmic. This is important to know when testing the output of the driver.
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9.4 Double pulses
It is possible that double pulses on the gate voltage occur. because of the way the
SR MOSFETs are controlled (see Figure 22).
VDS
VGS
019aaa773
Fig 22. Double pulses
10. Layout of the IC
When designing the layout the following things are important for getting the lowest
possible inductance:
• The sense connections must be as close as possible to the pins of the MOSFET
• The loop between the drain sense wire and the source sense wire must be as short as
possible
sensing close to the pins
S DG
DSB
GDB
VCC
loop as small as
possible
8 SSB
019aaa462
(1) DSB = Drain Sense (part) B
(2) SSB = Source Sense (part) B
(3) GDB = Gate Driver (part) B
Fig 23. Layout recommendations
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11. Overview calculations
11.1 DCM mode calculations
Simple presentation of the secondary current:
k + 1  
k
I sec = I amp  sin   1   t – k  t no    ------------  t  --------------------------  k  N
1
1
(19)
k + 1  
k + 1  
I sec = 0  --------------------------  t  -------------------------- + t no
1
1
The switching period can be calculated with Equation 20:
2
t sw = t pr + 2  t no = ------------ + 2  t no
1
(20)
PO the output power, VO the output voltage, and IO the output current are related in the
following way:
PO = VO  IO
(21)
A combination of the all equations above results in:

-----1
PO
1
= V O  ------------------
------ + t no
1

0
2
-----------1
2
I amp  sin   1  t  = ---  V O  I amp  ------------------------2

------------ + t no
1
(22)
1
2
= ---  V O  I amp  ---------------------------- 1  t no

1 + ------------------
The amplitude (Iamp in Equation 22) can be calculated with Equation 23:
t no
 PO
I amp =  1 + 2  ------  ---  ------

t pr
2 VO
(23)
The average current (Iavg) on the secondary side equals the load current, but the RMS
current (IRMS) equals:
t pr
-----2
I RMS =
1
------------------t pr
------ + t no
2
 Iamp
0
2
1 t no
 PO
2
 sin   1  t  = ---  -------  --- + -----2 t pr
2 VO
(24)
The voltage drop over the rectifier diode can be calculated with Equation 25:
V f  I d  = V f0 + R d  I d
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The dissipation in the two diodes together equals:
1
2
1
2
P =  ---  V f0  I amp + ---  R d  I amp   ------------------------

2
t no
1 + 2  -----t pr
(26)
2
PO 2
PO
t no 

=  V f0  ------- + -----  R d  --------2-   1 + 2  ------ 

VO 8
t pr  

VO
When MOSFETs are used instead of diodes the power dissipation is calculated with
Equation 27:
1
1
2
P = ---  R DSon  I amp  ------------------------2
t no
1 + 2  -----t pr
(27)
2
2
t no
pO

= -----  R DSon  --------2-   1 + 2  ------
8
t pr
VO
If the MOSFETs are switched on too late (tdelay) or switched off prematurely (tearly), the
dissipation can be calculated with Equation 28:
2  V f  I amp   2 –  cos   1  t delay  + cos   1  t till0    +
2
I amp   1   t delay + t till0    R d – R DSon  –
P loss =
1
2
---   R d – R DSon   I amp   sin  2   1  t delay  + sin  2   1  t till0   +
2
(28)
2
R DSon  I amp    
1
 ---------------------------- + t on   1
tsw / 2
tpr / 2
tno
tdelay
ttill0
1.0
sin(ω1 × t)
0.5
0
0
2 × 10−6
t
4 × 10−6
019aaa464
Fig 24. Definition of tpr, tsw, tno, tdelay, and ttill0
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11.2 CCM mode calculations
In case of CCM the secondary current has a slightly different shape. Figure 25 shows
three examples:
5
400
Vbridge
40
lprim
200
VCr
0
20
lsec
0
−5
2 × 10−6
0
4 × 10−6
0
0
2 × 10−6
t1
4 × 10−6
2 × 10−6
0
t1
4 × 10−6
t1
019aaa450
a. Example 1: fsw = 200 kHz; VI = 380 V; PO = 103 W
5
400
Vbridge
40
lprim
200
0
VCr
lsec
20
0
−5
0
2 × 10−6 4 × 10−6
t1
0
0
2 × 10−6 4 × 10−6
t1
0
2 × 10−6 4 × 10−6
t1
019aaa507
b. Example 2: fsw = 167 kHz; VI = 380 V; PO = 176 W
5
400
lsec
40
Vbridge
200
Iprim
0
VCr
20
0
−5
0
5 × 10−6
t1
0
0
5 × 10−6
t1
0
5 × 10−6
t1
019aaa508
c. Example 3: fsw = 143 kHz; VI = 380 V; PO = 328 W
Fig 25. Examples of current shapes (Iprim (left), Isec (middle)) and of VCr (right; Cr = resonance capacity) for
different output powers
The secondary current can be approximated with Equation 29:


I sec = I amp  sin   1   t + k  t till0    k  ------  t   k + 1    ------ – t till0  k  N
 1

1
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tpr / 2
ttill0
tsw / 2
1.0
sin (ω1 × t)
0.5
0
0
2 × 10−6
t
4 × 10−6
019aaa451
Fig 26. Definition of tpr, tsw and ttill0
See Figure 26 for the definition of the variables tsw, tpr and ttill0.
The equivalent to the DCM case PO can be written as Equation 30:
t pr
 ----- – t till0
2

2
P O = V O  ----------------------- 
t pr
------ – t till0
2

I amp  sin   1  t   dt
0
(30)
2  t till0
1 – cos     1 – ------------------- 


t pr  
2
= ---  V O  I amp  ------------------------------------------------------------------
2  t till0
2   1 – -------------------

t pr 
For a given PO and VO this expression can be rewritten as Equation 31:
I amp
2  t till0
2   1 – -------------------

p
t pr 

O
= ---  -------  ------------------------------------------------------------------2 VO
2  t till0
1 – cos     1 – ------------------- 


t pr  
(31)
Equation 31 is the expression for the effective current.
I RMS  t till0  =
2  t till0
2   1 – -------------------

t pr 
P
1 -----O 
---  -  ---  ------------------------------------------------------------------- 
2  t till0
2 VO 2
1 – cos    1 – -------------------

t pr 
2  t till0
sin 2     1 – -------------------

t pr 
1 – -----------------------------------------------------------------2  t till0
2     1 – -------------------

t pr 
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The voltage drop over the rectifier diode can be calculated with Equation 33:
V f  I d  = V f0 + R d  I d
(33)
The dissipation in the two diodes together equals:
2  t till0
2
   1 – -------------------

PO 1
PO
t pr 
P = V f0  ------- + ---  R d  --------2-  --------------------------------------------------------------------------2- 
VO 2
 t till0  
VO
 1 – cos     1 – 2------------------


t pr   
2
(34)
2  t till0 

sin  2     1 – -------------------  



t pr   
 1 – -----------------------------------------------------------------

2  t till0

2     1 – ------------------- 


t pr


Example:
•
•
•
•
•
•
tpr = 11 s
ttill0 = 500 ns
PO = 240 W
VO = 12 V
Rd = 5 m
Vf0 = 280 mV
The dissipation in the diodes equals: 7.925 W.
11.3 Input filter
R1
+
VI
VI
C1
D1
VC1 (t)
0
−VFd
t
−
019aaa988
Fig 27. Schematic of input filter
The output voltage of the input filter shown in Figure 27 can be calculated with
Equation 35:
t
t
V C1  t  = V C10  exp  – ------------------ + V I   1 – exp  – ------------------ 
 R 1  C 1

 R 1  C 1 
(35)
Where:
• VC1 = voltage on capacitor C1
• VC10 = boundary condition of the capacitor voltage
• VI = input voltage
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With Equation 35 tdelay can be calculated.
When:
•
•
•
•
VC10 = VF(D1) (forward voltage of diode D1)
VI = VF(MOSFET) (diode of MOSFET Q1 or Q2) (see Figure 11)
t = td
VC1 = Vth (220 mV)
Equation 35 changes to Equation 36:
td
td
V C1  t d  = V F  D1   exp  – ------------------ + V F  MOSFET    1 – exp  – ------------------  = V th
 R 1  C 1

 R 1  C 1 
(36)
Then tdelay can be calculated with Equation 37
 V th – V F  MOSFET  
t d = – R 1  C 1  ln  – --------------------------------------------------------
  V F  D1  – V F  MOSFET  
(37)
11.4 Parasitic inductance
di ds
V L  t  = L par  --------dt
(38)
If the secondary current can be calculated with Equation 39:
I DS  t  = I amp  sin   1  t 
(39)
then the induced voltage becomes:
d  I amp  sin   1  t  
V L  t  = L par  ---------------------------------------------------- = I amp  L par   1  cos   1   
dt
(40)
The total voltage measured equals:
V DS  t  = I amp  L par   1  cos   1  t  + R DSon  I amp  sin   1  t 
2
2
2
= I amp   L par   1 + R DSon   cos   1  t –  
(41)
R DSon
 = atan  -----------------------
 L par   1
Finally, the premature turn-off time equals t1 in:
t pr
V th


------ – t 1 = acos  ------------------------------------------------------------------------ + 
2
2
2
2
I

amp  L par   1 + R DSon
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11.5 Compensation filter
I sec  s  = I ds  s  + I RC  s 
di ds
R 1  I RC + V C1 = L par  --------- + R DSon  I DS
dt
(43)
du C1
I RC = C 1  -----------dt
L par
-------------= R1  C1
R DSon
(44)
V C1 = R DSon  I ds
(45)
The voltage drop over the measuring points caused by the parasitic inductance equals:
di sec
V DS  t  = L par  ----------- + R DSon  I sec
dt
(46)
Isec
IRC
Lpar
R1
RDSon
C1
+
VDS_sense
−
019aaa465
VDS_sense = DSA  SSA / DSB  SSB
Fig 28. Voltage drop over measuring points
I sec = I DS + I RC
di ds
R 1  I RC + V C1 = L par  --------- + R DSon  I ds
dt
I RC
du C1
= C 1  -----------dt

V C1 = V DS_sense
R 1  I RC + V DS_sense
I RC
(47)
d  I sec – I RC 
= L par  ------------------------------ + R DSon   I sec – I RC 
dt
du ds_sense
= C 1  ---------------------dt

du ds_sense
d  I sec – I RC 
du ds_sense
R 1  C 1  ---------------------- + V DS_sense = L par  ------------------------------ + R DSon   I sec – C 1  ----------------------

dt
dt 
dt
Laplace transformation
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du ds_sense
d  I sec – I RC 
 R 1 + R DSon   C 1  ---------------------- + V DS_sense = L par  ------------------------------ + R DSon  I sec 
dt
dt
 R 1 + R DSon   C 1  s  V DS_sense + V DS_sense = L par  s  I DS – s  I RC + R DSon  I sec 
V DS_sense
L par


-------------s+1
R DSon
s  I RC


= I sec  R DSon   --------------------------------------------------------------- – --------------------------------------------------------------  R 1 + R DSon   C 1  s + 1  R 1 + R DSon   C 1  s + 1


(48)
If the first term:
L par
-------------s+1
R DSon
-------------------------------------------------------------- = 1
 R 1 + R DSon   C 1  s + 1
(49)
and the second term:
s  I RC
------------------------------------------------------------- R 1 + R DSon   C 1  s + 1
(50)
are negligible, then:
V DS_sense = I sec  R DSon
(51)
The first term equals 1 if Equation 52 is valid:
L par
-------------s+1
L par
R DSon
--------------------------------------------------------------- = 1  -------------=  R 1 + R DSon   C 1 
 R 1 + R DSon   C 1  s + 1
R DSon
(52)
L par
C 1 = ----------------------------------------------------R DSon   R 1 + R DSon 
The second term is small because IRC is small.
11.6 Dimensioning of filter
Isec
IRC
Lpar
R1
RDSon
C1
+
VDS_sense
−
019aaa465
VDS_sense = DSA  SSA / DSB  SSB
Fig 29. Dimensioning of filter
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I sec = A  sin   1  t +   = A   cos     sin   1  t  + sin     cos   t  t  
s

(53)
cos      1 + sin     s
A  -----------------------------------------------------------2
2
s + 1
I sec = I DS + I RC
R 1  I RC + V C1
I RC
di ds
= L par  --------- + R DSon  I DS
dt
du C1
= C 1  ------------ =
dt
di ds
L par  --------- = –  R DSon + R 1   I DS + R 1  I sec
dt

du C1
C 1  ------------ = I sec – I DS
dt
V C1 = V ds_sense
 di ds 
 ---------   L
dt 
par

=
 du   0
C1
 ---------- dt 
R1

1
AN10954
Application note
0 –1
–  R DSon + R 1 
  
C1 
–1
+1  I DS   L par

 +
0   V C1  0
0 – 1

C1 
(54)
 di ds 
 --------- 
0  I sec
I sec
 I DS 
dt 

A
= A mat  
 + B mat   





du C1
0
0
0
 V C1
 -----------
 dt 
 L par
A mat = 
 0
B mat
+ u C1
 L par
= 
 0
0 –1
R DSon + R 1
  
C1 
–1
0 –1
–R1
  
C1 
1
– 1
0
0
0 
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with Laplace transformation and T-matrix with eigenvectors.
I sec 
x· = A mat  x + B mat    
 I sec 
 0    T  y· = A
mat  T  y + B mat  
0

x = T y
I sec 
–1
–1
y· = T  A mat  T  y + T  B mat     
 0

 = T
–1
 A mat  T 
I sec s – domain
–1
y· =   y + T  B mat   
 0

 s  I –    y = y0 + T
y = s  I – 
–1
 y0 +  s  I –  
x = T  s  I – 
x = T   sI –  
T
–1
 B mat  

–1
–1
–1
T
T
–1
–1
(57)
I sec  s 

0 
–1
I
cos      1 + sin     s
–1
-  T  B mat   sec 
 -----------------------------------------------------------2
2
 0
s + 1
 x0 +  s  I –  
 x 0 + T   sI –  
–1
–1
I
cos      1 + sin     s
–1
-  T  B mat   sec
 -----------------------------------------------------------2
2
 0
s + 1
cos      1 + sin     s
 -----------------------------------------------------------2
2
s + 1
A timedomain
 B mat   
 0

x  t  = T  exp  t   T
–1
 x 0 + T  exp 2  t   T
(58)
–1
A
 B mat   
 0
Where:
•
•
•
•
x0 = The boundary conditions
p1 and p2 = The poles of the system
T = the eigenvectors of the system
I = the identity matrix
0
 exp  p 1  t 
exp  t  = 

exp  p 2  t 
0
(59)
 f1  t 
exp 2  t  = 
0
(60)
0

f 2  t 
 1  cos    + p 1  sin   
f 1  t  = ---------------------------------------------------------------  exp  p 1  t  – cos   1  t   +
2
2
1 + p1
 1  sin    – p 2  cos   
---------------------------------------------------------------  sin   1  t   T
2
2
1 + p1
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 1  cos    + P 2  sin   
-   exp  p 1  t  – cos   1  t   +
f 2  t  = ---------------------------------------------------------------2
2
1 + P2
(62)
 1  sin    – P 2  cos   
----------------------------------------------------------------  sin   1  t 
2
2
1 + P2
V th – V I
With t delay = – RC  1n   -----------------------  can be calculated:  =  1  t delay .
V DS0 – V I
If t1 is the time Vc (t1) = Vth and tpr is the period time of secondary current then
ttill0 = tpr  t1.
The best choice for the capacitor value is when tdelay = ttill0
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12. Legal information
12.1 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
12.2 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
AN10954
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to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
12.3 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
GreenChip — is a trademark of NXP B.V.
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13. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.2
7.2.1
8
9
9.1
9.2
9.3
9.4
10
11
11.1
11.2
11.3
11.4
11.5
11.6
12
12.1
12.2
12.3
13
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Quick start-up. . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Resonant converter versus flyback . . . . . . . . . 5
Diodes as rectifiers . . . . . . . . . . . . . . . . . . . . . . 6
MOSFETs as rectifiers . . . . . . . . . . . . . . . . . . . . 8
Basic functionality of the TEA1795T . . . . . . . . 9
The turn-on function . . . . . . . . . . . . . . . . . . . . . 9
The turn-off function . . . . . . . . . . . . . . . . . . . . . 9
Improving the system . . . . . . . . . . . . . . . . . . . 10
Turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Immediate turn-off after turn-on . . . . . . . . . . . 10
False turn-on . . . . . . . . . . . . . . . . . . . . . . . . . 12
Parasitic turn-on . . . . . . . . . . . . . . . . . . . . . . . 13
Turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Premature turn-off. . . . . . . . . . . . . . . . . . . . . . 14
DCM versus CCM . . . . . . . . . . . . . . . . . . . . . . . 26
Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Unstable behavior of the control voltage
at low output power . . . . . . . . . . . . . . . . . . . . 26
Fast discharging of the gate in Regulation
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power supply in Off mode. . . . . . . . . . . . . . . . 27
Double pulses . . . . . . . . . . . . . . . . . . . . . . . . . 28
Layout of the IC . . . . . . . . . . . . . . . . . . . . . . . . 28
Overview calculations . . . . . . . . . . . . . . . . . . . 29
DCM mode calculations . . . . . . . . . . . . . . . . . 29
CCM mode calculations . . . . . . . . . . . . . . . . . 31
Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Parasitic inductance . . . . . . . . . . . . . . . . . . . . 34
Compensation filter. . . . . . . . . . . . . . . . . . . . . 35
Dimensioning of filter . . . . . . . . . . . . . . . . . . . 36
Legal information. . . . . . . . . . . . . . . . . . . . . . . 40
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 14 December 2010
Document identifier: AN10954
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