AN11149 TEA1792 GreenChip synchronous rectifier controller Rev. 1 — 3 September 2012 Application note Document information Info Content Keywords GreenChip, TEA1792T/TS, TEA1792AT/ATS, Synchronous Rectifier (SR) driver, high-efficiency Abstract The TEA1792T/TS is a member of the new generation of Synchronous Rectifier (SR) controllers for switched mode power supplies. Its high level of integration allows the design of cost-effective power supplies with a very low number of external components. The TEA1792T/TS are controller IC dedicated to synchronous rectification on the secondary side of discontinuous conduction mode and quasi-resonant flyback converters. The dedicated TEA1792AT/ATS version is available for resonant convertors. The TEA1792 versions are fabricated using the Silicon-On-Insulator (SOI) process. AN11149 NXP Semiconductors TEA1792 GreenChip synchronous rectifier controller Revision history Rev Date Description v.1 20120903 first issue Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] AN11149 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2012 © NXP B.V. 2012. All rights reserved. 2 of 14 AN11149 NXP Semiconductors TEA1792 GreenChip synchronous rectifier controller 1. Introduction The TEA1792T/TS are the controllers for Synchronous Rectification (SR) of quasi-resonant and Discontinuous Conduction Mode (DCM) flyback converters. They are successors to the TEA1791T SR controller and provide: • improved performance • the capability to select two different set points for the regulation level The TEA1792 is available in pin identical packages as the: • • • • TEA1792T (SO8 package) TEA1792TS (TSOP6 package) TEA1792AT (SO8 package) TEA1792ATS (TSOP6 package) The main difference between the TEA1792AT/ATS and the TEA1792T/TS is the shorter minimum rectification time. This feature makes the TEA1792AT/ATS ideal for higher switching frequencies (> 250 kHz) which are often used in DCM resonant converters. Remark: Unless otherwise stated, all values are typical. Refer to the relevant product data sheet (Ref. 1, Ref. 2, Ref. 3, Ref. 4) for more specific information. 1.1 Pinning information 656(16( *1' 9&& ,& '5,9(5 QF 6(/5(* DDD DDD Fig 1. TEA1792T/AT (SO8) pin configuration Table 1. AN11149 Application note Fig 2. TEA1792TS/ATS (TSOP6) pin configuration TEA1792 pin description Symbol Pin Description T/AT TS/ATS SRSENSE 1 1 synchronous timing input GND 2 2 ground n.c. 3 not present not connected or not present DRIVER 4 6 driver output for SR MOSFET n.c 5 5 not connected SELREG 6 4 selection input for driver regulation level n.c. 7 not present not connected or not present VCC 8 3 supply voltage All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2012 © NXP B.V. 2012. All rights reserved. 3 of 14 AN11149 NXP Semiconductors TEA1792 GreenChip synchronous rectifier controller 2. TEA1792T/TS application diagrams The TEA1792T/TS are developed as dedicated SR controllers for flyback converters. The TEA1792AT/ATS derivatives are developed to provide support for synchronous rectification in resonant convertors. The main difference between the two versions is the blanking time after turn-on. 2.1 TEA1792T/TS application for flyback convertors The application diagrams Figure 3 and Figure 4 show the configuration for high-side and low-side rectification. Both methods are valid for quasi-resonant and discontinuous conduction mode flyback converters using the TEA1792T/TS. TR Qsec Vo VIN RDRIVER CVCC GND RSRSENSE SELREG DRIVER Qprim PRIMARY SIDE CONTROLLER Cout IC VCC SRSENSE aaa-000138 Fig 3. TEA1792T/TS application diagram for high-side rectification in flyback convertors TR VIN Vo RSRSENSE PRIMARY SIDE CONTROLLER SRSENSE VCC Qprim Qsec RDRIVER Cout IC DRIVER SELREG GND aaa-000139 Fig 4. TEA1792T/TS application diagram for low-side rectification in flyback convertors Qprim and Qsec are the switches on the primary and secondary side respectively. The primary controller manages Qprim and the TEA1792 controller manages Qsec. The TEA1792 controller operates independently of the primary controller. AN11149 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2012 © NXP B.V. 2012. All rights reserved. 4 of 14 AN11149 NXP Semiconductors TEA1792 GreenChip synchronous rectifier controller 2.2 TEA1792AT/ATS application for resonant convertors The application diagrams Figure 5 shows the configuration for a resonant convertor using the TEA1792AT/ATS. VIN Qprim1 PRIMARY SIDE CONTROLLER Tr CHB Qprim2 Vo VCC VCC SRSENSE RSRSENSE1 Qsec1 DRIVER SRSENSE RSRSENSE2 IC Qsec2 IC1 GND DRIVER Cout IC IC2 GND 014aaa895 Fig 5. TEA1792AT/ATS application for resonant convertors The TEA1792AT/ATS are designed for Discontinuous Conduction Mode (DCM) adapters operating at higher switching frequencies. Resonant converters can also have higher frequency ranges (> 250 kHz). The smaller minimum rectification time of the TEA1792AT/ATS (0.95 s) guarantees stable operation at switching frequencies > 250 kHz. The TEA1792T/TS with a minimum rectification time of 2.1 s is ideally suited for switching frequencies < 250 kHz. AN11149 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2012 © NXP B.V. 2012. All rights reserved. 5 of 14 AN11149 NXP Semiconductors TEA1792 GreenChip synchronous rectifier controller 3. Functional description and application overview 3.1 SR control The TEA1792T/TS uses the SRSENSE pin as an input sense in the control of the drain-source voltage (VDS) of the MOSFET. No adjustment is necessary in the SR control. VSRSENSE 0V Vdeact(drv) (-12 mV typ.) Vreg(drv) (-42 mV/-30 mV typ.) Vact(drv) (-220 mV typ.) primary current 0A secondary current 0A VDRIVER 0V aaa-000137 Fig 6. Synchronous rectification signals The SR MOSFET is switched on by the DRIVER pin which is connected to the gate of the MOSFET. When the drain voltage on the SRSENSE pin is < 220 mV, the SR MOSFET is switched on. When the sensed voltage reaches 30 mV or 42 mV, the driver output voltage is regulated to maintain the sensed voltage on the SRSENSE pin. The regulation voltage level depends on the SELREG pin setting. At a very low drain current with the VSRSENSE > 12 mV, the driver is pulled to ground and the SR MOSFET is switched off. When the secondary stroke of the flyback converter is shorter than the minimum deactivation time tact(sr)(min) (1.8 s), the driver output is disabled. This feature saves energy during flyback convertor low-load conditions. When the secondary stroke is > tact(sr)(min) (2.1 s), the driver output is enabled. In addition, the minimum deactivation time is used to eliminate false switch-off due to high frequency ringing at the start of the secondary stroke. The driver output is enabled when the secondary stroke time is > 2.1 s. AN11149 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2012 © NXP B.V. 2012. All rights reserved. 6 of 14 AN11149 NXP Semiconductors TEA1792 GreenChip synchronous rectifier controller The best performance is obtained when the SRSENSE pin senses the drain of the SR MOSFET directly using the external 1 k series resistor. 3.2 Function of resistors in series with the SRSENSE pin All TEA1792T/TS pins are protected against ElectroStatic Discharge (ESD) to prevent IC damage when handled. Some application tests can trigger ESD protection. If the ESD protection on the SRSENSE pin is triggered, the pin is pulled to ground by the internal ESD protection component. As the SRSENSE pin senses the MOSFET drain voltage, protect the pin using a series resistor to limit surge current from a severe ESD event. Figure 3, Figure 4 and Figure 5 show how the current limiting resistor RSRSENSE is used to provide the ESD surge protection. A 1 k resistor value is sufficient to protect the SRSENSE pin. Sometimes false triggering of the MOSFET can occur, for example due to ringing or crosstalk due to the PCB layout. Increasing the RSRSENSE resistor value provides additional SR input filtering and improves performance. The drawback to this solution is increased activation and deactivation delay time values. Remark: Check the application carefully to achieve the optimal configuration. More information on false triggering of the MOSFET including possible causes and solutions are described in Section 4.2. 3.3 VCC supply The VCC(startup) voltage is 8.5 V and the VCC(stop) voltage is 8 V. Normally, a 1 F multilayer ceramic capacitor is placed between the VCC and GND pins to smooth the supply voltage. When the voltage on the VCC pin is above 8.5 V, the IC leaves the UnderVoltage LockOut (UVLO) state and activates the synchronous rectifier circuitry. The UVLO state is triggered when VCC < 8 V and the SR driver output is kept active-low. 3.4 VCC auxiliary supply In high-side rectification, the IC is supplied by an auxiliary winding which is tacked on to the secondary output winding. To get the full driver output capability, supply voltage VCC must be > 12 V. A supply voltage of 15 V is targeted which is set using the power output winding and the AUX winding turns ratio. N aux V CC = ------------ V OUT – 0.7 V N SEC (1) The average IC supply current depends on the dynamic gate charge transfer characteristic of the MOSFET. For example; conditions of 10 V gate-drive amplitude, VDS of < 1 V, CGS 75 nC and fsw = 100 kHz results in a drive current of 7.5 mA. The IC only consumes 1 mA. So in this case, the total supply current adds up to 8.5 mA. AN11149 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2012 © NXP B.V. 2012. All rights reserved. 7 of 14 AN11149 NXP Semiconductors TEA1792 GreenChip synchronous rectifier controller 3.5 Driver output The driver circuit to the external power MOSFET gate has a source capability of 400 mA and sink capability of 2.7 A. These capabilities ensure efficient operation, enabling fast switch-on and switch-off of the power MOSFET. The source stage is coupled to a 2.1 s timer. When the timer finishes, the source capability is reduced to a 5 mA to maintain the driver output voltage at the required level. The output voltage of the driver is limited to 10 V. The high-voltage output drives all MOSFET brands to the minimum on-state resistance RDSon. During start-up, the conditions VCC < VCC(startup) and UVLO force the driver output voltage LOW prevent false SR MOSFET switch-on. Design a MOSFET gate series resistor into the track from the TEA1792 DRIVER pin to the SR MOSFET gate input. If this gate series resistor is required due to switching noise reduction, check the SR MOSFET switch-off state. Recheck the MOSFET at a high temperature as well. When the power MOSFET on the primary side switches on, the drain-source voltage of the SR MOSFET rises with a high dV/dt. If the dV/dt is steep, the capacitive current flows from the drain to the gate through the MOSFET capacitor CDG. The current and a gate resistor increases the gate voltage VGS. However, the voltage increase must remain well below the SR MOSFET threshold voltage Vth to prevent switch-on. Therefore, limit the gate series resistor to between 4.7 and 10 . 3.6 SR level select The driver regulation voltage level Vreg(drv) is selected using the SELREG pin. When the SELREG pin is grounded, Vreg(drv) = 42 mV. When the SELREG pin is left open, Vreg(drv) = 30 mV. The SELREG pin has a 10 A internal pull-up current source. When the pin is short-circuited to ground, the pin selects the lowest Vreg(drv) level. If the pin is left open, the current source creates a logic HIGH-level on this pin and the highest Vreg(drv) value is selected. As a guideline, set the SELREG level to the low value of 42 mV for MOSFETs with a high RDSon of >10 m. Conversely, use the high value of 30 mV for MOSFETs with a low RDSon of <10 m. The choice has a small benefit on the behavior in low load conditions. The low value is the preferred setting when false triggering occurs as a result of large crosstalk or high current spikes in high load conditions. Always check and compare both settings for each application. AN11149 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2012 © NXP B.V. 2012. All rights reserved. 8 of 14 AN11149 NXP Semiconductors TEA1792 GreenChip synchronous rectifier controller 4. Recommendations to improve the application 4.1 Layout considerations Pay careful attention to the PCB layout to ensure the best possible results. Tracks from the MOSFET drain to the SRSENSE pin and from the MOSFET source to the GND pin form a loop. This loop must be as short as possible. To achieve this, route them as close as possible and parallel to each other. This routing prevents incorrect measurement values from being obtained because of the voltage drop over the tracks. The IC ground is used as reference by the internal circuits but it also shares the high driver output current pulses. In addition, IC ground is part of the very sensitive regulation control loop for the SR MOSFET. The IC ground copper track must be as wide and as low ohmic as possible. Direct the IC ground track very close to the MOSFET source and position the IC near the MOSFET. Connect the SRSENSE pin to the drain pin of the SR MOSFET using the series resistor. It is good practice to make the sense track a separate one to guarantee correct sense and regulation of the MOSFET VDS. 4.2 Short pulse prevention The TEA1792 uses the voltage across the MOSFET drain and source to control the gate-drive. The IC measures the VDS through the SRSENSE and GND pins. As soon as the SRSENSE level is <220 mV, the SR MOSFET is switched on. At the end of the 2.1 s blanking time, the SRSENSE level is resampled. When the level is >12 mV, the IC assumes that the secondary stroke has ended and the MOSFET is switched off immediately. In the next secondary stroke, the MOSFET driver is also disabled. The blanking timer is enabled for the next cycle. At the end of the blanking time, the SRSENSE level is sampled again. In this way, no SR action is performed at low-load which results in better efficiency for this condition. False triggering of the short pulse prevention can occur when ringing of the flyback exceeds the 2.1 s blanking time. See Figure 7 for a graphical representation. AN11149 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2012 © NXP B.V. 2012. All rights reserved. 9 of 14 AN11149 NXP Semiconductors TEA1792 GreenChip synchronous rectifier controller (1) CH1: source MOSFET. (2) CH2: gate-drive MOSFET. (3) False triggering. (4) SR drive disabled. (5) Normal regulation. Fig 7. High-side application: false triggering At the end of the blanking time, if the SRSENSE level is near to the regulation range level, a small disturbance can trigger the MOSFET to switch off for both the current and next cycle. False triggering is most likely to happen when the following conditions are valid: • low loads combined with a low RDSon MOSFET and large secondary ringing • high current spikes in the application as a result of poor PCB-layout in combination with a high frequency source such as PFC switching There are several solutions to eliminating or decreasing false triggering and unwanted MOSFET switch-off: • Check both levels of the regulation voltage with the SELREG pin open or connected to ground and select the setting with the best results • Improve the PCB-layout of the application see Section 4.1) • Use a general-purpose diode instead of a fast-diode in the primary RCD snubber network. This modification reduces the ringing at the beginning of the secondary stroke • Connect a filtering capacitor (5 pF to 33 pF) from pins SRSENSE to GND close to the IC. Alternatively, increase the series resistor value in the SRSENSE line (see Section 3.2) • Use a MOSFET with a higher RDSon. A higher value of RDSon contributes more margin for low load conditions. In general, MOSFETs with an RDSon as low as 7 m do not cause problems in a good design. MOSFETs with an RDSon <7 mΩ only have a very limited contribution to higher efficiency because of the increased capacitive switching losses. In addition, they are more expensive and more sensitive to false triggering AN11149 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2012 © NXP B.V. 2012. All rights reserved. 10 of 14 AN11149 NXP Semiconductors TEA1792 GreenChip synchronous rectifier controller • Create an offset on the SRSENSE input as shown in Figure 8. The offset also contributes to better performance of low RDSon MOSFETs. VOUT C1 R1 100 pF 10 kΩ VCC Z1 30 V R3 R2 2 MΩ SRSENSE IC 1 kΩ R4 Q1 DRIVER 4.7 Ω GND aaa-003178 Fig 8. TEA1792 schematic offset circuit low-side application The schematic shown in Figure 8 is drawn for a low-side application for ease of explanation. However, it is valid for high-side applications as well. The explanation of the circuit is based on the component values used in Figure 8. The components C1, R1, R2 and Z1 are added to create an offset on the SRSENSE pin. They basically form a charge pump circuit that creates 30 V across Zener diode Z1. Resistor R1 limits the peak current through Z1. The 30 V creates a 15 A current through resistors R2 and R3. This current lowers VSRSENSE by 15 mV. The 42 mV or 30 mV regulation level effectively becomes 27 mV or 15 mV. The 12 mV switch-off level is 3 mV on the drain of MOSFET Q1. Changing the value of R2 adjusts the offset. Place resistors R1 and R2 close to the IC to avoid noise on the SRSENSE pin. Remark: Evaluate the switch-off timing carefully. The MOSFET switches off later because the 12 mV switch-off level is also raised. AN11149 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2012 © NXP B.V. 2012. All rights reserved. 11 of 14 AN11149 NXP Semiconductors TEA1792 GreenChip synchronous rectifier controller 5. References AN11149 Application note [1] TEA1792T data sheet — GreenChip synchronous rectifier controller data sheet [2] TEA1792TS data sheet — GreenChip synchronous rectifier controller data sheet [3] TEA1792AT data sheet — GreenChip synchronous rectifier controller data sheet [4] TEA1792ATS data sheet — GreenChip synchronous rectifier controller data sheet [5] UM10526 user manual — GreenChip synchronous rectifier controller add-on board user manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2012 © NXP B.V. 2012. All rights reserved. 12 of 14 AN11149 NXP Semiconductors TEA1792 GreenChip synchronous rectifier controller 6. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. GreenChip — is a trademark of NXP B.V. All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2012 © NXP B.V. 2012. All rights reserved. 13 of 14 AN11149 NXP Semiconductors TEA1792 GreenChip synchronous rectifier controller 7. Contents 1 1.1 2 2.1 2.2 3 3.1 3.2 3.3 3.4 3.5 3.6 4 4.1 4.2 5 6 6.1 6.2 6.3 7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 TEA1792T/TS application diagrams . . . . . . . . 4 TEA1792T/TS application for flyback convertors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 TEA1792AT/ATS application for resonant convertors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description and application overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SR control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Function of resistors in series with the SRSENSE pin. . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCC supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCC auxiliary supply . . . . . . . . . . . . . . . . . . . . . 7 Driver output . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SR level select . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommendations to improve the application 9 Layout considerations. . . . . . . . . . . . . . . . . . . . 9 Short pulse prevention . . . . . . . . . . . . . . . . . . . 9 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 3 September 2012 Document identifier: AN11149