PIC24FXXKMXXX/KLXXX Flash Programming Specification

PIC24FXXKMXXX/KLXXX
PIC24FXXKMXXX/KLXXX Flash
Programming Specifications
1.0
DEVICE OVERVIEW
2.0
This document defines the programming specifications
for the PIC24FXXKMXXX/KLXXX family of 16-bit
microcontroller devices. This is required only for
developing
programming
support
for
the
PIC24FXXKMXXX/KLXXX family. Users of any one of
these devices should use the development tools that
are already supporting the device programming.
PIC24FXXKMXXX/KLXXX family devices are programmed exclusively using In-Circuit Serial
Programming™ (ICSP™).
The ICSP programming method is the most direct
method for programming the device. It provides a native,
low-level programming capability to erase, program and
verify the device. Section 3.0 “Device Programming –
ICSP” describes the ICSP method.
The programming specifications are specific to the
following devices:
• PIC24F04KL100
• PIC24F08KL302
• PIC24F04KL101
• PIC24F08KL401
• PIC24F08KL200
• PIC24F08KL402
• PIC24F08KL201
• PIC24F16KL401
• PIC24F08KL301
• PIC24F16KL402
• PIC24FV08KM101(1)
• PIC24FV16KM202(1)
PIC24FV08KM204(1)
• PIC24FV08KM202(1)
• PIC24FV16KM104(1)
• PIC24FV16KM102(1)
PIC24FV08KM102(1)
• PIC24FV16KM204(1)
•
•
Note 1:
2.1
Power Requirements
Devices in the PIC24FXXKLXXX and PIC24FXXKMXXX
families are 3.3V supply designs. The devices can
operate from 1.8V to 3.6V.
Devices in the PIC24FVXXKMXXX families are 5.0V
supply designs. The device can operate from 2.0V to
5.5V; an internal regulator operates the core logic at
3.25V.
Includes corresponding PIC24FXXKMXXX
devices.
TABLE 2-1:
PROGRAMMING OVERVIEW OF
THE PIC24FXXKMXXX/KLXXX 
FAMILY
Table 2.1 provides the pins that are required for programming, which are indicated in Figure 2-2. Refer to
the specific device data sheet for complete pin descriptions. Note that all power supply and ground pins must
be connected appropriately for programming.
PIN DESCRIPTIONS (DURING PROGRAMMING)
During Programming
Pin Name
Pin Name
Pin Type
MCLR/VPP
P
Programming Enable
VDD
P
Power Supply
VSS
VSS
P
Ground
CEFC
VCAP
P
Stabilizing Capacitor for Voltage Regulator(1)
PGECx
PGEC
I
Programming Pin Pair: Serial Clock
PGEDx
PGED
I/O
Programming Pin Pair: Serial Data
MCLR/VPP
VDD
Pin Description
Legend: I = Input, O = Output, P = Power
Note 1: PIC24FVXXKMXXX devices only.
 2011-2013 Microchip Technology Inc.
DS30625D-page 1
PIC24FXXKMXXX/KLXXX
2.1.1
ON-CHIP VOLTAGE REGULATOR
CONNECTIONS
For PIC24FVXXKMXXX devices, an on-chip regulator
provides power to the core from the other VDD pins. A
low-ESR capacitor (such as high-quality ceramic or
tantalum) must be connected to the VDDCORE pin
(Figure 2-1). This helps to maintain the stability of the
regulator. The specifications for core voltage and capacitance are listed in Section 5.0 “AC/DC Characteristics
and Timing Requirements”. PIC24FXXKMXXX and
PIC24FXXKLXXX devices do not use an on-chip
regulator.
FIGURE 2-1:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
5.0V
PIC24FVXXKMXXX
VDD
VCAP
CEFC
(10 F typ)
VSS
Note 1: These are typical operating voltages. Refer
to Section 5.0 “AC/DC Characteristics and
Timing Requirements” for the full operating
ranges of VDD and VDDCORE.
DS30625D-page 2
 2011-2013 Microchip Technology Inc.
PIC24FXXKMXXX/KLXXX
FIGURE 2-2:
PIC24FXXKLXXX PIN DIAGRAMS
MCLR/VPP
PGEC2
PGED2
PGED3
PGEC3
VDD
VSS
PGED3
PGEC3
20
19
18
17
16
15
14
13
12
11
VDD
VSS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
VSS
PGED3
PGEC3
6 7 8 9 10
1
2
3
4
5
6
7
8
9
10
PIC24FXXKLX01
15
14
PIC24FXXKLX01 13
12
11
MCLR/VPP
PGEC2
PGED2
PGED1
PGEC1
PIC24FXXKLX02
20 19 18 17 16
PGED1 1
PGEC1 2
3
4
5
14
13
12
11
10
9
8
20-Pin PDIP
PGED2
PGEC2
MCLR/VPP
VDD
VSS
20-Pin QFN
1
2
3
4
5
6
7
PIC24FXXKLX00
14-Pin PDIP
28-Pin PDIP
MCLR/VPP
VDD
Vss
28-Pin QFN
28 27 26 25 24 23 22
21
20
19 PGEC2
PIC24FXXKLX02 18 PGED2
17
16
15
8 9 10 11 12 13 14
VDD
PGED3
PGEC3
PGED1 1
PGEC1 2
3
4
VSS 5
6
7
 2011-2013 Microchip Technology Inc.
MCLR/VPP
PGED1
PGEC1
VSS
VDD
PGED3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PGEC2
PGED2
PGEC3
DS30625D-page 3
PIC24FXXKMXXX/KLXXX
PIC24F(V)XXKMXXX PIN DIAGRAMS
20 19 18 17 16
PGED1 1
15
PGEC1 2
14
3 PIC24F(V)XXKMX01 13
12
4
11 VCAP(1)
5
PGED3
PGEC3
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
VSS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
VSS
VCAP(1)
PGED3
PGEC3
6 7 8 9 10
MCLR/VPP
PGEC2
PGED2
PGED1
PGEC1
PIC24F(V)XXKMX01
20-Pin PDIP
PGED2
PGEC2
MCLR/VPP
VDD
VSS
20-Pin QFN
PIC24F(V)XXKMX02
FIGURE 2-3:
28-Pin PDIP
MCLR/VPP
VDD
Vss
MCLR/VPP
28 27 26 25 24 23 22
21
20
19 PGEC2
PIC24F(V)XXKMX02 18 PGED2
17 VCAP(1)
16
15
8 9 10 11 12 13 14
PGED1
PGEC1
VSS
VDD
PGED3
VDD
PGED3
PGEC3
44-Pin QFN/TQFP
PGEC3
PGED3
PGEC3
PGED3
VDD
VSS
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
VCAP(1) 7
8
PGED2 9
PGEC2 10
11
12
36
35
34
33
32
31 VSS
30 VDD
29
28
27
26
25
PIC24F(V)XXKMX04
13 14 15 16 17 18 19 20 21 22 23 24
PGED1
PGEC1
PGED1
PGEC1
VSS
VDD
DS30625D-page 4
PGEC3
48-Pin QFN
44 43 42 41 40 39 38 37 36 35 34
33
1
32
2
3
31
30
4
29 VSS
5
PIC24F(V)XXKMX04
28 VDD
6
(1)
VCAP
27
7
26
PGED2 8
25
PGEC2 9
24
10
11
23
12 13 14 15 16 17 18 19 20 21 22
Note 1:
PGEC2
PGED2
VCAP(1)
VDD
VSS
PGED1 1
PGEC1 2
3
4
VSS 5
6
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VSS
VDD
28-Pin QFN
PIC24FVXXKMXXX devices only. PIC24FXXKMXXX devices do not use VCAP.
 2011-2013 Microchip Technology Inc.
PIC24FXXKMXXX/KLXXX
2.2
Memory Map
Table 2-2 provides the program memory and data
EEPROM size, and the number of memory rows
present in each device variant.
The program memory map for the PIC24FXXKMXXX/KLXXX devices extends from 000000h to
FFFFFEh. Code storage is located at the base of the
memory map and supports up to 5.5K instruction words
(about 16 Kbytes).
The erase operation can be done on one word, half of
a row or one row at a time. The program operation can
be done only one word at a time.
Additionally, PIC24FXXKMXXX/KLXXX family devices
have an on-chip data EEPROM. This data EEPROM is
mapped to the program memory area from location,
7FFE00h to 7FFFFEh.
TABLE 2-2:
MEMORY SIZES FOR PIC24FXXKMXXX/KLXXX DEVICES
Program Memory
Upper Address
(Instruction Words)
Flash Rows
Data EEPROM Size
(Words)
Data EEPROM
Rows
PIC24F16KL4XX
2BFEh (5.5K)
176
256
32
PIC24F08KL4XX
15FEh (2.75K)
88
256
32
PIC24F08KL3XX
15FEh (2.75K)
88
128
16
PIC24F08KL2XX
15FEh (2.75K)
88
—
—
PIC24F04KL1XX
0AFEh (1.375K)
44
—
—
PIC24FV16KM204
2BFEh (5.5K)
176
256
32
PIC24FV16KM202
2BFEh (5.5K)
176
256
32
PIC24FV08KM204
15FEh (2.75K)
88
256
32
PIC24FV08KM202
15FEh (2.75K)
88
256
32
PIC24FV16KM104
2BFEh (5.5K)
176
256
32
PIC24FV16KM102
2BFEh (5.5K)
176
256
32
PIC24FV08KM102
15FEh (2.75K)
88
256
32
PIC24FV08KM101
15FEh (2.75K)
88
256
32
PIC24F16KM204
2BFEh (5.5K)
176
256
32
PIC24F16KM202
2BFEh (5.5K)
176
256
32
PIC24F08KM204
15FEh (2.75K)
88
256
32
PIC24F08KM202
15FEh (2.75K)
88
256
32
PIC24F16KM104
2BFEh (5.5K)
176
256
32
PIC24F16KM102
2BFEh (5.5K)
176
256
32
PIC24F08KM102
15FEh (2.75K)
88
256
32
PIC24F08KM101
15FEh (2.75K)
88
256
32
Device
 2011-2013 Microchip Technology Inc.
DS30625D-page 5
PIC24FXXKMXXX/KLXXX
Locations, 800000h through 8007FEh, are reserved for
executive code memory. This region stores the debugging executive and the Diagnostic Words. The debug
executive is used for in-circuit debugging. This region
of memory cannot be used to store user code.
TABLE 2-3:
CONFIGURATION REGISTER
LOCATIONS
Configuration Register
Address
FBS
F80000
The device Configuration registers are implemented
from location, F80000h to F80010h, and can be erased
or programmed, one register at a time. Table 2-3
provides the implemented Configuration registers and
their locations.
FGS
F80004
FWDT
F8000A
Locations, FF0000h and FF0002h, are reserved for the
Device ID registers. These bits can be used by the
programmer to identify the device type that is being programmed. For more information, see Section 4.0
“Device ID”. The Device ID registers read out normally,
even after code protection is applied.
FPOR
F8000C
FICD
F8000E
FOSCSEL
F80006
FOSC
F80008
Figure 2-4 illustrates the memory map for the
PIC24FXXKMXXX/KLXXX family variants.
DS30625D-page 6
 2011-2013 Microchip Technology Inc.
PIC24FXXKMXXX/KLXXX
FIGURE 2-4:
PROGRAM MEMORY MAP
000000h
User Flash
Code Memory
(5632 x 24-bit)
User Memory
Space
00AFEh/0015FEh/002BFEh(1)
Reserved
Data EEPROM(2)
Executive
Code Memory
(1016 x 24-bit)
Configuration Memory
Space
Diagnostic Words
7FFE00h/7FFF00h(1)
800000h
8007F2h
8007F4h
8007FEh
800800h
Reserved
Configuration Registers
Device ID
(2 x 16-bit)
F80000h
F80010h
FEFFFEh
FF0000h
FF0002h
FF0004h
Reserved
FFFFFEh
Note 1:
2:
The upper address boundaries for user program memory are device-specific. See Table 2-2 for details.
PIC24F08KL2XX and PIC24F04KL1XX devices do not have a data EEPROM section.
 2011-2013 Microchip Technology Inc.
DS30625D-page 7
PIC24FXXKMXXX/KLXXX
3.0
DEVICE PROGRAMMING –
ICSP
FIGURE 3-1:
HIGH-LEVEL ICSP™
PROGRAMMING FLOW
Start
The ICSP method is a special programming
protocol that allows reading and writing to the
PIC24FXXKMXXX/KLXXX device family memory.
ICSP is the most direct method used to program a
device. This is accomplished by applying control codes
and instructions, serially to the device, using PGECx
and PGEDx pins.
Enter ICSP™ Mode
Perform Bulk
Erase
In ICSP mode, the system clock is taken from the
PGECx pin, regardless of the device’s oscillator Configuration bits. All of the instructions are shifted serially to
an internal buffer, loaded into the Instruction Register
(IR) and then executed. No program is fetched from the
internal memory. Instructions are fed in, 24 bits at a time.
PGEDx is used to shift data in, and PGECx is used as
both the serial shift clock and the CPU execution clock.
Program Memory
Verify Program
Program Data EEPROM Memory
Note:
3.1
During ICSP operation, the operating
frequency of PGECx should not exceed
8 MHz.
Verify Data EEPROM Memory
Overview of the Programming
Process
Program Configuration Bits
Figure 3-1 illustrates the high-level overview of the
programming process.
Verify Configuration Bits
After entering the ICSP mode, perform the following:
1.
2.
3.
4.
5.
Bulk Erase the device.
Program and verify the code memory.
Program and verify the data EEPROM memory.
Program and verify the device configuration.
Program the code-protect the Configuration bits,
if required.
Exit ICSP Mode
End
TABLE 3-1:
3.2
ICSP Operation
Upon entry into ICSP mode, the CPU is Idle. An internal state machine governs the execution of the CPU. A
4-bit control code is clocked in, using PGECx and
PGEDx, and this control code is used to command the
CPU (see Table 3-1).
The SIX control code is used to send instructions to the
CPU for execution and the REGOUT control code is
used to read data out of the device via the VISI register.
DS30625D-page 8
CPU CONTROL CODES IN
ICSP™ MODE
4-Bit
Mnemonic
Control Code
Description
0000b
SIX
Shift in 24-bit instruction
and execute.
0001b
REGOUT
Shift out the VISI
(0784h) register.
0010b-1111b N/A
This is reserved.
 2011-2013 Microchip Technology Inc.
PIC24FXXKMXXX/KLXXX
3.2.1
SIX SERIAL INSTRUCTION
EXECUTION
The SIX control code allows execution of the
PIC24FXXKMXXX/KLXXX family assembly instructions. When the SIX code is received, the CPU is
suspended for 24 clock cycles, as the instruction is then
clocked into the internal buffer. Once the instruction is
shifted in, the state machine allows it to be executed over
the next four PGC clock cycles. While the received
instruction is executed, the state machine simultaneously
shifts in the next 4-bit command (see Figure 3-2).
Coming out of Reset, the first 4-bit control code is
always forced to SIX and a forced NOP instruction is
executed by the CPU. Five additional PGECx clocks
are needed on start-up, thereby resulting in a 9-bit SIX
command instead of the normal 4-bit SIX command.
After the forced SIX is clocked in, the ICSP operation
returns to normal. That is, the next 24 clock cycles load
the first instruction word to the CPU.
• The CPU does not automatically stall to account
for pipeline changes. A CPU stall occurs when an
instruction modifies a register, which is used by
the instruction immediately following the CPU stall
for Indirect Addressing. During normal operation,
the CPU forces a NOP while the new data is read.
To account for this, while using ICSP, any indirect
references to a recently modified register should
be proceeded with a NOP.
For example, MOV #0x0,W0, followed by MOV
[W0],W1, must have a NOP inserted in between.
If a two-cycle instruction modifies a register, which is
used indirectly, it requires two following NOPs. One
NOP executes the second half of the instruction and
the other NOP stalls the CPU to correct the pipeline.
For example, TBLWTL [W0++],[W1], should be
followed by 2 NOPs.
• The device Program Counter (PC) continues to
automatically increment during the ICSP instruction execution, even though the Flash memory is
not being used. As a result, it is possible for the
PC to be incremented so that it points to invalid
memory locations.
Note:
To account for this forced NOP, all example
codes in this specification begin with a
NOP to ensure that no data is lost.
3.2.1.1
Differences Between SIX Instruction
Execution and Normal Instruction
Execution
Examples of invalid memory spaces are unimplemented Flash addresses or the vector space
(location, 0x0 to 0x1FF).
There are some differences between executing instructions using the SIX ICSP command and normal device
instruction execution. As a result, the code examples in
this specification might not match those required to
perform the same operations during normal device
operation.
If the PC ever points to these locations, it causes
the device to reset, possibly interrupting the ICSP
operation. To prevent this, instructions should be
periodically executed to reset the PC to a safe
space. The optimal method of achieving this is to
perform a “GOTO 0x200” instruction.
The differences are:
• Two-word instructions require 2 SIX operations to
clock in all of the necessary data.
Examples of two-word instructions are GOTO and
CALL.
• Two-cycle instructions require 2 SIX operations to
complete. The first SIX operation shifts in the
instruction and begins to execute it. A second SIX
operation, which should shift in a NOP to avoid losing data, allows the CPU clocks required to finish
executing the instruction.
Examples of two-cycle instructions are Table Read
(TBLRD) and Table Write (TBLWT) instructions.
3.2.2
REGOUT SERIAL INSTRUCTION
EXECUTION
The REGOUT control code allows the data to be
extracted from the device in ICSP mode. It is used to
clock the contents of the VISI register out of the device
and over the PGEDx pin. After the REGOUT control
code is received, the CPU is held Idle for 8 cycles. After
this, an additional 16 cycles are required to clock the
data out (see Figure 3-3).
The REGOUT code is unique, as the PGEDx pin is an
input when the control code is transmitted to the
device. However, after the control code is processed,
the PGEDx pin becomes an output as the VISI register
is shifted out.
Note 1: After the contents of VISI are shifted out,
the PIC24FXXKMXXX/KLXXX devices
maintain PGEDx as an output until the first
rising edge of the next clock is received.
2: Data changes on the falling edge and
latches on the rising edge of PGECx.
For all data transmissions, the Least
Significant bit (LSb) is transmitted first.
 2011-2013 Microchip Technology Inc.
DS30625D-page 9
PIC24FXXKMXXX/KLXXX
FIGURE 3-2:
SIX SERIAL EXECUTION
P1
1
2
4
3
5
6
7
8
9
1
2
3
4
5
6
7
8
17 18 19 20 21 22 23 24
1
2
3
4
PGECx
P4
P3
P2
PGEDx 0
0
0
0
0
Execute PC – 1,
Fetch SIX
Control Code
0
0
0
0
P4A
P1A
P1B
LSb X
X
X
X
X
X
X
X
X
X
X
X
X
X MSb
0
24-Bit Instruction Fetch
0
0
0
Execute 24-Bit
Instruction, Fetch
Next Control Code
Only for
Program
Memory Entry
PGEDx = Input
FIGURE 3-3:
1
REGOUT SERIAL EXECUTION
2
3
4
1
2
7
8
1
2
3
4
5
6
11
12 13 14
15 16
1
2
3
4
PGECx
P4
PGEDx
1
0
0
P4A
P5
0
Execute Previous Instruction, CPU Held in Idle
Fetch REGOUT Control Code
PGEDx = Input
DS30625D-page 10
LSb 1
2
3
4
...
10 11 12 13 14 MSb
Shift Out VISI Register<15:0>
PGEDx = Output
0
0
0
0
No Execution Takes Place,
Fetch Next Control Code
PGEDx = Input
 2011-2013 Microchip Technology Inc.
PIC24FXXKMXXX/KLXXX
3.3
3.3.2
Entering ICSP Mode
3.3.1
Entering the ICSP Program/Verify mode, using the VPP
pin, is the same as entering the mode using MCLR.
The only difference is the programming voltage applied
to VPP is VIHH, and before presenting the key sequence
on PGEDx, an interval of at least P18 should elapse
(see Figure 3-5).
LOW-VOLTAGE ICSP ENTRY
As illustrated in Figure 3-4, the following processes are
involved in entering ICSP Program/Verify mode using
MCLR:
1.
2.
3.
MCLR is briefly driven high, then low.
A 32-bit key sequence is clocked into PGEDx.
MCLR is then driven high within a specified
period of time and held.
Once the key sequence is complete, an interval of at
least P7 should elapse and the voltage should remain
at VIHH. The voltage, VIHH, must be held at that level for
as long as the Program/Verify mode is to be maintained. An interval of at least P7 must elapse before
presenting the data on PGEDx.
The programming voltage, VIH, is applied to MCLR; this
is VDD in the case of PIC24FXXKMXXX/KLXXX
devices. There is no minimum time requirement for
holding at VIH. After VIH is removed, an interval of at
least P18 must elapse before presenting the key
sequence on PGEDx.
Signals appearing on PGEDx before P7 has elapsed
will not be interpreted as valid.
Upon a successful entry, the program memory can be
accessed and programmed in serial fashion. While in
ICSP mode, all unused I/Os are placed in a
high-impedance state.
The key sequence is a specific 32-bit pattern:
‘0100 1101 0100 0011 0100 1000 0101
0001’ (more easily remembered as 4D434851h in
hexadecimal). The device will enter Program/Verify
mode only if the sequence is valid. The Most Significant
bit (MSb) of the most significant nibble must be shifted in
first.
3.3.3
CODE-PROTECT ICSP ENTRY
When code protection is employed on the PIC24FXXKMXXX/KLXXX devices (BWRP, GSS0 or GWRP = 0),
then the voltage on VDD must be above VBULK in order
to erase, and then program, the device. Care must be
taken in the design and layout of a board so that any
parts connected to VDD can withstand what may be an
increase in voltage if the device is running below
VBULK.
Once the key sequence is complete, VIH must be
applied to MCLR and held at that level for as long as the
Program/Verify mode is to be maintained. An interval of
at least P19 and P7 must elapse before presenting data
on PGEDx. Signals appearing on PGECx, before P7 has
elapsed, would not be interpreted as valid.
FIGURE 3-4:
HIGH-VOLTAGE ICSP ENTRY
ENTERING ICSP™ MODE USING LOW-VOLTAGE ENTRY
P6
P19
P14
VIH
MCLR
P7
VIH
VDD
Program/Verify Entry Code = 4D434851h
0
b31
PGEDx
1
b30
0
b29
0
b28
1
b27
...
0
b3
0
b2
0
b1
1
b0
PGECx
P1A
P1B
P18
FIGURE 3-5:
ENTERING ICSP™ MODE USING HIGH-VOLTAGE ENTRY
P7
VIHH
P6
VPP
VDD
Program/Verify Entry Code = 4D434851h
0
b31
PGEDx
1
b30
0
b29
0
b28
1
b27
...
0
b3
0
b2
0
b1
1
b0
PGECx
P18
 2011-2013 Microchip Technology Inc.
P1A
P1B
DS30625D-page 11
PIC24FXXKMXXX/KLXXX
3.4
Flash Memory Programming in
ICSP Mode
3.4.1
PROGRAMMING OPERATIONS
The NVMCON register controls the Flash memory write
and erase operations. To program the device, set the
NVMCON register to select the type of erase operation
(see Table 3-2) or write operation (see Table 3-3). Set
the WR control bit (NVMCON<15>) to initiate the
program.
In ICSP mode, all programming operations are
self-timed. There is an internal delay between setting
and automatic clearing of the WR control bit when the
programming operation is complete. Refer to
Section 5.0 “AC/DC Characteristics and Timing
Requirements” for information on the delays
associated with various programming operations.
3.4.2
NVMCON
Value
All erase and write cycles are self-timed. The WR bit
should be polled to determine if the erase or write cycle
is complete. Start a programming cycle as follows:
NVMCON, #WR
4064h
Erase the code memory and
Configuration registers (does not erase
executive code and Device ID 
registers).
404Ch
Erase the General Segment and
Configuration bits associated with it.
4068h
Erase the boot segment and
Configuration bits associated with it.
405Ah(1)
Erase four rows of code memory.
4059h
(1)
Erase two rows of code memory.
4058h
(1)
Erase a row of code memory.
4050h
Erase the entire data EEPROM
memory and Configuration bits
associated with it.
405Ah(1)
Erase eight words of data EEPROM
memory.
4059h(1)
Erase four words of data EEPROM
memory.
4058h(1)
Erase one word of data EEPROM
memory.
4054h
Erase all of the Configuration registers
(except the code-protect Configuration
bits).
4058h(1)
Erase all of the Configuration registers
except for FBS and FGS.
Note 1:
The destination address decides the
region (code memory, data EEPROM
memory or Configuration register) of the
erased rows/words.
TABLE 3-3:
NVMCON
Value
NVMCON VALUES FOR
WRITE OPERATIONS
Write Operation8
4004h(1)
Write one Configuration register.
4004h(1)
Program one row (32 instruction words)
of code memory or executive memory.
4004h(1)
Program one word of data EEPROM
memory.
Note 1:
DS30625D-page 12
NVMCON VALUES FOR
ERASE OPERATIONS
Erase Operation
STARTING AND STOPPING A
PROGRAMMING CYCLE
The WR bit (NVMCON<15>) is used to start an erase
or write cycle. Initiate the programming cycle by setting
the WR bit.
BSET
TABLE 3-2:
The destination address decides the
region (code memory, data EEPROM
memory or Configuration register) of the
erased rows/words.
 2011-2013 Microchip Technology Inc.
PIC24FXXKMXXX/KLXXX
3.5
FIGURE 3-6:
Erasing Program Memory
To erase the program memory (all of the code memory,
data memory and Configuration bits, including the
code-protect bits), set the NVMCON register to 4064h
and then execute the programming cycle.
Figure 3-6 illustrates the ICSP programming process
for Bulk Erase. This process includes the ICSP command code, which must be transmitted (for each
instruction), LSb first, using the PGECx and PGEDx
pins (see Figure 3-2).
BULK ERASE FLOW
Start
Write 4064h to NVMCON SFR
Set the WR bit to Initiate Erase
Delay P11 + P10 Time
Table 3-4 provides the steps for executing the serial
instruction for the Bulk Erase mode.
Note:
End
Program memory must be erased before
writing any data to program memory.
TABLE 3-4:
Command
(Binary)
SERIAL INSTRUCTION EXECUTION FOR CHIP ERASE
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Set the NVMCON to erase the entire program memory.
0000
0000
24064A
883B0A
MOV
MOV
#0x4064, W10
W10, NVMCON
Step 3: Set the TBLPAG and perform a dummy Table Write to select the erased memory.
0000
0000
0000
0000
0000
0000
200000
880190
200000
BB0800
000000
000000
MOV
MOV
MOV
TBLWTL
NOP
NOP
#<PAGEVAL>, W0
W0, TBLPAG
#0x0000, W0
W0, [W0]
BSET
NOP
NOP
NVMCON, #WR
Step 4: Initiate the erase cycle.
0000
0000
0000
A8E761
000000
000000
Step 5: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.
0000
0000
0000
0000
0000
0000
0001
0000
000000
040200
000000
803B02
883C22
000000
<VISI>
000000
 2011-2013 Microchip Technology Inc.
NOP
GOTO
0x200
NOP
MOV
NVMCON, W2
MOV
W2, VISI
NOP
Clock out the contents of the VISI register.
NOP
DS30625D-page 13
PIC24FXXKMXXX/KLXXX
3.6
Writing Code Memory
The procedure for writing code memory is the same as
writing the Configuration registers. The difference is
that the 32 instruction words are programmed, one at a
time. To facilitate this operation, working registers,
W0:W5, are used as temporary holding registers for the
data to be programmed. Figure 3-8 illustrates the code
memory writing flow.
Table 3-5 provides the ICSP programming details,
including the serial pattern with the ICSP command
code, which must be transmitted, LSb first, using the
PGECx and PGEDx pins (see Figure 3-2).
In Step 1 of Table 3-5, the Reset vector is exited, in
Step 2, the NVMCON register is initialized for programming a full row of code memory and in Step 3, the 24-bit
starting destination address for programming is loaded
into the TBLPAG and W7 registers. The upper byte of
the starting destination address is stored in TBLPAG
and the lower 16 bits of the destination address are
stored in W7.
To minimize the programming time, a packed
instruction format is used (see Figure 3-7).
code memory is programmed in 32 instruction words at
a time, Steps 3 to 5 are repeated eight times to load all
the write latches (see Step 6).
After the write latches are loaded, initiate programming
by writing to the NVMCON register in Steps 7 and 8. In
Step 9, the internal PC is reset to 200h. This is a
precautionary measure to prevent the PC from incrementing to unimplemented memory when large
devices are being programmed. Finally, in Step 10,
repeat Steps 3 through 9 until all of the code memory is
programmed.
FIGURE 3-7:
PACKED INSTRUCTION
WORDS IN W0:W5
15
8
W0
7
0
LSW0
W1
MSB1
W2
MSB0
LSW1
W3
LSW2
W4
MSB3
W5
MSB2
LSW3
In Step 4 of Table 3-5, four packed instruction words
are stored in working registers, W0:W5, using the MOV
instruction. The Read Pointer, W6, is initialized.
Figure 3-7 illustrates the contents of W0:W5, holding
the packed instruction word data. In Step 5, eight
TBLWT instructions are used to copy the data from
W0:W5 to the write latches of the code memory. Since
TABLE 3-5:
Command
(Binary)
SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Set the NVMCON to program 32 instruction words.
0000
0000
24004A
883B0A
MOV
MOV
#0x4004, W10
W10, NVMCON
Step 3: Initialize the Write Pointer (W7) for the TBLWT instruction.
0000
0000
0000
200xx0
880190
2xxxx7
MOV
MOV
MOV
#<DestinationAddress23:16>, W0
W0, TBLPAG
#<DestinationAddress15:0>, W7
Step 4: Load W0:W5 with the next 4 instruction words to program.
0000
0000
0000
0000
0000
0000
DS30625D-page 14
2xxxx0
2xxxx1
2xxxx2
2xxxx3
2xxxx4
2xxxx5
MOV
MOV
MOV
MOV
MOV
MOV
#<LSW0>, W0
#<MSB1:MSB0>, W1
#<LSW1>, W2
#<LSW2>, W3
#<MSB3:MSB2>, W4
#<LSW3>, W5
 2011-2013 Microchip Technology Inc.
PIC24FXXKMXXX/KLXXX
TABLE 3-5:
Command
(Binary)
SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY (CONTINUED)
Data
(Hex)
Description
Step 5: Set the Read Pointer (W6) and load the (next set of) write latches.
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
EB0300
000000
BB0BB6
000000
000000
BBDBB6
000000
000000
BBEBB6
000000
000000
BB1BB6
000000
000000
BB0BB6
000000
000000
BBDBB6
000000
000000
BBEBB6
000000
000000
BB1BB6
000000
000000
CLR
NOP
TBLWTL
NOP
NOP
TBLWTH.B
NOP
NOP
TBLWTH.B
NOP
NOP
TBLWTL
NOP
NOP
TBLWTL
NOP
NOP
TBLWTH.B
NOP
NOP
TBLWTH.B
NOP
NOP
TBLWTL
NOP
NOP
W6
[W6++], [W7]
[W6++], [W7++]
[W6++], [++W7]
[W6++], [W7++]
[W6++], [W7]
[W6++], [W7++]
[W6++], [++W7]
[W6++], [W7++]
Step 6: Repeat Steps 3 though 5, eight times, to load the write latches for 32 instructions.
Step 7: Initiate the write cycle.
0000
0000
0000
A8E761
000000
000000
BSET
NOP
NOP
NVMCON, #WR
Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.
0000
0000
0000
0000
0000
0001
0000
040200
000000
803B02
883C22
000000
<VISI>
000000
GOTO
0x200
NOP
MOV
NVMCON, W2
MOV
W2, VISI
NOP
Clock out contents of the VISI register.
NOP
Step 9: Reset device internal PC.
0000
0000
040200
000000
GOTO
NOP
0x200
Step 10: Repeat Steps 3 through 9 until the entire code memory is programmed.
 2011-2013 Microchip Technology Inc.
DS30625D-page 15
PIC24FXXKMXXX/KLXXX
FIGURE 3-8:
PROGRAM CODE MEMORY FLOW
Start
N=1
LoopCount = 0
Configure
Device for
Writes
Load 2 Bytes
to Write
Buffer at <Addr>
N=N+1
No
All
bytes
written?
Yes
N=1
LoopCount =
LoopCount + 1
Start Write Sequence
and Poll for WR bit
to be Cleared
No
All
locations
done?
Yes
End
DS30625D-page 16
 2011-2013 Microchip Technology Inc.
PIC24FXXKMXXX/KLXXX
3.7
Writing Data EEPROM
Figure 3-9 illustrates the flow of programming the data
EEPROM memory. The procedure is the same as
writing code memory. The only difference is that just
one word is programmed in each operation. When
writing data EEPROM, one word is programmed during
each operation. Working register, W0, is used as a
temporary holding register for the data to be
programmed.
TABLE 3-6:
Command
(Binary)
Table 3-6 provides the ICSP programming details for
writing data EEPROM.
Note:
When writing to EEPROM, always set the
TBLPAG register to 7Fh. This is the upper
byte address of all locations of data
EEPROM.
INSTRUCTION EXECUTION FOR WRITING DATA EEPROM
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Set the NVMCON to program 1 data word.
0000
0000
24004A
883B0A
MOV
MOV
#0x4004, W10
W10, NVMCON
Step 3: Initialize the Write Pointer (W7) for the TBLWT instruction.
0000
0000
0000
2007F0
880190
2FExx7
MOV
MOV
MOV
#0x7F, W0
W0, TBLPAG
#<DestinationAddress15:0>, W7
Step 4: Load W0 with the data word to program and load the write latch.
0000
0000
0000
0000
2xxxx0
BB1B80
000000
000000
MOV
TBLWTL
NOP
NOP
#<Data_Word_Value>, W0
W0, [W7++]
BSET
NOP
NOP
NVMCON, #WR
Step 5: Initiate the write cycle.
0000
0000
0000
A8E761
000000
000000
Step 6: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.
0000
0000
0000
0000
0000
00001
0000
040200
000000
803B02
883C22
000000
<VISI>
000000
GOTO
0x200
NOP
MOV
NVMCON, W2
MOV
W2, VISI
NOP
Clock out contents of the VISI register.
NOP
Step 7: Reset device internal PC.
0000
0000
040200
000000
GOTO
NOP
0x200
Step 8: Repeat Steps 4 through 7 until the entire data EEPROM memory is programmed.
 2011-2013 Microchip Technology Inc.
DS30625D-page 17
PIC24FXXKMXXX/KLXXX
FIGURE 3-9:
PROGRAM DATA EEPROM MEMORY FLOW
Start
LoopCount = 0
Configure
Device for
Writes
Load 2 Bytes
to Write
Buffer at <Addr>
LoopCount =
LoopCount + 1
Start Write Sequence
and Poll for WR bit
to be Cleared
No
All
locations
done?
Yes
End
DS30625D-page 18
 2011-2013 Microchip Technology Inc.
PIC24FXXKMXXX/KLXXX
3.8
Writing Configuration Registers
The procedure for writing the Configuration registers is
the same as for writing code memory. The only difference is that only one word is programmed in each
operation. When writing Configuration registers, one
word is programmed during each operation. Only working register, W0, is used as a temporary holding register
for the data to be programmed.
Table 3-7 provides the default values of the
Configuration registers.
Note:
When writing to the Configuration registers, always set the TBLPAG register to
F8h. This is the upper byte address of all
locations of the Configuration registers.
Table 3-7 provides the ICSP programming details for
programming the Configuration registers, including the
serial pattern with the ICSP command code. This code
must be transmitted, LSb first, using the PGECx and
PGEDx pins (see Figure 3-2).
In Step 1 of Table 3-8, the Reset vector is exited. In
Step 2 and 4, the 24-bit starting destination address for
programming is loaded into the TBLPAG register and
the W7 register. In Step 3, the NVMCON register is initialized for programming the Configuration register. In
Step 5, the Configuration register data is loaded to W6.
In Step 6, TBLWT instructions are used to copy the data
from W6 to the write latch of the Configuration register.
 2011-2013 Microchip Technology Inc.
After the write latch is loaded, the programming is initiated by setting the write bit in the NVMCON register in
Steps 7 and 8. In Step 9, the internal PC is reset to 200h.
This is a precautionary measure to prevent the PC from
incrementing to unimplemented memory when large
devices are being programmed. Finally, in Step 10,
repeat Steps 5 through 9 to write other Configuration
registers. While programming other Configuration registers, load W6 with their respective values and W7 with
their respective addresses.
TABLE 3-7:
Configuration
Registers
DEFAULT VALUES FOR
CONFIGURATION REGISTER
SERIAL INSTRUCTION
Value
FBS
0Fh
FGS
03h
FOSCSEL
E1h
FOSC
3Bh
FWDT
DFh
(1)
FPOR
FICD
Note 1:
FBh
E3h
The I2C1SEL bit (FPOR<4>) is only
implemented on
PIC24FXXKLX02/KMX02/KMX04 devices
and in all other devices, it should be
programmed as ‘1’.
DS30625D-page 19
PIC24FXXKMXXX/KLXXX
TABLE 3-8:
Command
(Binary)
SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERS
Data
(Hex)
Command
(Binary)
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Initialize the Write Pointer (W7) for the TBLWT instruction.
0000
200007
MOV
#0x0000, W7
Step 3: Set the NVMCON register to program the Configuration registers.
0000
0000
24004A
883B0A
MOV
MOV
#0x4004, W10
W10, NVMCON
Step 4: Initialize the TBLPAG register.
0000
0000
200F80
880190
MOV
MOV
#0xF8, W6
W0, TBLPAG
Step 5: Load the Configuration register data to W6.
0000
2xxxx6
MOV
#<FBS_VALUE>, W6
Step 6: Write the Configuration register data to the write latch and increment the Write Pointer.
0000
0000
0000
0000
000000
BB1B86
000000
000000
NOP
TBLWTL
NOP
NOP
W6, [W7++]
Step 7: Initiate the write cycle.
0000
0000
0000
A8E761
000000
000000
BSET
NOP
NOP
NVMCON, #WR
Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.
0000
0000
0000
0000
0000
0001
0000
040200
000000
803B02
883C22
000000
<VISI>
000000
GOTO
0x200
NOP
MOV
NVMCON, W2
MOV
W2, VISI
NOP
Clock out contents of the VISI register.
NOP
Step 9: Reset device internal PC.
0000
0000
040200
000000
GOTO
NOP
0x200
Step 10: Repeat Steps 5 through 9 to write other Configuration registers. Load W6 with their respective values and
W7 with their respective addresses.
DS30625D-page 20
 2011-2013 Microchip Technology Inc.
PIC24FXXKMXXX/KLXXX
3.8.1
CODE-PROTECT 
CONFIGURATION BITS
The FBS and FGS Configuration registers are special
Configuration registers which control the code protection
for the boot segment and General Segment, respectively. For each segment, two forms of code protection
are provided. One form prevents code memory from
being written (write protection), while the other prevents
code memory from being read (read protection).
It is imperative that all code protection bits should be ‘1’
while the device is being programmed and verified.
Only after the device is programmed and verified,
should any of the above bits be programmed to ‘0’.
Note:
All bits in the FBS and FGS Configuration
registers can only be programmed to a
value of ‘0‘. Bulk Erasing the chip is the
only way to reprogram the code-protect
bits from on (‘0’) to off (‘1’).
The BWRP and GWRP bits control write protection,
and the BSS and GSS0 bits control read protection.
When write protection is enabled, any programming
operation to code memory will fail. When read protection is enabled, any read from code memory will cause
a 00h to be read, regardless of the actual contents of
the code memory.
TABLE 3-9:
Bit Field
PIC24FXXKMXXX/KLXXX FAMILY CONFIGURATION BITS
Register
Description
BOREN<1:0>
FPOR<1:0>
Brown-out Reset Enable bits
11 = Brown-out Reset is enabled in hardware; SBOREN bit is disabled
10 = Brown-out Reset is enabled only while device is active and disabled in
Sleep; SBOREN bit is disabled
01 = Brown-out Reset is controlled with the SBOREN bit setting
00 = Brown-out Reset is disabled in hardware; SBOREN bit is disabled
BORV<1:0>
FPOR<6:5>
Brown-out Reset Voltage bits
11 = Brown-out Reset is set to low trip point(1)
10 = Brown-out Reset is set to middle trip point(1)
01 = Brown-out Reset is set to high trip point(1)
00 = Downside protection on POR is enabled (low-power BOR is selected)
BSS<2:0>
FBS<3:1>
Boot Segment Program Flash Code Protection bits
111 = No boot segment; all program memory space is General Segment
110 = Standard security; boot segment starts at 0200h, ends at 0AFEh
101 = Standard security; boot program Flash segment starts at 0200h, ends
at 15FEh(2)
100 = Reserved
011 = Reserved
010 = High-security boot segment starts at 0200h, ends at 0AFEh
001 = High-security, boot segment starts at 0200h, ends at 15FEh(2)
000 = Reserved
BWRP
FBS<0>
Boot Segment Program Flash Write Protection bit
1 = Boot segment may be written
0 = Boot segment is write-protected
DEBUG
FICD<7>
Background Debugger Enable bit
1 = Background debugger is disabled
0 = Background debugger functions are enabled
Note 1:
2:
3:
4:
For the particular value of a trip point, refer to the specific device data sheet.
This selection is available only on PIC24F16KLXXX/KMXXX devices.
This applies only to 28-pin devices.
The MCLRE Configuration bit can only be changed when using the VPP-Based Test mode entry. This 
prevents a user from accidentally locking out the device from a low-voltage test entry.
 2011-2013 Microchip Technology Inc.
DS30625D-page 21
PIC24FXXKMXXX/KLXXX
TABLE 3-9:
Bit Field
PIC24FXXKMXXX/KLXXX FAMILY CONFIGURATION BITS (CONTINUED)
Register
Description
FCKSM<1:0>
FOSC<7:6>
FNOSC<2:0>
FOSCSEL<2:0> Oscillator Selection bits
111 = Fast RC Oscillator with Divide-by-N (FRCDIV)
110 = 500 kHz Low-Power FRC Oscillator with Divide-by-N (LPFRCDIV)
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (HS+PLL, EC+PLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Divide-by-N with PLL module (FRCDIV+PLL)
000 = Fast RC Oscillator (FRC)
FWDTEN<1:0>
FWDT<7,5>
Watchdog Timer Enable bits
11 = WDT is enabled in hardware
10 = WDT is controlled with the SWDTEN bit
01 = WDT is enabled only while the device is active and is disabled in Sleep;
SWDTEN bit is disabled
00 = WDT is disabled in hardware; SWDTEN bit is disabled
GSS0
FGS<1>
General Segment Code Flash Code Protection bit
1 = No protection
0 = Standard security is enabled
GWRP
FGS<0>
General Segment Code Flash Write Protection bit
1 = General Segment may be written
0 = General Segment is write-protected
ICS<1:0>
FICD<1:0>
ICD Pin Placement Select bits
11 = ICD EMUC/EMUD pins are shared with PGEC1/PGED1
10 = ICD EMUC/EMUD pins are shared with PGEC2/PGED2
01 = ICD EMUC/EMUD pins are shared with PGEC3/PGED3
00 = Reserved; do not use
IESO
FOSCSEL<7>
Internal External Switchover bit
1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled)
0 = Internal External Switchover mode is disabled (Two-Speed Start-up is
disabled)
I2C1SEL(3)
FPOR<4>
Alternate I2C1 Pin Mapping bit(3)
1 = Default location for SCL1/SDA1 pins
0 = Alternate location for SCL1/SDA1 pins
MCLRE(4)
FPOR<7>
MCLR Pin Enable bit(4)
1 = MCLR pin is enabled; RA5 input pin is disabled
0 = RA5 input pin is enabled; MCLR is disabled
OSCIOFNC
FOSC<2>
CLKO Enable Configuration bit
1 = CLKO output signal is active on the OSCO pin; the primary oscillator must
be disabled or configured for the External Clock mode (EC) for the CLKO
to be active (POSCMD<1:0> = 11 or 00)
0 = CLKO output is disabled
Note 1:
2:
3:
4:
Clock Switching and Monitor Selection Configuration bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
For the particular value of a trip point, refer to the specific device data sheet.
This selection is available only on PIC24F16KLXXX/KMXXX devices.
This applies only to 28-pin devices.
The MCLRE Configuration bit can only be changed when using the VPP-Based Test mode entry. This 
prevents a user from accidentally locking out the device from a low-voltage test entry.
DS30625D-page 22
 2011-2013 Microchip Technology Inc.
PIC24FXXKMXXX/KLXXX
TABLE 3-9:
Bit Field
PIC24FXXKMXXX/KLXXX FAMILY CONFIGURATION BITS (CONTINUED)
Register
Description
LPRCSEL
FOSCSEL<6>
Internal LPRC Oscillator Power Select bit
1 = High-Power/High-Accuracy mode
0 = Low-Power/Low-Accuracy mode
SOSCSRC
FOSCSEL<5>
Secondary Oscillator Clock Source Power Selection Configuration bit
1 = SOSC analog crystal function is available on the SOSCI/SOSCO pins
0 = SOSC crystal is disabled; digital SCLKI function is selected on the SOSCO pin
POSCMD<1:0>
FOSC<1:0>
Primary Oscillator Configuration bits
11 = Primary Oscillator mode is disabled
10 = HS Oscillator mode is selected (4 MHz-25 MHz)
01 = XT Oscillator mode is selected (100 kHz-4 MHz)
00 = External Clock mode is selected
POSCFREQ<1:0> FOSC<4:3>
Primary Oscillator Frequency Range Configuration bits
11 = Primary oscillator/external clock input frequency is greater than 8 MHz
10 = Primary oscillator/external clock input frequency is between 100 kHz and
8 MHz
01 = Primary oscillator/external clock input frequency is less than 100 kHz
00 = Reserved; do not use
PWRTEN
FPOR<3>
Power-up Timer Enable bit
1 = PWRT is enabled
0 = PWRT is disabled
SOSCSEL
FOSC<5>
Secondary Oscillator Select bit
1 = Secondary oscillator is configured for high-power operation
0 = Secondary oscillator is configured for low-power operation
FWPSA
FWDT<4>
WDT Prescaler bit
1 = WDT prescaler ratio of 1:128
0 = WDT prescaler ratio of 1:32
WDTPS<3:0>
FWDT<3:0>
Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1
WINDIS
FWDT<6>
Windowed Watchdog Timer Disable bit
1 = Standard WDT is selected; windowed WDT is disabled
0 = Windowed WDT is enabled
Note 1:
2:
3:
4:
For the particular value of a trip point, refer to the specific device data sheet.
This selection is available only on PIC24F16KLXXX/KMXXX devices.
This applies only to 28-pin devices.
The MCLRE Configuration bit can only be changed when using the VPP-Based Test mode entry. This 
prevents a user from accidentally locking out the device from a low-voltage test entry.
 2011-2013 Microchip Technology Inc.
DS30625D-page 23
PIC24FXXKMXXX/KLXXX
3.9
Reading Code Memory
To read the code memory, execute a series of TBLRD
instructions and clock out the data using the REGOUT
command.
Table 3-10 provides the ICSP programming details for
reading code memory. In Step 1, the Reset vector is
exited. In Step 2, the 24-bit starting source address for
reading is loaded into the TBLPAG register and the W6
register. The upper byte of the starting source address
is stored in TBLPAG and the lower 16 bits of the source
address are stored in W6.
TABLE 3-10:
Command
(Binary)
To minimize the reading time, the packed instruction
word format, which was used for writing, is also used
for reading (see Figure 3-7). In Step 3, the Write
Pointer, W7, is initialized. In Step 4, two instruction
words are read from code memory and clocked out of
the device through the VISI register, using the
REGOUT command. Step 4 is repeated until the
required amount of code memory is read.
SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Initialize TBLPAG and the Read Pointer (W6) for the TBLRD instruction.
0000
0000
0000
200xx0
880190
2xxxx6
MOV
MOV
MOV
#<SourceAddress23:16>, W0
W0, TBLPAG
#<SourceAddress15:0>, W6
Step 3: Initialize the Write Pointer (W7) to point to the VISI register.
0000
0000
207847
000000
MOV
NOP
#VISI, W7
Step 4: Read and clock out the contents of the next two locations of code memory through the VISI register, using 
the REGOUT command.
0000
0000
0000
0001
0000
0000
0000
0000
0000
0000
0000
0001
0000
0000
0000
0000
0001
0000
BA1B96
000000
000000
<VISI>
000000
BADBB6
000000
000000
BAD3D6
000000
000000
<VISI>
000000
BA0BB6
000000
000000
<VISI>
000000
TBLRDL
[W6], [W7]
NOP
NOP
Clock out contents of VISI register.
NOP
TBLRDH
[W6++], [W7]
NOP
NOP
TBLRDH.B [++W6], [W7--]
NOP
NOP
Clock out contents of VISI register.
NOP
TBLRDL
[W6++], [W7]
NOP
NOP
Clock out contents of VISI register.
NOP
Step 5: Reset device internal PC.
0000
0000
040200
000000
GOTO
NOP
0x200
Step 6: Repeat Steps 4 and 5 until the required code memory is read.
DS30625D-page 24
 2011-2013 Microchip Technology Inc.
PIC24FXXKMXXX/KLXXX
3.10
Reading Data EEPROM Memory
The procedure for reading data EEPROM memory is
the same as reading the code memory. The only difference is that the 16-bit data words are read instead of
the 24-bit words.
TABLE 3-11:
Command
(Binary)
Table 3-11 provides the ICSP programming details for
reading data memory.
Note:
When reading from EEPROM, always set
the TBLPAG register to 7Fh. This is the
upper byte address of all locations of data
EEPROM.
SERIAL INSTRUCTION EXECUTION FOR READING DATA EEPROM MEMORY
Data
(Hex)
Description
Step 1: Exit Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Initialize TBLPAG and the Read Pointer (W6) for the TBLRD instruction.
0000
0000
0000
2007F0
880190
2FExx6h
MOV
MOV
MOV
#0x7F, W0
W0, TBLPAG
#<SourceAddress15:0>, W6;(FExx)
Step 3: Initialize the Write Pointer (W7) to point to the VISI register.
0000
0000
207847
000000
MOV
NOP
#VISI, W7
Step 4: Read and clock out the contents of the next location of data EEPROM memory through the VISI register,
using the REGOUT command.
0000
0000
0000
0001
0000
BA1B96
000000
000000
<VISI>
000000
TBLRDL
[W6++], [W7]
NOP
NOP
Clock out contents of VISI register.
NOP
Step 5: Repeat Step 4 until the required data EEPROM memory is read.
Step 6: Reset device internal PC.
0000
0000
040200
000000
GOTO
NOP
 2011-2013 Microchip Technology Inc.
0x200
DS30625D-page 25
PIC24FXXKMXXX/KLXXX
3.11
Reading Configuration Memory
The procedure for reading a Configuration register is
the same as reading the code memory. The only difference is that the 16-bit data words are read (with the
upper byte read being all ‘0‘s) instead of the 24-bit
words. There are eight Configuration registers and they
are read, one register at a time.
TABLE 3-12:
Command
(Binary)
Table 3-12 provides the ICSP programming details for
reading all of the Configuration registers.
Note:
When reading from the Configuration registers, always set the TBLPAG register to
F8h. This is the upper byte address of all
locations of the Configuration registers.
The Read Pointer, W6, should be
initialized to 00h.
SERIAL INSTRUCTION EXECUTION FOR READING ALL THE CONFIGURATION
REGISTERS
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Initialize TBLPAG, the Read Pointer (W6) and the Write Pointer (W7) for the TBLRD instruction.
0000
0000
0000
0000
0000
200F80
880190
200007
207847
000000
MOV
MOV
MOV
MOV
NOP
#0xF8, W0
W0, TBLPAG
#0x0000,W6
#VISI, W7
Step 3: Read the Configuration register and write it to the VISI register (located at 784h) and clock out the 
VISI register, using the REGOUT command.
0000
0000
0000
0001
BA0BB6
000000
000000
<VISI>
TBLRDL
[W6++], [W7]
NOP
NOP
Clock out contents of VISI register.
Step 4: Repeat Step 3 to read other Configuration registers. Load W6 with their respective addresses.
Step 5: Reset device internal PC.
0000
0000
DS30625D-page 26
040200
000000
GOTO
NOP
0x200
 2011-2013 Microchip Technology Inc.
PIC24FXXKMXXX/KLXXX
3.12
Verifying Code Memory, Data
EEPROM Memory and
Configuration Registers
To verify the code memory, read the code memory
space and compare it with the copy held in the programmer’s buffer. To verify the data EEPROM and
Configuration registers, follow the similar procedure.
Figure 3-10 illustrates the verify process flowchart. Memory reads occur, 1 byte at a time; hence, 2 bytes must be
read to compare with the word in the programmer’s
buffer. Refer to Section 3.9 “Reading Code Memory”
for implementation details of reading code memory.
Additionally, the data EEPROM and Configuration
registers can also be verified.
Note:
Code memory should be verified immediately after writing if code protection is
enabled. Since Configuration registers
include the device code protection bit, the
device will not be readable or verifiable if a
device Reset occurs after the code-protect
bits are set (Value = 0).
FIGURE 3-10:
3.13
Exiting ICSP Mode
Exit the Program/Verify mode by removing VIH from
MCLR/VPP, as illustrated in Figure 3-11. The only
requirement to exit is that an interval of P16 should
elapse between the last clock, and program signals on
PGECx and PGEDx, before removing VIH.
FIGURE 3-11:
EXITING ICSP™ MODE
P16
P17
VIH/VIHH
MCLR
VDD
VIH
PGEDx
PGECx
PGD = Input
VERIFY CODE MEMORY
FLOW
Start
Set TBLPTR = 0
Read Low Byte
with Post-Increment
Read High Byte
with Post-Increment
Does
Word = Expect
Data?
No
Failure
Report Error
Yes
No
All
code memory
verified?
Yes
End
 2011-2013 Microchip Technology Inc.
DS30625D-page 27
PIC24FXXKMXXX/KLXXX
4.0
DEVICE ID
TABLE 4-1:
DEVICE IDs
Device ID
The Device ID region of memory can be used to
determine the mask, variant and manufacturing
information about the device. The Device ID region is
2 x 16 bits and it can be read using the READC command. This region of memory is read-only and can also
be read when code protection is enabled.
Table 4-1 provides the Device ID for each device and
Table 4-2 provides the Device ID registers. Table 4-3
describes the bit field of each register.
DEVID
PIC24F16KL402
4B14h
PIC24F16KL401
4B1Eh
PIC24F08KL402
4B04h
PIC24F08KL401
4B0Eh
PIC24F08KL302
4B00h
PIC24F08KL301
4B0Ah
PIC24F08KL201
4B06h
PIC24F08KL200
4B05h
PIC24F04KL101
4B02h
PIC24F04KL100
4B01h
PIC24FV16KM204
TABLE 4-2:
551F
PIC24FV08KM204
5517
PIC24FV16KM104
550F
PIC24FV16KM202
551B
PIC24FV08KM202
5513
PIC24FV16KM102
550B
PIC24FV08KM102
5503
PIC24FV08KM101
5501
PIC24F16KM204
551E
PIC24F08KM204
5516
PIC24F16KM104
550E
PIC24F16KM202
551A
PIC24F08KM202
5512
PIC24F16KM102
550A
PIC24F08KM102
5502
PIC24F08KM101
5500
PIC24FXXKMXXX/KLXXX DEVICE ID REGISTERS
Bit
Address
Name
15
FF0000h
DEVID
FF0002h
DEVREV
TABLE 4-3:
Bit Field
14
13
12
11
10
9
8
7
6
5
FAMID<7:0>
3
2
1
0
DEV<7:0>
—
REV<3:0>
DEVICE ID BITS DESCRIPTION
Register
Description
FAMID<7:0>
DEVID
Encodes the family ID of the device.
DEV<7:0>
DEVID
Encodes the individual ID of the device.
REV<3:0>
DEVREV
Encodes the revision number of the device.
DS30625D-page 28
4
 2011-2013 Microchip Technology Inc.
PIC24FXXKMXXX/KLXXX
4.1
Checksums
4.1.1
Table 4-4 describes how to calculate the checksum for
each device.
CHECKSUM COMPUTATION
Checksums for the PIC24FXXKMXXX/KLXXX family
are 16 bits. The checksum is calculated by summing
the following:
• Contents of the code memory locations
• Contents of the Configuration registers
TABLE 4-4:
All memory locations are summed, one byte at a time,
using only their native data size. More specifically,
Configuration registers are summed by adding the
lower two bytes of these locations (the upper byte is
ignored), while the code memory is summed by adding
all three bytes of the code memory.
CHECKSUM COMPUTATION
Chip Checksum with
0xAAAAAA at 0x00
Location and
at Last Location
0xBF8D
Read Code Protection
Checksum Computation
Erased
Checksum
Value
PIC24F16KLXXX
Disabled
CFGB + SUM (0:002BFEh)
0xC18B
Enabled
0
0x0000
0x0000
PIC24F08KLXXX
Disabled
CFGB + SUM (0:0015FE)
0xE28B
0xE08D
Enabled
0
0x0000
0x0000
PIC24F04KLXXX
Disabled
CFGB + SUM (0:000AFE)
0x730B
0x710D
Enabled
0
0x0000
0x0000
Disabled
CFGB + SUM (0:002BFE)
0xC279
0xC07B
Enabled
0
0x0000
0x0000
Disabled
CFGB + SUM (0:0015FE)
0xE379
0xE17B
Device
PIC24FV16KMXXX
(1)
PIC24FV08KMXXX(1)
Legend: Item
SUM[a:b] =
CFGB
=
Enabled
0
0x0000
Description
Byte sum of locations, a to b inclusive (all 3 bytes of code memory)
Configuration Block (masked):
0x0000
For PIC24FXXKLXXX devices: The byte sum of (FBS & 0x000F + FGS & 0x0003 + FOSCSEL & 0x00E7 + 
FOSC & 0x00FF + FWDT & 0x00FF + FPOR & 0x00FB + FICD & 0x0083).
For PIC24FVXXKMXXX devices: The byte sum of (FBS & +0x0F + FGS & 0x03 + FOSCSEL & 0xE7 +
FOSC & 0xFF + FWDT & 0xFF + FPOR & 0xFF + FICD & 0x83)
Note 1:
Includes PIC24FXXKMXXX devices.
 2011-2013 Microchip Technology Inc.
DS30625D-page 29
PIC24FXXKMXXX/KLXXX
5.0
AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
TABLE 5-1:
STANDARD OPERATING CONDITIONS
Standard Operating Conditions
Operating Temperature: 0C to +70C and programming: +25C is recommended.
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
D110
VDD
Supply Voltage During Programming
2.0
5.5
V
Normal programming,
PIC24FVXXKMXXX
D111
VDD
Supply Voltage During Programming
1.8
3.60
V
Normal programming,
PIC24FXXKLXXX/KMXXX
D112
IPP
Programming Current on MCLR
—
50
µA
D113
IDDP
Supply Current During Programming
—
2
mA
V
D031
VIL
Input Low Voltage
VSS
0.2 VDD
D041
VIH
Input High Voltage
0.8 VDD
VDD
V
D042
VIHH
Programing Voltage on VPP
7.75
9
V
D080
VOL
Output Low Voltage
—
0.4
V
IOL = 8.5 mA @ 3.6V
D090
VOH
Output High Voltage
1.4
—
V
IOH = -3.0 mA @ 3.6V
D100
VBULK
Bulk Erase Voltage
2.5
—
V
D115
RGOUT
Regulator Output Voltage
3.1
3.6
V
D120
CEFC
External Filter Capacitor Value
4.7
—
µF
—
50
pF
To meet AC specifications
125
—
ns
ICSP™ mode
Series resistance < 3 Ohm
recommended;
< 5 Ohm required.
D012
CIO
Capacitive Loading on I/O Pin (PGEDx)
P1
TPGC
Serial Clock (PGECx) Period
P1A
TPGCL
Serial Clock (PGECx) Low Time
50
—
ns
ICSP mode
P1B
TPGCH
Serial Clock (PGECx) High Time
50
—
ns
ICSP mode
P2
TSET1
Input Data Setup Time to Serial Clock 
15
—
ns
P3
THLD1
Input Data Hold Time from PGECx
15
—
ns
P4
TDLY1
Delay Between 4-Bit Command and
Command Operand
40
—
ns
P4A
TDLY1A
Delay Between 4-Bit Command Operand and
the Next 4-Bit Command
40
—
ns
P5
TDLY2
Delay Between the Last PGECx  of 
Command Byte and the First PGECx  of
Read of Data Word
20
—
ns
P6
TSET2
VDD Setup Time to MCLR 
100
—
ns
P7
THLD2
Input Data Hold Time from MCLR  VPP  (from
VIHH to VIH)
25
—
ms
P10
TDLY6
PGECx Low Time After Programming
400
—
ns
P11
TDLY7
Chip Erase Time
2.5
—
ms
P12
TDLY10
Page (4 rows) Erase Time
2.5
—
ms
P13
TDLY9
Row Programming Time
1.25
—
ms
P14
TR
MCLR Rise Time to Enter ICSP™ mode
—
1.0
s
P15
TVALID
Data Out Valid from PGECx 
10
—
ns
P16
TDLY10
Delay Between Last PGECx  and MCLR 
0
—
s
P17
THLD3
MCLR to VDD 
—
100
ns
P18
TKEY1
Delay Between First MCLR and First
PGECx for Key Sequence on PGEDx
1
—
ms
P19
TKEY2
Delay Between Last PGECx for Key
Sequence on PGEDx and Second MCLR 
1
—
ms
DS30625D-page 30
 2011-2013 Microchip Technology Inc.
PIC24FXXKMXXX/KLXXX
APPENDIX A:
REVISION HISTORY
Rev A Document (09/2011)
This is the initial release of this document.
Rev B Document 11/2011
Corrects configuration default values in Table 3-7 and
corrects checksum values in Table 4-4.
Rev C Document 4/2012
Added PIC24FXXKMXXX device information.
Rev D Document 5/2013
Corrects checksum values for PIC24FV16KMXXX and
PIC24FV08KMXXX in Table 4-4. Edits to the minimum
value for Parameter D042 in Table 5-1.
 2011-2013 Microchip Technology Inc.
DS30625D-page 31
PIC24FXXKMXXX/KLXXX
NOTES:
DS30625D-page 32
 2011-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2011-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-218-8
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2011-2013 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS30625D-page 33
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS30625D-page 34
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
11/29/12
 2011-2013 Microchip Technology Inc.