Stand-alone or In-System Programming Applications for AT18F Series Configurators 1. Overview The AT18F Series Configurators, which include AT18F010-30XU (1M), AT18F00230XU (2M), AT18F040-30XU (4M), and AT18F080-30XU (7M) devices, are pin-compatible/functional compatible with Xilinx® XCFxxS Series Platform Flash PROMs. These devices can be used to configure Xilinx Spartan®-II, Spartan-IIE, Spartan-3, Spartan-3E, Spartan-3A, Virtex®, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4LX/FX/SX, and Virtex-5-LX/LXT/SXT Series FPGAs, as well as Atmel AT40KAL Series FPGAs. AT18F Series Configurators Application Note This application note provides the application circuit diagrams and programming methods to program and configure Atmel and Xilinx FPGAs in its Master Serial mode. To perform stand-alone (drop-in) programming of the AT18F Series Configurators, the user could simply select the device algorithm in the programming software to program the configurator with Atmel’s AT18F-DK3 programming kit or any industrial standalone programmers (third-party programmers such as BP, Data I/O, Hi-Lo, etc.) that supports AT18F Series Configurators. Intel MCS hex object file (*.mcs) that is generated for a compatible density of Xilinx Platform Flash PROM can be used to program the AT18F Series Configurator for Xilinx FPGA application. For Atmel AT40KAL FPGA applications, an MCS file (also called *.hxr), which is generated from Atmel IDS software, can also be renamed to *.mcs in order to use it as an Intel MCS86 hex object file in order to program the AT18F Series Configurator for configuring Atmel AT40KAL Series FPGAs. After the configurator is programmed, it can be dropped into the target system board to configure the FPGA such as shown in Figures 1-2 and 1-3. Figure 1-1. Stand-alone (Drop-in) Programming Method for Atmel ATF18FX Series Configurator Programming Software Target System: AT18F AT18FX Stand-alone Programmer: Atmel AT18F-DK3 or Third-party Programmers that Support the AT18F Series Configurators 3684A–CNFG–4/08 Figure 1-2. VCCJ Stand-alone (Drop-in) Programming Circuit for AT18F Series Configurator in Atmel AT40KAL FPGA Application 3.3V VCCINT(1) Atmel AT40KAL FPGA in Master Serial Mode Atmel AT18F010/002/040/080 VCCINT(1) D0 D0 VCCO CLK CCLK VCCJ(1) CE CON OE/RESET INIT CF RESET GND Note: MODE PINS (M2, M1, M0) GND 1. For the appropriate voltage setting refer to the device datasheet. Figure 1-3. Stand-alone (drop-in) Programming Circuit for AT18F Series Configurator in Xilinx FPGA Application VCCO(2) VCCO(2) VCCO(2) VCCINT(1) (3) Note 4.7 kOhm Atmel AT18F010/002/040/080 4.7 kOhm VCCJ(1) VCCO(1) VCCINT(1) D0 Xilinx FPGA in Master Serial Mode DIN VCCO(1) CLK CCLK VCCJ(1) CE DONE OE/RESET INIT_B CF MODE PINS(2) PROG_B GND VCCAUX(1) GND Notes: 1. For the appropriate voltage setting refer to the device datasheet. 2. Different families of Xilinx FPGA might have different mode pin labels. Connecting all configuration mode pins to circuit ground (GND) will setup the Master Serial Mode of the FPGA for configuration loading. Refer to the appropriate FPGA datasheet for more details. 3. Different external Pull-up resistor value might be required on DONE pin of the FPGA, refer to FPGA datasheet for details. 2 Stand-alone/ISP for the AT18F 3684A–CNFG–4/08 Stand-alone/ISP for the AT18F For Stand-alone (Drop-in) Programming, since the configurator is pre-programmed in standalone programmer before dropping into the target board to configure the FPGA, JTAG pins (TDI, TMS, TCK, and TDO pins) will not be used in such case. However, connecting JTAG pins to JTAG ISP header as shown in the JTAG ISP circuit is also valid to use for drop-in (Stand-alone programming) of the configurator. To perform In-System Programming (ISP) through JTAG (Joint Test Action Group) interface, an Atmel JTAG ISP cable is required in order to provide communication between the programmer and the configurator as shown in Figure 1-4. Figures 1-5, 1-6 and 1-7 show the recommended ISP circuits. Atmel JTAG Configurator Programming System (JCPS) software, which supports Atmel AT18F-DK3 programming kit can be downloaded from Atmel web site at: http://www.atmel.com/dyn/products/tools.asp?family_id=625 For In-System Programming of the AT18F Series Configurator with the FPGA in the JTAG chain, you can follow the tutorial in the help menu of the JCPS software to set the FPGA in 6-bit or 10-bit Bypass mode depends on the FPGA family. Also, Figures 1-6 and 1-7 only show the AT18F Series Configurators connected in the JTAG chain as the first device, and the FPGA connected in the JTAG chain as the second device. However, such connection order can be inverted to have the FPGA connected in the JTAG chain as the first device, and the Configurator connected in the JTAG chain as the second device. Figure 1-4. JTAG In-System Programming Method for AT18F Series Configurator(1) D O IS W C NL P A O B A LE D Programming Software Co LE lo r S tr ip e Cable Converter D AT18F X Target System: AT18F Note: 1. Atmel JCPS Software does not support Xilinx JTAG programming cable. The Atmel JTAG ISP cable ATDH1151VPC or the JTAG ISP cable with a cable converter, included in the AT10FDK3 Development Kit, must be used for programming AT18F Series devices. 3 3684A–CNFG–4/08 Figure 1-5. JTAG In-system Programming Circuit Diagram for AT18F Series Configurator in Atmel AT40KAL Series FPGA Application VCCJ(1) VCCO(1) VCCINT(1) Atmel AT40KAL FPGA in Master Serial Mode Atmel AT18F010/002/040/080 VCCINT(1) JTAG ISP Header TCK GND TDO VCCJ TMS NC NC NC TDI GND D0 D0 VCCO(1) CLK CCLK VCCJ(1) CE CON OE/RESET Note: INIT CF TDI TMS TDO TCK GND MODE PINS (M2, M1, M0) RESET GND 1. For the appropriate voltage setting, refer to the device datasheet. Figure 1-6. JTAG In-system Programming Circuit for AT18F Series Configurator to Configure Xilinx FPGA VCCO(1,2) VCCO(1,2) VCCO(1,2) VCCINT(1) TMS (3) Note Xilinx FPGA in Master Serial Mode DIN VCCO(1) CLK CCLK VCCJ(1) CE DONE OE/RESET INIT_B JTAG ISP Header(4) VREF D0 4.7 kOhm Atmel AT18F010/002/040/080 4.7 kOhm VCCJ(1) VCCO(1) VCCINT(1) TDI CF MODE PINS(2) VCCAUX(1) PROG_B (4) TMS TCK (4) TDO (4) TDO TDI TMS TCK TCK TDI GND GND TDO NC NC Notes: 1. For the appropriate voltage setting, refer to the device datasheet. 2. Different families of Xilinx FPGA might have different mode pin labels. Connecting all Configuration mode pins to circuit ground (GND) will setup the Master Serial Mode of the FPGA for configuration loading. Refer to the appropriate FPGA datasheet for details. 3. Different external Pull-up resistor value might be required on DONE pin of the FPGA. Refer to FPGA datasheet for details. 4. Ground pins (GND) in JTAG ISP header are optional pins. These pins are not required for programming the device on the exiting target boards. However, for new design, it is recommended to have such connection to have common ground between target board and the programmer. Also, Serial resistors on TMS, TCK, and TDI lines are depending on VCCJ setting (Resistor = 0 ohm for VCCJ = 2.5V, and Resistor > 68 Ohms for VCCJ = 3.3V). 4 Stand-alone/ISP for the AT18F 3684A–CNFG–4/08 Stand-alone/ISP for the AT18F Cascaded Configurators can be used to configure multiple FPGAs in Master Serial and Slave Serial modes as shown in Figure 1-7. This circuit not only can be used for JTAG In-System programming of the AT18F Series Configurators with Atmel JTAG ISP cable, it can also be used for drop-in (stand-alone) programming after both AT18F Series Configurators are pre-programmed by stand-alone programmer. VCCINT(1) D0 VCCINT(1) (4) VCCO(2) VCCO(2) (3) Note MODE PINS(2) VCCJ(1) CE VCCJ(1) CE DONE DONE INIT_B INIT_B PROG_B PROG_B TDI TDI TMS TMS OE/RESET OE/RESET TMS CF TMS CF TCK TDO TCK TDO VCCAUX(1) TCK TCK GND CCLK CEO TDI TDI NC VCCAUX(1) DIN CCLK CEO TDO MODE PINS(2) DOUT CLK TDI (4) DIN VCCO(1) VREF TCK Xilinx FPGA in Master Serial Mode CLK JTAG ISP Header (4) Xilinx FPGA in Master Serial Mode VCCO(1) (4) TMS D0 4.7 kOhm Atmel Device #1 AT18F010/002/040/080 4.7 kOhm Atmel Device #2 AT18F010/002/040/080 VCCO(2) JTAG In-system Programming Circuit for Cascaded AT18F Series Configurators to Configure Multiple Xilinx FPGAs VCCJ (1) VCCO(1) VCCINT (1) Figure 1-7. GND GND TDO GND TDO NC Notes: 1. For the appropriate voltage setting, refer to the device datasheet. 2. Different families of Xilinx FPGA might have different mode pin labels and mode pin settings. Reference to Xilinx FPGA datasheet to setup Master Serial mode and Slave Serial mode for FPGA configuration loading. 3. Different external Pull-up resistor value might be required on DONE pin of the FPGA. Refer to FPGA datasheet for details. 4. Ground pins (GND) in JTAG ISP header are optional pins. These pins are not required for programming the device on the exiting target boards. However, for new design, it is recommended to have such connection to have common ground between target board and the programmer. Also, Serial resistors on TMS, TCK, and TDI lines are depending on VCCJ setting (Resistor = 0 Ohm for VCCJ = 2.5V, and Resistor > 68 Ohms for VCCJ = 3.3V). Important Note All circuit connection diagrams in this document are only provided as reference. Designer’s should study the AC/DC characteristics of the devices in order to construct the circuit for their own applications 5 3684A–CNFG–4/08 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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