APPLICATION NOTE
SAMA5D2 Low-Power Modes Implementation
Atmel | SMART SAMA5D2 Series
Scope
The Atmel® | SMART SAMA5D2 Series is a high-performance, power-efficient
embedded MPU based on the ARM® Cortex®-A5 processor.
This application note explains in detail how to enter and exit the low-power modes
of SAMA5D2 by providing software and hardware examples. The purpose of this
application note is to help users understand the low-power performance of
SAMA5D2, and design power-efficient systems for their own applications.
This application note is a supplement to the SAMA5D2 Series datasheet. It should
be used in conjunction with the following reference documents available on
www.atmel.com.
Reference Documents
XXXXXXXX
Type
Title
Atmel Lit. No.
Datasheet
SAMA5D2 Series Datasheet
11267
User Guide
SAMA5D2-XULT User Guide
44028
Atmel-44042B-ATARM-SAMA5D2-Low-Power-Modes-Implementation-ApplicationNote_01-Oct-15
Table of Contents
1.
Overview of SAMA5D2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
1.2
2.
3
4
4
4
4
Power Consumption Measurement on SAMA5D2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
3.
SAMA5D2 Internal Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAMA5D2 Low-Power Consumption Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1
Backup Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.2
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.3
Ultra Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SAMA5D2 Low-Power Mode Measurement Examples and Results . . . . . . . . . . . . . . . . 7
3.1
3.2
3.3
3.4
Backup Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.1
How to Enter Backup Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.2
How to Exit Backup Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ultra Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.1
How to Enter ULP0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.2
How to Exit ULP0 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.3
How to Enter ULP1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.4
How to Exit ULP1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3.1
How to Enter Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3.2
How to Exit Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Low-Power Mode Measurement Result Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
SAMA5D2 Low-Power Modes Implementation [APPLICATION NOTE]
Atmel-44042B-ATARM-SAMA5D2-Low-Power-Modes-Implementation-ApplicationNote_01-Oct-15
1.
Overview of SAMA5D2 Power Supply
1.1
SAMA5D2 Internal Power Domains
SAMA5D2 includes several power supply rails. Table 1-1 shows these power supply rails and the corresponding
power domains.
Table 1-1.
SAMA5D2 Power Supplies
Name
Voltage Range,
Nominal
Associated
Ground
VDDCORE
1.10V – 1.32V, 1.20V
GNDCORE
VDDPLLA
1.10V – 1.32V, 1.20V
GNDPLLA
PLLA Cell
VDDUTMIC
1.10V – 1.32V, 1.20V
GNDUTMI
USB device and host UTMI+ core
VDDHSIC
1.10V – 1.30V, 1.20V
GNDUTMI
USB Inter IC device and host UTMI+ interface
1.70V – 1.90V, 1.80V
VDDIODDR
1.14V – 1.30V, 1.20V
1.29V – 1.45V, 1.35V
Powers
Core, including the processor, the embedded memories and the
peripherals
LPDDR / DDR2 interface I/O lines
GNDIODDR
1.43V – 1.57V, 1.50V
LPDDR2 / LPDDR3 interface I/O lines
DDR3L interface I/O lines
DDR3 interface I/O lines
VDDIOP0
1.65V – 3.60V
GNDIOP0
Peripheral I/O lines
VDDIOP1
1.65V – 3.60V
GNDIOP1
Peripheral I/O lines
VDDIOP2
1.65V – 3.60V
GNDIOP2
Peripheral I/O lines
VDDISC
1.65V – 3.60V
GNDISC
Peripheral I/O lines
VDDSDMMC
1.65V – 3.60V
GNDSDMMC
SDMMC I/O lines
VDDUTMII
3.00V – 3.60V, 3.30V
GNDUTMII
USB device and host UTMI+ interface
VDDOSC
1.65V – 3.60V
GNDOSC
Main Oscillator Cell and PLL UTMI. If PLL UTMI or USB is used, the
range is restricted to 3.00V – 3.60V
VDDAUDIOPLL
3.00V – 3.60V, 3.30V
VDDADC
2.40V – 3.60V, 3.30V
GNDADC
Analog-to-Digital Converter
VDDANA
1.65V – 3.60V, 3.30V
GNDANA
VDD Analog
VDDFUSE
2.25V – 2.75V, 2.50V
GNDFUSE
Fuse box for programming. It can be tied to ground with a 100Ω
resistor for fuse reading only. It must be powered for fuse
programming and to switch to Secure mode
GNDDPLL
Audio PLL
Slow Clock Oscillator, the internal 32-kHz RC Oscillator and a part of
the System Controller
1. When USB is not used, implement the following two steps to save the power consumption on this power rail:
USB device: set the DETACH bit to 1 and the PULLD_DIS bit to 0 in register UDPHS_CTRL. Any other combinations of
these two bits may cause additional consumption.
USB host: force all USB host ports to suspend by setting the SUSPEND_A, SUSPEND_B and SUSPEND_C bits to 1 in
register SFR_OHCIICR, at the end of the USB suspend routine.
VDDBU
Note:
GNDAUDIOPLL
1.65V – 3.60V
GNDBU
SAMA5D2 Low-Power Modes Implementation [APPLICATION NOTE]
Atmel-44042B-ATARM-SAMA5D2-Low-Power-Modes-Implementation-ApplicationNote_01-Oct-15
3
1.2
SAMA5D2 Low-Power Consumption Modes
SAMA5D2 devices offer three main low-power modes: Backup mode, Idle mode and Ultra Low-power mode.
These modes provide combinations of different low-power consumption and wake-up time, which can adapt to
different application requirements.
1.2.1
Backup Mode
The Backup mode allows to achieve the lowest power consumption in the system with limited functionality. In
this mode, only the back area is powered, maintaining the RTC, the backup registers, the backup SRAM and the
security module running.
The Backup mode functionality has been extended with the possibility to keep the DDR memory in self-refresh
state, which is used to keep the DDR contents when the system is powered-off.
1.2.2
Idle Mode
The purpose of Idle mode is to optimize power consumption of the device versus response time. In this mode,
only the core clock is stopped. The peripheral clocks, including the DDR controller clock, can be enabled. The
current consumption in this mode is application-dependent.
1.2.3
Ultra Low-Power Mode
The purpose of the Ultra Low-power mode is to achieve the lowest power consumption with the system in
Retention mode and able to resume on wake-up events (any interrupt or hardware event). This mode is a
combination of the Wait for Interrupt mode of the ARM core and the system clocks frequency reduced or shutoff.
The Ultra Low-power mode features two submodes: ULP0 mode and ULP1 mode. ULP0 mode maintains a very
low frequency clock to wake up on any interrupt. The higher the frequency, the shorter the wake-up time.
ULP1 differs slightly from ULP0 in two aspects:
4
1.
In ULP0 mode, the system clock is switched to Slow Clock; while in ULP1 mode, all the clocks are
switched off and the system clock is switched to the 12-MHz RC oscillator.
2.
The wake-up sources for ULP1 are limited to the following list:
–
WKUP0 pin (level transition, configurable debouncing)
–
WKUP1 pin to WKUP8 pin (shared with PIOBU0 to PIOBU7)
–
RTC alarm
–
USB Resume from Suspend mode
–
SDMMC card detect
–
Secumod wake-up signal
–
RXLP event
–
ACC event
–
Any SleepWalking™ event coming from TWI, FLEXCOMx, SPI, ADC
SAMA5D2 Low-Power Modes Implementation [APPLICATION NOTE]
Atmel-44042B-ATARM-SAMA5D2-Low-Power-Modes-Implementation-ApplicationNote_01-Oct-15
2.
Power Consumption Measurement on SAMA5D2
2.1
Hardware
The power consumption measurement is based on the SAMA5D2-XULT board. On the SAMA5D2-XULT board,
all SAMA5D2 power rails are supplied by a Power Management IC: ACT8945AQJ405 (refer to ACT8945A
Specification). Figure 2-1 is the PMIC part schematic (refer to the Schematics Section in SAMA5D2-XULT User
Guide).
Figure 2-1.
PMIC Schematic
U2
VDD_5V_IN
VIN_5V
2
3
33
Q7
IRLML6402
R21
2.2M 1%
R22
1.5M 1%
nSTAT
20
VDD_3V3
R7
23
1
R27
R16
R17
100R 1%
100R 1%
R20
100R 1%
22
11
12
13
19
27
26
C7
DNP(1nF)
DNP(8.2K 1%)
0R
R41
DNP(0R)
SHDN
R9
1K
C10
PWRHLD
R12
100K
Q3
BSS138
2
WAKE UP
GNDP3
EXPAD
41
GNDA
GNDP12
TP11
SMD
3
1
100nF
nPBIN
14
TP14
SMD
2
9
49.9K 1%
OUT5
PWREN
C8
100nF
R13
49.9K 1%
[9]
SW3
OUT3
18
Q1
BSS138
VSYS_5V
R44
100R 1%
VBAT
29
30
VBAT
24
1
2
3
J3
1X3Pin
1
2
J4
DNP(Header 1X2 2.00MM)
C19
4.7uF
38
2
L5
2.2uH
C20
10uF
C23
10uF
C24
100nF
VDD_1V2
SW2
OUT2
VSEL
BP3
2
CHGLEV
nRSTO
nIRQ
nPBSTAT
nLBO
SDA
SCL
OUT4
Tact Switch BP2
1
Q2
BSS138
RED
C167
100nF
VDD_1V35
VSYS_5V
R14
1
D1
C176
10uF
ISET
REFBP
Tact Switch
3
C164
10uF
36
34
L6
2.2uH
C22
10uF
C37
10uF
C38
100nF
15
17
L1
2.2uH
C3
10uF
C2
10uF
C1
100nF
VDDFUSE
10
3
28
C163
10uF
VDD_3V3
R30
25
R15
100K
R8
68K
31
32
39
35
16
6
40
VSYS_5V
R26
VSYS_5V
TH
SW1
OUT1
nPBSTAT
PMIC_LBO/EXP_PC8
PMIC_TWD0_PD21
PMIC_TWCK0_PD22
BAT1
BAT2
37
PMIC_CHGLEV_PA12
[9,10,12,14,15] NRST
[7] PMIC_IRQ_PB13
LBI
C166
47nF
2.43K 1%
10K
10K
R6
3.9K 1%
[8,15]
[8]
[8]
ACIN
VBAT
11K 1%
R24
[7]
21
R18
DNP(11K 1%)
VSYS_5V
VSYS1
VSYS2
VP1
VP2
VP3
INL
NC1
3
R11
CHGIN
C165
4.7uF
5V_EXT_INP
1
[15]
ACT8945AQJ405-T
D9
RB160M-60TR
OUT6
OUT7
4
VDD_2V5
5
VDD_3V3
8
VDD_3V3
7
VDD_1V8
R327
0R
R330
0R
VDD_3V3_LP
VDD_LED
1
L3
VDDSDHC1V8
2
180ohm at 100MHz
C169
4.7uF
C17
4.7uF
C173
4.7uF
C13
4.7uF
R19
0R
RESET
Place TP11 and TP14 to Bottom.
SAMA5D2 Low-Power Modes Implementation [APPLICATION NOTE]
Atmel-44042B-ATARM-SAMA5D2-Low-Power-Modes-Implementation-ApplicationNote_01-Oct-15
5
Figure 2-2.
Power Supply Schematics
JPR6
Jumper
VDD_3V3
D6
BAT54C
JP6
Header 1X2
VDDBU
1
R280
2
100R 1%
D5
RB160M-60TR
1
2
3
C44
DNP(1uF)
+ C42
0.2F/3.3V
R139
DNP(2.2K)
C46
100nF
(Super)-Capacitor
energy storage
Populate R if
no Super Cap
JP7
JPR7
Header 1X2 Jumper
VDDIODDR
1
2
VDD_1V35
For DDR3
For MPU
JPR4
JP4
Header 1X2 Jumper
1
2
VDDCORE
VDDPLLA
10uH_150mA
L12
VDD_1V2
R129
2R2
VDDUTMIC
1
L18
2
180ohm at 100MHz
1
L16
VDDHSIC
2
180ohm at 100MHz
VDDIOP2
1
JPR5
JP5
Header 1X2 Jumper
L7
2
180ohm at 100MHz
VDD_3V3
L8
VDDIOP1
2
1
2
1
180ohm at 100MHz
1
L9
180ohm at 100MHz
1
VDDIOP0
2
L10
VDDISC
2
180ohm at 100MHz
VDDOSC
JP3
JPR3
Header 1X2 Jumper
2R2
R284
0R
R303
0R
L20 10uH_150mA
1
2
VDD_3V3_LP
R293
1
L19
VDDANA
180ohm at 100MHz
1
L23
2
180ohm at 100MHz
R300
VDDUTMII
2
VDDAUDIOPLL
2R2
L22 10uH_150mA
Board Setup for Measurement
Before any measurement, check the jumper settings on the XULT board.
The default jumper settings are as follows:
JUMPER DESCRIPTION
PART DEFAULT FUNCTION
JP1
OPEN
Disable EDBG
JP2
OPEN
Disable Debug
JP3
CLOSE
I VDD_3V3_LP Measurement
JP4
CLOSE
I VDDCORE Measurement
JP5
CLOSE
I VDDISC+VDDIOP0/1/2 Measurement
JP6
CLOSE
I VDDBU Measurement
JP7
CLOSE
I VDDIODDR_MPU Measurement
JP8
CLOSE
I VDD_5V_IN Measurement
JP9
OPEN
Disable CS of SPI&QSPI&eMMC Memory
For more information on the XULT board, refer to the SAMA5D2-XULT User Guide.
6
SAMA5D2 Low-Power Modes Implementation [APPLICATION NOTE]
Atmel-44042B-ATARM-SAMA5D2-Low-Power-Modes-Implementation-ApplicationNote_01-Oct-15
Idle Mode and ULP Mode Consumption Measurement
The power consumption of VDDCORE is measured by connecting an ammeter (Agilent 34410A 61/2) in series
with Jumper JP4.
Backup Mode Consumption Measurement
The power consumption of VDDBU is measured by connecting an ammeter (Agilent 34410A 61/2) in series with
Jumper JP6. When DDR is set to self-refresh state, the user can also connect an ammeter (Agilent 34410A 61/2)
in series with Jumper JP7 to check the power consumption of VDDIODDR.
On the SAMA5D2-XULT board, VDDBU is powered by the 3.3V power output from PMIC. However, the
following Backup mode consumption measurement requires VDDBU to range from 1.6V to 3.6V (with 0.1V
step), so an external power supply, instead of PMIC, is used to power the VDDBU power rail.
Note:
After entering Backup mode, remember to first disconnect the 5V power supply from the XULT board before
measuring the VDDBU power consumption.
Wake-up Time Measurement
In the example provided in this AN, the time slot is measured from the wake-up source pin status change to the
moment of the first instruction execution as wake-up time (here, the first instruction is changing one GPIO
(PA13) output status).
Note:
2.2
To wake up the system from low-power modes, the 5V power supply on XULT board must be kept connected.
Software
The project used in the following measurements is based on SAMA5D2 Software Package (IAR7.40), available
on www.atmel.com.
3.
SAMA5D2 Low-Power Mode Measurement Examples and Results
3.1
Backup Mode
3.1.1
How to Enter Backup Mode
The Backup mode is entered by shutting down all the power rails except VDDBU.
Sample code:
// Enable Wake-up 0 as Input source and define its input type to low level.
SHDWC->SHDW_WUIR = 0x00001;
//Define wake up mode and Debounce counter
SHDWC->SHDW_MR = SHDW_MR_WKMODE0(2) | SHDW_MR_CPTWK0(1);
//Assert the SHDN pin to enter backup with correct Key input
SHDWC->SHDW_CR = SHDW_CR_KEY(0xA5) | SHDW_CR_SHDW;
To enter Backup mode while keeping the DDR memory in Self-refresh mode, maintain both the backup area
and the VDDIODDR powered. The sequence below must be performed to enter the Backup Self-refresh mode:
Software saves all the context information to resume (application-dependent).
Put the DDR in Self-refresh mode and wait until the self-refresh status is OK (refer to section MPDDRC).
Set the BUMEN bit in the SFRBU_DDRBUMCR register.
Enter the Backup mode as described above.
SAMA5D2 Low-Power Modes Implementation [APPLICATION NOTE]
Atmel-44042B-ATARM-SAMA5D2-Low-Power-Modes-Implementation-ApplicationNote_01-Oct-15
7
Sample code:
//Check if DDR Backup Mode is enabled; if not, continue to do following
setting.
if(!(SFRBU_DDRBUMCR) & 0x1))
{
//Check if self-refresh is done; if not, continue.
while(!(MPDDRC->MPDDRC_LPR&MPDDRC_LPR_SELF_DONE));
//Disable the DDR Controller clock signal at PMC level for the periph. ID
13
PMC->PMC_PCR = ( PMC_PCR_CMD | PMC_PCR_GCKCSS_MCK_CLK | (ID_MPDDRC));
//Disable ddrclk
PMC->PMC_SCDR |= PMC_SCDR_DDRCK;
//Enable DDR Backup Mode
SFRBU_DDRBUMCR = (0x1<<0);
}
3.1.2
How to Exit Backup Mode
To exit Backup mode, the SHDN pin (connected to the enable of the external Power Management IC) must be
driven high by an internal event (RTC) or by one of the following external events:
WKUP0 to WKUP8 pin (level transition, configurable debouncing)
Character received on a serial com receiver (RXLP)
Analog comparison
The method to exit Backup mode with DDR in self-refresh is the same as described for the Backup mode. Once
the system is restarted, the software checks the state of the BUMEN bit in the SFRBU_DDRBUMCR register
and re-initialize the DDR controller. The DDR memory exits Self-refresh mode when a memory access in the
DDR memory space is performed.
3.2
Ultra Low-Power Mode
Ultra Low-Power mode (ULP) includes two submodes: ULP0 mode and ULP1 mode.
3.2.1
How to Enter ULP0 mode
The sequence to enter ULP0 mode is detailed below. The code used to enter this mode must be executed out of
the internal SRAM.
1.
Set the DDR to Self-Refresh mode.
2.
Set the interrupts to wake up the system.
3.
Disable all peripheral clocks.
4.
Set the I/Os to an appropriate state and disable the USB transceivers (refer to the Special Function
Registers (SFR) section in the SAMA5D2 Series datasheet).
5.
Switch the system clock to Slow Clock.
6.
Disable the PLLs, the main oscillator and the 12-MHz RC oscillator.
7.
Enter the Wait for Interrupt mode and disable the PCK clock in the PMC_SCDR register.
Sample code:
//Save status before entering ULP mode
read_reg[0] = PMC->PMC_PCSR0;
read_reg[1] = PMC->PMC_PCSR1;
8
SAMA5D2 Low-Power Modes Implementation [APPLICATION NOTE]
Atmel-44042B-ATARM-SAMA5D2-Low-Power-Modes-Implementation-ApplicationNote_01-Oct-15
read_reg[2] = PMC->PMC_SCSR;
read_reg[3] = PMC->CKGR_UCKR;
Save_Misc_Power();
//Configure wakeup pin and enable interrupt
Keep_wakeup_source();
//Switch system clock to Slow Clock
Configure_custom_PCK_MCK (&clock_test_setting[use_clock_setting]);
PMC->PMC_SCDR = PMC_SCDR_PCK;
asm("wfi");
3.2.2
How to Exit ULP0 Mode
The wake-up from ULP0 mode is triggered by any enabled interrupt. In the sample code of this AN, Push Button
(BP1) is used as the wake-up source. When resuming, the software re-configures the system (oscillator, PLL,
etc.) to the same state as before WFI.
3.2.3
How to Enter ULP1 Mode
The sequence to enter the ULP1 mode is detailed below. The code used to enter this mode must be executed
out of the internal SRAM.
1.
Set the DDR to Self-Refresh mode.
2.
Set the events to enable a system wake-up.
3.
Disable all peripheral clocks.
4.
Set the I/Os to an appropriate state and disable the USB transceivers.
5.
Switch the system clock to the 12-MHz RC oscillator.
6.
Disable the PLLs and the main oscillator.
7.
Enter the ULP1 mode by either:
–
setting the WAITMODE bit in CKGR_MOR, or
–
setting the LPM bit in PMC_FSMR and executing the processor WaitForEvent (WFE) instruction.
Then, immediately after setting the WAITMODE bit or using the WFE instruction, wait for the
PMC_SR.MCKRDY bit to be set.
Sample code:
//Remember system&peripheral&UTMI clock status
read_reg[0] = PMC->PMC_PCSR0;
read_reg[1] = PMC->PMC_PCSR1;
read_reg[2] = PMC->PMC_SCSR;
read_reg[3] = PMC->CKGR_UCKR;
//Disable system/peripheral clocks
Save_Misc_Power();
//Ultra low power mode 1 needs RC12 for Main Clock
Configure_custom_PCK_MCK (&clock_test_setting[use_clock_setting]);
//Set RTC alarm for wake up resource(after 30 secs, RTC generates an
interrupt)
start_RTC_timer_for_wakeup(30);
//Set Fast Start-up Register to enter ULP1 mode and RTC alarm enable
PMC->PMC_FSMR |= PMC_FSMR_LPM | PMC_FSMR_RTCAL;
//Disable PCK clock
PMC->PMC_SCDR = PMC_SCDR_PCK;
SAMA5D2 Low-Power Modes Implementation [APPLICATION NOTE]
Atmel-44042B-ATARM-SAMA5D2-Low-Power-Modes-Implementation-ApplicationNote_01-Oct-15
9
asm("WFE");
asm("WFE");
//Wait core to enter in WAITMODE using CKGR_MOR or PMC_FSRM register
while((PMC->PMC_SR & PMC_SR_MCKRDY) == 0);
void Save_Misc_Power(void)
{
unsigned int read_reg;
//Disable system clocks
PMC->PMC_SCDR = PMC_SCDR_DDRCK | PMC_SCDR_LCDCK | PMC_SCDR_UHP |
PMC_SCDR_UDP | PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2 |
PMC_SCDR_ISCCK;
//Disable all peripheral clocks
PMC->PMC_PCDR0 = 0xFFFFFFFF;
PMC->PMC_PCDR1 = 0xFFFFFFFF;
PMC->CKGR_UCKR = PMC->CKGR_UCKR & ~CKGR_UCKR_UPLLEN;
PMC->CKGR_UCKR = PMC->CKGR_UCKR & ~CKGR_UCKR_BIASEN;
}
3.2.4
How to Exit ULP1 Mode
The method to exit ULP1 mode is similar to the method described for ULP0 mode. However, the wake-up
sources are limited to a list specified in Section 1.2.3.
In the sample code of this AN, RTC is used as the wake-up source.
3.3
Idle Mode
3.3.1
How to Enter Idle Mode
This mode is entered via the Wait for Interrupt (WFI) instruction and PCK disabling.
Sample code:
//Disable PCK
PMC->PMC_SCDR = PMC_SCDR_PCK;
//Enter Idle mode
asm("wfi");
3.3.2
How to Exit Idle Mode
The processor can be awakened from Idle mode by an interrupt. The system resumes where it was before
entering WFI mode. In the sample code of this AN, Push Button (BP1) is used as the wake-up source. So,
before entering Idle mode, the corresponding PIO must be configured as wake-up source.
Sample code:
static void configure_buttons(void)
{
int i = 0;
for (i = 0; i < ARRAY_SIZE(button_pins); ++i){
//Configure PIOs as inputs.
pio_configure(&button_pins[i], 1);
10
SAMA5D2 Low-Power Modes Implementation [APPLICATION NOTE]
Atmel-44042B-ATARM-SAMA5D2-Low-Power-Modes-Implementation-ApplicationNote_01-Oct-15
//Adjust PIO debounce filter parameters, use 10 Hz filter.
pio_set_debounce_filter(&button_pins[i], 10);
//Initialize PIOs interrupt with its handlers, see PIO definition in
board.h.
pio_configure_it(&button_pins[i]);
pio_add_handler_to_group(button_pins[i].group,
button_pins[i].mask, pio_handler);
//Enable PIO line interrupts.
pio_enable_it(button_pins);
}
}
SAMA5D2 Low-Power Modes Implementation [APPLICATION NOTE]
Atmel-44042B-ATARM-SAMA5D2-Low-Power-Modes-Implementation-ApplicationNote_01-Oct-15
11
3.4
Low-Power Mode Measurement Result Summary
Table 3-1 below shows a summary of Low-power mode measurement results (Typ@25°). For more
measurement results, refer to the Electrical Characteristics section in the SAMA5D2 Series datasheet.
Table 3-1.
Low-power Mode Configuration Summary
Low-power Mode
Backup
Sub-mode:
-
Ultra Low-power
Self-refresh
ULP0
64-kHz RC Oscillator,
32-kHz Oscillator, RTC,
Backup Memory and
Registers, POR
Idle
ULP1
ON
12 MHz RC Oscillator
OFF
VDDCORE Regulator
ON
OFF
ON
Core
OFF
(Not powered)
Powered
(Not clocked)
Memory, Peripherals
OFF
(Not powered)
Powered
(512 Hz)
Powered
(Not clocked)
Mode Entry
Shutdown Controller,
DDR in Self-refresh
DDR in Self-refresh,
Flexcom
Frequency reduced
Shutdown Controller
SleepWalking
in PMC, WFI
Potential Wake-up
Sources
WKUP0 pin, any
PIOBU configured as
WKUP pin, RTC
alarm, any level
above comparator
source or character
received
Backup mode
sources
Core at Wake-up
Reset
PIO State While in Lowpower Mode
Reset
PIO State at Wake-up
Consumption(2)
Wake-up Time(1)
Start-up time
DDR in Self-refresh, DDR in Self-refresh,
PMC Wait mode
WFI
Any interrupt
Wake-up pins, WOL
Any interrupt
Clocked back
at 512 Hz
Clocked back
at 12 MHz
Clocked back
at full speed
Previous state saved
Inputs with pull-ups
IVDDBU= 4.22 μA typ(3)
at 25°/3.0V
Powered
(Clocked)
Unchanged
IVDDBU= 4.22 μA typ
at 25°/3.0V
IVDDIODDR= 40 μA
(3)
0.19 mA at 25°/1.1V 0.17 mA at 25°/1.1V
74.3 mA at 25°/1.1V
0.25 mA at 25°/1.2V 0.23 mA at 25°/1.2V
81.6 mA at 25°/1.2V
Start-up time
300 mS
30 µS
880 ns at 498 MHz
Notes:
1. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device
works with the main oscillator. The user has to add the PLL startup time if it is needed in the system. The wake-up time is
defined as the time taken for wake-up until the first instruction is fetched.
2. The external loads on PIOs are not taken into account in the calculation.
3. Total current consumption.
12
SAMA5D2 Low-Power Modes Implementation [APPLICATION NOTE]
Atmel-44042B-ATARM-SAMA5D2-Low-Power-Modes-Implementation-ApplicationNote_01-Oct-15
Revision History
Table 3-2.
SAMA5D2 Low-Power Modes Implementation Revision History
Doc. Rev.
Date
Changes
44042B
01-Oct-15
Added Note (1) to Table 1-1 “SAMA5D2 Power Supplies”.
44042A
07-Sep-15
First issue
SAMA5D2 Low-Power Modes Implementation [APPLICATION NOTE]
Atmel-44042B-ATARM-SAMA5D2-Low-Power-Modes-Implementation-ApplicationNote_01-Oct-15
13
XXX
ARM Connected Logo
XXXXXX
Atmel Corporation
1600 Technology Drive, San Jose, CA 95110 USA
T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
|
www.atmel.com
© 2015 Atmel Corporation. / Rev.: Atmel-44042B-ATARM-SAMA5D2-Low-Power-Modes-Implementation-ApplicationNote_01-Oct-15.
Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and
other countries. ARM®, ARM Connected® logo, and others are the registered trademarks or trademarks of ARM Ltd. Other terms and product names may be
trademarks of others.
DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right
is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE
ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT
SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES
FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this
document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information
contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended,
authorized, or warranted for use as components in applications intended to support or sustain life.
SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where
the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written
consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems.
Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are
not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.