APPLICATION NOTE
Powering Atmel SAMA5D4 MPUs with ActivePMU PMICs
Atmel | SMART SAMA5D4 Series
Scope
To support enhanced power supply applications on its Atmel ® | SMART
SAMA5D4x MPU, Atmel has selected two ActivePMU Power Management
Integrated Circuits (PMICs) from the active-semi portfolio:
ACT8865—seven-channel (3 DC/DC converters + 4 LDO regulators) PMU
ACT8945A—seven-channel (3 DC/DC converters + 4 LDO regulators) PMU
with integrated linear Li-Po/Li-Ion battery charger
This application note provides developers with the following content:
Recommended application schematics with associated functional
descriptions
A description of the PMIC Power-Saving Mode and its use with Atmel MPU
low-power modes
A high-level description of an available Linux driver
Reference Documents
Title
ACT8865 Datasheet (available at www.active-semi.com)
ACT8945A Datasheet (available at www.active-semi.com)
SAMA5D4 Series Datasheet
Atmel Lit. No.
–
–
11238
SMART
Atmel-44000B-ATARM-Powering-Atmel-SAMA5D4-with-ActivePMU-PMICs-ApplicationNote_30-Apr-15
Table of Contents
Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.
Power Supply Overview of Atmel SAMA5D4x Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
1.2
1.3
1.4
1.5
1.6
2.
ACT8865 and ACT8945A: Reference Schematics and Description . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
3.
First Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On From Backup Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Power-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Off Upon Input Power Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
13
14
Active-Semi PMICs and Atmel SAMA5D4x Low-Power Modes . . . . . . . . . . . . . . . . . . . 15
4.1
4.2
5.
ACT8865 Reference Schematic and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ACT8945A Reference Schematic and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Passive Components Selection and PCB Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . 9
Digital Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional Description of a Typical Use Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
3.2
3.3
3.4
4.
Atmel SAMA5D4x Power Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Atmel SAMA5D4x VCCCORE Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Atmel SAMA5D4x VDDBU Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Power Supply Topologies and Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Clock Circuits Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power Supplies Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Active-Semi PMIC Power-Saving Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SAMA5D4x Series Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Linux Driver Content and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1
5.2
5.3
5.4
5.5
5.6
Linux Voltage and Current Regulator Framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACT8865 Regulator Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Kernel Configurations to Enable ACT8865 Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Declaring the Regulator Device Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Regulator Consumer Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Regulator Sysfs Entries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
18
18
20
20
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2
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1.
Power Supply Overview of Atmel SAMA5D4x Systems
1.1
Atmel SAMA5D4x Power Rails
Atmel SAMA5D4x MPUs power rails and their respective operating ranges are listed in Table 1-1. An approximate
current consumption is provided for each rail in order to size the corresponding regulator. Accurate numbers and
descriptions are provided in the device datasheet.
Depending on the application complexity, SAMA5D4x power input pins may be grouped into two (e.g. 3.3V +
1.8V), three (e.g. 3.3V + 1.8V + 1.2V) or more power planes. In secure applications, or any application that
requires writing into the internal fuse box, an additional 2.5V power rail is needed to supply the VDDFUSE input
pin.
The SAMA5D4x series also features a backup power domain intended to retain information during power-down
periods by means of a storage element (e.g., a battery or a super-capacitor). It is supplied by the VDDBU pin and
must be fed through a 2V regulator.
Table 1-1.
SAMA5D4x Series Power Supply Inputs
Power Rail
Circuit Supplied by the Power Rail
Range
Consumption
VDDCORE
Core Voltage Regulator
1.62–1.98V, 1.80V
0.35A
VDDIODDR
External Memory Interface I/O lines
1.70–1.90V, 1.80V
1.14–1.32V, 1.20V
0.05A
0.03A
VDDIOM
NAND and HSMC Interface I/O lines
1.65–1.95V, 1.80V
3.00–3.60V, 3.30V
0.03A
VDDIOP
Peripheral I/O lines
1.65–3.60V
0.03A
VDDUTMIC
USB Device and host UTMI+ core logic
1.10–1.32V, 1.20V
0.02A
VDDUTMII
USB Device and host UTMI+ interface
3.00–3.60V, 3.30V
0.02A
VDDPLLA
PLLA
1.10–1.32V, 1.20V
0.02A
VDDOSC
Main oscillator and UTMI PLL
1.65–3.60V, 3.30V
0.001A
VDDANA
Analog-to-Digital Converter, and other analog
circuits
3.00–3.60V, 3.30V
–
VDDFUSE
Programmable Fuse Box
2.25–2.75V, 2.50V
0.05A
VDDBU
Backup domain
1.88–2.12V, 2.00V
0.0001A
In all modes other than Backup mode, each power supply input must be powered to operate the device. The only
exception to this rule is the VDDFUSE input which can be left unpowered if the fuse box is not used in Write mode.
1.2
Atmel SAMA5D4x VCCCORE Generation
Atmel SAMA5D4x devices embed a linear low dropout (LDO) voltage regulator to generate their core logic power
supply (VCCCORE). The input of this regulator is VDDCORE and its output is internally connected to some of the
VCCCORE pins. The remaining VCCCORE pins are fed from the VCCCORE plane of the printed circuit board
(PCB). This plane must contain at least one 10µF capacitor (max 20µF) to ensure the regulator stability. Additional
10nF to 100nF capacitors of X5R or X7R type must be connected to each VCCCORE pin for proper decoupling.
This regulator cannot be shut down and therefore the VCCCORE pins cannot be fed by an external voltage
regulator at the risk of creating a short circuit between the internal regulator and the external one.
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3
1.3
Atmel SAMA5D4x VDDBU Generation
The SAMA5D4x series embeds a backup power domain which supplies a Real-Time Clock circuit, a backup
memory and others. This power domain is designed for ultra-low-power consumption (8µA typ.) and is therefore
suited to be supplied by a storage element such as a super-capacitor or a battery. The operating range of VDDBU
(2V±120mV) calls for the use of an external voltage regulator. Low-power LDO regulators in the S-1206 series
from Seiko Instruments and NCP4682 series from ON Semiconductor with a typical 1µA operating current meet
the criteria.
Figure 1-1.
VDDBU Generation
5.0V
(Main Power
Source)
3.0V
Backup
Battery
2.0V
LDO
(e.g :
BAS40-05)
1µF
(e.g : S-1206 series
or NCP4682 series)
VDDBU
1µF
As described in the SAMA5D4x series datasheet, the VDDBU power supply must always be the first power source
applied to the system and the last one disconnected from the system. It is therefore good practice to monitor the
storage element discharge in order to shutdown the system before the VDDBU voltage goes out of its operating
range,
If the backup functionality of the SAMA5D4x device is not used in the application, VDDBU can be fed directly from
the main power source through a 2.0V regulator. In case of input power loss, small storage capacitors (e.g., 1µF)
help to extend the presence of the VDDBU voltage after a system shutdown, thus ensuring a clean power-down.
1.4
Power Supply Topologies and Power Distribution
1.4.1
2-channel Topology
In the simplest applications of the SAMA5D4x, a 2-rail power supply topology (3.3V/1.8V) can be used as shown in
Figure 1-2. However, this supply schematic has the following limitations:
4
The fuse box cannot be accessed in Write mode because VDDFUSE = 0V.
The analog section of the device (VDDANA) is powered from the (noisy) digital 3.3V rail.
Powering Atmel SAMA5D4 with ActivePMU PMICs [APPLICATION NOTE]
Atmel-44000B-ATARM-Powering-Atmel-SAMA5D4-with-ActivePMU-PMICs-ApplicationNote_30-Apr-15
Figure 1-2.
2-channel Power Distribution Example on SAMA5D4x Series Equipped with a 1.8V External Memory
1.8V
VDDIODDR
VDDCORE
REG1
VCCCOREx
Core
Regulator
VDDUTMIC
VDDPLLA
VDDIOP
VDDIOM
VDDOSC
3.3V
REG2
VDDUTMII
VDDANA
100R
VDDFUSE
3.0V
Coin Cell
Battery
1.4.2
2.0V
LDO
VDDBU
SAMA5D4x
5-channel Topology and Active-Semi PMICs
A 5-channel power supply topology can be used to lift the aforementioned limitations on VDDFUSE and VDDANA.
As shown n Figure 1-3, the power supply based on Active-Semi PMICs follows this architecture:
3.3V (analog)
3.3V (digital)
1.8V (digital)
1.2V (digital)(1)
2.5V (analog)
Note:
1.
Optional rail. In case of (SAMA5D4x + DDR2) design, this rail may not be needed. In case of (SAMA5D4x +
LPDDR2), this rail can supply the VDDIODDR input.
For maximum efficiency, the three digital power supply channels are generated by three integrated step-down
converters. The 3.3V and 2.5V analog rails are supplied by two integrated low-dropout (LDO) regulators. Power
distribution to the device and its external components mainly depends on the external components themselves. As
an example, a SAMA5D4x + LPDDR2 design operates VDDIODDR from the 1.2V rail whereas this power pin is
fed by the 1.8V rail on a SAMA5D4x + DDR2 design. If the 1.2V digital rail is not used in the application, the
external components associated to this PMIC output can be omitted from the following schematics.
Active-Semi PMICs have four integrated LDO regulators (OUT4–OUT7) with low noise and high PSRR
performance. OUT4 defaults to 2.5V at startup and is intended to supply the VDDFUSE power input of SAMA5D4x
devices in applications accessing the fuse box in Write mode (e.g., secure applications). This supply channel can
be reassigned to another external component or can be switched off by software in other types of applications.
This output starts by default and must therefore be decoupled. OUT5 defaults to 3.3V at startup and is intended to
feed the VDDANA power input. For both OUT4 and OUT5 channels, the device power consumption on these rails
leaves a large amount of output current available for other external components. However, wiring an external
component on OUT5 along with the VDDANA input prevents this component from being powered off during
operation as the VDDANA input can not be left unpowered.
The remaining LDO channels (OUT6, OUT7) default to OFF at startup. They can be turned on and adjusted under
software control through the I2C link to supply a wide range of external components ranging from digital ICs to
analog/RF ICs such as an audio codec or an RF transceiver.
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The power supply sequencing of the five supply channels is ensured by the Active-Semi PMICs as per
recommendations in the Atmel device datasheet. Therefore the turn-on sequence is the following:
1.
3.3V (both LDO5 and DCDC3)
2.
1.8V (DCDC1)
3.
1.2V (DCDC2).
4.
2.5V (LDO4)
Note that VDDBU must always be present first before ramping the power supplies.
Figure 1-3.
Power Distribution Example on SAMA5D4x Series with ACT8865 (1.8V Memory Case)
1.8V
VDDIODDR
VDDCORE
DCDC1
VCCCOREx
Input
Source
(e.g. 5V)
DCDC2
Core
Regulator
VDDUTMIC
(unused)
VDDPLLA
VDDIOP
3.3V
VDDIOM
VDDOSC
VDDUTMII
DCDC3
2.5V
VDDFUSE
LDO4
3.3V
VDDANA
LDO5
LDO6
LDO7
ACT8865
6
2.0V
LDO
VDDBU
3.0V
Battery
Powering Atmel SAMA5D4 with ActivePMU PMICs [APPLICATION NOTE]
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SAMA5D4x
1.5
Clock Circuits Power Supply
SAMA5D4x devices have separate power supply inputs for their oscillators and PLL circuits. These analog circuits
can therefore be decoupled from the digital (core and I/Os) activity of the device and thus generate less jittered
clocks. Atmel highly recommends to feed these power supply inputs with low noise sources for applications where
clock jitter is important (e.g., high-speed USB). The simplest way to do this is to filter the digital rails with an LC
network as shown in Figure 1-4. Choosing a 20 kHz corner frequency is a good trade-off between component
size/cost and the necessary high frequency attenuation for clock circuits. The inductors must be sized for low DC
resistance and good DC superimposition characteristics (TDK MLZ series and Taiyo Yuden CBM series are
possible choices). The serial resistor in the filter schematic must be adjusted to take the inductor DCR into
account. Example of inductors: Taiyo Yuden CBMF1608T100K (10 µH, 0.36 Ω, 115 mA, 0603) and TDK
MLZ1608N100L (10 µH, 0.6 Ω, 60 mA, 0603).
Figure 1-4.
Recommended Filter on Clock Circuits Power Supply
VDD_3V3
or
VDD_1V8
2.2
10µH
VDDOSC
4.7µF 10nF
2.2
VCCCORE
10µH
VDDPLLA
4.7µF 10nF
1.6
Power Supplies Monitoring
Active-Semi PMICs have an input supply monitor and a power-fail detector on each regulated output which can
generate an interrupt upon a power-fail detection. It is good practice to enable these monitors to detect as early as
possible an input power loss or a fault on any power supply.
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2.
ACT8865 and ACT8945A: Reference Schematics and Description
2.1
ACT8865 Reference Schematic and Description
ACT8865 Reference Schematic
active-semi
VSYS
31
C1
4.7µF
C2
4.7µF
C3
4.7µF
VDD_3V3
R30
4.7k
NRST_3V
R4
1
C31
1nF
R6
1.5k
R31
68k
MPU_NRST_2V
R7
1.5k
C8
1µF
R8
10k
VSYS
5
INL45
6
INL67
ACT8865
30
23
VDDREF
32
REFBP
27
11
nRSTO
nIRQ
13
nPBSTAT
MPU_PIOy
22
21
MPU_TWD
MPU_TWCK
option
(auto-start)
15
SDA
SCL
C9
10µF
C10
100nF
VDD_1V2
L2 2.2µH
C12
10µF
C13
10µF
C14
100nF
VDD_3V3
L3 2.2µH
SW3
19
OUT3
C15
10µF
C16
10µF
C17
100nF
VDD_2V5
VSEL
17
PWREN
OUT4
3
OUT5
4
OUT6
7
OUT7
8
VDD_3V3A
VDD_AUX1
EXPAD
C8
2.2µF
C8
2.2µF
C9
2.2µF
C10
2.2µF
33
14
28
Q3
BSN20
2
PB2
18
PB1
MPU_SHDN
GNDP3
NC1
C25
100nF
VDD_AUX2
nPBIN
GNDP2
9
GNDP1
R12 50k
PWRHLD
GNDA
10
Q2
BSS138
R19
100k
C8
10µF
(option, only if
1.2V needed)
20
RST
50k
R20
100k
Q1
BSS138
R18
1k
VDD_1V8
L1 2.2µH
CST
100nF
VSYS
R19
47k
C5
4.7µF
SW2
24
OUT2
12
MPU_PIOx
C4
4.7µF
SW1
1
OUT1
C8
47nF
R32
110k
C30
22pF
VP1
26
VP2
16
VP3
25
NC2
29
Figure 2-1.
POWER-ON RESET
In this schematic, the power input is VSYS, which can range from 3.5V to 5.5V to start the device. VSYS feeds the
DCDC power inputs (VP1, VP2 and VP3), the LDO regulators power inputs (INL45, INL67) and the reference
voltage power input (VDDREF). This last pin is RC filtered to attenuate high-frequency noise on this sensitive part
of the PMIC. VDD_1V8, VDD_3V3, VDD_2V5, and VDD_3V3A are to be connected to the power supply inputs of
the device. VDD_AUX1 and VDD_AUX2 are two available channels for the applications. If the VDD_1V2 rail is not
needed in the application, SW2 and OUT2 can be left unconnected and in this case, the ACT8865 Buck 2 must be
shut down by software.
8
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2.2
ACT8945A Reference Schematic and Description
Figure 2-2.
ACT8945A Reference Schematic
Wall Adapter Input
VWall (5V)
33
C5
4.7µF
VBUS
ACT8945A
21
Q1
Si2301BDS
R1
11k
R2
3.9k
VSYS
active-semi
CHGIN
ACIN
R3 2.2M
20
C31
1nF
MPU_NRST_2V
23
R6
1.5k
R31
68k
R7
1.5k
R32
110k
C30
22pF
32
39
C7
10µF
C1
4.7µF
C2
4.7µF
C3
4.7µF
C4
4.7µF
35
16
6
28
nSTAT
29
BAT
30
BAT
LBI
R4
1.5M
NRST_3V
31
VBAT
VDD_3V3
R30
4.7k
VSYS
VSYS
VP1
VP2
VP3
INL
R5
2.4k
R8
10k
1
ISET
TH
C6
4.7µF
38
VDD_1V8
L1 2.2µH
SW1
2
OUT1
11
nRSTO
CHGLEV
12
nIRQ
13
nPBSTAT
19
nLBO
Li+ Battery
24
REFBP
C11
47nF
VBAT
C8
10µF
C9
10µF
C10
100nF
22
MPU_PIOw
MPU_PIOx
MPU_PIOy
MPU_PIOz
VDD_1V2
36
SW2
34
OUT2
27
SDA
26
MPU_TWD
MPU_TWCK
SCL
10
OUT4
4
OUT5
5
OUT6
8
OUT7
7
C25
100nF
VDD_3V3
L3 2.2µH
C15
10µF
C16
10µF
nPBIN
C17
100nF
VDD_AUX1
NC1
R19
50k
C26
100nF
VDD_AUX2
41
Q3
BSN20
14
PB2
40
PB1
MPU_SHDN
R19
100k
C14
100nF
VDD_3V3A
EXPAD
9
GNDP3
R12 50k
PWRHLD
GNDP12
option
(auto-start)
GNDA
VSYS
37
Q1
BSS138
R18
1k
C13
10µF
VDD_2V5
R20
100k
Q2
BSS138
25
3
R19
47k
15
SW3
17
OUT3
VSEL
18
PWREN
R9
8.2k
VSYS
C12
10µF
(option, only if
1.2V needed)
C18
2.2µF
C19
2.2µF
C20
2.2µF
C21
2.2µF
POWER-ON RESET
In this schematic, the power inputs are the Li-Ion or Li-Po battery (VBAT), the Wall adapter (VWall) and the USB
voltage VBUS. ACT8945A contains a battery charger and an automatic power switch function that allows the
integrated regulators (DCDCs and LDOs) to run from a single voltage (VSYS) that is built from one of these three
inputs. VSYS feeds the DCDC power inputs (VP1, VP2 and VP3), and the LDO regulators power input INL.
VDD_1V8, VDD_3V3, VDD_2V5, and VDD_3V3A are to be connected to the power supply inputs of the device.
VDD_AUX1 and VDD_AUX2 are two available channels for the applications. If the VDD_1V2 rail is not needed in
the application, SW2 and OUT2 can be left unconnected. In this case, the ACT8865 Buck 2 must be shut down by
software.
2.3
Passive Components Selection and PCB Layout Recommendation
The passive components selection around the DCDCs and LDOs of Active-Semi PMICs is described in these
components’ datasheets. It is very important to follow these recommendations and to properly decouple the
regulator inputs of these PMICS to limit the DCDCs switching currents into the ground and power planes.
A recommended PCB layout/placement is provided with the Active-Semi Evaluation Kit. This is a good starting
point to place and route these PMICs. Moreover, Atmel recommends placing these PMICs as close as possible to
the power source (input connector or regulator output) to limit again switching currents into the ground and power
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planes. In case of inductive power source (long wires), it is good practice to decouple this input with large
capacitors (> 47 µF).
2.4
Digital Interfaces
This section describes the following signals shared between the PMIC and the device:
I2C serial lines SDA and SCL
nRSTO, nPBSTAT, nIRQ outputs
These signals are all of open-drain type and must be pulled-up to the appropriate power rail (in most cases
VDD_3V3 or VDDBU). Due to the low-power constraints generally applied to the VDDBU domain, connections
between the PMIC and an device I/O referenced to VDDBU should be made with maximum care. When possible,
designers may use the programmable pull-up resistor integrated in the device I/O lines to save external resistors.
Two other inputs are available (ACT8945A):
2.4.1
VSEL— selection of the DCDC1 default voltage
CHGLEV—selection of the charge current
I2C Interface
The Active-Semi PMICs are controlled as slave I2C devices. They can be connected to any of the Two-Wire
Interface (TWI) peripherals of the Atmel device. Depending on the programmed speed and the PCB layout
parasitics, external pull-up resistors may be needed on the TWD and TWCK lines to ensure rising edges on these
signals are fast enough. On the programming side, the TWI peripheral should be configured in Master mode as
follows:
7-bit slave address
one byte internal address
one data byte
transfer speed up to 400 kHz (Fast mode)
Due to a limitation of the Active-Semi I 2 C interface, Atmel recommends
dedicating one TWI interface to the PMIC. This interface must not be shared
with any other component. That limitation is documented in the "Errata info"
section of each Active-Semi component datasheet.
However, if sharing cannot be avoided, it is important to ensure that:
IMPORTANT
- the other components are powered by default at startup (i.e. supplied by one
of the OUT1 to OUT5 outputs). This avoids creating a leakage path from the
device I/O pin to an unpowered plane through integrated input pin protection
circuits, and hence losing control on the data or clock line;
- the byte corresponding to the PMIC slave address (1011011x) will never be
sent over the TWD line except to address the PMIC. Otherwise, the PMIC will
force the TWD line to 0 (see "Errata info" section of the relevant Active-Semi
datasheet).
2.4.2
nRSTO Output
The nRSTO signal is the active-low system reset signal. It should be carefully connected to the NRST input of the
SAMA5D4x device that has no internal pull-up and no internal pull-down and that is referenced to VDDBU. One
error to avoid is to pull-up the nRSTO line with a resistor to VDDBU. As VDDBU is an “always-on” power supply in
many applications, there can be cases where the PMIC is not supplied sufficiently to properly assert the nRSTO
line (i.e. the SAMA5D4x is not in reset state) but provides enough voltage on some logic cells. Refer to the R30,
R31, and R32 network in the reference schematics for a recommended solution.
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The PMIC asserts nRSTO low in the following cases:
during a start-up sequence
during a shutdown sequence (either an automatic or a manual shutdown)
upon a reset request on the nPBIN input
When the nPBIN pin is tied to ground through 0Ω (see PB2 in the reference schematic), a system reset is issued.
The nRSTO line is asserted low as soon as the nPBIN is tied to ground and remains low 64 ms after the nPBIN is
released.
2.4.3
nPBSTAT Output
The nPBSTAT output reflects the status of the nPBIN pin in VDDIO level (VDDIO being a generic name for the rail
that supplies the device I/O pin to which nPBSTAT is connected). In the reference schematic, nPBSTAT defaults
to VDD_3V3 and when PB1 is pressed, nPBSTAT is asserted low by the PMIC. This line can be used as an
interrupt source of the device or it can be polled by the device to implement “short” or “long” press detections,
consequently starting specific software routines. Note that pressing PB2 would also assert nPBSTAT (in addition
to nRSTO).
2.4.4
nIRQ Output
The nIRQ line allows the PMIC to interrupt the device on various alarm cases:
The programmable voltage system monitor detects a low input voltage.
One or several regulated outputs drop(s) below the power-good threshold.
A charger related event is detected (e.g., input charger connection/disconnection, safety timeout).
nIRQ can be wired on any GPIO configured by software as an interrupt source. It is generally not useful to wire it
on the device FIQ input.
2.4.5
VSEL Input
This input selects either 1.0V (VSEL = high) or 1.2V (VSEL to ground) as the output voltage for the DCDC2
(OUT2). Depending on the application needs, designers may wire this pin either to VSYS or to ground.
2.4.6
CHGLEV Input (ACT8945A)
This input selects the level of charging current. When high, the nominal charging current is used (e.g., 450 mA
when the USB input is detected). When low, ACT8945A uses the “preconditioning” current, typically the nominal
current divided by 5 (e.g., 90 mA for the USB case). It is recommended to strongly pull down this input to ensure a
low-level on this pin under reset conditions of the device. If not pulled down, the device I/O that defaults to the
“input-pull-up” state when nRSTO is low applies a ‘1’ to this input and hence forces the nominal charging current.
In most cases, this is not an acceptable behavior as the nominal charging current should be first negotiated
between a device and its host. The recommended maximum pull down resistor value is 8.2 kΩ.
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3.
Functional Description of a Typical Use Case
This section describes how Active-Semi PMICs can power on and power off the device power supplies. A typical
application that switches between running and sleeping periods is analyzed in detail (See Figure 3-1). The backup
domain (VDDBU) of the device is powered by a storage element (e.g., a battery followed by a 2.0V regulator) and
the device is placed in Backup mode prior to switching off the supply channels of the PMIC. This case uses the
shutdown controller of the device to enter and leave the Backup mode.
As ACT8865 and ACT8945A only differ in the integration of a Battery Charger + Automatic Power Switch function,
most of the following descriptions are common to both ICs. This application case focuses on non-battery powered
applications (ACT8865). Each important phase illustrated in the timing diagram (e.g., first start-up, software
shutdown) is described in detail in the following sections. The application input voltage is called VSYS which is
either the PMIC input voltage (ACT8865) or the automatic power-switch output (ACT8945A).
Figure 3-1.
Typical Application Timing Diagram
VSYS
VDDBU
(2.0V Regulated)
App. Status
Software Shutdown routine
with shutdown command
OFF
Supply Start.
Processor Reset
Application is running...
Application is in Backup Mode.
RTC is running...
Supply Start.
Proc. Reset
Backup mode exit
upon wake-up event
(e.g., RTC alarm)
PWRHLD
(SHDN)
nPBIN
PB1 pressed
nPBIN activated
by SHDN
VDD_3V3
VDD_1V8
VDD_1V2
(if needed)
VDD_2V5
VDD_3V3A
nRSTO
nPBSTAT
~70 ms
12
long button press
detected by SW
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~70 ms
Application
is running...
3.1
First Power-On
From an OFF state and when VSYS is greater than 3.5V, the application is powered up by asserting the nPBIN to
ground through a 50 kΩ resistor, either manually with a user button (PB1) or automatically at VSYS ramp-up with
the optional CST/RST network from VDDREF input (or VSYS in ACT8945A) to Q3 gate. ACT8865/ACT8945A
require their PWRHLD input to be held to ‘1’ before the nPBIN pin is released. This is achieved by connecting the
PWRHLD pin to the SHDN output of Atmel device through the Q1/Q2 network. This “buffer” network prevents the
VDDBU power supply from back-powering the main power supply when this latter is OFF or disconnected(Note:).
The SHDN pin, designed to control an external regulator enable pin, defaults to ‘1’ (VDDBU level) before the
system starts. At power-on, the PMIC sequences the ramp-up of the five rails (VDD_3V3 and VDD_3V3A,
VDD_1V8, VDD_1V2 and VDD_2V5) and de-asserts the nRSTO line after a typical 64 ms delay. The remaining
channels (OUT6–OUT7) are enabled by software through the I2C serial port.
Figure 3-2.
Typical First Power-On Waveforms (Automatic Start with CST and RST)
VDD_3V3
All Channels
Note:
3.2
2.0V
As a general rule to avoid extra leakages in the VDDBU power domain, the I/Os of the device belonging to
the VDDBU power domain (WKUP0 and SHDN) must not be directly connected to the I/Os of the PMIC. In
case of direct connection, leakage paths from the VDDBU power domain to the main power domain can be
created through the ESD protection diodes of these I/Os.
Power-On From Backup Mode
If the device is in Backup mode, i.e., with only VDDBU pin powered from a storage element, the system can wake
up on either an event on the WKUP0/1 inputs or an RTC alarm event. When such an event occurs, the device
drives the SHDN pin up to ‘1’ (VDDBU level). This transition on the SHDN output is applied to the gate of Q3
through R18/C25 to create a pulse low on nPBIN (through 50 kΩ resistor) which makes the PMIC start. The high
level on SHDN is also applied to the PWRHLD input of the PMIC as required.
3.3
Software Power-Off
When running, the system can be shut down by first stopping the OUT6 and OUT7 LDO regulators through the I2C
interface and then de-asserting the PWRHLD pin of the PMIC. This de-assertion is done by issuing the shutdown
command in the Shutdown Control Register of the device (SHDW_CR.SHDW = 1) which drives the SHDN pin
down to ‘0’.
When the PWRHLD input falls, the PMIC shuts down which means the nRSTO line is asserted low and the
regulators OUT1–OUT5 are simultaneously stopped.
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Assertion of the shutdown command makes the device enter Backup mode. To exit this mode, the application
must have configured the wake-up source (WKUP0 pin event or RTC alarm event) before asserting the shutdown
command. Refer to the Shutdown Controller (SHDWC) section and the Electrical Characteristics section (Lowpower Modes) of the Atmel device datasheet for further details.
Figure 3-3.
Typical Software Power-Off Waveforms
All Channels
Note:
3.4
1.0V
The ACT8865/ACT8945A PMICs have a special MSTROFF bit which can use an I2C command to perform
a power-off. When sending this command over the I2C bus, the nRSTO line falls abnormally before the
“stop-condition” of the I2C transfer. Atmel does not recommend to use this method. In case this feature is to
be used, it is advisable to install a few microseconds delay network on the nRSTO line of the PCB.
Power-Off Upon Input Power Loss
I n c a s e o f i n p u t p o w e r l o s s ( V S Y S ) , t h e s ys t e m p o w e r - o f f c a n a l s o b e m a n a g e d b y t h e P M I C .
ACT8865/ACT8945A integrate a programmable system voltage monitor that compares the VDDREF (ACT8865)
or VSYS (ACT8945A) input to a programmable threshold set to 3.0V by default. If the input power falls below this
threshold, one of two possible actions occurs:
An “Under Voltage Alarm” interrupt is sent to the device through the nIRQ line and a software power-off is
started by the application. In particular, for SAMA5D4x devices equipped with an external LPDDR2 memory,
this flag can be used to avoid an “Uncontrolled Power-Off” of the LPDDR2 device.
The PMIC initiates an automatic power-off sequence (without device intervention).
The behavior of the PMIC in response to the system voltage monitor is programmed by the nSYSMODE[ ] bit (see
ACT8865/ACT8945A datasheets).
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4.
Active-Semi PMICs and Atmel SAMA5D4x Low-Power Modes
4.1
Active-Semi PMIC Power-Saving Mode
ACT8865 and ACT8945A integrated DCDCs feature a Power-Saving Mode (PSM) to reduce their power
consumption at light output load. By default at startup, the DCDCs operate in fixed frequency Pulse Width
Modulation (PWM) mode. This mode achieves the best ripple and regulation performance. Typically, when
operated in PWM mode, the three DC/DC converters current consumption is about 20 mA @ 5V input voltage or
15 mA @ 3.7V.
To operate the DCDCs in PSM, the application needs to clear the MODE[] bits of registers REG1, REG2 and
REG3 in the PMIC user interface. The current consumption is then reduced to 330µA @ 5V input or
300 µA @ 3.7V. The penalty of this mode is a slightly higher output voltage ripple (about 10 mVpp compared to
less than 5 mVpp in PWM) and higher transient output voltage under load steps. Figure 4-1 reports output voltage
ripple on VDD_1V2 for both the PSM and the PWM modes. These curves are obtained with the following
conditions: VIN = 5V, VDD_1V2 = 1.2V. The red curve is the switching node (SW2), and the blue curve is the
output voltage AC-coupled at 10 mV/division.
Figure 4-1.
Ripple Performance in Power-Saving Mode (Left) and in PWM Mode (Right)
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Figure 4-2 reports transient load regulation on VDD_1V2 for both PSM and PWM mode. The load step (red curve)
is 0–100 mA in PSM and 0–500 mA in PWM mode. The rise and fall time of the load current is 1 µs. These curves
are obtained with the following conditions: VIN = 5V, VDD_1V2 = 1.2V. The blue curve is the output voltage ACcoupled at 50 mV/division.
Figure 4-2.
Transient Load Performance in Power-Saving Mode (Left) and in PWM Mode (Right)
When the MODE[] bits of registers REG1, REG2 and REG3 are cleared, the DCDCs automatically transition from
PWM mode to PSM at light load current and conversely transition back to PWM mode if the load current is
increased (wake-up cases).
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4.2
SAMA5D4x Series Low-Power Modes
Table 4-1 summarizes the low-power modes of SAMA5D4x devices with indicative power consumption figures at
25 °C. In Idle mode and in Ultra Low-Power mode, the power supplies are still ON with reduced power
consumption and it is therefore relevant to set the DC/DC converters in PSM.
Table 4-1.
Active Power Supplies in SAMA5D4x Low-Power Modes
Power Rail
Backup Mode
Idle Mode
Ultra Low-Power Mode
VDD_3V3
OFF
Application dependent
200 µA(3)
VDD_1V8
OFF
54 mA(1)
5.9 mA(2)
VDDBU
Notes:
1.
2.
3.
7 µA typical
MCK at 170 MHz
MCK at 750 kHz
Typical conditions
For maximum regulation performance, the PSM should be activated as late as possible in the process of entering
the Ultra Low-Power mode of the device. In a similar way, the PWM mode should be restored as soon as possible
when re-entering Run mode.
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5.
Linux Driver Content and Description
5.1
Linux Voltage and Current Regulator Framework
The PMIC driver is implemented as a regulator driver under the voltage and current regulator framework. The
framework is designed to provide a standard kernel interface to control voltage and current regulators. It provides
the following four parts:
Regulator Driver—The regulator is defined as a device that supplies power to other devices. The framework
provides the interface to allow drivers to register the regulators and provide operations to the core.
Consumer Driver—The consumer is defined as a device that is supplied by a regulator. The framework
provides the interface to allow the consumer to complete the control over their supply voltage and current
limit.
Machine Special Setup Code—The framework provides interface to allow the machine special setup code to
create the voltage/current constraints for each regulator, and to create a regulator tree whereby some
regulators are supplied by others. It is substituted by the device tree in the latest version.
Userspace Interface—The framework also exports useful information to userspace via sysfs.
For more information about the Linux regulator framework, refer to the Linux kernel document.
Documentation/power/regulator/overview.txt.
5.2
ACT8865 Regulator Driver
The ACT8865 regulator driver source code is available at:
drivers/regulator/act8865-regulator.c.
As mentioned above, the Active-Semi PMIC (ACT8865) is controlled as a slave I 2C device, so the ACT8865
regulator driver is implemented as an I 2 C client driver using the i2c_driver model. The code configures the
regulator_desc structure for each regulator, and registers the regulators to the core by invoking
devm_regulator_register(). To ease the development, the register map library (regmap) and the helper functions
are used.
5.3
Kernel Configurations to Enable ACT8865 Driver
The ACT8865 driver is enabled through the kernel configuration.
Device Drivers --->
[*] Voltage and Current Regulator Support --->
<*> Active-semi act8865 voltage regulator
5.4
Declaring the Regulator Device Node
To make the regulators work, the ACT8865 device must be properly declared in the device tree files.
ACT8865 is declared as an I2C client device with the I2C slave address 0x5B assigned by the property ‘reg’.
More regulator properties defined as the regulator binding are available in the Linux kernel document.
Documentation/devicetree/bindings/regulator/regulator.txt.
Documentation/devicetree/bindings/regulator/act8865-regulator.txt
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For example, the regulator device node on the SAMA5D4x-EK is declared as follows:
i2c0: i2c@f8014000 {
status = "okay";
pmic: act8865@5b {
compatible = "active-semi,act8865";
reg = <0x5b>;
status = "okay";
regulators {
vcc_1v8_reg: DCDC_REG1 {
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vcc_1v2_reg: DCDC_REG2 {
regulator-name = "1V2_HDMI";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vcc_3v3_reg: DCDC_REG3 {
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_2v5_reg: LDO_REG1 {
regulator-name = "FUSE_2V5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
vdd_3v3_reg: LDO_REG2 {
regulator-name = "VDDANA";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_1v8_reg: LDO_REG3 {
regulator-name = "1V8_AUDIO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
};
};
};
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The values of the regulator properties are assigned by the hardware design, such as regulator-min-microvolt and
regulator-max-microvolt. It is advisable to name the ‘regulator-name’ property with the supply name in the
schematic to ease system analysis.
5.5
Regulator Consumer Driver
The regulator consumer uses a regulator to change the power supply voltage or turn on/off the power. The
consumer selects the regulator to use in the regulator mapping.
This mapping can be achieved through the device tree using the bindings below in the consumer node.
- <name>-supply: phandle to the regulator node
The name is used as the power supply ID to have access to its supply regulator.
The regulator framework provides the consumer driver interfaces to set regulator voltage and enable/disable it.
The detailed description of consumer interfaces is available in the Linux kernel document.
Documentation/devicetree/bindings/regulator/consumer.txt.
Add WM8904 consumer node property to point to the corresponding regulator node with the proper power ID in the
device tree.
i2c0: i2c@f8014000 {
status = "okay";
wm8904: codec@1a {
compatible = "wm8904";
reg = <0x1a>;
DCVDD-supply = <&vdd_1v8_reg>;
DBVDD-supply = <&vdd_3v3_reg>;
AVDD-supply = <&vdd_1v8_reg>;
CPVDD-supply = <&vdd_1v8_reg>;
MICVDD-supply = <&vdd_3v3_reg>;
};
};
5.6
Regulator Sysfs Entries
Useful regulator information can be read from the user space via sysfs. This method is useful to monitor device
power consumption and status.
For more information, refer to the Linux kernel document.
Documentation/ABI/testing/sysfs-class-regulator
# cd /sys/class/regulator/
# ls
regulator.0 regulator.2 regulator.4 regulator.6
regulator.1 regulator.3 regulator.5 regulator.7
# ls regulator.1/
device
suspend_disk_microvolts
max_microvolts
suspend_disk_state
microvolts
suspend_mem_microvolts
min_microvolts
suspend_mem_state
name
suspend_standby_microvolts
num_users
suspend_standby_state
power
type
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state
uevent
subsystem
# ls regulator.2/
device
suspend_disk_microvolts
max_microvolts
suspend_disk_state
microvolts
suspend_mem_microvolts
min_microvolts
suspend_mem_state
name
suspend_standby_microvolts
num_users
suspend_standby_state
power
type
state
uevent
subsystem
# cat regulator.2/name
1V2_HDMI
# cat regulator.2/type
voltage
# cat regulator.2/state
enabled
# cat regulator.2/max_microvolts
1200000
# cat regulator.2/min_microvolts
1200000
# cat regulator.2/microvolts
1200000
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Revision History
Table 5-1.
Doc. Rev.
Powering Atmel SAMA5D4 with ActivePMU PMICs Revision History
Date
Changes
Table 1-1, “SAMA5D4x Series Power Supply Inputs”: changed VDDUTMIC and VDDOSC.
44000B
30-Apr-15
Figure 1-4, “Recommended Filter on Clock Circuits Power Supply”: removed VDDUTMIC and
associated components.
Figure 2-2, “ACT8945A Reference Schematic”: NC1 now pin 40. PWREN now pin 18.
Removed NC2.
44000A
22
01-Oct-14
First release
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contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended,
authorized, or warranted for use as components in applications intended to support or sustain life.
SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where
the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written
consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems.
Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are
not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.