AVR096: Migrating from ATmega128 to AT90CAN128 This application note is a guide to help current ATmega128 users convert existing designs to AT90CAN128. The information given will also help users migrating from any ATmega microcontroller to AT90CAN128. Additionally, the electrical characteristics of the AT90CAN128 are different than those of ATmega128. Check the datasheets of both of these products for detailed information. Features 8-bit Microcontroller The main features of the ATmega128 have been carried over to the AT90CAN128. • • • • • • • • • • Advance RISC Architecture 128 KB Flash & 4 KB E 2PROM with Software Security 4 KB internal RAM & 64 KB external RAM Watchdog Timer, 8-bit Timer & 8-bit Real Time Timer & Two 16-bit Timers 8-channel 10-bit SAR ADC & Analog Comparator Dual USART, SPI & TWI 8 External Interrupts POR/PFD & Sleep Modes Operating Voltage from 2.7V up to 5.5V 16 MHz Maximum Frequency (5V range) Application Note The more important evolution is the full-CAN (Controller Area Network) peripheral implementation in the AT90CAN128. Other features have been added such as three General Purpose Registers (one of them is bit-accessible) and two Digital Input Disable Registers for analog I/Os. To be compatible with the new generation of 8-bit AVR microcontrollers (i.e. ATmega169), the register mapping had been re-modelled. This new distribution restructures the addressing to improve its coherence and thus to privilege readability. The AT90CAN128 also has some improvements on Timers, Analog to Digital Converter and Clocks. 4313B–AVR–03/04 Pin Configuration The AT90CAN128 is functionally pin compatible with ATmega128. Certain pins have been upgraded with regard to their associated alternate functions, the change of the timers/counters index and the voluntary removal ATmega103 compatibility. VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) 50 49 GND 51 PF7 (ADC7 / TDI) 54 53 52 PF5 (ADC5 / TMS) PF6 (ADC6 / TDO) 55 57 56 PF3 (ADC3) PF4 (ADC4 / TCK) 58 PF1 (ADC1) PF2 (ADC2) 60 59 AREF PF0 (ADC0) 62 61 AVCC GND PA2 (AD2) 49 64 PA1 (AD1) 50 63 VCC PA0 (AD0) GND 51 PF7 (ADC7 / TDI) 54 53 52 PF5 (ADC5 / TMS) PF6 (ADC6 / TDO) 55 57 56 PF3 (ADC3) PF4 (ADC4 / TCK) 58 PF1 (ADC1) PF2 (ADC2) PF0 (ADC0) 59 AREF 62 61 60 AVCC GND 64 63 Figure 1. Pin Configuration PEN 1 48 PA3 (AD3) (n.c.) 1 48 PA3 (AD3) (RXD0 / PDI) PE0 2 47 PA4 (AD4) (RXD0 / PDI) PE0 2 47 PA4 (AD4) 46 PA5 (AD5) INDEX CORNER INDEX CORNER (TXD0 / PDO) PE1 3 46 PA5 (AD5) (TXD0 / PDO) PE1 3 (XCK0 / AIN0) PE2 4 45 PA6 (AD6) (XCK0 / AIN0) PE2 4 45 PA6 (AD6) (OC3A / AIN1) PE3 5 44 PA7 (AD7) (OC3A / AIN1) PE3 5 44 PA7 (AD7) PG2 (ALE) (OC3B / INT4) PE4 6 43 PG2 (ALE) (OC3B / INT4) PE4 6 43 (OC3C / INT5) PE5 7 42 PC7 (A15) (OC3C / INT5) PE5 7 42 PC7 (A15 / CLKO) (T3 / INT6) PE6 8 41 PC6 (A14) (T3 / INT6) PE6 8 (IC3 / INT7) PE7 9 40 PC5 (A13) (IC3 / INT7) PE7 9 (SS) PB0 10 39 PC4 (A12) (SS) PB0 10 39 PC4 (A12) (SCK) PB1 11 38 PC3 (A11) (SCK) PB1 11 38 PC3 (A11) ATmega128 (top view) AT90CAN128 (top view) 41 PC6 (A14) 40 PC5 (A13) (MOSI) PB2 12 37 PC2 (A10) (MOSI) PB2 12 37 PC2 (A10) (MISO) PB3 13 36 PC1 (A9) (MISO) PB3 13 36 PC1 (A9) PC0 (A8) 30 31 32 (TXCAN / XCK1) PD5 (RXCAN / T1) PD6 (T0) PD7 (IC1) PD4 29 (TXD1 / INT3) PD3 28 (RXD1 / INT2) PD2 27 (SCL / INT0) PD0 25 (SDA / INT1) PD1 26 XTAL2 23 XTAL1 24 VCC 21 19 (TOSC1) PG4 GND 22 18 (TOSC2) PG3 RESET 20 17 (OC0A / OC1C) PB7 (T2) PD7 32 PG0 (WR) (T1) PD6 31 33 (XCK1) PD5 30 16 (IC1) PD4 29 (OC1B) PB6 (TXD1 / INT3) PD3 28 PG0 (WR) (RXD1 / INT2) PD2 27 33 (SCL / INT0) PD0 25 16 (SDA / INT1) PD1 26 PG1 (RD) (OC1B) PB6 XTAL2 23 34 XTAL1 24 35 15 GND 22 14 (OC1A) PB5 VCC 21 (OC2A) PB4 PG1 (RD) RESET 20 PC0 (A8) 34 (TOSC1) PG4 19 35 15 (TOSC2) PG3 18 14 (OC2 / OC1C) PB7 17 (OC0) PB4 (OC1A) PB5 Table 1. Changed Pins Pin 2 ATmega128 AT90CAN128 Comments for AT90CAN128 1 PEN (n.c.) Not connected Removal ATmega103 compatibility mode. 14 PB4 (OC0) PB4 (OC2A) The asynchronous-Real Time Timer/Counter index becomes 2 instead of 0. 17 PB7 (OC2/OC1C) PB7 (OC0A/OC1C) The synchronous 8-bit Timer/Counter index becomes 0 instead of 2. 18 PG3 (TOSC2) PG3 (TOSC2) 19 PG4 (TOSC1) PG4 (TOSC1) 30 PD5 (XCK1) PD5 (XCK1/TXCAN) 31 PD6 (T1) PD6 (T1/RXCAN) Addition of CAN I/O’s as alternate functions. These alternate functions are enabled once the CAN peripheral is switched “ON”. 32 PD7 (T2) PD7 (T0) The synchronous 8-bit Timer index becomes 0 instead of 2. 42 PC7 (A15) PC7 (A15/CLKO) Addition of Clock output (CLKO) as alternate function. This alternate function is enabled/disabled by CKOUT fuse of the Fuse Low Byte. No pin name changes, the TOSC crystal is always connected to the Asynchronous-Real Time Timer/Counter but the index of this timer/counter becomes 2 instead of 0. AVR096 4313B–AVR–03/04 AVR096 AVR CORE System Clock Sources Four sources for system clock are available in AT90CAN128: • On-chip oscillator for external crystal or ceramic resonator • On-chip oscillator for external low-frequency crystal • Calibrated internal RC oscillator • External clock Unlike ATmega128, no external RC network can be connected to XTAL1 pin. Amplifier Mode XTAL1 and XTAL2 are input and output, respectively, from an inverting amplifier of the on-chip oscillators. On ATmega128, the CKOPT fuse selects between two oscillator amplifier modes. If CKOPT is programmed, the oscillator output oscillates with a full rail-to-rail swing on the output. If CKOPT is unprogrammed, the oscillator has a smaller output swing. This mode is not present on ATmega128CAN11. Prescaler The Clock Prescaler Register - CLKPR of ATmega128CAN11, replaces the XTAL Divide Control Register - XDIV. The clock division factor (CLKPS[3..0] field of CLKPR) is now a 2n number from 1 up to 256. Table 1. Clock Prescaler Select ATmega128 XDIV[6..0] d CLKDIV8 Fuse Frequency fCLK = fSource Clock / (129-d) AT90CAN128 CLKPS[3..0] Frequency 0x0 fCLK = fSource Clock 0x1 fCLK = fSource Clock / 2 0x2 fCLK = fSource Clock / 4 0x3 fCLK = fSource Clock / 8 0x4 fCLK = fSource Clock / 16 0x5 fCLK = fSource Clock / 32 0x6 fCLK = fSource Clock / 64 0x7 fCLK = f Source Clock / 128 0x8 fCLK = f Source Clock / 256 0x9 to 0xF Reserved A new fuse (CKDIV8 - bit 7 of Fuse Low Byte) determines the initial value of the clock prescaler in AT90CAN128. If CKDIV8 is unprogrammed, the prescaler is initialized with “0x0”. Programmed, the prescaler is initialized with “0x3”, giving a division factor of “8” at start-up. 3 4313B–AVR–03/04 Table 2. Clock Prescaler Initialization ATmega128 XDIV[6..0] Frequency 0x00 fCLK = fSource Clock / 129 AT90CAN128 CKDIV8 CLKPS[3..0] Frequency 1 0x0 fCLK = fSource Clock 0 0x3 fCLK = fSource Clock / 8 Oscillator Calibration During reset, hardware loads the calibration byte into the OSCCAL Register and thereby automatically calibrates the internal RC Oscillator. OSCCAL Register is accessible by software. In ATmega128, 8 bits of OSCCAL Register are used, in AT90CAN128, only the 7 low significant bits are used. Sleep Modes The Extended Standby sleep mode of ATmega128 disappears in the sleep mode list of AT90CAN128. The active clock domains and wake-up sources in the different sleep modes does not change. Table 3. Sleep Modes ATmega128 AT90CAN128 Sleep Mode Select SM[2..0] Reset Logic 4 0 Idle Idem 1 ADC Noise Reduction Idem 2 Power-down Idem 3 Power-save Idem 4 “reserved” Idem 5 “reserved” Idem 6 Standby Idem 7 Extended Standby “reserved” The AT90CAN128 reset logic differs from the ATmega128 one by the Brown-Out Detection (BOD). This is due to a new set of fuse bits (See “Fuse Bits” on page 7.). AVR096 4313B–AVR–03/04 AVR096 Table 4. Brown-Out Detection ATmega128 AT90CAN128 Detected level Typ. VBOT Setting Detected level Typ. VBOT Setting Disable BODEN(1)=“1” Disable BODLEVEL[2..0](3)=“111” 4.1 V (4) BODLEVEL[2..0](3)=“110” 4.0 V (4) BODLEVEL[2..0](3) =“101” 3.9 V (4) BODLEVEL[2..0](3) =“100” 3.8 V (4) BODLEVEL[2..0](3)=“011” 2.7 V (4) BODLEVEL[2..0](3) =“010” 2.6 V (4) BODLEVEL[2..0](3) =“001” 2.5 V (4) BODLEVEL[2..0](3) =“000” BODEN(1)=“0” BODLEVEL(2)=“0” 4.0 V (1) BODEN =“0” BODLEVEL(2)=“1” 2.7 V Notes: Interrupt Table 1. 2. 3. 4. BODEN: Fuse Bit 6 - Fuse Low Byte of ATmega128. BODLEVEL: Fuse Bit 7 - Fuse Low Byte of ATmega128. BODLEVEL[2..0]: Fuse Bits 3, 2 & 1 - Extended Fuse Byte of AT90CAN128. Theorical values, refer to AT90CAN128 data sheet. There are two additional interrupts in AT90CAN128, the CAN interrupts. All the Timer/Counter1 interrupts have been clustered (c.f. TIMER1 COMPC interrupt). The interrupts are compatible up to the 14th vector. Table 5. Interrupt Table Vector No. Program Address(2) 1 0x0000(1) 2 ATmega128 AT90CAN128 Interrupt Source Interrupt Source External Reset pin, POR, BOR, WD Reset & JTAG AVR Reset Idem 0x0002 External Interrupt Request 0 Idem 3 0x0004 External Interrupt Request 1 Idem 4 0x0006 External Interrupt Request 2 Idem 5 0x0008 External Interrupt Request 3 Idem 6 0x000A External Interrupt Request 4 Idem 7 0x000C External Interrupt Request 5 Idem 8 0x000E External Interrupt Request 6 Idem 9 0x0010 External Interrupt Request 7 Idem 10 0x0012 T/C2 Compare Match Idem 11 0x0014 T/C2 Timer Overflow Idem 12 0x0016 T/C1 Capture Event Idem 13 0x0018 T/C1 Compare Match A Idem 5 4313B–AVR–03/04 Table 5. Interrupt Table (Continued) 6 AT90CAN128 Interrupt Source Interrupt Source Program Address(2) 14 0x001A T/C1 Compare Match B 15 0x001C T/C1 Timer Overflow T/C1 Compare Match C 16 0x001E T/C0 Compare Match T/C1 Timer Overflow 17 0x0020 T/C0 Timer Overflow T/C0 Compare Match 18 0x0022 SPI Transfer Complete T/C0 Timer Overflow 19 0x0024 USART0, Rx Complete CAN Transfer Complete or Error 20 0x0026 USART0 Data Register Empty CAN Timer Overrun 21 0x0028 USART0, Tx Complete SPI Transfer Complete 22 0x002A ADC Conversion Complete USART0, Rx Complete 23 0x002C EEPROM Ready USART0 Data Register Empty 24 0x002E Analog Comparator USART0, Tx Complete 25 0x0030 T/C1 Compare Match C Analog Comparator 26 0x0032 T/C3 Capture Event ADC Conversion Complete 27 0x0034 T/C3 Compare Match A EEPROM Ready 28 0x0036 T/C3 Compare Match B T/C3 Capture Event 29 0x0038 T/C3 Compare Match C T/C3 Compare Match A 30 0x003A T/C3 Timer Overflow T/C3 Compare Match B 31 0x003C USART1, Rx Complete T/C3 Compare Match C 32 0x003E USART1 Data Register Empty T/C3 Timer Overflow 33 0x0040 USART1, Tx Complete USART1, Rx Complete 34 0x0042 TWI Interface USART1 Data Register Empty 35 0x0044 Store Program Memory Ready USART1, Tx Complete 36 0x0046 / TWI Interface 37 0x0048 / Store Program Memory Ready Notes: ATmega103 Compatibility ATmega128 Vector No. Idem 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset. 2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. The ATmega103 compatibility mode of ATmega128 does not exist in AT90CAN128. For further information, please refer to “ATmega103 and ATmega128 Compatibility” section of ATmega128 datasheet. AVR096 4313B–AVR–03/04 AVR096 Memory Fuse Bits Extended Fuse Byte All the valid bits of Extended Fuse Byte of AT90CAN128 are different from those of ATmega128. Table 6. Extended Fuse Byte ATmega128 AT90CAN128 Bit Fuse High Byte Name Description Name Description 7 - - - - 6 - - - - 5 - - - - 4 - - - - 3 - - BODLEVEL2 2 - - BODLEVEL1 1 M103C ATmega103 compatibility mode BODLEVEL0 0 WDTON Watchdog Timer always “on” TA0SEL Brown-out detector trigger level (Reserved for factory tests) Only the bit number 4 of Fuse High Byte of AT90CAN128 is different from the one in ATmega128. Table 7. Fuse High Byte ATmega128 AT90CAN128 Bit Name Description Name Description 7 OCDEN Enable OCD Idem Idem 6 JTAGEN Enable JTAG Idem Idem 5 SPIEN Enable serial program and data downloading Idem Idem 4 CKOPT Oscillator option 3 EESAVE E2PROM is preserved through the chip erase 2 BOOTSZ1 WDTON Idem BOOTSZ0 0 BOOTRST Idem Idem Select boot size 1 Watchdog Timer always “on” Idem Idem Select reset vector Idem Idem 7 4313B–AVR–03/04 Fuse Low Byte Bits number 7 and 6 of Fuse Low Byte of AT90CAN128 are different from those of ATmega128. Table 8. Fuse Low Byte ATmega128 AT90CAN128 Bit Name Description Name Description 7 BODLEVEL Brown-out detector trigger level CKDIV8 Divide clock by 8 at start-up 6 BODEN Brown-out detector enable CKOUT Clock output enable 5 SUT1 Idem Select start-up time Idem 4 SUT0 Idem 3 CLKSEL3 Idem 2 CLKSEL2 Idem Select clock source Signature Bytes Idem 1 CLKSEL1 Idem 0 CLKSEL0 Idem Because AT90CAN128 and ATmega128 mainly differ by their I/O modules, only the third byte changes. Table 9. Signature Bytes Byte JTAG Identification Register ATmega128 AT90CAN128 Value Value Description 0 Manufacturer 0x1E (ATMEL) Idem 1 Flash Memory Size 0x97 (128 KB) Idem 2 Device 0x02 0x81 For the same reason as signature bytes, only the part number field changes (revision field not included). Table 10. JTAG Identification Register ATmega128 AT90CAN128 Field Field Value Device Revision Field Value Register Value (1) 0x0 0x0 Part Number 0x9702 Manufacturer ID (+ lsb=0) 0x01E Idem lsb 0x1 Idem Notes: 8 Register Value (1) 0x9781 0x0970201F 0x0978101F 1. Refer to data sheets for the last revision field value. AVR096 4313B–AVR–03/04 AVR096 I/O Modules External Memory Interface In AT90CAN128, CLKO (Clock output) has been added as alternate function of PC7 (Port C - Bit 7). Another alternate function of PC7 is A15 (external memory interface address 15). Because CLKO is enabled/disabled by CKOUT fuse, it has priority over any external memory interface setting. If CLKO is enabled, the minimum setting of XMM field in External Memory Control Register B - XMCRB - must be “001” to be in agreement with the PC7 configuration. Synchronous 8-bit Timer/Counter Index/Name The Timer/Counter2 of ATmega128 becomes Timer/Counter0 in AT90CAN128. The features of the Timer/Counter are maintained. The I/O pin locations remain unchanged (See “Pin Configuration” on page 2). Asynchronous 8-bit Timer/Counter Index/Name The Timer/Counter0 of ATmega128 becomes Timer/Counter2 in AT90CAN128. The features of the Timer/Counter are maintained, especially the asynchronous mode. The I/O pin locations remain unchanged (See “Pin Configuration” on page 2.). Asynchronous Clock An external clock source can be applied to PG4 (TOSC1) pin for asynchronous operation on Timer/Counter2 of AT90CAN128. In this configuration, PG3 (TOSC2) is available as standard I/O. Table 11. Asynchronous Timer Sources ATmega128 Source Setting AT90CAN128 Source Default at start-up CLK IO TOSC oscillator for external watch crystal Notes: Synchronous Timer/Counter Prescaler AS0(1)=“0” AS0(1)=“1” Setting Default at start-up CLKIO AS2(2)=“0” EXCLK(3)=“0” TOSC oscillator for ext. watch crystal AS2(2)=“1” EXCLK(3)=“0” External clock on TOSC1 pin AS2(2)=“1” EXCLK(3)=“1” 1. AS0: Bit 3 - Timer/Counter0 ASSR (ATmega128). 2. AS2: Bit 3 - Timer/Counter2 ASSR (AT90CAN128). 3. EXCLK: Bit 4 - Timer/Counter2 ASSR (AT90CAN128). The prescaler reset of the synchronous timers/counters of ATmega128 is named PRS321 due to the index of the three timers/counters driven by this prescaler. On AT90CAN128, automatically its name becomes PRS310. Asynchronous Timer/Counter Prescaler The prescaler reset of the asynchronous timers/counter of ATmega128 is named PRS0 due to the index of the timer/counter driven by this prescaler. On AT90CAN128, automatically its name becomes PRS2. 9 4313B–AVR–03/04 ADC A new feature has been added in ADC of AT90CAN128: the auto triggering. A conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. Table 12. ADC Conversions ATmega128 Mode Setting Mode Setting Single conversion start ADCS(1)=“1” ADFR(2)=“0” Single conversion start ADCS(1)=“1” ADATE(3)=“0” Free running mode start ADCS(1)=“1” ADFR(2)=“1” Starting with trigger source: Free running mode ADCS(1)=“1” ADATE(3)=“1” ADST[2..0] (4)=“000” - - Starting with trigger source: Analog comparator ADCS(1)=“1” ADATE(3)=“1” ADST[2..0] (4)=“001” - - Starting with trigger source: Ext. Int. Request 0 ADCS(1)=“1” ADATE(3)=“1” ADST[2..0] (4)=“010” - Starting with trigger source: T/C0 compare match ADCS(1)=“1” ADATE(3)=“1” ADST[2..0](4)=“011” - Starting with trigger source: T/C0 overflow ADCS(1)=“1” ADATE(3)=“1” ADST[2..0] (4)=“100” - - Starting with trigger source: T/C1 compare match B ADCS(1)=“1” ADATE(3)=“1” ADST[2..0] (4)=“101” - - Starting with trigger source: T/C1 overflow ADCS(1)=“1” ADATE(3)=“1” ADST[2..0](4)=“110” - - Starting with trigger source: T/C1 capture event ADCS(1)=“1” ADATE(3)=“1” ADST[2..0](4)=“111” Free running mode stop ADFR(2)=“0” Free running mode stop ADATE(3)=“0” - - Notes: 10 AT90CAN128 1. 2. 3. 4. ADCS: Bit 6 - ADCSRA (ATmega128 & AT90CAN128). ADFR: Bit 5 - ADCSRA (ATmega128). ADATE: Bit 5 - ADCSRA (AT90CAN128). ADST[2..0]: Bits 2..0 - ADCSRB (AT90CAN128). AVR096 4313B–AVR–03/04 AVR096 I/O Registers The I/O space definition of the ATmega128 and the AT90CAN128 is shown in the “Register Summary” section of the datasheets respectively. All I/O registers are placed in the I/O space from address 0x20 up to 0xFF. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions. • The I/O registers from 0x20 up to 0x5F may be also accessed by the specific instructions IN and OUT but 0x20 must be subtracted to these addresses. • I/O registers within the address range 0x20 - 0x3F also are directly bit-accessible using the SBI/CBI/SBIS/SBIC instructions but 0x20 must be subtracted to these addresses. Some of the status flags are cleared by writing a logical one. Note that the SBI instructions operates on such status flags in this address range. • For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST and LD instructions can be used. Note: Migrating an assembler source code from ATmega128 to AT90CAN128 may force to change the assembler line of an I/O register access. Table 13. I/O Registers ATmega128 AT90CAN128 (0x95) UCSR0C (0x90) UBRR0H (0x8C) TCCR3C (0x8B) TCCR3A COM3A [1,0] (0x8A) TCCR3B (0x89) TCNT3H (0x88) TCNT3L (0xCA) Idem Idem (0xCE) Idem Idem Idem Idem Idem Idem Idem Idem (0xCD) Idem Idem (0xC2) Idem Idem (0xC5) Idem Idem (0x92) Idem Idem (0x90) Idem Idem (0x91) Idem Idem T/C3 Counter Register High Byte (0x95) Idem Idem T/C3 Counter Register Low Byte (0x94) Idem Idem UPM1 [1,0] UCSZ1 [1,0] FE1 DOR1 UPE1 U2X1 MPCM1 TCEN1 UCSZ12 RXB81 TXB81 (0xC9) USART1 Baud Rate Register Low Byte (0xCC) UDRIE1 UDRE1 (0xC8) RXEN1 USART1 I/O Data Register UPM0 [1,0] USART0 Baud Rate Register High FOC3C FOC3B - ICES3 UCSZ0 [1,0] UCPOL0 UMSEL0 - USBS0 USART1 Baud Rate Register High - - COM3B [1,0] - COM3C [1,0] WGM3 [3,2] WGM3 [1,0] CS3[2..0] Bit 0 UBRR1H Name Bit 1 (0x98) Add. Bit 2 TXCIE1 UBRR1L Bit 3 RXCIE1 (0x99) Bit 4 TXC1 UCSR1B Bit 5 RXC1 (0x9A) Bit 6 UCSR1A Bit 7 (0x9B) UCPOL1 Bit 0 UDR1 Register Content Bit 1 (0x9C) Bit 2 - USBS1 Bit 3 UCSR1C Bit 4 Bit 7 (0x9D) Bit 5 Name FOC3A UMSEL1 Bit 6 Add. ICNC3 Register Content 11 4313B–AVR–03/04 Table 13. I/O Registers (Continued) ATmega128 AT90CAN128 (0x84) OCR3BL T/C3 Output Compare B Register Low Byte (0x9A) Idem Idem (0x83) OCR3CH T/C3 Output Compare C Register High Byte (0x9D) Idem Idem (0x82) OCR3CL T/C3 Output Compare C Register Low Byte (0x9C) Idem Idem (0x81) ICR3H T/C3 Input Capture Register High Byte (0x97) Idem Idem (0x80) ICR3L T/C3 Input Capture Register Low Byte (0x96) Idem Idem (0x6F) TIMSK1 - - - (0x71) TIMSK3 - - - 0x16-(0x36) TIFR1 - - - 0x18-(0x38) TIFR3 - - - (0x82) Idem Idem Idem (0x78) OCR1CL T/C1 Output Compare C Register Low Byte (0x8C) Idem Idem (0x74) TWCR (0xBC) Idem Idem (0x73) TWDR (0xBB) Idem Idem (0x72) TWAR (0xBA) Idem Idem (0x71) TWSR TWPS [1,0] (0xB9) Idem Idem (0x70) TWBR TWI Bit Rate Register (0xB8) Idem Idem (0x6F) OSCCAL CAL[7..0] (0x66) Idem - (0x6D) XMCRA (0x74) XMCRA SRE TWI I/O Data Register TWS[7..3] - SRL[2..0] - SRW0 [1,0] SRW11 TWA[6..0] - Bit 0 Bit 1 CAL[6..0] SRL[2..0] SRW11 - SRW10 OCF1C Idem TWIE (0x8D) TWEN T/C1 Output Compare C Register High Byte TWWC - TWSTO OCR1CH TWSTA (0x79) TWEA TCCR1C TWINT (0x7A) TWGCE OCF3C TOV3 OCF3B OCF3A ICF3 - FOC1C - - FOC1B ETIFR - FOC1A (0x7C) ETIMSK TOIE1 Idem TOIE3 Idem TOV1 (0x9B) TOV3 T/C3 Output Compare B Register High Byte OCF3A OCF1A OCIE3A OCIE1A OCR3BH OCF3C OCF1C OCIE3C OCIE1C (0x85) OCIE1C Idem OCIE3C Idem TOIE3 (0x98) OCIE3B T/C3 Output Compare A Register Low Byte OCIE3A OCR3AL ICIE3 (0x86) Bit 2 Idem ICIE1 Idem OCR3AH ICIE3 (0x99) (0x87) ICF1 Name ICF3 Add. OCF3B OCF1B OCIE3B OCIE1B Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Register Content T/C3 Output Compare A Register High Byte (0x7D) 12 Name Bit 6 Add. Bit 7 Register Content SRW0 [1,0] AVR096 4313B–AVR–03/04 AVR096 Table 13. I/O Registers (Continued) ATmega128 AT90CAN128 ISC0 [1,0] (0x69) Idem Idem 0x37-(0x57) Idem Idem PORTG[4..0] 0x14-(0x34) Idem Idem - DDG[4..0] 0x13-(0x33) Idem Idem - PING[4..0] 0x12-(0x32) Idem Idem PORTF (0x61) DDRF PORTF[7..0] 0x11-(0x31) Idem Idem DDF[7..0] 0x10-(0x30) Idem Idem Idem Idem Idem SPH Stack Pointer Register High Byte Idem Idem Idem 0x3D-(0x5D) SPL Stack Pointer Register Low Byte Idem Idem Idem 0x3C-(0x5C) XDIV (see page 3) XDIVEN (0x61) CLKPR 0x3B-(0x5B) RAMPZ - 0x3B-(0x5B) Idem Idem 0x3A-(0x5A) EICRB (0x6A) Idem Idem 0x39-(0x59) EIMSK INT[7..0] 0x1D-(0x3D) Idem Idem 0x38-(0x58) EIFR INTF[7..0] 0x1C-(0x3C) Idem Idem (0x6E) TIMSK0 - - - - - - (0x6F) TIMSK1 - - ICIE1 - OCIE1C OCIE1B (0x70) TIMSK2 - - - - - - 0x15-(0x35) TIFR0 - - - - - - 0x16-(0x36) TIFR1 - - ICF1 - OCF1C OCF1B 0x17-(0x37) TIFR2 - - - - - - N Z C RAMPZ0 TOV0 TOIE0 ISC4 [1,0] OCIE0 TOIE1 TOV1 - OCF0 - ISC5 [1,0] OCIE1B OCIE1A OCF1A - OCF1B - ISC6 [1,0] ICIE1 TOIE2 OCIE2 - ICF1 TIFR (see page 9) (see page 9) - TOV2 0x36-(0x56) V XDIV[6..0] ISC7 [1,0] OCF2 0x37-(0x57) S CLKPCE SREG TIMSK (see page 9) (see page 9) H SWWSRE 0x3F-(0x5F) 0x3E-(0x5E) - - - CLKPS[3..0] TOIE0 (0x62) TOIE1 - TOIE2 - - TOV0 - PING TOV1 DDRG (0x63) TOV2 (0x64) ISC1 [1,0] OCF2A OCF1A OCF0A OCIE2A OCIE1A OCIE0A - ISC2 [1,0] Bit 0 Idem Bit 1 Idem Bit 2 - Bit 3 - Bit 4 PORTG Bit 5 (0x65) Bit 6 (0x75) SPMEM - T XMM[2..0] PGERS SPMCSR I Name PGWRT (0x68) Bit 7 Bit 3 EICRA ISC3 [1,0] Add. BLBSET (0x6A) Bit 0 Bit 4 - XMCRB Register Content Bit 1 Bit 5 - (0x6C) Bit 2 Bit 6 - Name RWWSB - Add. SPMIE XMBK Bit 7 Register Content 13 4313B–AVR–03/04 Table 13. I/O Registers (Continued) ATmega128 AT90CAN128 MCUCR - - 0x34-(0x54) MCUSR - - - (0xB0) TCCR2A PUD PUD - - WGM21 WDRF BORF T/C0 Counter Register (0xB2) TCNT2 T/C2 Counter Register 0x31-(0x51) OCR0 (see page 9) T/C0 Output Compare Register (0xB3) OCR2A T/C2 Output Compare A Register 0x30-(0x50) ASSR (see page 9) (0xB6) Idem 0x2F-(0x4F) TCCR1A COM1A [1,0] WGM1 [1,0] (0x80) Idem Idem 0x2E-(0x4E) TCCR1B (0x81) Idem Idem 0x2D-(0x4D) TCNT1H T/C1 Counter Register High Byte (0x85) Idem Idem 0x2C-(0x4C) TCNT1L T/C1 Counter Register Low Byte (0x84) Idem Idem 0x2B-(0x4B) OCR1AH T/C1 Output Compare A Register High Byte (0x89) Idem Idem 0x2A-(0x4A) OCR1AL T/C1 Output Compare A Register Low Byte (0x88) Idem Idem 0x29-(0x49) OCR1BH T/C1 Output Compare B Register High Byte (0x8B) Idem Idem 0x28-(0x48) OCR1BL T/C1 Output Compare B Register Low Byte (0x8A) Idem Idem 0x27-(0x47) ICR1H T/C1 Input Capture Register High Byte (0x87) Idem Idem 0x26-(0x46) ICR1L T/C1 Input Capture Register Low Byte (0x86) Idem Idem 0x25-(0x45) TCCR2 (see page 9) 0x24-(0x44) TCCR0A 0x24-(0x44) TCNT2 (see page 9) T/C2 Counter Register 0x26-(0x46) TCNT0 T/C0 Counter Register 0x23-(0x43) OCR2 (see page 9) T/C2 Output Compare Register 0x27-(0x47) OCR0A T/C0 Output Compare A Register 14 COM2 [1,0] CS1[2..0] CS2[2..0] COM0A [1,0] OCR2UB CS2[2..0] TCN2UB - WGM01 WGM1 [3,2] - WGM00 - COM1C [1,0] - FOC0A COM1B [1,0] OCR0UB - TCN0UB - WGM21 ICES1 WGM20 FOC2 - COM2A [1,0] AS2 TCNT0 (see page 9) CS0[2..0] EXCLK 0x32-(0x52) AS0 TCCR0 (see page 9) TCR0UB - Bit 0 0x35-(0x55) - iVCE SE - iVCE - PORF MCUCR SM[2..0] TCR2UB 0x35-(0x55) Bit 1 - SRW0 [1,0] EXTRF IVSEL IVSEL - SRW10 Bit 2 - SRL[2..0] SRW11 Bit 3 Bit 4 - JTRF Bit 5 SMCR WGM20 Bit 6 SRE 0x33-(0x53) JTD Bit 7 XMCRA JTD Bit 0 IVCE (0x74) FOC2A EXTRF Name PORF Bit 1 IVSEL Bit 2 SM2 BORF Bit 3 SM0 WDRF Bit 4 SM1 Add. 0x33-(0x53) - COM0 [1,0] WGM01 - JTRF Bit 5 SE Bit 6 SRW10 - WGM00 MCUCSR Register Content ICNC1 0x34-(0x54) MCUCR SRE 0x35-(0x55) JTD Name FOC0 Add. Bit 7 Register Content CS0[2..0] AVR096 4313B–AVR–03/04 AVR096 Table 13. I/O Registers (Continued) ATmega128 AT90CAN128 0x31-(0x51) Idem Idem (0x60) Idem Idem 0x23-(0x43) GTCCR (0x7B) ADCSRB 0x35-(0x55) MCUCR 0x22-(0x42) Idem Idem Bit 0 Name Bit 1 Add. Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Register Content Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Name Bit 6 Add. Bit 7 Register Content EEPROM Address Register High ADHSM ACME - - - ADTS[2..0] - - PUD - - 0x21-(0x41) Idem Idem 0x1D-(0x3D) EEDR EEPROM I/O Data Register 0x20-(0x40) Idem Idem 0x1C-(0x3C) EECR 0x1F-(0x3F) Idem Idem 0x1B-(0x3B) PORTA PORTA[7..0] 0x02-(0x22) Idem Idem 0x1A-(0x3A) DDRA DDA[7..0] 0x01-(0x21) Idem Idem 0x19-(0x39) PINA PINA[7..0] 0x00-(0x20) Idem Idem 0x18-(0x38) PORTB PORTB[7..0] 0x05-(0x25) Idem Idem 0x17-(0x37) DDRB DDB[7..0] 0x04-(0x24) Idem Idem - - EERE EEPROM Address Register Low Byte EEWE EEARL EEMWE 0x1E-(0x3E) - Idem 0x14-(0x34) DDRC DDC[7..0] 0x07-(0x27) Idem Idem 0x13-(0x33) PINC PINC[7..0] 0x06-(0x26) Idem Idem 0x12-(0x32) PORTD PORTD[7..0] 0x0B-(0x2B) Idem Idem 0x11-(0x31) DDRD DDD[7..0] 0x0A-(0x2A) Idem Idem SPSR 0x2D-(0x4D) Idem Idem 0x0D-(0x2D) SPCR 0x2C-(0x4C) Idem Idem 0x0C-(0x2C) UDR0 (0xC6) Idem Idem 0x0B-(0x2B) UCSR0A Idem Idem 0x0A-(0x2A) UCSR0B Idem Idem - - - - SPR0 SPI2X 0x0E-(0x2E) SPR1 Idem CPHA Idem Idem CPOL Idem MSTR 0x09-(0x29) 0x2E-(0x4E) DORD PIND[7..0] SPI I/O Data Register WCOL PIND SPDR SPE 0x10-(0x30) 0x0F-(0x2F) TXC0 Idem Idem TXCIE0 Idem 0x08-(0x28) SPIF 0x03-(0x23) PORTC[7..0] SPIE PINB[7..0] PORTC RXC0 PINB 0x15-(0x35) RXCIE0 0x16-(0x36) - FE0 DOR0 UPE0 U2X0 MPCM0 (0xC0) RXEN0 TCEN0 UCSZ02 RXB80 TXB80 UDRIE0 UDRE0 USART0 I/O Data Register (0xC1) PSR310 - iVCE - EEARH - PSR2 - IVSEL TSM - 0x1F-(0x3F) EERIE - - JTD - PSR321 - WDP[2..0] PSR0 (see page 9) (see page 10) - PUD SFIOR 0x20-(0x40) - WDE - ACME WDTCR WDCE 0x21-(0x41) OCDR[6..0] ADHSM OCDR TMS 0x22-(0x42) IDRD OCDR[7..0] 15 4313B–AVR–03/04 Table 13. I/O Registers (Continued) ATmega128 AT90CAN128 0x05-(0x25) ADCH ADC Data Register High Byte 0x04-(0x24) ADCL 0x03-(0x23) PORTE 0x02-(0x22) 0x01-(0x21) 0x00-(0x20) (0x79) Idem Idem ADC Data Register Low Byte (0x78) Idem Idem PORTE[7..0] 0x0E-(0x2E) Idem Idem DDRE DDE[7..0] 0x0D-(0x2D) Idem Idem PINE PINE[7..0] 0x0C-(0x2C) Idem Idem PINF PINF[7..0] 0x0F-(0x2F) Idem Idem ACIE ADIE ADIF ADRF ADSC ACD ADEN Idem Idem Idem (0x7A) ADPS[2..0] ADATE Idem MUX[4..0] Idem Idem ACIS [1,0] Idem (0x7C) REFS [1,0] ACIC Idem ACI Idem ACO 0x30-(0x50) ADLAR Idem ACBG Idem Bit 0 ADCSRA (see page 10) Name Bit 1 0x06-(0x26) Add. (0xC4) Bit 2 ADMUX Bit 3 0x07-(0x27) Bit 4 ACSR Bit 5 0x08-(0x28) Bit 6 USART0 Baud Rate Register Low Byte Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Name UBRR0L 16 Bit 5 Add. 0x09-(0x29) Note: Bit 6 Register Content Bit 7 Register Content Idem Some AT90CAN128 I/O registers are not listed in the hereinabove table because there is no corresponding registers/peripherals in ATmega128 (i.e. CAN registers). AVR096 4313B–AVR–03/04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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