ANM081 Migration from TSC80C32/TSC80C52 to TS80C32X2/ TS80C52X2 1. Description Due to market request, to improve specification and to optimize and rationalize the offer of its microcontroller family, Atmel Wireless & Microcontrollers has redesigned the core of its TSC80C32/TSC80C52 microcontroller. This application note compares the SFRs, DC characteristics, AC characteristics between TSC80C32,TSC80C52 and the new TS80C32X2, TS80C52X2. It should be noted also that the new TS80C32X2,TS80C52X2 core includes the programmable clock doubler feature which is described in a specific application note: ANM072. 2. Features Improvement TSC80C32/C52 TS80C32X2/C52X2 256b RAM Yes Yes 32 I/Os Yes Yes 3 16 bit-Timers Yes Yes Timer 2 : Clock Output Mode No Yes Timer 2 : Auto reload Up/Down Mode No Yes 6 Interrupt Sources Yes Yes 4 priority level interrupt system No Yes Wake up from Power Down by Reset Yes Yes Wake up from Power Down by INT0 & INT1 No Yes UART Yes Yes Enhanced UART Framing error dectection Multi processor communication X2 Mode Dual Data Pointer Power Off Flag Commercial Temperature Industrial Temperature Asynchronous port reset No No No No No No Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes 40 Mhz X1 Mode 60 Mhz eq. X2 Mode 30 MHz X1 Mode 40 MHz eq. X2 Mode Maximum Frequency @ 5V 44 MHz Maximum Frequency @ 3V 16 Mhz X1 mode is standard mode (12 clocks per instruction) X2 mode is new mode (6 clocks per instruction) Rev. A - May 2, 2000 1 ANM081 3. SFR Mapping Hereafter a SFR mapping comparison table between TSC80C32/C52 and TS80C32 X2/C52X2 TSC80C32/C52 Old Core TS80C32X2/C52X2 New Core PCON Register (Sfr:87h) PCON Register (Sfr:87h) 7 6 5 4 3 2 1 0 SMOD - - - GF1 GF0 PD IDL 7 6 SMOD SMOD 1 0 5 4 3 2 1 0 - POF GF1 GF0 PD IDL Reset Value : 000x 0000b Reset Value : 00x1 0000b Comments : Power On flag , EUART TSC80C32/C52 Old Core TS80C32X2/C52X2 New Core Reserved Register (Sfr:8Fh) CKCON Register (Sfr:8Fh) 7 6 5 4 3 2 1 0 - - - - - - - X2 Reset Value : xxxx xxx0b Comments : X2 mode TSC80C32/C52 Old Core TS80C32X2/C52X2 New Core SCON Register (Sfr:98h) SCON Register (Sfr:98h) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 SM0 SM1 SM2 REN TB8 RB8 TI RI FE/ SM0 SM1 SM2 REN TB8 RB8 TI RI Reset Value : 0000 0000b Reset Value : 0000 0000b Comments : EUART : FE/SM0 Framing Error TSC80C32/C52 Old Core TS80C32X2/C52X2 New Core Reserved (Sfr:0A2h) AUXR1 Register (Sfr:0A2h) 7 6 5 4 3 2 1 0 - - - - GF3 0 - DPS Reset Value : xxxx 00x0b Comments : Dual DPTR 2 Rev. A - May 2, 2000 ANM081 TSC80C32/52 Old Core TS80C32X2/C52X2 New Core Reserved (Sfr:0A9h) SADDR Register (Sfr:0A9h) 7 6 5 4 3 2 1 0 Reset Value : 0000 0000b Comments : EUART : Multiprocessor communication TSC80C32/C52 Old Core TS80C32X2/C52X2 New Core Reserved (Sfr:0B7h) IPH Register (Sfr:0B7h) 7 6 5 4 3 2 1 0 - - - PSH PT1H PX1H PT0H PX0H 1 0 Reset Value : xxx0 0000b Comments : 4 level priority interrupt TSC80C32/C52 Old Core TS80C32X2/C52X2 New Core Reserved (Sfr:0B9h) SADEN Register (Sfr:0B9h) 7 6 5 4 3 2 Reset Value : 0000 0000b Comments : EUART : Multi processor communication All other registers are identical 4. DC Parameters TSC80C32/TSC80C52 : Vcc = 5V +/-10% ; T = -40 to +85˚C ; T=0 to 70˚C TS80C32X2/TS80C52X2 : Vcc = 5V +/-10% ; T = -40 to +85˚C ; T=0 to 70˚C Symbol Parameters TSC80C32 TSC80C52 Min VIH IPD Input High Voltage except XTAL1,RST Power Down Current Rev. A - May 2, 2000 Max 0.2Vcc+1.4 TS80C32X2 TS80C52X2 Min Comments Max 0.2Vcc+0.9 75 Unit V 50 µΑ Vcc = 2.0V to 5.5V 3 ANM081 5. AC Parameters 5.1. TS80C32X2/TS80C52X2 (M Version) 5.1.1. External Program Memory Characteristics TSC80C32 TSC80C52 Symbol t t t t t t t t t LHLL AVLL LLAX LLIV LLPL PLPH PLIV PXIX PXIZ t AVIV t PLAZ Parameter Cond. TS80C32X2-Mxx TS80C52X2-Mxx 16 20 25 16 20 25 Unit MHz MHz MHz MHz MHz MHz ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in input instruction hold after PSEN Min Min Min Max Min Min Max Min 110 40 35 185 45 165 125 0 90 30 35 170 40 130 110 0 70 20 35 130 30 100 85 0 115 47.5 47.5 220 52.5 167.5 147.5 0 90 35 35 170 40 130 110 0 70 25 25 130 30 100 80 0 ns ns ns ns ns ns ns ns Input instruction float after PSEN Address to valid instruction in PSEN low to address float Max Max Max 50 230 10 45 210 10 35 170 8 55.5 272.5 10 43 210 10 33 160 10 ns ns ns 5.1.2. External Data Memory Characteristics TSC80C32 TSC80C52 Symbol t t t t t t t t t t t t t t t t 4 RLRH WLWH RLDV RHDX RHDZ LLDV AVDV LLWL LLWL AVWL QVWX WHQX QVWH TRLAZ WHLH WHLH Parameter RD pulse width WR pulse width RD Low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to to WR High RD low to address float RD or WR high to ALE high RD or WR high to ALE high Cond. Min Min Max Min Max Max Max Min Max Min Min Min Min Min Min Max TS80C32X2-Mxx TS80C52X2-Mxx 16 20 25 16 20 25 MHz MHz MHz MHz MHz MHz 340 340 240 0 90 435 480 150 250 180 35 40 380 0 35 90 270 270 210 0 90 370 400 135 170 180 35 35 325 0 35 60 210 210 175 0 80 290 320 120 130 140 30 30 250 0 25 45 355 355 287.5 0 105 460 502.5 162.5 212.5 225 47.5 52.5 422.5 0 47.5 77.5 280 280 225 0 80 360 390 125 175 175 35 40 335 0 35 65 220 220 175 0 60 280 300 95 145 135 25 30 265 0 25 55 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Rev. A - May 2, 2000 ANM081 5.1.3. Serial Port Timing - Shift register TSC80C32 TSC80C52 Symbol t t t t t XLXL QVXH XHQX XHDX XHDV Parameter Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock edge Input data hold after clock rinsing edge Clock rising edge to input data valid Cond. Min Min Min Min Max TS80C32X2-Mxx TS80C52X2-Mxx 16 20 25 16 20 25 MHz MHz MHz MHz MHz MHz 750 563 63 0 563 600 480 90 0 450 480 380 65 0 350 750 575 105 0 492 600 450 80 0 367 480 350 60 0 267 Unit ns ns ns ns ns 5.2. TS80C32X2/TS80C52X2 (L Version) 5.2.1. External Program Memory Characteristics TSC80C32 TSC80C52 Symbol t t t t t t t t t t t LHLL AVLL LLAX LLIV LLPL PLPH PLIV PXIX PXIZ AVIV PLAZ Parameter ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float Rev. A - May 2, 2000 Cond. Min Min Min Max Min Min Max Min Max Max Max TS80C32X2-Mxx TS80C52X2-Mxx 16 20 25 16 20 25 MHz MHz MHz MHz MHz MHz 110 40 35 185 45 165 125 0 50 230 10 90 30 35 170 40 130 110 0 45 210 10 70 20 35 130 30 100 85 0 35 170 8 110 42.5 42.5 215 47.5 162.5 142.5 0 47.5 267.5 10 85 30 30 165 35 125 105 0 35 205 10 65 20 20 125 25 95 75 0 25 155 10 Unit ns ns ns ns ns ns ns ns ns ns ns 5 ANM081 5.2.2. External Data Memory Characteristics TSC80C32 TSC80C52 Symbol t t t t t t t t t t t t t t t t RLRH WLWH RLDV RHDX RHDZ LLDV AVDV LLWL LLWL AVWL QVWX WHQX QVWH TRLAZ WHLH WHLH Parameter RD pulse width WR pulse width RD Low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to to WR High RD low to address float RD or WR high to ALE high RD or WR high to ALE high Cond. Min Min Max Min Max Max Max Min Max Min Min Min Min Min Min Max TS80C32X2-Mxx TS80C52X2-Mxx 16 20 25 16 20 25 MHz MHz MHz MHz MHz MHz 340 340 240 0 90 435 480 150 250 180 35 40 380 0 35 90 270 270 210 0 90 370 400 135 170 180 35 35 325 0 35 60 210 210 175 0 80 290 320 120 130 140 30 30 250 0 25 45 350 350 282.5 0 100 455 497.5 157.5 217.5 220 167.5 42.5 417.5 0 42.5 82.5 275 275 220 0 75 355 385 120 180 170 130 30 330 0 30 70 215 215 170 0 55 275 295 90 150 130 100 20 260 0 20 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5.2.3. Serial Port Timing - Shift register TSC80C32 TSC80C52 Symbol t t t t t 6 XLXL QVXH XHQX XHDX XHDV Parameter Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock edge Input data hold after clock rinsing edge Clock rising edge to input data valid Cond. Min Min Min Min Max TS80C32X2-Lxx TS80C52X2-Lxx 16 20 25 16 20 25 MHz MHz MHz MHz MHz MHz 750 563 63 0 563 600 480 90 0 450 480 380 65 0 350 750 575 105 0 492 600 450 80 0 367 480 350 60 0 267 Unit ns ns ns ns ns Rev. A - May 2, 2000 ANM081 5.3. TS80C32X2/TS80C52X2 (V Version) 5.3.1. External Program Memory Characteristics TSC80C32 TSC80C52 Symbol t t t t t t t t t t t Parameter Cond. TS80C32X2-Vxx TS80C52X2-Vxx 25 30 40 25 30 40 MHz MHz MHz MHz MHz MHz Unit AVIV ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in Min Min Min Max Min Min Max Min Max Max 70 20 35 130 30 100 85 0 35 170 60 15 35 100 25 80 65 0 30 130 40 9 30 70 15 65 45 0 20 80 72 27 27 138 32 105 95 0 35 170 58.7 20.3 20.3 111.3 25.3 85.0 75.0 0.0 28.3 136.7 42.0 12.0 12.0 78.0 17.0 60.0 50.0 0.0 20.0 95.0 ns ns ns ns ns ns ns ns ns ns PLAZ PSEN low to address float Max 8 6 5 10 10.0 10.0 ns LHLL AVLL LLAX LLIV LLPL PLPH PLIV PXIX PXIZ 5.3.2. External Data Memory Characteristics TSC80C32 TSC80C52 Symbol t t t t t t t t t t t t t t t t RLRH WLWH RLDV RHDX RHDZ LLDV AVDV LLWL LLWL AVWL QVWX WHQX QVWH TRLAZ WHLH WHLH Parameter RD pulse width WR pulse width RD Low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to to WR High RD low to address float RD or WR high to ALE high RD or WR high to ALE high Rev. A - May 2, 2000 Cond. Min Min Max Min Max Max Max Min Max Min Min Min Min Min Min Max TS80C32X2-Vxx TS80C52X2-Vxx 25 30 40 25 30 40 MHz MHz MHz MHz MHz MHz 210 210 175 0 80 290 320 120 130 140 30 30 250 0 25 45 180 180 135 0 70 235 260 90 115 115 20 20 215 0 20 40 100 100 90 0 45 150 180 60 95 65 10 10 160 0 15 35 225.0 225.0 177.0 0.0 65.0 285.0 310.0 100.0 140.0 140.0 52.5 32.0 270.0 0.0 30.0 50.0 185.0 185.0 143.7 0.0 51.7 231.7 250.0 80.0 120.0 113.3 40 25.3 223.3 0.0 23.3 43.3 135.0 135.0 102.0 0.0 35.0 165.0 175.0 55.0 95.0 80.0 30 17.0 165.0 0.0 15.0 35.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 ANM081 5.3.3. Serial Port Timing - Shift register TSC80C32 TSC80C52 Symbol t t t t t 8 XLXL QVXH XHQX XHDX XHDV Parameter Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock edge Input data hold after clock rinsing edge Clock rising edge to input data valid Cond. Min Min Min Min Max TS80C32X2-Vxx TS80C52X2-Vxx 25 30 40 25 30 40 MHz MHz MHz MHz MHz MHz 480 380 65 0 350 400 300 50 0 300 250 170 35 0 200 480.0 350.0 60.0 0.0 267.0 400.0 283.3 46.7 0.0 200.3 300.0 200.0 30.0 0.0 117.0 Unit ns ns ns ns ns Rev. A - May 2, 2000 ANM081 6. Packages VQFP44 TQFP44 PQFP44 F1 PQFP44 F2 PQFP44 F2 PQFP44 F1 VFQP44 TQFP44 Min Max Min Max Min Max Min Max Rev. A - May 2, 2000 A C D D1 E E1 e f J L N1 N2 1.90 2.40 2.00 2.40 1.6 1.20 0.10 0.20 0.10 0.20 0.10 0.20 0.09 0.20 12.10 12.50 13.65 14.15 11.90 12.10 12.00 9.90 10.10 9.90 10.1 9.90 10.10 10.00 12.10 12.50 13.65 14.15 11.90 12.10 12.00 9.90 10.10 9.90 10.10 9.90 10.10 10.00 0.80 0.25 0.45 0.20 0.40 0.35 0.00 0.20 0.00 0.30 0.05 0.05 0.15 0.35 0.65 0.65 0.95 0.45 0.75 0.45 0.75 11 11 11 11 11 11 11 11 0.80 0.80 0.80 0.30 0.45 9 ANM081 7. Cross Reference if -xx stands for -12, -16, -20, -25, -30, -36, -40 then * = -M if -xx stands for -44, then * = -V, if -xx stands for -L16 or -L20, then * = -L Old ATMEL part New ATMEL part Old ATMEL part New ATMEL part P80C32-xx S80C32-xx F180C32-xx F280C32-xx V80C32-xx T80C32-xx D80C32-xx Q80C32-xx R80C32-xx IP80C32-xx IS80C32-xx IF180C32-xx IF280C32-xx IV80C32-xx IT80C32-xx ID80C32-xx IQ80C32-xx IR80C32-xx P80C32-L16 S80C32-L16 F180C32-L16 F280C32-L16 V80C32-L16 T80C32-L16 D80C32-L16 Q80C32-L16 R80C32-L16 IP80C32-L16 IS80C32-L16 IF180C32-L16 IF280C32-L16 IV80C32-L16 IT80C32-L16 ID80C32-L16 IQ80C32-L16 IR80C32-L16 AX80C32-xx MX80C32-xx TS80C32X2-*CA TS80C32X2-*CB TS80C32X2-*CC TS80C32X2-*CE TS80C32X2-*CE TS80C32X2-*CE No equivalent No equivalent No equivalent TS80C32X2-*IA TS80C32X2-*IB TS80C32X2-*IC TS80C32X2-*IE TS80C32X2-*IE TS80C32X2-*IE No equivalent No equivalent No equivalent TS80C32X2-LCA TS80C32X2-LCB TS80C32X2-LCC TS80C32X2-LCE TS80C32X2-LCE TS80C32X2-LCE No equivalent No equivalent No equivalent TS80C32X2-LIA TS80C32X2-LIB TS80C32X2-LIC TS80C32X2-LIE TS80C32X2-LIE TS80C32X2-LIE No equivalent No equivalent No equivalent No equivalent No equivalent P80C52-XX S80C52-XX F180C52-XX F280C52-XX V80C52-XX T80C52-XX D80C52-XX Q80C52-XX R80C52-XX IP80C52-XX IS80C52-XX IF180C52-XX IF280C52-XX IV80C52-XX IT80C52-XX ID80C52-XX IQ80C52-XX IR80C52-XX P80C52-L16 S80C52-L16 F180C52-L16 F280C52-L16 V80C52-L16 T80C52-L16 D80C52-L16 Q80C52-L16 R80C52-L16 IP80C52-L16 IS80C52-L16 IF180C52-L16 IF280C52-L16 IV80C52-L16 IT80C52-L16 ID80C52-L16 IQ80C52-L16 IR80C52-L16 AX80C52-XX MX80C52-XX TS80C52X2-*CA TS80C52X2-*CB TS80C52X2-*CC TS80C52X2-*CE TS80C52X2-*CE TS80C52X2-*CE TS80C52X2-*CJ TS80C52X2-*CK No equivalent TS80C52X2-*IA TS80C52X2-*IB TS80C52X2-*IC TS80C52X2-*IE TS80C52X2-*IE TS80C52X2-*IE TS80C52X2-*IJ TS80C52X2-*IK No equivalent TS80C52X2-LCA TS80C52X2-LCB TS80C52X2-LCC TS80C52X2-LCE TS80C52X2-LCE TS80C52X2-LCE TS80C52X2-LCJ TS80C52X2-LCK No equivalent TS80C52X2-LIA TS80C52X2-LIB TS80C52X2-LIC TS80C52X2-LIE TS80C52X2-LIE TS80C52X2-LIE TS80C52X2-LIJ TS80C52X2-LIK No equivalent No equivalent No equivalent 10 Rev. A - May 2, 2000 ANM081 8. Bibliography TSC80C32/TSC80C52 datasheet Rev.H (13 Feb. 97) TS80C32X2/TS80C52X2/TS87C52X2 datasheet Rev. B (Aug. 31,1999) Rev. A - May 2, 2000 11