ACS1823 Datasheet

ACS1823
Ultra Low Jitter Dual PLL Frequency Synthesizer
WIRELESS, SENSING & TIMING PRODUCT GROUP
Features
The ACS1823 is ideal for high performance frequency
synthesis and frequency disciplining via external
analog or digital control loops with applications in
telecommunications, cellular basestations, broadcast
video and test and measurement Applications.







CLKOUT1P
In “Software Controlled Synthesizer” mode, the local
CPU can continuously update the fractional feedback
divider to tune the output frequencies. Typically this
mode is used with an external phase detector and
control loop to generate output clocks traceable to a
reference source.

CLKOUT3P
In the “Fixed Synthesizer” mode, no further CPU
intervention is needed and the outputs directly track
changes in the reference frequency. This mode can
be used for either non-traceable clock generation or
in conjunction with an externally controlled oscillator
(such as VCXO) to generate a traceable clock.

VSS
CLKOUT1N
The ACS1823 can be used in two modes. In both
modes the initial configuration is set up either
through the factory-programmed default configuration
option, or by a local CPU over the device’s I2C or SPI
interface.

Configurable dual frequency synthesizer with
four ultra-low phase noise outputs
Less than 250 fs typical rms jitter (12 KHz –
20 MHz integration band, fCLKOUT = 125MHz,
30.72 MHz fundamental mode XTAL)
Four outputs configurable as LVDS, LVPECL,
CML or LVCMOS
Output frequency Ranges:
o 2 KHz – 933.33 MHz
o 1075MHz – 1400 MHz
Typical 1ppt (parts per trillion) ultra-fine
output frequency resolution
Reference clock
o Fundamental Mode Crystal: 10 MHz –
60 MHz
o 3rd OT Crystal: 60 MHz – 114.285
MHz
o Crystal interface may be over-driven
by an oscillator, VCXO, TCXO or OCXO
2
I C or SPI CPU interface
Serial Interface access to PLL dividers
disciplining the output frequency
Factory-programmed default configuration
option (contact Semtech for details)
o Four pin-selectable configurations
VDD = 3.3V
7 × 7mm 48-lead QFN Pb-free, ROHS
compliant package
CLKOUT4N
VDD
CLKOUT3N
The ACS1823 generates up to four individually
programmable output frequencies from 2 kHz – 1400
MHz. The frequencies are generated from either a
fundamental mode or 3rd overtone crystal. The
ACS1823 can also be driven by a crystal oscillator,
VCXO, TCXO, or OCXO.

CLKOUT2N
VSS
CLKOUT4P
The ACS1823 is a highly flexible, dual-PLL frequency
synthesizer with four programmable outputs capable
of generating ultra-low phase noise clocks.
VDD
CLKOUT2P
Description
DATASHEET
48 47 46 45 44 43 42 41 40 39 38 37
I2C_SPI 1
RESETB 2
Applications
VDD
VSS
VSS
VDD
XTALA
 Macro Base Station Baseband Card
 Wireless Small Cell
36 VDD
35 SDI
3
34 ADD2_SS
4
33 ADD1
5
32 ADD0
6
31 VSS
ACS1823
7
30 SDA_SDO
29 SCL_SCLK
XTALB 8
 Data Converters, Test and Measurement and
Broadcast Video
28 VSS
VSS 9
VDD 10
27 CNFG1
VDD 11
VDD 12
26 CNFG0
25 VSS
NC
NC
NC
NC
VDD
RATE1
NC
RATE0
NC
NC
NC
VDD
13 14 15 16 17 18 19 20 21 22 23 24
Figure 1 : 48-QFN, 7mm x 7mm
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Ordering Information
Part Number
Configuration
ACS1823I004MLT
Dual Synthesizer with factory-preprogrammed
configuration
Package
48-Lead
QFN
Dual Synthesizer with factory-preprogrammed
configuration
ACS1823I004MLTR
Packing
Tray
(260
devices)
Tape / Reel
(3000
devices)
Feature Description
The ACS1823 low-jitter dual frequency synthesizer can generate up to four individually programmable clock outputs
from a crystal oscillator interface using either a fundamental or 3rd Overtone crystal. The oscillator port also provides
an option to use temperature compensated OCXO/TCXO reference clocks for applications requiring long term
frequency stability.
The dual PLLs offer great flexibility and eliminate the need for two PLL chips to support two different standards. For
example, one PLL could be used for Ethernet Clocks (25 MHz, 125 MHz, 156.25 MHz) and the other PLL could be
used to generate a W-CDMA reference frequency such as 30.72 MHz.
Besides supporting free running or fixed frequency synthesis in asynchronous systems such as Ethernet, the
ACS1823 can also serve as a low phase noise, software controlled frequency synthesizer or Numerically Controlled
Oscillator (NCO) forming part of a larger system loop. In this case, the I2C/SPI serial interface allows microprocessor
control of the APLL 34-bit fractional feedback divider in very small steps to steer the output frequency.
Alternatively, if an analog control loop is desired, the ACS1823 may be driven by an upstream VCXO that is steered
by a control voltage. The ACS1823 will track the VCXO frequency while generating low phase noise output clocks.
An integrated high PSRR voltage regulator simplifies power integrity and requires VDD = 3.3V.
Functional Block Diagram
OUT1H
RATE0
VCO
XTAL
XO
Doubler
RATE1
APFD
2.15 – 2.8
GHz
ODIV
/1, /5,
/25
OUT1L
2n
{0 ≤n≥ 19}
Fout = 2kHz – 933.33MHz
1075MHz -1400 MHz
/2, /3,
/4, /5
OUT2H
FXTAL = 10MHz – 120MHz
/1, /5,
/25
AFB
CLKOUT1
OUT2L
2n
{0 ≤n≥ 19}
CLKOUT2
/19, /20 .. /255 + A/233
A = 0, 1, 2 .. (233-1)
ADD0
APLL A
ADD1
ADD2_CSB
SDI
APLL B
SPI
OUT3H
/1, /5,
/25
OUT3L
2n
{0 ≤n≥ 19}
Fout = 2kHz – 933.33MHz
1075MHz -1400 MHz
SCL_SCLK
SDI
SDA_SDO
CLKOUT3
I2C
OUT4H
/1, /5,
/25
OUT4L
2n
{0 ≤n≥ 19}
CLKOUT4
Figure 2: ACS1823 Functional Block Diagram
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
ACS1823
Pin Description
Name
I/O
Signal
1
I2C_SPI
IPD
LVCMOS
2
RESETB
I
LVCMOS
3
4
5
6
VDD
VSS
VSS
VDD
7
XTALA
I
Analog
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
XTALB
VSS
VDD
VDD
VDD
VDD
NC
NC
RATE0
NC
NC
RATE1
NC
NC
VDD
NC
NC
VSS
CNFG0
I
Analog
Ground
Supply
Supply
Supply
Supply
I
3-Level
I
3-Level
27
CNFG1
28
VSS
29
SCL_SCLK
I
LVCMOS
30
SDA_SDO
I/O
LVCMOS
31
VSS
32
ADD0
IPU
LVCMOS
33
ADD1
IPU
LVCMOS
34
ADD2_SS
IPU
LVCMOS
35
SDI
IPD
LVCMOS
Supply
Ground
Ground
Supply
Supply
Ground
IPD
LVCMOS
Ground
Ground
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Description
Serial interface mode select
Set serial interface to I2C mode (I2C_SPI=Low) or SPI slave mode
(I2C_SPI=High). Internally pulled down.
Reset
Hardware Reset, High to Low transition restores all internal logic to the power
on state.
3.3V Supply
Supply Ground
Supply Ground
3.3V supply
External crystal/system reference clock
Connect external crystal between Pins 6 and 7; can also be AC coupled to a
differential or single ended reference clock source.
Supply ground
3.3V supply
3.3V supply
3.3V supply
3.3V supply
Not Connected
Not Connected
Oscillator mode selector 0, internally pulled to center
Not Connected
Not Connected
Oscillator mode selector 1, internally pulled to center
Not Connected
Not Connected
3.3V supply
Not Connected
Not Connected
Supply Ground
Dual function pins: For factory-programmed parts selects one of four preprogrammed configurations. Used in conjunction with RATE0 and RATE1.
Internally pulled down.
Supply Ground
Serial CLOCK (I2C /SPI).
Serial clock for I2C or SPI interface
Serial Data (I2C)/Serial Data Out (SPI)
Bidirectional serial data in I2C mode, or serial data output in SPI mode. In I2C
mode SDA_SDO requires an external pull up resistor.
Supply ground
Address bit 0 (I2C)
Bit 0 of I2C interface address in I2C mode. Internally pulled up.
Address bit 1 (I2C)
Bit 1 of I2C interface address in I2C mode. Internally pulled up.
Address bit 2 (I2C), Slave Select (SPI)
Bit 2 of I2C interface address in I2C mode, or Slave Select input in SPI mode.
Internally pulled up.
Serial Data In (SPI)
Serial data input in SPI mode (must connect SDI to GND for normal slave
mode operation in I2C). Internally pulled down.
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ACS1823
ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
Name
36
VDD
37
CLKOUT1P
O
Differential
38
CLKOUT1N
O
Differential
39
VSS
40
CLKOUT3P
O
Differential
41
CLKOUT3N
O
Differential
42
VDD
43
CLKOUT4N
O
Differential
44
CLKOUT4P
O
Differential
45
VSS
46
CLKOUT2N
O
Differential
47
CLKOUT2P
O
Differential
48
VDD
Supply
--
EP
Ground
I/O
DATASHEET
Signal
Description
Supply
3.3V supply
Clock 1 output
Positive LVPECL/CML/LVDS/CMOS compatible Clock Output
Clock 1 output
Negative LVPECL/CML/LVDS/CMOS Clock Output
Supply ground
Clock 3 output
Positive LVPECL/CML/LVDS/CMOS compatible Clock Output
Clock 3 output
Negative LVPECL/CML/LVDS/CMOS Clock Output
3.3V supply
Clock 4 output
Negative LVPECL/CML/LVDS/CMOS compatible Clock Output
Clock 4 output
Positive LVPECL/CML/LVDS/CMOS compatible Clock Output
Supply ground
Clock 2 output
Negative LVPECL/CML/LVDS/CMOS compatible Clock Output
Clock 2 output
Positive LVPECL/CML/LVDS/CMOS compatible Clock Output
3.3V supply
Exposed pad.
Must be soldered to the circuit board ground for proper thermal and electrical
performance.
Ground
Supply
Ground
Table 1 : ACS1823 Pin Listing
Note: All VDD pins must be connected to the same voltage.
Theory of Operation
Analog Phase Locked Loop operation (APLL)
The ACS1823 contains a pair of independent APLL slices, with each slice consisting of a Voltage Controlled
Oscillator (VCO), fractional Feedback Divider (AFB), a Phase and Frequency Detector (APFD) and a high-speed Output
Divider (ODIV).
The VCO has an operational range of 2.15 GHz – 2.80 GHz and is locked to the specified multiple of the device’s
reference clock by the AFB and APFD. When locked, the high-speed ODIV divider is used to pre-scale the VCO output
prior to driving the lower speed output clock dividers (OUTnH and OUTnL).
When using the device as a “software controlled synthesizer” or NCO, frequency adjustment is achieved by using
either I2C or SPI commands to modify the integer and fractional portions of the fractional feedback divider.
For ease of configuration, the “CleanClock” software tool is may be used to calculate coefficient register values
based on reference frequency, output frequency and target VCO rate. The tool automatically configures all divider
ratios and assigns the relevant frequency plan. When using the associated evaluation board, this graphical user
interface allows users to continually monitor device status on a USB connected windows based PC.
The theory of operation descriptions below are intended to illustrate device functionality as device settings do not
need to be manually calculated.
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DATASHEET
XO Crystal Oscillator / Reference Oscillator
The on-chip reference oscillator used by the VCOs can be configured for use with a fundamental / third order mode
crystal or driven by an AC coupled external low noise sinusoidal clock input (XO, VCXO, TCXO, or OCXO).
RATE1
RATE0
Correct configuration of the XTALA/XTALB oscillator port is dependent on both input frequency and driver type. The
oscillator mode is defined by the RATE[1:0] pins as described in Table 2.
L
L
L
M
M
M
H
H
H
L
M
H
L
M
H
L
M
H
XTALA/XTALB Oscillator mode
Oscillator frequency
(range)
MHz
Fundamental crystal
External Oscillator
20 – 60
Reserved Do Not Use
3rd overtone crystal
60 – 114.285
External Oscillator
External Oscillator
10 - 20
Fundamental crystal
Reserved Do Not Use
Table 2: ACS1823 Reference Clock Configuration
Two basic modes of operation are supported by the PLL:
1) Software Controlled Synthesizer mode:
For optimal performance when the I2C/SPI port is used to remotely adjust the AFB divider ratio, the
reference XTALA/XTALB frequency should ideally be chosen to create a fractional ratio with the target output
frequency on CLKOUT.
2) Fixed Frequency Synthesizer mode:
When used to simply multiply the reference oscillator by a static ratio, best jitter performance is achieved
when the APLL is operated in integer only mode which requires the VCO frequency to be an exact integer
multiple of the reference oscillator connected to XTALA/XTALB. If this is not possible, it is recommended to
select a crystal oscillator that is not near a multiple or sub-multiple of the output frequency on CLKOUT.
XO Doubler Circuit
For optimal performance, it is recommended to operate the APFD above 60MHz. This may be achieved either by
using a reference oscillator above 60MHz, or (for lower rate frequencies) enabling the on chip XO Doubler Circuit
which multiplies the XTALA/XTALB rate by a factor of two.
For XTALA/XTALB rates below 30MHz output jitter will increase due to the APFD frequency dropping below 60MHz.
If the input reference frequency is above 60 MHz, the XO Doubler feature should not be used.
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WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Interfacing an external reference source on XTALA and XTALB
A high quality sinusoidal external reference clock can be used in place of the crystal at XTAL/XTALB. The figure below
provides examples of single ended and differential interfaces to the XTALA/XTALB inputs. Note that the output jitter
performance depends on the quality and frequency of the VCO reference clock. Jitter generation specifications in
the AC-Characteristics Table are given for a crystal chosen with attention to spur frequencies. Use of an external
clock instead of a crystal may impact the total output jitter.
Figure 3 : ACS1823 Reference Clock Input Interfaces
Divider Configuration
Frequency synthesis in the APLL Slice is configured by setting appropriate division rates in the various frequency
dividers that operate in the feedback and output signal paths. It may be helpful to refer to the block diagram when
reading through the detailed description which follows.
OUT1H
RATE0
VCO
XTAL
XO
Doubler
RATE1
APFD
2.15 – 2.8
GHz
ODIV
/1, /5,
/25
OUT1L
2n
{0 ≤n≥ 19}
Fout = 2kHz – 933.33MHz
1075MHz -1400 MHz
/2, /3,
/4, /5
OUT2H
FXTAL = 10MHz – 120MHz
/1, /5,
/25
AFB
CLKOUT1
OUT2L
2n
{0 ≤n≥ 19}
CLKOUT2
/19, /20 .. /255 + A/233
A = 0, 1, 2 .. (233-1)
ADD0
APLL A
ADD1
ADD2_CSB
SDI
APLL B
SPI
OUT3H
/1, /5,
/25
OUT3L
2n
{0 ≤n≥ 19}
Fout = 2kHz – 933.33MHz
1075MHz -1400 MHz
SCL_SCLK
SDI
SDA_SDO
CLKOUT3
I2C
OUT4H
/1, /5,
/25
OUT4L
2n
{0 ≤n≥ 19}
CLKOUT4
Figure 4 : APLL Slice Block Diagram
Each APLL slice has an AFB feedback divider with integer and fractional components and a high speed ODIV output
divider. Each of the four device outputs can select the output from either slice and divide it through a two-stage
divider to generate the final output frequency. This mechanism allows multiple different, but related, frequencies to
be generated by a single slice. In the following discussion on frequency selection, the slice-specific and outputspecific dividers are considered together.
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DATASHEET
APLL Output Dividers
The APLL includes 3 stages of output dividers:
1) Very High Speed Post Divider

ODIV
Allowed divider values are /2, /3, /4, /5
2) Two stages High/Low speed output dividers dedicated to each output path.

OUT1H, OUT2H, OUT3H, OUT4H
Allowed divider values are /1, /5, /25

OUT1L, OUT2L, OUT1L, OUT2L
Allowed divider values are 1, /2n, {0 ≤ n ≤ 19}.
/1, /2, /4, /8, /16, /32.../219.
The output frequency of each of the outputs is the VCO frequency divided by these three dividers and is given by the
following equation.


 = ∗ 
∗

where n = 1..4

Where:
= Frequency of the CLKOUTn pin.

= Frequency of the VCO. The VCO range is 2.15 GHz – 2.8 GHz.
 = Divide ratio of the Very High Speed Post Divider.
  = Divide ratio of the High Speed post divider. Subscript n = [1..4] and defines the CLKOUTn path
  = Divide ratio of the Low Speed post divider. Subscript n = [1..4] and defines the CLKOUTn path
AFB Feedback Divider
The APLL feedback divider consists of integer and fractional components and its value determines the multiplication
factor of the crystal resonator or oscillator reference which sets the VCO frequency per the following equation.
 =  ∗  ∗ 
= Frequency of the VCO

= Frequency of the crystal resonator or oscillator reference.
 = On-chip frequency doubler circuit which can be enabled or not. When enabled, the input frequency is
multiplied by 2 at the input to the analog phase detector. Allowed values are 1 or 2.

= Analogue Feedback Divider ratio given by
 + 
 = Integer Feedback Divider value. The allowed range is 19…255

 = Fractional Feedback Divider Value. The allowed values are: 34 ,
2
Where :
0 ≤ x ≤ (234) -1
And:
x = 0, forces feedback divider into integer only mode.
The combined equation relating the reference frequency to the output frequency is as follows.
 =
 ∗  ∗ ( +  )
 ∗   ∗  
=

 ∗   ∗  
To calculate appropriate divider settings for given reference and output frequencies, the Semtech Clean Clock
software can be used. This is available on request from Semtech.
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DATASHEET
Software Controlled Synthesizer Mode
When using the ACS1823 in software controlled NCO synthesizer mode, the output frequency is steered by
modifying the AFB feedback divider to adjust the frequency ratio between VCO and the XTALA/XTALB reference
oscillator. The 34 bit fractional  divider allows this ratio to be controlled with a worst case tuning resolution
of 3.5 parts per trillion (ppt). To protect against partial or incomplete frequency update, both  and 
dividers need to be written before the new ratio is transferred to the APLL. Register update only occurs when the
 MSB byte is written in the register map.
NCO tuning resolution is dependent on the ratio between  and  . It may be estimated by the following simple
relationship which ignores the effects of fixed point arithmetic.
 =
 ∗ 
 ∗ 234
Example
Using the following device configuration the NCO tuning resolution may be quickly estimated by:
 =
30.726 ∗ 2
= 1.4 
2.59 ∗ 234
Where:

=
=
=

30.72 MHz
2
2.5 GHz
In practice, the NCO tuning resolution is dependent on the rounding affects introduced by the fixed point dividers,
and may be found by calculating the VCO frequency change caused by incrementing the  divider.
For the  ,  and  rates listed above, the ideal AFB feedback divider ratio would be


=
=
40 (dec)
0.6901041666667 (dec)
First step is to determine the required value ‘x’ to be written into the  register:
 =  ∗ 234
hence:
 = 0.6901041666667 ∗ 234
= 11,855,899,307 (dec)
(Rounded to nearest integer)
= 02_2_
(34 bit hexadecimal)
This gives an actual VCO frequency of:  = 2,500,000,000.00119 Hz
Now increment the  divider
x + 1 = 02_2_ (hex)
= 1,185,899,308
(dec)
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Given:
 =

234
 =
1,185,899,308
234
Then:
DATASHEET
= 0.690104166724
This gives a revised VCO frequency of:  = 2,500,000,000.00477 Hz
For the configuration used in this example, an increase of 1 LSB in the  value increases the fVCO frequency
by 0.00358Hz or 1.43 ppt
VCO Operation
The APLL contains a fully integrated Voltage Controlled Oscillator with an allowed range of 2.15 GHz to 2.8 GHz. The
VCO circuit integrates all required filter and charge pump components avoiding the need for external components.
Following initial Divider configuration, the VCO calibration circuit must be activated to lock the APLL to the reference
oscillator. Calibration ensures the optimum VCO operating setup and is performed automatically at power-up and
reset.
Once calibrated the VCO may be pulled by +/- 500ppm without the requirement to re-calibrate.
When using both APLL slices optimum jitter performance is attained when the VCO frequencies are a minimum of 50
MHz apart.
Factory Pre-configuration
If desired, the ACS1823 can be factory pre-configured with default register settings, reducing the configuration
necessary by the local CPU. In this mode, the customer can provide Semtech with the required device setting and a
unique part number will be assigned for that configuration.
CNFG
[1:0]
To support multiple applications with a single custom part number, up to four completely independent
configurations can be pre-programmed. The particular configuration to use is determined by the state of the
CNFG[1:0] pins at reset. Table 3 shows the pin settings for selecting a particular pre-programmed configuration.
L
L
H
H
L
H
L
H
Configuration Set
Configuration 1
Configuration 2
Configuration 3
Configuration 4
Table 3 : ACS1823 Factory Pre-programmed Configuration Selection
Note that when using a factory pre-programmed part, it is still necessary to set the RATE[1:0] pins to match the
reference clock source type and frequency range as shown in Table 2.
Please contact Semtech for details of the process for defining a factory pre-programmed configuration.
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CLKOUT Divider Paths
Each output path has a multiplexer at the beginning of the divider chain allowing source selection from either APLL.
Although there is no restriction on APLL selection, optimum jitter performance is achieved when the odd clock paths
(CLKOUT1 & CLKOUT3) are driven from slice A and the even clock paths (CLKOUT2 & CLKOUT4) are driven from
slice B.
CLKOUT Drivers
Universal drivers are used to drive the CLKOUT signal. These highly flexible drivers can be configured to match
LVPECL, CML, LVDS or LVCMOS interconnection standards. Options exist to enable on chip termination (100 ohm or
50 ohm) for driving differential signal schemes. Note that the use of on chip termination will increase current
consumption.
For systems that require signal conditioning to prevent unwanted reflections or fast rising edges, options exist to
allow the output clock signals to be slew rate limited. For CMOS mode, a range of driver strengths is provided
allowing the output current to be optimized depending on load conditions
Buffered Reference Oscillator Path
For applications that require a buffered version of the reference XTALA/XTALB oscillator an APLL bypass mode is
available in register 0x029 for CLKOUT3 that provides access to the XTALA/XTALB frequency via the universal output
driver.
Power Up Sequence
Power up Qualification
The device contains an internal power on reset watchdog circuit and crystal oscillator envelope detector. Both
circuits are activated during the power up sequence and require the following conditions to be met before
commencing startup:1) VDD Rail exceeds 2.25V
2) Voltage level on RESETB exceeds 0.7 * VDD
3) XTALA/XTALB oscillator has an amplitude in excess of 500mVpp
Once these qualification conditions are met, the device will commence startup.
Startup sequence
Once the qualification criterions are met the startup sequence will begin. Once started, the sequence will complete
within 500ms.
1)
2)
3)
4)
5)
6)
7)
8)
Pause for internal supply regulator startup
Pause for power supply settling & reference clock settling
Clear/Reset all digital registers and Flip Flops
Assign target configuration as defined by device pins CNFG[1:0]
Pause for analogue settling
Calibrate internal APLL oscillator
Pause to allow APLL loop to settle following calibration
Device enters normal operation
Assertion of the RESETB pin will force the device to restart the sequence at step 3).
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Electrical Specifications
Table 4: Operating conditions
Parameter
Ambient Operating
Temperature
Supply Voltage
VDD = 3.3 V 10%
Symbol
Min
Typ
Max
Unit
TA
-40
-
+85
oC
VDD
2.97
3.3
3.63
V
Symbol
Min
Typ
Max
Unit
Comments
Table 5: Absolute maximum ratings
Parameter
Supply voltage
LVCMOS, Three-level input
voltage
Clock input voltage
Oscillator input voltage
Operating junction temperature
Storage temperature
ESD Rating,
VDD
VLOGIC
-0.5
-0.3
3.8
VDD+0.3
V
V
VCLKINn
VREFn
TJ,OPER
TSTORAGE
ESDHBM
-0.3
-0.3
-55
-55
4,000
VDD+0.3
1.2+0.3
125
150
V
V
oC
oC
V
ESD rating,
ESDCDM
1,000
Latchup tolerance
Comments
V
Complies with JESD78
Table 6: DC characteristics
(VDD = 3.3  10%, TA = -40 to +85oC. Typical values are for VDD = 3.3 V, and TA = 25oC, unless otherwise noted.
Parameter
Supply Current
Single PLL
Fixed Synthesizer mode
Single PLL
Software Controlled
Synthesizer mode
Dual PLL
Fixed Synthesizer mode
Dual PLL
Software Controlled
Synthesizer mode
Revision 1.1
February, 2016 © Semtech Corp.
Symbol
Min
Typ
Max
Unit
IDD
190
215
mA
IDD
240
270
mA
IDD
365
400
mA
IDD
455
510
mA
Page 11
Comments
VDD = 3.3 V, one PLL, two
LVPECL outputs enabled at
156.25MHz
Not including external
termination currents.
VDD = 3.3 V, one PLL, two
LVPECL outputs enabled at
156.25MHz
Not including external
termination currents.
VDD = 3.3 V, two PLLs, four
LVPECL outputs enabled at
156.25MHz
Not including external
termination currents.
VDD = 3.3 V, two PLLs, four
LVPECL outputs enabled at
156.25MHz
Not including external
termination currents.
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
Parameter
Supply current,
‘Power Down’ mode
Symbol
Min
IDD
DATASHEET
Typ
Max
50
LVCMOS mode inputs (RESETB, CNFG0, CNFG1)
LVCMOS input voltage, high
VIH
0.7VDD
LVCMOS input voltage, low
VIL
mA
0.3VDD
Differential mode clock outputs (CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4)
Differential output resistance
LVDS Mode
RD
100
CML Mode
100
LVCMOS mode clock outputs (CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4)
LVCMOS output voltage, high
VOH
VDD - 0.4
LVCMOS output voltage, low
VOL
0.4
Crystal/reference clock inputs (XTALA, XTALB)
Single ended input resistance
RXTALA,
RXTALB
Single ended input voltage,
VXTALA,
-0.5
external clock input
VXTALB
12
I2C/SPI Inputs (SCL_SCLK, SDA_SDO, ADD0, ADD1, ADD2_SS, SDI)
Input voltage, high
VIH
0.7VDD
Input voltage, low
VIL
Input current, high
IIH
Input current, low
IIL
Noise margin, high
Noise margin, low
VnL
VnH
0.2VDD
0.1VDD
I2C/SPI outputs (SDA_SDO)
Output voltage, high
Output voltage, low
Output current, high
Output current, low
VOH
VOL
IOH
IOL
VDD - 0.4
Revision 1.1
February, 2016 © Semtech Corp.
Page 12
Unit
Comments
VDD = 3.3 V, RESETB = Low.
V
V
Ω
V
V
-
kΩ
1.2
V
0.3VDD
V
V
20
A
20
A
0.4
2
2
V
V
mA
mA
IOH = 4mA
IOL = -4mA
VIN = VDD
(pins with internal pull-downs)
VIN = GND
(pins with internal pull-ups)
IOH = 2 mA
IOL = -2 mA
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
Parameter
Three-level inputs (RATE0, RATE1)
Input voltage, high
Input voltage, mid
Input voltage, low
Input current, high
Input current, mid
Input current, low
Symbol
Min
VIH
VIM
VIL
0.85VDD
0.45VDD
DATASHEET
Typ
Max
0.55VDD
0.15VDD
-20
-2
+2
20
Unit
Comments
V
V
V
A
A
A
Table 7: AC Characteristics
(VDD = 3.3  10%, TA = -40 to +85oC. Typical values are for VDD = 3.3 V, and TA = 25oC, unless otherwise noted.)
Parameter
Symbol
Crystal/reference oscillator (XTALA, XTALB)
Reference oscillator crystal
frequency
fXTAL
3rd Overtone
Fundamental
External sinusoidal reference
fREF
input
External crystal load
C
capacitance
Peak to peak external
sinusoidal reference input
VIN
voltage,
Min
Typ
Max
60
10
114.285
60
10
114.285
8
Unit
MHz
Comments
Use XO Doubler when fXTAL (or
fREF) is lower than 60 MHz
MHz
pf
500
1,200
mV
Based on 30.72 MHz
Fundamental mode crystal
AC coupled input at XTALA,
XTALB input connected to GND
(ground) through a 0.1F
capacitor.
Voltage Controlled Oscillator
VCO operating frequency
Fvco
2.15
2.80
GHz
VCO tuning resolution
Su
0.25
3.50
ppt
Differential mode clock outputs (CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4)
Differential output voltage
LVPECL mode
1,100
1,670
1,900
CML mode
VOD
300
530
700
LVDS mode
500
870
1100
Low swing LVDS mode
350
640
800
Frequency
fCLKOUT
LVPECL, CML or LVDS
2,000
1.40×109
Duty cycle
dUTY
45
55
Output rise/fall time
tOR, tOF
250
350
Revision 1.1
February, 2016 © Semtech Corp.
Page 13
mVPP
Re-calibration required for >
±500 ppm change in
operating frequency.
Via I2C/SPI external tuning
word.
Measured driving into
standard load with on chip
termination disabled and
nominal swing, slew and drive
current settings.
Hz
%
ps
20% to 80% into standard
load.
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
Parameter
Symbol
Min
DATASHEET
Typ
Max
Unit
Comments
LVCMOS mode clock outputs (CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4 when in LVCMOS mode)
Output frequency
fCLKOUT
2,000
250x106
Hz
20 pF load, 20% to 80%
Output rise/fall time
2
ns
Reset timing (RESETB)
Reset pulse width
Reset to SPI/I2C ready
Reset to CLKOUTn output valid
Squelch to CLKOUTn output
active
100
s
ms
tCLKOUT
500
ms
tCLKOUT
10
s
tRESET
tREADY
1
(Note 2).
Time for internal APLL and
divider startup. (Note 1).
CLKOUTnEN squelch time
(Note 3).
(Note 1) Qualification time allows oscillator settling prior to automatic APLL calibration..
(Note 2) Output valid time measured from the point where VDD >= 3.0V, ResetB >= 0.7 * VDD, fCLKOUT > 1 MHz.
(Note 3) Time measured from completion of I2C/SPI write to CLKOUTnEN register 0x015
Microprocessor Interface
Table 8: Microprocessor interface timing characteristics
(VDD = 3.3  10%, TA = -40 to +85oC. Typical values are for VDD = 3.3V, and TA = 25oC, unless otherwise noted.)
Note: When the device is powered down, SCL/SDA are clamped to GND.
Parameter
I2C
Symbol
Min
Typ
“I2C-bus
mode timing specifications (SCL, SDA), per NXP
2012”
SCL frequency
fSCL
0
SCL period, low
tLOW
1.3
SCL period, high
tHIGH
0.6
SDA setup time
tSU;DAT
100
SDA hold time
tHD;DAT
0
Repeated start setup time
tSU;STA
0.6
Start condition hold time
tHD;STA
0.6
Stop condition hold time
tHD;STO
0.6
Bus free time between start
tBUF
1.3
and stop
Input hysteresis
VHYS
0.05VDD
Input glitch suppression
tSP
SPI mode timing specifications (ADD2_SS, SCLK, SDO, SDI)
SCLK Period
t1
100
Revision 1.1
February, 2016 © Semtech Corp.
Page 14
Max
Unit
Comments
specification and user manual, Rev. 5 – 9 October
400
200
kHz
s
s
ns
ns
s
s
s
s
V
ns
ns
In addition, the SCLK
frequency must not exceed ¼
of the fXTAL oscillator
frequency, after optional
doubling.
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
Parameter
SCLK 20 to 80% rise time
SCLK 20 to 80% fall time
SCLK low duration
SCLK high duration
SCLK fall to SDO active
ADD2_SS rise to SDO tri-state
ADD2_SS to SCLK setup time
ADD2_SS to SCLK hold time
SDI to SCLK setup time
SDI to SCLK hold time
Minimum time between
sequential slave select
Symbol
tr
tf
t2
t3
t4
t5
t6
t7
t8
t9
t10
Min
DATASHEET
Typ
Max
Unit
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
30
25
25
25
20
25
20
25
Comments
Figure 5 : I2C Interface Timing
Revision 1.1
February, 2016 © Semtech Corp.
Page 15
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Two-wire (I2C) microprocessor interface
When Pin I2C_SPI = Low, ACS1823 supports Fast Mode (400 kHz clock) two-wire (I2C) communication. In I2C mode,
bidirectional serial data is communicated on SDA and the serial clock on SCL. Consistent with normal practice for
the I2C interface, SDA and SCL must normally be provided with appropriate external pull-up resistors to VDD for
proper operation (I2C is an open drain interface). The three LSBs of the internal I2C slave address are set by the pins
ADD2, ADD1 and ADD0, making the I2C interface address 1101(ADD2)(ADD1)(ADD0)(R/W).
The format for an I2C write to ACS1823 is:
S
Slave Addr
O
A
Byte Addr
A
Data
A
S
A
Data
A
P
The format for an I2C read command is:
S
Slave Addr
O
A
Byte Addr
Slave Addr
1
A
Data
A
Data
A
P
Where S indicates the I2C ‘start’ condition, A indicates the I2C ‘acknowledge’ condition and P indicates the I2C ‘stop’
condition; ACS1823 supports multiple data word read and writer operations.
Four-wire (SPI) serial microprocessor interface
When Pin I2C_SPI = High, ACS1823 supports four-wire Serial Peripheral Interface (SPI) communication. In SPI mode,
serial data is input on SDI, serial data is output on SDO, serial clock is input on SCLK and slave select is input on SS;
the maximum clock rate in SPI mode is one quarter of the oscillator frequency, after optional internal frequency
doubling. When operated in SPI mode, external pull up resistors should not be used (SPI is not an open drain
interface).
SPI configuration is defined in the register map at address 0x004.
The SPI protocol consists of a read/write bit, 7 bits of address and 1 or more bytes of data. The interface provided
on ACS1823 supports many configurable variations, including




clock polarity: (CPOL in conventional SPI)
o CPOL=0, the clock is normally low
o CPOL=1, the clock is normally high (default)
clock edge selection: (CPHA)
o CPHA=CPOL, data is captured on the rising edge, propagated on the falling edge of SCK (default)
o CPHA=!CPOL, data is captured on falling edge, propagated on rising edge of SCK
endianness: (BITORDER)
o BITORDER = 0, lsb-first
o BITORDER = 1, msb-first (default)
RW bit: (RWBIT_POS)
o RWBIT_POS = 0, RW bit at beginning of address field. (default)
o RWBIT_POS = 1, RW bit at end of address field
An example default mode of SPI write and read operations are shown in the following diagrams, showing only 8 bit
accesses.
Revision 1.1
February, 2016 © Semtech Corp.
Page 16
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Figure 6 : SPI write operation (default) - single byte
Figure 7 : SPI Read operation (default) - single byte
SDA_SDO is tristated while ADD2_SS is inactive (high) to allow multi-slave operation with shared signaling.
Note that the data driven out on SDA_SDO is a copy of the signaling driven in on SDI during the previous cycle. This
can be used by the host to raise confidence that the previous access was successful. The data portion of a read
access is the exception of course, as the data being driven out is the read data itself.
Multi-byte accesses
Multi-byte accesses are also supported by continuing the data byte field while ADD2_SS is held low
Revision 1.1
February, 2016 © Semtech Corp.
Page 17
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Register Map Paging and Addressing (I2C / SPI)
The ACS1823 addressing range is split into pages to accommodate substantially more than the 128 registers
supported by an unpaged 7 bit addressing scheme.
The page register used by ACS1823 resides at address 0x000.
For example register addresses within the range 0x001 – 0x07f (Page 0) require the page register to be programed
0x00 which is the default value following power up or reset. To access register addresses within the range 0x080 –
0x0FF the page register must be written to hold 0x01. Once programmed all subsequent I2C/SPI physical
addresses will be offset to access Page 1.
Care must be taken when using auto increment mode for multi-byte register access to avoid inadvertent crossing of
page boundaries.
Figure 8 : Register Map Page Structure
Revision 1.1
February, 2016 © Semtech Corp.
Page 18
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Register Map Summary
R0 = Read Only
R/W = Read/Write
Type
Register Usage
Address
(Hex)
Register name
page_register
000
R/W
7 (MSB)
6
5
4
3
2
1
0 (LSB)
Register Map Paging and Addressing
Page Address[3:0]
General Purpose, Input/Output Divider and Output Control
ctrl_enableB
ctrl_enableA
ctrl_mode
ctrl_ext_cfg
001
002
003
004
R/W
R/W
R/W
R/W
Reserved
–
ctrl_out_div2
ctrl_out_div4
ctrl_out_div1
ctrl_out_div3
ctrl_clkout_mux
ctrl_op_lvpecl_2_4
ctrl_op_cml_2_4
ctrl_op_lvds_2_4
ctrl_op_drive_2_4
ctrl_op_lvpecl_1_3
ctrl_op_cml_1_3
ctrl_op_lvds_1_3
ctrl_op_drive_1_3
005
013
014
015
016
01C
01D
01E
01F
020
021
022
023
024
025
026
027
028
029
ctrl_op_pullup
ctrl_xo_double
02A
02B
R/W
R/W
Reserved
02C
0D7
–
apllA_dco_clk
Reserved
0D8
0D9
0DF
0E0
0E1
0E2
0E3
0E4
117
R/W
-
118
119
11F
120
121
R/W
ctrl_rx_div_enable
ctrl_op_drive
Reserved
DCO_B
DCO_A
I2C_SLAVE_ADDR
R/W
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OUT4MUX
I_CML
OUT2MUX
TERM2EN
CML2_50R
I_CML
TERM1EN
CML1_50R
PD4EN
PD2EN
SPI
RW Bit
SPI
Bit Order
SYNTH_B
SPI active
edge
SYNTH_A
SPI SCK
polarity
OUT4EN
OUT3EN
OUT2EN
OUT1EN
CLKOUT3EN
CLKOUT4EN
CLKOUT1EN
CLKOUT2EN
OUT2L_DIVIDER_RATIO
OUT2H_DIVIDER_RATIO
OUT4L_DIVIDER_RATIO
OUT4H_DIVIDER_RATIO
OUT1L_DIVIDER_RATIO
OUT1H_DIVIDER_RATIO
OUT3L_DIVIDER_RATIO
OUT3H_DIVIDER_RATIO
OUT3MUX
OUT1MUX
TERM4EN
CML4_50R CML2_100R CML4_100R
CMOS_DRIVE2_4
I_LVDS
SWING2
SWING4
TERM2EN
TERM4EN
SLEW_2_4
CLKOUT4MODE
CLKOUT2MODE
TERM3EN
CML3_50R CML1_100R CML3_100R
CMOS_DRIVE1_3
I_LVDS
SWING1
SWING3
TERM1EN
TERM3EN
SLEW_1_3 /
CLKOUT3MODE
CLKOUT1MODE
XO
PU4EN
PU2EN
PD3EN
PD1EN
PU3EN
PU1EN
XO_DBL_EN
Slice A Analog PLL Control
apllA_enable
Reserved
apllA_odivider
Reserved
R/W
–
DCO_RATE
APLL_EN
ODIV_RATIO
R/W
–
Slice B Analog PLL Control
apllB_dco_clk
Reserved
apllB_enable
Reserved
R/W
–
Revision 1.1
February, 2016 © Semtech Corp.
DCO_RATE
APLL_EN
Page 19
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Type
Register Usage
Address
(Hex)
Register name
apllB_odivider
Reserved
122
123
124
1A0
R/W
–
afbA_cnfg
1A1
R/W
afbA_fraction0
afbA_fraction1
afbA_fraction2
afbA_fraction3
afbA_fraction4
afbA_integer0
afbA_integer1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
1A9
1B0
–
afbB_cnfg
1B1
R/W
afbB_fraction0
afbB_fraction1
afbB_fraction2
afbB_fraction3
afbB_fraction4
afbB_integer0
afbB_integer1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
1BA
400
–
chip_id
Reserved
irq_mask_rising1
401
402
403
RO
R/W
R/W
Reserved
irq_mask_rising3
404
405
R/W
R/W
Reserved
irq_mask_falling1
406
407
R/W
R/W
Reserved
irq_mask_falling3
408
409
R/W
R/W
irq_cn_st_status
Reserved
irq_status_rising1
40A
40B
40C
RO
R/W
R/W
Reserved
irq_status_rising3
40D
40E
R/W
R/W
Reserved
40F
R/W
R0 = Read Only
R/W = Read/Write
7 (MSB)
6
5
4
3
2
1
0 (LSB)
ODIV_RATIO
Slice A Fractional Feedback Divider Control
CALIBRATE_
MODE
CALIBRATE
AFB_FRACTION[7:0]
AFB_FRACTION[15:8]
AFB_FRACTION[23:16]
AFB_FRACTION[31:24]
AFB_FRACTION[33:32]
AFB_INTEGER[7:0]
AFB_INTEGER
[8]
Slice B Fractional Feedback Divider Control
CALIBRATE_
MODE
CALIBRATE
AFB_FRACTION [7:0]
AFB_FRACTION [15:8]
AFB_FRACTION [23:16]
AFB_FRACTION [31:24]
AFB_FRACTION [33:32]
AFB_INTEGER [7:0]
AFB_INTEGER
[8]
Interrupt and Miscellaneous Control
Revision 1.1
February, 2016 © Semtech Corp.
CHIP_ID
DCOLCK_A_
MSK_R
DCOLCK_B_
MSK_R
DCOLCK_A_
MSK_F
DCOLCK_B_
MSK_F
IRQ
DCOLCK_A_
IRQ_R
DCOLCK_B_
IRQ_R
Page 20
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
R0 = Read Only
R/W = Read/Write
Type
Register Usage
Address
(Hex)
Register name
irq_status_falling1
410
R/W
Reserved
irq_status_falling3
411
412
R/W
R/W
Reserved
irq_status_live1
413
414
RO
RO
Reserved
irq_status_live3
415
416
RO
RO
ctrl_reset
417
R/W
7 (MSB)
6
5
4
3
2
1
0 (LSB)
DCOLCK_A_
IRQ_F
DCOLCK_B_
IRQ_F
DCOLCK_A_
IRQ
DCOLCK_B_
IRQ
HARD_RST
Register Map Descriptions
Address (Hex): 0x000
Register name
Bit 7
page_register
Bit 6
Bit 5
Description
Bit 4
Page Sub Address Register.
Bit 3
Bit 2
Bit 1
Bit 0
Page Address[3:0]
Bit No
Description
Bit Value
Value Description
[7:4]
Do not use
-
[3:0]
Page Sub Address
0000
Page sub range 0x000 – 0x07F
Register containing Register Map page
number. Once programmed all subsequent
I2C/SPI physical addresses will be offset by
the Page Sub Address multiplied by 0x80.
0001
Page sub range 0x080 – 0x0FF
0010
Page sub range 0x100 – 0x17F
0011
Page sub range 0x180 – 0x1FF
example:
0100
Page sub range 0x200 – 0x27F
Writing to register 0x1A8
0101
Page sub range 0x280 – 0x2FF
1) Write value 0x03 to I2C/SPI Address 0x00
- All subsequent register writes now offset
by address 0x180.
0110
Page sub range 0x300 – 0x37F
0111
Page sub range 0x380 – 0x3FF
2) Write data to I2C/SPI Address 0x28
- Data will be written to register 0x1A8
(0x180 + 0x28 = 0x1A8)
1000
Page sub range 0x400 – 0x47F
1001
Do Not Use
:
1111
Revision 1.1
February, 2016 © Semtech Corp.
Page 21
-
:
:
:
Do Not Use
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x001
Register name
Bit 7
ctrl_enableB
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) Control register for Digital Control Loop
B
Bit 2
Bit 1
Bit 0
DCO_B
Bit No
Description
[7:3]
2
Bit Value
Do not use
-
-
0
Fixed Synthesizer Mode
1
Software Synthesizer Mode (Slice B)
DCO B
interface enable
[1:0]
Value Description
Do not use
(Slice B)
-
Address (Hex): 0x002
Register name
Bit 7
ctrl_enableA
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) Control register for Digital Control Loop
A
Bit 2
Bit 1
Bit 0
DCO_A
Bit No
Description
[7:3]
2
Bit Value
Do not use
-
-
0
Fixed Synthesizer Mode
1
Software Synthesizer Mode (Slice A)
DCO A
interface enable
[1:0]
Value Description
Do not use
Revision 1.1
February, 2016 © Semtech Corp.
-
Page 22
(Slice A)
-
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x003
Register name
Bit 7
Bit No
ctrl_mode
Bit 6
Bit 5
Description
Bit 4
Description
[7:2]
1
Bit Value
Do not use
Bit 2
Bit 1
Bit 0
SYNTH_B
SYNTH_A
Value Description
-
-
SYNTH_B
Synthesizer Software Control loop power
0
Bit 3
(R/W) Control Register Synthesizer enables
0
Software Synthesizer mode
1
Fixed Synthesizer mode
0
Software Synthesizer mode
1
Fixed Synthesizer mode
SYNTH_A
Synthesizer Software Control loop power
Address (Hex): 0x004
Register name
Bit 7
ctrl_ext_cfg
Bit 6
Bit 5
Description
Bit 4
I2C_SLAVE_ADDR
Bit No
Description
[7:4]
Bit 3
Bit 2
Bit 1
Bit 0
RWBIT_POS
BITORDER
CPHA
CPOL
Bit Value
I2C_SLAVE_ADDR
(R/W) Microprocessor port configuration
Value Description
1101
I2C slave address upper four bits
RWBIT_POS
0
RW bit is before the address field
SPI mode RW bit position
1
RW bit is after the address field
BITORDER
0
Transmit LSB first
SPI mode bit order
1
Transmit MSB first
CPHA
0
Use falling edge
SPI mode control bit to set active edge
1
Use rising edge
CPOL
0
SCK is normally low
SPI mode control bit to set SCK polarity
1
SCK is normally high
Upper 4 bits of device I2C Slave Address.
Total address length is 7 bits where the the
lower 3 bits are defined by the logic values
assigned to the physical Address bit pins as
defined in the Pin Description Table.
3
2
1
0
Revision 1.1
February, 2016 © Semtech Corp.
Page 23
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x005 – 0x013
Register name
Bit 7
Reserved
Bit 6
Bit No
Description
[7:0]
Do not use
Bit 5
Description
Bit 4
Test Register. Do not use.
Bit 3
Bit Value
Bit 2
Bit 1
Bit 0
Value Description
-
-
Address (Hex): 0x014
Register name
Bit 7
Bit No
[7:4]
3
2
1
0
ctrl_rx_div_enable
Bit 6
Bit 5
Description
Bit 4
Description
(R/W) Control register for output divider paths
Bit 3
Bit 2
Bit 1
Bit 0
OUT4EN
OUT3EN
OUT2EN
OUT1EN
Bit Value
Do not use
0000
Value Description
Reserved
OUT4EN
0
Disable
CLKOUT4 high and low speed divider path
1
Enable
OUT3EN
0
Disable
CLKOUT3 high and low speed divider path
1
Enable
OUT2EN
0
Disable
CLKOUT2 high and low speed divider path
1
Enable
OUT1EN
0
Disable
CLKOUT1 high and low speed divider path
1
Enable
Revision 1.1
February, 2016 © Semtech Corp.
Page 24
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x015
Register name
Bit 7
Bit No
ctrl_op_drive
Bit 6
Bit 5
Description
Bit 4
Description
[7:4]
3
2
1
0
Bit 3
Bit 2
Bit 1
Bit 0
CLKOUT3EN
CLKOUT4EN
CLKOUT1EN
CLKOUT2EN
Bit Value
Do not use
0011
CLKOUT3 pin enable
CLKOUT4 pin enable
CLKOUT1 pin enable
CLKOUT2 pin enable
(R/W) Output Pad enable
Value Description
Reserved
0
Disable CLKOUT3 output driver
1
Enable CLKOUT3 output driver
0
Disable CLKOUT4 output driver
1
Enable CLKOUT4 output driver
0
Disable CLKOUT1 output driver
1
Enable CLKOUT1 output driver
0
Disable CLKOUT2 output driver
1
Enable CLKOUT2 output driver
Address (Hex): 0x016 - 0x01C
Register name
Bit 7
Reserved
Bit 6
Bit No
Description
[7:0]
Do not use
Revision 1.1
February, 2016 © Semtech Corp.
Bit 5
Description
Bit 4
Bit 3
Bit Value
-
Page 25
(R/W) Test Register. Do not use.
Bit 2
Bit 1
Bit 0
Value Description
-
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x01D
Register name
Bit 7
ctrl_out_div2
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) OUT2 Output Divider control
Bit 2
Bit 1
OUT2L_DIVIDER_RATIO
Bit No
7
[6:2]
Description
OUT2H_DIVIDER_RATIO
Bit Value
Not used
-
Value Description
Not used.
OUT2L_DIVIDER_RATIO
00000
Set divider ratio 2^0
CLKOUT2 second stage low speed output
divider ratio
00001
Set divider ratio 2^1
:
:
10010
Set divider ratio 2^18
10011
Set divider ratio 2^19
10100
Undefined, do not use.
10101
Undefined, do not use.
:
11111
[1:0]
:
Undefined, do not use.
OUT2H_DIVIDER_RATIO
00
Set divider ratio 1
CLKOUT2 first stage output divider
01
Set divider ratio 1
10
Set divider ratio 5
11
Set divider ratio 25
Revision 1.1
February, 2016 © Semtech Corp.
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Bit 0
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x01E
Register name
Bit 7
ctrl_out_div4
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) OUT4 Output Divider control
Bit 2
Bit 1
OUT4L_DIVIDER_RATIO
Bit No
7
[6:2]
Description
OUT4H_DIVIDER_RATIO
Bit Value
Not used
-
Value Description
Not used.
OUT4L_DIVIDER_RATIO
00000
Set divider ratio 2^0
CLKOUT4 second stage low speed output
divider ratio
00001
Set divider ratio 2^1
:
:
10010
Set divider ratio 2^18
10011
Set divider ratio 2^19
10100
Undefined, do not use.
10101
Undefined, do not use.
:
11111
[1:0]
:
Undefined, do not use.
OUT4H_DIVIDER_RATIO
00
Set divider ratio 1
CLKOUT4 first stage output divider
01
Set divider ratio 1
10
Set divider ratio 5
11
Set divider ratio 25
Revision 1.1
February, 2016 © Semtech Corp.
Page 27
Bit 0
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x01F
Register name
Bit 7
ctrl_out_div1
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) OUT1 Output Divider control
Bit 2
Bit 1
OUT1L_DIVIDER_RATIO
Bit No
7
[6:2]
Description
OUT1H_DIVIDER_RATIO
Bit Value
Not used
-
Value Description
Not used.
OUT1L_DIVIDER_RATIO
00000
Set divider ratio 2^0
CLKOUT1 second stage low speed output
divider ratio
00001
Set divider ratio 2^1
:
:
10010
Set divider ratio 2^18
10011
Set divider ratio 2^19
10100
Undefined, do not use.
10101
Undefined, do not use.
:
11111
[1:0]
:
Undefined, do not use.
OUT1H_DIVIDER_RATIO
00
Set divider ratio 1
CLKOUT1 first stage output divider
01
Set divider ratio 1
10
Set divider ratio 5
11
Set divider ratio 25
Revision 1.1
February, 2016 © Semtech Corp.
Page 28
Bit 0
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x020
Register name
Bit 7
ctrl_out_div3
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) OUT3 Output Divider control
Bit 2
Bit 1
OUT3L_DIVIDER_RATIO
Bit No
7
[6:2]
Description
OUT3H_DIVIDER_RATIO
Bit Value
Reserved
-
Value Description
Reserved. Do Not Modify
OUT3L_DIVIDER_RATIO
00000
Set divider ratio 2^0
CLKOUT3 second stage low speed output
divider ratio
00001
Set divider ratio 2^1
:
:
10010
Set divider ratio 2^18
10011
Set divider ratio 2^19
10100
Undefined, do not use.
10101
Undefined, do not use.
:
11111
[1:0]
:
Undefined, do not use.
OUT3H_DIVIDER_RATIO
00
Set divider ratio 1
CLKOUT3 first stage output divider
01
Set divider ratio 1
10
Set divider ratio 5
11
Set divider ratio 25
Revision 1.1
February, 2016 © Semtech Corp.
Page 29
Bit 0
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x021
Register name
ctrl_clkout_mux
Description
Bit 7
Bit 6
Bit 5
Bit 4
OUT4MUX
OUT2MUX
OUT3MUX
OUT1MUX
Bit No
Description
7
6
5
4
[3:0]
Bit 3
Bit Value
(R/W) CLKOUT Source Select
Bit 2
Bit 1
Bit 0
Value Description
OUT4MUX
0
CLKOUT4 driven by SLICE<A>
CLKOUT4 source selection between
SLICE<A> and SLICE<B>
1
CLKOUT4 driven by SLICE<B>
OUT2MUX
0
CLKOUT2 driven by SLICE<A>
CLKOUT2 source selection between
SLICE<A> and SLICE<B>
1
CLKOUT2 driven by SLICE<B>
OUT3MUX
0
CLKOUT3 driven by SLICE<A>
CLKOUT3 source selection between
SLICE<A> and SLICE<B>
1
CLKOUT3 driven by SLICE<B>
OUT1MUX
0
CLKOUT1 driven by SLICE<A>
CLKOUT1 source selection between
SLICE<A> and SLICE<B>
1
CLKOUT1 driven by SLICE<B>
Reserved.
-
Reserved. Do Not Modify
Address (Hex): 0x022
Register name
Bit 7
Bit No
ctrl_op_lvpecl_2_4
Bit 6
Bit 5
TERM2EN
TERM4EN
Description
Bit 4
Bit 3
Description
Bit Value
(R/W) LVPECL termination control for CLKOUT2
and CLKOUT4
Bit 2
Bit 1
Bit 0
Value Description
7
Reserved
-
Do Not Modify
6
TERM2EN
0
Disable LVPECL on chip termination
LVPECL enable control for CLKOUT2 on chip
termination
1
Enable LVPECL on chip termination
TERM4EN
0
Disable LVPECL on chip termination
LVPECL enable control for CLKOUT4 on chip
termination
1
Enable LVPECL on chip termination
Reserved
-
Do Not Modify
5
[4:0]
Revision 1.1
February, 2016 © Semtech Corp.
Page 30
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x023
Register name
ctrl_op_cml_2_4
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
I_CML
CML2_50R
CML4_50R
CML2_100R
CML4_100R
Bit No
Description
Bit Value
(R/W) CML and CMOS termination control for
CLKOUT2 and CLKOUT4
Bit 2
Bit 1
Bit 0
CMOS_DRIVE2_4
Value Description
7
I_CML
-
Do Not Modify
6
CML2_50R
0
Disable CML on chip termination
CML enable control for CLKOUT2 50 ohm on
chip termination
1
Enable CML on chip termination
CML4_50R
0
Disable CML on chip termination
CML enable control for CLKOUT4 50 ohm on
chip termination
1
Enable CML on chip termination
CML2_100R
0
Disable CML on chip termination
CML enable control for CLKOUT2 100 ohm
on chip termination
1
Enable CML on chip termination
CML4_100R
0
Disable CML on chip termination
CML enable control for CLKOUT4 100 ohm
on chip termination
1
Enable CML on chip termination
CMOS_DRIVE2_4
00
Drive strength x1
Output drive strength on CLKOUT2 and
CLKOUT4
01
Drive strength x2
10
Drive strength x4
11
Drive strength x8
0
Do Not Modify
5
4
3
[2:1]
0
Reserved
Revision 1.1
February, 2016 © Semtech Corp.
Page 31
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x024
Register name
Bit 7
ctrl_op_lvds_2_4
Bit 6
Bit 5
Description
Bit 4
I_LVDS
Bit No
[7:6]
Description
(R/W) LVDS termination control for CLKOUT2
and CLKOUT4
Bit 3
Bit 2
Bit 1
SWING2
SWING4
TERM2EN
Bit Value
-
Do Not Modify
I_LVDS
0
Nominal LVDS current
LVDS current control for CLKOUT2 and
CLKOUT4
1
High LVDS current
4
Reserved
-
Do Not Modify
3
SWING2
0
Nominal swing
LVDS output swing control CLKOUT2
1
Low Level swing
SWING4
0
Nominal swing
LVDS output swing control CLKOUT4
1
Low Level swing
TERM2EN
0
Enable LVDS termination
Controls LVDS on chip termination for
CLKOUT2
1
Disable LVDS termination
TERM4EN
0
Enable LVDS termination
Controls LVDS on chip termination for
CLKOUT4
1
Disable LVDS termination
2
1
0
Revision 1.1
February, 2016 © Semtech Corp.
Page 32
TERM4EN
Value Description
Reserved
5
Bit 0
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x025
Register name
Bit 7
ctrl_op_drive_2_4
Bit 6
Bit 5
Description
Bit 4
Bit 3
SLEW_2_4
Bit No
[7:5]
4
[3:2]
[1:0]
Description
(R/W) Driver modes for CLKOUT2 and
CLKOUT4
Bit 2
CLKOUT4MODE
Bit Value
-
Do Not Modify
SLEW_2_4
0
Nominal Slew Rate
Common control for output driver slew rate
for CLKOUT2 and CLKOUT4
1
Fast Slew Rate
CLKOUT4MODE.
00
LVPECL mode
CLKOUT4 drive format selection
01
CML mode
10
LVDS mode
11
CMOS mode
CLKOUT2MODE.
00
LVPECL mode
CLKOUT2 drive format selection
01
CML mode
10
LVDS mode
11
CMOS mode
Page 33
Bit 0
CLKOUT2MODE
Value Description
Reserved
Revision 1.1
February, 2016 © Semtech Corp.
Bit 1
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x026
Register name
Bit 7
Bit No
ctrl_op_lvpecl_1_3
Bit 6
Bit 5
TERM1EN
TERM3EN
Description
Bit 4
Bit 3
Description
Bit Value
(R/W) LVPECL termination control for CLKOUT1
and CLKOUT3
Bit 2
Bit 1
Value Description
7
Reserved
-
Do Not Modify
6
TERM1EN
0
Disable LVPECL on chip termination
LVPECL enable control for CLKOUT1 on chip
termination
1
Enable LVPECL on chip termination
TERM3EN
0
Disable LVPECL on chip termination
LVPECL enable control for CLKOUT3 on chip
termination
1
Enable LVPECL on chip termination
Reserved
-
Do Not Modify
5
[4:0]
Revision 1.1
February, 2016 © Semtech Corp.
Page 34
Bit 0
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x027
Register name
ctrl_op_cml_1_3
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
I_CML
CML1_50R
CML3_50R
CML1_100R
CML3_100R
Bit No
Description
Bit Value
(R/W) CML and CMOS termination control for
CLKOUT1 and CLKOUT3
Bit 2
Bit 1
CMOS_DRIVE1_3
Value Description
7
I_CML
-
Do Not Modify
6
CML1_50R
0
Disable CML on chip termination
CML enable control for CLKOUT1 50 ohm on
chip termination
1
Enable CML on chip termination
CML3_50R
0
Disable CML on chip termination
CML enable control for CLKOUT3 50 ohm on
chip termination
1
Enable CML on chip termination
CML1_100R
0
Disable CML on chip termination
CML enable control for CLKOUT1 100 ohm
on chip termination
1
Enable CML on chip termination
CML3_100R
0
Disable CML on chip termination
CML enable control for CLKOUT3 100 ohm
on chip termination
1
Enable CML on chip termination
5
4
3
[2:1]
0
CMOS_DRIVE1_3
00
Drive strength x1
Output drive strength on CLKOUT1 and
CLKOUT3
01
Drive strength x2
10
Drive strength x4
11
Drive strength x8
Reserved
Revision 1.1
February, 2016 © Semtech Corp.
0
Page 35
Bit 0
Do Not Modify
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x028
Register name
Bit 7
ctrl_op_lvds_1_3
Bit 6
Bit 5
Description
Bit 4
I_LVDS
Bit No
[7:6]
Description
(R/W) LVDS termination control for CLKOUT1 and
CLKOUT3
Bit 3
Bit 2
Bit 1
SWING1
SWING3
TERM1EN
Bit Value
-
Do Not Modify
I_LVDS
0
Nominal LVDS current
LVDS current control for CLKOUT1 and
CLKOUT3
1
High LVDS current
4
Reserved
-
Do Not Modify
3
SWING1
0
Nominal swing
LVDS output swing control CLKOUT1
1
Low Level swing
SWING3
0
Nominal swing
LVDS output swing control CLKOUT3
1
Low Level swing
TERM1EN
0
Enable LVDS termination
Controls LVDS on chip termination for
CLKOUT1
1
Disable LVDS termination
TERM3EN
0
Enable LVDS termination
Controls LVDS on chip termination for
CLKOUT3
1
Disable LVDS termination
2
1
0
Revision 1.1
February, 2016 © Semtech Corp.
Page 36
TERM3EN
Value Description
Reserved
5
Bit 0
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x029
Register name
ctrl_op_drive_1_3
Bit 7
Bit 6
Bit 5
Description
Bit 4
SLEW_1_3 /
XO
Bit No
Description
[7:5]
4
Bit 1
Bit 0
OPDRV1MODE
Value Description
Reserved
-
Do Not Modify
SLEW_3_1
0
Nominal Slew Rate
Common control for output driver slew rate for
CLKOUT3 and CLKOUT1
1
Fast Slew Rate
0
CLKOUT3 (CMOS) driven by OUT3L Divider
1
CLKOUT3 (CMOS) driven by buffered XTAL
CLKOUT3MODE.
00
LVPECL mode
CLKOUT3 drive format selection
01
CML mode
10
LVDS mode
11
CMOS mode
CLKOUT1MODE.
00
LVPECL mode
CLKOUT1 drive format selection
01
CML mode
10
LVDS mode
11
CMOS mode
When CLKOUT3 is in CMOS mode, this bit
enables the XTAL input clock to be buffered
and transmitted on the CLKOUT3 pins.
[1:0]
Bit 2
OPDDRV3MODE
Bit Value
XO
[3:2]
Bit 3
(R/W) Driver modes for CLKOUT1 and
CLKOUT3
Revision 1.1
February, 2016 © Semtech Corp.
Page 37
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x02A
Register name
ctrl_op_pullup
Description
(R/W) Output Driver pull up / down modes
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PD4EN
PD2EN
PU4EN
PU2EN
PD3EN
PD1EN
PU3EN
PU1EN
Bit No
7
6
5
4
3
2
1
0
Description
Bit Value
Value Description
PD4EN
0
Disable pull down
Weak Pull Down Enable control for CLKOUT4
1
Enable pull down
PD2EN
0
Disable pull down
Weak Pull Down Enable control for CLKOUT2
1
Enable pull down
PU4EN
0
Disable pull up
Weak Pull up Enable control for CLKOUT4
1
Enable pull up
PD2EN
0
Disable pull up
Weak Pull up Enable control for CLKOUT2
1
Enable pull up
PD3EN
0
Disable pull down
Weak Pull Down Enable control for CLKOUT3
1
Enable pull down
PD1EN
0
Disable pull down
Weak Pull Down Enable control for CLKOUT1
1
Enable pull down
PU3EN
0
Disable pull up
Weak Pull up Enable control for CLKOUT3
1
Enable pull up
PU1EN
0
Disable pull up
Weak Pull up Enable control for CLKOUT1
1
Enable pull up
Revision 1.1
February, 2016 © Semtech Corp.
Page 38
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x02B
Register name
Bit 7
ctrl_xo_double
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) Crystal Oscillator buffer control
register
Bit 2
Bit 1
Bit 0
XO_DBL_EN
Bit No
[7:4]
3
[2:0]
Description
Bit Value
Value Description
Reserved
-
Do Not Modify
XO_DBL_EN
0
Doubler disable
Frequency doubler circuit control. When
enabled increases internal clock frequency
by a factor of 2.
1
Doubler enable
Reserved
-
Do Not Modify
Address (Hex): 0x02C - 0x0DF
Register name
Bit 7
Bit No
[7:0]
Reserved
Bit 6
Bit 5
Description
Bit 4
Description
Bit Value
Reserved
Revision 1.1
February, 2016 © Semtech Corp.
Bit 3
-
Page 39
(R/W) Test Register. Do not Modify
Bit 2
Bit 1
Bit 0
Value Description
Do Not Modify
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x0D8
Slice <s> = A
Register name
Bit 7
apll<s>_dco_clk
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) Frequency Synthesizer Clock Rate
Bit 2
Bit 1
Bit 0
DCO_RATE
Bit No
Description
[7:3]
Reserved
[2:0]
DCO_RATE
Bit Value
-
Frequency Synthesizer Clock rate. Defines
Synthesizer control word update rate.
Recommended rate is Fs/4
000
001
010
011
100
101
110
111
Value Description
Do Not Modify
Do not use
Do not use
Do not use
Update Clock Rate = Fs/4
Update Clock Rate = Fs/5
Update Clock Rate = Fs/6
Update Clock Rate = Fs/7
Update Clock Rate = Fs/8
Address (Hex): 0x0D9 - 0x0DF
Register name
Bit 7
Bit No
Reserved
Bit 6
Bit 5
Description
Bit 4
Description
[7:0]
Bit 3
Bit Value
Reserved
-
(R/W) Test Register. Do not Modify
Bit 2
Bit 1
Bit 0
Value Description
Do Not Modify
Address (Hex): 0x0E0
Slice <s> = A
Register name
Bit 7
apll<s>_enable
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) APLL enable register
Bit 2
Bit 1
Bit 0
APLLEN
Bit No
Description
7
[6:0]
Bit Value
Value Description
APLLEN
0
Disable APLL
Control bit to power up APLL
1
Enable APLL
Reserved
Revision 1.1
February, 2016 © Semtech Corp.
1111111
Page 40
Do not modify
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x0E1 – 0x0E2
Register name
Bit 7
Bit No
[7:0]
Reserved
Bit 6
Bit 5
Description
Bit 4
Description
Bit 3
Bit Value
Reserved
-
(R/W) Test Register. Do not Modify
Bit 2
Bit 1
Bit 0
Value Description
Do Not Modify
Address (Hex): 0x0E3
Slice <s> = A
Register name
Bit 7
apll<s>_odivider
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) High speed APLL O divider
configuration
Bit 2
Bit 1
Bit 0
ODIV_RATIO[1:0]
Bit No
Description
Bit Value
[7:6]
Reserved
-
[5:4]
ODIV_RATIO[1:0]
Defines the High Speed APLL O divider ratio
[3:0]
00
01
10
11
Reserved
-
Value Description
Do Not Modify
Divide by 2
Divide by 3
Divide by 4
Divide by 5
Do Not Modify
Address (Hex): 0x0E4 – 0x117
Register name
Bit 7
Bit No
[7:0]
Reserved
Bit 6
Bit 5
Description
Bit 4
Description
Bit Value
Reserved
Revision 1.1
February, 2016 © Semtech Corp.
Bit 3
-
Page 41
(R/W) Test Register. Do not Modify
Bit 2
Bit 1
Bit 0
Value Description
Do Not Modify
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x118
Slice <s> = B
Register name
Bit 7
apll<s>_dco_clk
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) Frequency Synthesizer Clock Rate
Bit 2
Bit 1
Bit 0
DCO_RATE
Bit No
Description
[7:3]
Reserved
[2:0]
DCO_RATE
Bit Value
-
Frequency Synthesizer Clock rate. Defines
Synthesizer control word update rate.
Recommended rate is Fs/4
000
001
010
011
100
101
110
111
Value Description
Do Not Modify
Do not use
Do not use
Do not use
Update Clock Rate = Fs/4
Update Clock Rate = Fs/5
Update Clock Rate = Fs/6
Update Clock Rate = Fs/7
Update Clock Rate = Fs/8
Address (Hex): 0x119 – 0x11F
Register name
Bit 7
Bit No
[7:0]
Reserved
Bit 6
Bit 5
Description
Bit 4
Description
Bit Value
Reserved
Address (Hex): 0x120
Address (Hex): 0x121
Address (Hex): 0x122
Address (Hex): 0x123
Bit 3
-
apll<B>_enable
reserved
reserved
apll<B>_odivider
(R/W) Test Register. Do not Modify
Bit 2
Bit 1
Bit 0
Value Description
Do Not Modify
Use description for Reg 0x0E0, Slice = B
Use description for Reg 0x0E1, Slice = B
Use description for Reg 0x0E2, Slice = B
Use description for Reg 0x0E3, Slice = B
Address (Hex): 0x124 – 0x1A0
Register name
Bit 7
Bit No
Reserved
Bit 6
Bit 5
Description
Bit 4
Description
Revision 1.1
February, 2016 © Semtech Corp.
Bit 3
Bit Value
Page 42
(R/W) Test Register. Do not Modify
Bit 2
Bit 1
Bit 0
Value Description
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
[7:0]
Reserved
DATASHEET
-
Do Not Modify
Address (Hex): 0x1A1
Slice <s> = A
Register name
Bit 7
Bit No
afb<s>_cnfg
Bit 6
Bit 5
Description
Bit 4
Description
[7:2]
1
0
Bit 3
Bit Value
Reserved
-
CALIBRATE_MODE
Configuration bit to select between automatic
calibration on startup or manual calibration
(R/W) AFB and VCO calibration register
Bit 2
Bit 1
Bit 0
CALIBRATE_
MODE
CALIBRATE
Value Description
Do Not Modify
0
Automatic VCO calibration
1
Manual VCO calibration
0
Normal mode.
1
Invokes manual calibration of VCO on rising
edge.
CALIBRATE
Toggle bit from 0 to 1 to start manual
calibration of VCO. Requires
CALIBRATE_MODE to be set to manual mode.
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DATASHEET
Address (Hex): 0x1A2
Slice <s> = A
Register name
Bit 7
afb<s>_fraction0
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) AFB feedback divider fractional
coefficient
Bit 2
Bit 1
Bit 0
AFB_FRACTION[7:0]
Bit No
[7:0]
Description
Bit Value
AFB_FRACTION[7:0]
Value Description
Use Ratio Calculated by CleanClock GUI or
calculate as defined in Divider Configuration
Section of datasheet.
Bits 7:0 of a 34 bit word defining the
fractional portion of the AFB feedback divider
-
Multi-byte protection requires write to register
afb<s>_integer1 before value is transferred.
Address (Hex): 0x1A3
Slice <s> = A
Register name
Bit 7
afb<s>_fraction1
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) AFB feedback divider fractional
coefficient
Bit 2
Bit 1
Bit 0
AFB_FRACTION[15:8]
Bit No
[7:0]
Description
Bit Value
AFB_FRACTION[15:8]
Value Description
Use Ratio Calculated by CleanClock GUI or
calculate as defined in Divider Configuration
Section of datasheet.
Bits 15:8 of a 34 bit word defining the
fractional portion of the AFB feedback divider
-
Multi-byte protection requires write to register
afb<s>_integer1 before value is transferred.
Address (Hex): 0x1A4
Slice <s> = A
Register name
Bit 7
afb<s>_fraction2
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) AFB feedback divider fractional
coefficient
Bit 2
Bit 1
Bit 0
AFB_FRACTION[23:16]
Bit No
[7:0]
Description
Bit Value
AFB_FRACTION[23:16]
Use Ratio Calculated by CleanClock GUI or
calculate as defined in Divider Configuration
Section of datasheet.
Bits 23:16 of a 34 bit word defining the
fractional portion of the AFB feedback divider
Revision 1.1
February, 2016 © Semtech Corp.
Value Description
Page 44
-
Multi-byte protection requires write to register
afb<s>_integer1 before value is transferred.
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x1A5
Slice <s> = A
Register name
Bit 7
afb<s>_fraction3
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) AFB feedback divider fractional
coefficient
Bit 2
Bit 1
Bit 0
AFB_FRACTION[31:24]
Bit No
[7:0]
Description
Bit Value
AFB_FRACTION[31:24]
Value Description
Use Ratio Calculated by CleanClock GUI or
calculate as defined in Divider Configuration
Section of datasheet.
Bits 31:24 of a 34 bit word defining the
fractional portion of the AFB feedback divider
-
Multi-byte protection requires write to register
afb<s>_integer1 before value is transferred.
Address (Hex): 0x1A6
Slice <s> = A
Register name
Bit 7
afb<s>_fraction4
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) AFB feedback divider fractional
coefficient
Bit 2
Bit 1
Bit 0
AFB_FRACTION[33:32]
Bit No
Description
[7:2]
Reserved
[1:0]
AFB_FRACTION[33:32]
Bit Value
Value Description
Do Not Use
-
Bits 33:32 of a 34 bit word defining the
fractional portion of the AFB feedback divider
Use Ratio Calculated by CleanClock GUI or
calculate as defined in Divider Configuration
Section of datasheet.
Multi-byte protection requires write to register
afb<s>_integer1 before value is transferred.
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DATASHEET
Address (Hex): 0x1A7
Slice <s> = A
Register name
Bit 7
afb<s>_integer0
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) AFB feedback divider integer coefficient
Bit 2
Bit 1
Bit 0
AFB_INTEGER[7:0]
Bit No
[7:0]
Description
Bit Value
AFB_INTEGER[7:0]
Value Description
Use Ratio Calculated by CleanClock GUI or
calculate as defined in Divider Configuration
Section of datasheet.
Bits 7:0 of an 8 bit word defining the integer
portion of the AFB feedback divider
-
Multi-byte protection requires write to register
afb<s>_integer1 before value is transferred.
Address (Hex): 0x1A8
Slice <s> = A
Register name
Bit 7
afb<s>_integer1
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) AFB feedback divider integer coefficient
Bit 2
Bit 1
Bit 0
AFB_INTEGER
[8]
Bit No
[7:1]
0
Description
Bit Value
Reserved
Value Description
Do Not Use
AFB_INTEGER[8]
-
MSB bit of an 8 bit word defining the fractional
portion of the AFB feedback divider.
Use Ratio Calculated by CleanClock GUI
Multi-byte protection requires write to register
afb<s>_integer1 before value is transferred.
AFB register update triggers on write to this bit
Address (Hex): 0x1A9 – 0x1B0
Register name
Bit 7
Bit No
[7:0]
Reserved
Bit 6
Bit 5
Description
Bit 4
Description
Bit Value
Reserved
Revision 1.1
February, 2016 © Semtech Corp.
Bit 3
-
Page 46
(R/W) Test Register. Do not Modify
Bit 2
Bit 1
Bit 0
Value Description
Do Not Modify
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
Address (Hex): 0x1B1
Address (Hex): 0x1B2
Address (Hex): 0x1B3
Address (Hex): 0x1B4
Address (Hex): 0x1B5
Address (Hex): 0x1B6
Address (Hex): 0x1B7
Address (Hex): 0x1B8
afb<B>_cnfg
afb<B>_fraction0
afb<B>_fraction1
afb<B>_fraction2
afb<B>_fraction3
afb<B>_fraction4
afb<B>_integer0
afb<B>_integer1
DATASHEET
Use description for Reg 0x1A1, Slice = B
Use description for Reg 0x1A2, Slice = B
Use description for Reg 0x1A3, Slice = B
Use description for Reg 0x1A4, Slice = B
Use description for Reg 0x1A5, Slice = B
Use description for Reg 0x1A6, Slice = B
Use description for Reg 0x1A7, Slice = B
Use description for Reg 0x1A8, Slice = B
Address (Hex): 0x1BA – 0x400
Register name
Bit 7
Bit No
[7:0]
Reserved
Bit 6
Bit 5
Description
Bit 4
Description
Bit Value
Reserved
Revision 1.1
February, 2016 © Semtech Corp.
Bit 3
-
Page 47
(R/W) Test Register. Do not Modify
Bit 2
Bit 1
Bit 0
Value Description
Do Not Modify
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
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Address (Hex): 0x401
Register name
Bit 7
chip_id
Bit 6
Description
Bit 5
Bit 4
Bit 3
(RO) Chip Revision ID register
Bit 2
Bit 1
Bit 0
CHIP_ID
Bit No
Description
Bit Value
[7:4]
Reserved
0000
[3:0]
CHIP_ID
-
Value Description
Do Not Modify
Die Revision
Address (Hex): 0x402
Register name
Bit 7
Reserved
Bit 6
Bit No
Description
Bit 5
Bit 4
Description
[7:0]
Bit 3
Bit Value
Reserved
-
(R/W) Test Register. Do not Modify
Bit 2
Bit 1
Bit 0
Value Description
Do Not Modify
Address (Hex): 0x403
Register name
Bit 7
irq_mask_rising1
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) Alarm Rising edge interrupt
sensitivity mask
Bit 2
Bit 1
Bit 0
DCOLCK_A_MSK
_R
Bit No
[7:5]
4
[3:0]
Description
Bit Value
Reserved
000
Value Description
Do Not Modify
DCOLCK_A_MSK_R [Rising Edge]
0
Disable or mask Interrupt
SLICE<A> Interrupt mask for APLL lock flag
1
Enable Interrupt
Reserved
Revision 1.1
February, 2016 © Semtech Corp.
0000
Page 48
Do Not Modify
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WIRELESS, SENSING & TIMING PRODUCT GROUP
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Address (Hex): 0x404
Register name
Bit 7
Reserved
Bit 6
Bit No
Description
Bit 5
Bit 4
Description
[7:0]
Bit 3
Bit Value
Reserved
-
(R/W) Test Register. Do not Modify
Bit 2
Bit 1
Bit 0
Value Description
Do Not Modify
Address (Hex): 0x405
Register name
Bit 7
irq_mask_rising3
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) Alarm Rising edge interrupt
sensitivity mask
Bit 2
Bit 1
Bit 0
DCOLCK_B_MSK
_R
Bit No
[7:5]
4
[3:0]
Description
Bit Value
Reserved
000
Value Description
Do Not Modify
DCOLCK_B_MSK_R [Rising Edge]
0
Disable or mask Interrupt
SLICE<B> Interrupt mask for APLL lock flag
1
Enable Interrupt
Reserved
0000
Do Not Modify
Address (Hex): 0x406
Register name
Bit 7
Bit No
[7:0]
Reserved
Bit 6
Bit 5
Description
Bit 4
Description
Bit Value
Reserved
Revision 1.1
February, 2016 © Semtech Corp.
Bit 3
-
Page 49
(R/W) Test Register. Do not Modify
Bit 2
Bit 1
Bit 0
Value Description
Do Not Modify
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
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Address (Hex): 0x407
Register name
Bit 7
irq_mask_falling1
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) Alarm falling edge interrupt
sensitivity mask
Bit 2
Bit 1
Bit 0
DCOLCK_A_MSK
_F
Bit No
Description
[7:5]
Bit Value
Reserved
4
[3:0]
000
Value Description
Do Not Modify
DCOLCK_A_MSK_F [Falling Edge]
0
Disable or mask Interrupt
SLICE<A> Interrupt mask for APLL lock flag
1
Enable Interrupt
Reserved
0000
Do Not Modify
Address (Hex): 0x408
Register name
Bit 7
Reserved
Bit 6
Bit No
Description
Bit 5
Bit 4
Description
[7:0]
Bit 3
Bit Value
Reserved
-
(R/W) Test Register. Do not Modify
Bit 2
Bit 1
Bit 0
Value Description
Do Not Modify
Address (Hex): 0x409
Register name
Bit 7
irq_mask_falling3
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) Alarm falling edge interrupt
sensitivity mask
Bit 2
Bit 1
Bit 0
DCOLCK_B_MSK
_F
Bit No
[7:5]
4
[3:0]
Description
Bit Value
Reserved
000
Value Description
Do Not Modify
DCOLCK_B_MSK_F [Falling Edge]
0
Disable or mask Interrupt
SLICE<B> Interrupt mask for APLL lock flag
1
Enable Interrupt
Reserved
Revision 1.1
February, 2016 © Semtech Corp.
0000
Page 50
Do Not Modify
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x40A
Register name
irq_cn_st_status
Bit 7
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/0) IRQ status
Bit 2
Bit 1
Bit 0
IRQ
Bit No
Description
Bit Value
Value Description
7
Reserved
-
Do Not Modify
6
IRQ
0
No Interrupt
Status of interrupt IRQ signal. Configured by
interrupt mask bits.
1
Interrupt is active
Reserved
-
Do Not Modify
[5:0]
Address (Hex): 0x40B
Register name
Bit 7
Bit No
[7:0]
Reserved
Bit 6
Description
Bit 5
Bit 4
Description
Bit 3
Bit Value
Reserved
-
(R/W) Test Register. Do not Modify
Bit 2
Bit 1
Bit 0
Value Description
Do Not Modify
Address (Hex): 0x40C
Register name
Bit 7
irq_status_rising1
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) Alarm Rising edge interrupt
sensitivity status
Bit 2
Bit 1
Bit 0
DCOLCK_A_IRQ
_R
Bit No
[7:5]
4
[3:0]
Description
Bit Value
Value Description
Reserved
-
Do Not Modify
DCOLCK_A_IRQ_R [Rising Edge]
0
No IRQ Event
SLICE<A> Interrupt status for APLL lock flag
1
IRQ Event has occurred. Clear on write.
Reserved
-
Do Not Modify
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Address (Hex): 0x40D
Register name
Bit 7
Reserved
Bit 6
Bit No
Description
Bit 5
Bit 4
Description
[7:0]
Bit 3
Bit Value
Reserved
-
(R/W) Test Register. Do not Modify
Bit 2
Bit 1
Bit 0
Value Description
Do Not Modify
Address (Hex): 0x40E
Register name
Bit 7
irq_status_rising3
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) Alarm Rising edge interrupt
sensitivity status
Bit 2
Bit 1
Bit 0
DCOLCK_B_IRQ
_R
Bit No
[7:5]
4
[3:0]
Description
Bit Value
Value Description
Reserved
-
Do Not Modify
DCOLCK_B_IRQ_R [Rising Edge]
0
No IRQ Event
SLICE<B> Interrupt mask for APLL lock flag
1
IRQ Event has occurred. Clear on write.
Reserved
-
Do Not Modify
Address (Hex): 0x40F
Register name
Bit 7
Bit No
[7:0]
Reserved
Bit 6
Bit 5
Description
Bit 4
Description
Bit Value
Reserved
Revision 1.1
February, 2016 © Semtech Corp.
Bit 3
-
Page 52
(R/W) Test Register. Do not Modify
Bit 2
Bit 1
Bit 0
Value Description
Do Not Modify
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
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Address (Hex): 0x410
Register name
Bit 7
irq_status_falling1
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) Alarm falling edge interrupt
sensitivity status
Bit 2
Bit 1
Bit 0
DCOLCK_A_IRQ
_F
Bit No
Description
[7:5]
4
[3:0]
Bit Value
Value Description
Reserved
-
Do Not Modify
DCOLCK_A_IRQ_F [Falling Edge]
0
No IRQ Event
SLICE<A> Interrupt status for APLL lock flag
1
IRQ Event has occurred. Clear on write.
Reserved
-
Do Not Modify
Address (Hex): 0x411
Register name
Bit 7
Reserved
Bit 6
Bit No
Description
Bit 5
Bit 4
Description
[7:0]
Bit 3
Bit Value
Reserved
-
(R/W) Test Register. Do not Modify
Bit 2
Bit 1
Bit 0
Value Description
Do Not Modify
Address (Hex): 0x412
Register name
Bit 7
irq_status_falling3
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) Alarm falling edge interrupt
sensitivity status
Bit 2
Bit 1
Bit 0
DCOLCK_B_IRQ
_F
Bit No
[7:5]
4
[3:0]
Description
Bit Value
Value Description
Reserved
-
Do Not Modify
DCOLCK_B_IRQ_F [Falling Edge]
0
No IRQ Event
SLICE<B> Interrupt status for APLL lock flag
1
IRQ Event has occurred. Clear on write.
Reserved
-
Do Not Modify
Revision 1.1
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WIRELESS, SENSING & TIMING PRODUCT GROUP
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Address (Hex): 0x413
Register name
Bit 7
Bit No
[7:0]
Reserved
Bit 6
Description
Bit 5
Bit 4
Description
Bit 3
Bit Value
Reserved
-
(RO) Test Register. Do not Modify
Bit 2
Bit 1
Bit 0
Value Description
Do Not Modify
Address (Hex): 0x414
Register name
Bit 7
irq_status_live1
Bit 6
Bit 5
Description
Bit 4
Bit 3
(RO) Alarm live status
Bit 2
Bit 1
Bit 0
DCOLCK_A_IRQ
Bit No
[7:5]
4
[3:0]
Description
Bit Value
Value Description
Reserved
-
Do Not Modify
DCOLCK_A_IRQ [Live Status]
0
No IRQ Event
SLICE<A> Interrupt status for APLL lock flag
1
IRQ Event is currently active
Reserved
-
Do Not Modify
Address (Hex): 0x415
Register name
Bit 7
Bit No
[7:0]
Reserved
Bit 6
Bit 5
Description
Bit 4
Description
Bit Value
Reserved
Revision 1.1
February, 2016 © Semtech Corp.
Bit 3
-
Page 54
(RO) Test Register. Do not Modify
Bit 2
Bit 1
Bit 0
Value Description
Do Not Modify
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Address (Hex): 0x416
Register name
Bit 7
irq_status_live3
Bit 6
Bit 5
Description
Bit 4
Bit 3
(RO) Alarm live status
Bit 2
Bit 1
Bit 0
DCOLCK_B_IRQ
Bit No
[7:5]
4
[3:0]
Description
Bit Value
Value Description
Reserved
-
Do Not Modify
DCOLCK_B_IRQ [Live Status]
0
No IRQ Event
SLICE<B> Interrupt mask for APLL lock flag
1
IRQ Event is currently active
Reserved
-
Do Not Modify
Address (Hex): 0x417
Register name
Bit 7
ctrl_reset
Bit 6
Bit 5
Description
Bit 4
Bit 3
(R/W) Reset Control Register
Bit 2
Bit 1
Bit 0
HARD_RST
Bit No
[7:1]
0
Description
Bit Value
Value Description
Reserved
-
Do Not Modify
HARD_RST
0
Full Chip Reset
1
Normal Mode
Revision 1.1
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Applications Information
Jitter and Phase Noise
Parameter
Symbol
Min
Typ
Max
PLL performance fXTAL = 30.72 MHz fundamental mode crystal OCXO
PLL pull in range (max
500
fractional offset from nominal)
Spurious noise
NSpur
-40
Clock multiplication jitter generation: CLKOUT1 & 3
Typical conditions: Slice A active. Slice B disabled, CLKOUT 2 & 4 disabled.
fCLKOUT1 = 622.08MHz
JGen, rms
12kHz - 20MHz
0.31
fCLKOUT1 = 155.52MHz
JGen, rms
12kHz - 20MHz
0.32
fCLKOUT1 = 622.08MHz
JGen, rms
0.32
50kHz - 80MHz
fCLKOUT1=669.3265823MHz
JGen, rms
0.11
1.875MHz - 20MHz
fCLKOUT1 = 125MHz
JGen, rms
0.16
637kHz - 10MHz
fCLKOUT1 = 156.25MHz
JGen, rms
0.27
1.875MHz - 20MHz
fCLKOUT1 = 122.88MHz
JGen, rms
0.27
12kHz to 20MHz
Skew (CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4)
Output phase change over
300
500
t_Temp
temperature
Unit
Comments
ppm
dBc
At maximum spur, with fCLKOUT
not an integer or near-integer
multiple of fXTAL. (Note 1).
psrms
OC-48
psrms
OC-48
psrms
OC-192
psrms
OTU-2 FEC
psrms
Gigabit Ethernet
psrms
10G Ethernet
psrms
BTS system clock
ps
-40oC to +85oC.
(Note 1) Spurs measured as power (dBc) using Agilent 5052B. CLKOUT drive is LVPECL differential into balun with 50 ohm single ended load.
Revision 1.1
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Jitter Generation with 30.72MHz XTALA/B Reference Oscillator
Figure 9 : Single Slice FCLKOUT1 = 122.88MHz (LVPECL)
Figure 10 : Dual Slice FCLKOUT1 = 122.88MHz (LVPECL), F CLKOUT2 = 10MHz (CMOS)
Revision 1.1
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Figure 11 : Single Slice FCLKOUT1 = 622.08MHz (LVPECL)
Figure 12 : Dual Slice FCLKOUT1 = 622.08MHz (LVPECL), F CLKOUT2 = 10MHz (CMOS)
Revision 1.1
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
High speed input and output interfaces
The internal configuration of the high speed differential CLKINn input includes weak on-chip termination which sets
the common mode when AC-coupling is used; external dual 50Ω single ended or 100Ω differential termination must
be provided near the chip inputs for proper operation
Figure 13 : High Speed Input Configuration
The ACS1823 CLKOUTn output ports may be internally configured to drive CML, LVDS and LVPECL termination
schemes. Common mode output voltage is determined by the interface mode and selection of VDD. Both the
CLKINn+ and CLKOUTn+ interfaces may also be configured for single ended LVCMOS operation (up to 250MHz), with
the corresponding CLKINn- and CLKOUTn- pins unused.
Figure 14 : LVPECL, LVDS Mode High Speed Output Configurations
Figure 15 : CML Mode High Speed Output Configurations
Revision 1.1
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
The CLKOUTn outputs can be individually disabled (squelched) using the serial control interface. When disabled, the
output drivers are disconnected from VDD and the output dividers and output driver current sources are disabled to
conserve power
Package Outline Drawing
Figure 10 : ACS1823 Package Mechanical Drawing
Revision 1.1
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Recommended PCB Layout
Figure 11 : ACS1823 Recommended PCB Footprint
For optimal thermal performance, a minimum 8-layer PCB with at least 49 thermal vias and 2 plane layers, as per
JEDEC specifications JESD51-5 and JESD51-7 should be used. With such a PCB, and the recommended PCB land
pattern, the following thermal resistances can be achieved:
Θjc
Θja ( 0 m/s airflow)
Θja ( 1 m/s airflow)
Θja ( 2 m/s airflow)
Revision 1.1
February, 2016 © Semtech Corp.
– 9.0 °C/W
– 15.4 °C/W
– 12.1 °C/W
– 10.7 °C/W
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Revision History
The Revision Status, as shown in top right corner of the datasheet, may be TARGET, PRELIMINARY, or FINAL, and
refers to the status of the Device (not the datasheet), with the design cycle. TARGET status is used when the design
is being realized but is not yet physically available, and the datasheet content reflects the intention of the design.
The datasheet is raised to PRELIMINARY status when initial prototype devices are physically available, and the
datasheet content more accurately represents the realization of the design. The datasheet is only raised to FINAL
status after the device has been fully characterized, and the datasheet content updated with measured, rather than
simulated parameter values.
Revision
Number
Date
Revision Description
1.0
February 2016
1.1
February 2016
Added Current Consumption values derived from Production Test limits and
updated synthesizer modes in register map.
FINAL DATASHEET - Formal Release.
Part number updated to production release
Revision 1.1
February, 2016 © Semtech Corp.
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ACS1823
WIRELESS, SENSING & TIMING PRODUCT GROUP
DATASHEET
Disclaimers
Life support- This product is not designed or intended for use in life support equipment, devices or systems, or other critical
applications. This product is not authorized or warranted by Semtech for such use.
Right to change- Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are
advised to obtain the latest version of the relevant information before placing orders.
Compliance to relevant standards- Operation of this device is subject to the User's implementation, and design practices. It is
the responsibility of the user to ensure equipment using this device is compliant to any relevant standards.
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
Contacts
For Additional Information, contact the following:
Semtech Corporation Advanced Communications Product Group
E-mail:
[email protected]
[email protected]
Internet:
http://www.semtech.com
USA:
Mailing Address: P.O. Box 6097, Camarillo, CA 93011-6097
Street Address: 200 Flynn Road, Camarillo, CA 93012-8790
Tel: +1 805 498 2111, Fax: +1 805 498 3804
FAR EAST:
11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, R.O.C.
Tel: +886 2 2748 3380 Fax: +886 2 2748 3390
EUROPE:
Semtech Ltd., Units 2 and 3, Park Court, Premier Way,
Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN
Tel: +44 (0)1794 527 600 Fax: +44 (0)1794 527 601
ISO9001
CERTIFIED
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