LT8582 - Dual 3A Boost/Inverting/SEPIC DC/DC Converter with Fault Protection

LT8582
Dual 3A Boost/Inverting/SEPIC
DC/DC Converter with
Fault Protection
DESCRIPTION
FEATURES
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Dual 42V, 3A Combined Power Switch
Master/Slave (1.7A/1.3A) Switch Design
Wide Input Range: 2.5V to 22V Operating, 40V
Maximum Transient
Power Good Pin for Event Based Sequencing
Switching Frequency Up to 2.5MHz
Each Channel Easily Configurable as a Boost, SEPIC,
Inverting or Flyback Converter
Low VCESAT Switch: 270mV at 2.75A (Typical)
Can be Synchronized to an External Clock
Output Short-Circuit Protection
High Gain SHDN Pin Accepts Slowly Varying Input
Signals
24-Pin 7mm × 4mm DFN Package
The LT®8582 is a dual independent channel PWM DC/DC
converter with a power good pin and built-in fault protection
to help guard against input overvoltage and overtemperature conditions. Each channel consists of a 42V master
switch and a 42V slave switch that can be tied together
for a total current limit of 3A.
The LT8582 is ideal for many local power supply designs.
Each channel can be easily configured in boost, SEPIC,
inverting, or flyback configurations. Together, the two channels can produce a 12V and a –12V output with 14.4W of
combined output power from a 5V input. In addition, the
LT8582’s slave switch allows the part to be configured in
high voltage, high power charge pump topologies that
are more efficient and require fewer components than
traditional circuits.
APPLICATIONS
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The LT8582 also features innovative SHDN pin circuitry that
allows for slowly varying input signals and an adjustable
undervoltage lockout function. Additional features such as
output short protection, frequency foldback and soft-start
are integrated. The LT8582 is available in a 24-pin 7mm
× 4mm DFN package.
Local Power Supply
Vacuum Fluorescent Display (VFD) Bias Supplies
TFT-LCD Bias Supplies
Automotive Engine Control Unit (ECU) Power
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patents including 7579816.
TYPICAL APPLICATION
Efficiency and Power Loss
(Load Between 12V and –12V Outputs)
1.5MHz, 5V to ±12V
4.7μH
4.7μF
SWA1
VIN1
215k
SWB1
SHDN1
PG1
VC1
10μF
SS1
SYNC1
6.49k
RT1
CLKOUT1
90
2.8
80
2.4
70
2.0
60
1.6
FBX1
GATE1
LT8582
3.2
100
6.04k
130k
CLKOUT2
53.6k
0.1μF
4.7nF
47pF
53.6k
0.1μF
2.2nF
47pF
50
1.2
40
0.8
POWER LOSS (W)
100k
VOUT1
12V
550mA
10μF
EFFICIENCY (%)
VIN
5V
GND
SYNC2
100k
215k
PG2
RT2
SHDN2
SS2
VIN2
0.4
30
20
0
14.7k
VC2
0.1
0.4
0.3
0.2
LOAD CURRENT (A)
0.5
0
0.6
8582 TA01b
10μF
GATE2
143k
SWA2
4.7μF
FBX2
2.2μF
4.7μH
s
s
4.7μH
SWB2
8582 TA01a
VOUT2
–12V
550mA
8582f
1
LT8582
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
VIN1 Voltage ............................................... –0.3V to 40V
SWA1/SWB1 Voltage.................................. –0.4V to 42V
RT1 Voltage ................................................. –0.3V to 5V
SS1 Voltage .............................................. –0.3V to 2.5V
FBX1 Voltage................................................ –0.3V to 5V
VC1 Voltage .................................................. –0.3V to 2V
SHDN1 Voltage .........................................................40V
SHDN1 Current ......................................................–1mA
SYNC1 Voltage.......................................... –0.3V to 5.5V
GATE1 Voltage ........................................... –0.3V to 60V
PG1 Voltage ............................................... –0.3V to 40V
PG1 Current ........................................................±0.5mA
CLKOUT1 ........................................................... (Note 5)
Operating Junction Temperature Range
LT8582E ............................................ –40°C to 125°C
LT8582I ............................................. –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
TOP VIEW
SWA1
VIN1
PG1
GATE1
VC1
FBX1
FBX2
VC2
GATE2
PG2
VIN2
SWA2
1
2
3
4
5
6
7
8
9
10
11
12
25
GND
24
23
22
21
20
19
18
17
16
15
14
13
SWB1
CLKOUT1
SHDN1
RT1
SS1
SYNC1
SYNC2
SS2
RT2
SHDN2
CLKOUT2
SWB2
DKD PACKAGE
24-LEAD (7mm × 4mm) PLASTIC DFN
TJMAX = 125°C, θJA = 34°C/W, θJC = 7°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
Note: Absolute maximum ratings are shown for channel 1 only. Channel 2
ratings are identical.
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8582EDKD#PBF
LT8582EDKD#TRPBF
8582
24-Pin (7mm × 4mm) Plastic DFN
–40°C to 125°C
LT8582IDKD#PBF
LT8582IDKD#TRPBF
8582
24-Pin (7mm × 4mm) Plastic DFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
8582f
2
LT8582
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN, unless otherwise noted (Note 2). Specifications
are identical for both channels unless noted otherwise.
PARAMETER
CONDITIONS
MIN
l
Minimum Input Voltage VIN
VIN Overvoltage Lockout
TYP
MAX
UNITS
2.3
2.5
V
22.2
24.5
27
V
Positive Feedback Voltage
l
1.185
1.204
1.220
V
Negative Feedback Voltage
l
2
7
16
mV
Positive FBX Pin Bias Current
VFBX = Positive Feedback Voltage, Current into Pin
l
81
83.3
85
μA
Negative FBX Pin Bias Current
VFBX = Negative Feedback Voltage, Current out of Pin
l
81
83.3
85.5
μA
Error Amp Transconductance
ΔI = 10μA
Error Amp Voltage Gain
Quiescent Current
VSHDN = 2.5V, Not Switching
Quiescent Current in Shutdown
VSHDN = 0
Reference Line Regulation
2.5V ≤ VIN ≤ 20V
l
l
2.125
170
l
200
SYNC High Level for Sync
l
1.3
SYNC Low Level for Sync
l
Switching Frequency, fOSC
RT = 31.6kΩ
RT = 407kΩ
Switching Frequency in Foldback
Compared to Normal fOSC
Switching Frequency Range
Free-Running or Synchronizing
SYNC Clock Pulse Duty Cycle
280
μmhos
80
V/V
2.1
2.5
mA
0
1
μA
0.01
0.05
%/V
2.5
200
2.875
230
MHz
kHz
1/6
VSYNC = 0V to 2V
ratio
2500
kHz
V
20
0.4
V
80
%
Recommended Min SYNC Ratio fSYNC/fOSC
3/4
ratio
Minimum Off-Time
45
ns
Minimum On-Time
55
ns
SWA Current Limit
Minimum Duty Cycle
Maximum Duty Cycle
l
l
1.8
1.3
2.4
1.8
3
2.5
A
A
SWA FAULT Current Limit
Minimum Duty Cycle
Maximum Duty Cycle
l
l
2.2
1.6
2.8
2.3
3.5
3.0
A
A
SW Current Sharing, ISWB/ISWA
SWA and SWB Tied Together
SWA + SWB Current Limit
Minimum Duty Cycle, ISWB/ISWA = 0.79
Maximum Duty Cycle, ISWB/ISWA = 0.79
l
l
3.3
2.3
4.3
4.1
5.4
4.5
A
A
SWA + SWB FAULT Current Limit
Minimum Duty Cycle, ISWB/ISWA = 0.79
Maximum Duty Cycle, ISWB/ISWA = 0.79
l
l
4
2.8
5
4
6.3
5.4
A
A
Switch VCESAT
ISWA + ISWB = 2.75A
270
SWA Leakage Current
VSWA = 5V, VSHDN = 0
0.01
1
μA
SWB Leakage Current
VSWB = 5V, VSHDN = 0
0.01
1
μA
SS Charge Current
VSS = 30mV, Current Flows out of SS Pin
l
8.8
11.7
μA
SS Discharge Current
Part in FAULT, VSS = 2.1V, Current Flows into SS Pin
l
5.7
8.8
11.7
μA
SS High Detection Voltage
Part in FAULT
l
1.65
1.84
2
V
SS Low Detection Voltage
Part Exiting FAULT
l
15
55
100
mV
SHDN Minimum Input Voltage High
Active Mode, SHDN Rising
Active Mode, SHDN Falling
l
l
1.26
1.21
1.31
1.27
1.4
1.35
V
V
SHDN Input Voltage Low
Shutdown Mode
l
0.3
V
0.79
5.7
A/A
mV
8582f
3
LT8582
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN, unless otherwise noted (Note 2). Specifications
are identical for both channels unless noted otherwise.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SHDN Pin Bias Current
VSHDN = 3V
VSHDN = 1.3V
VSHDN = 0V
10.1
45
12.1
0
65
14.1
0.1
μA
μA
μA
CLKOUT Output Voltage High
1mA out of CLKOUT Pin
1.9
2.1
2.3
V
CLKOUT Output Voltage Low
1mA into CLKOUT Pin
30
200
mV
50
%
22.5
42
72
%
%
%
CCLKOUT = 120pF
25
ns
CLKOUT Fall Time
CCLKOUT = 120pF
15
ns
GATE Pull-Down Current
VGATE = 3V
VGATE = 20V
GATE Leakage Current
VGATE = 50V, GATE Off
PG Threshold for Positive Feedback Voltage
VFBX Rising
CLKOUT1 Duty Cycle
All TJ
CLKOUT2 Duty Cycle
TJ = –40°C
TJ = 25°C
TJ = 125°C
CLKOUT Rise Time
l
l
PG Threshold for Negative Feedback Voltage VFBX Falling
PG Hysteresis for Feedback Voltage
0.8
0.8
1
1
1.2
1.2
mA
mA
0.01
1
μA
1.09
1.15
1.20
V
20
65
120
mV
4
PG Output Voltage Low
100μA into PG Pin, VFBX = 1V
PG Leakage Current
VPG = 40V, VFBX = 1.204V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8582E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the
–40°C to 125°C operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8582I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
l
mV
70
150
mV
0.01
1
μA
Note 3: Current limit guaranteed by design and/or correlation to static test.
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation over the specified maximum operating junction
temperature may impair device reliability.
Note 5: Do not apply a positive or negative voltage or current source to
CLKOUT, otherwise permanent damage may occur.
8582f
4
LT8582
TYPICAL PERFORMANCE CHARACTERISTICS
Switch Current Limit vs Duty
Cycle
TA = 25°C, unless otherwise noted.
Switch Current Sharing
Switch Saturation Voltage
350
5
1.0
VSW1 = VSW2
0.9
3
2
1
0.8
250
0.7
ISWB/ISWA (A/A)
4
SATURATION VOLTAGE (mV)
SWA + SWB CURRENT (A)
300
200
150
20
30
40 50 60 70
DUTY CYCLE (%)
80
0.1
0
90
0.5
0
2.5
1.5
1
2
SWA + SWB CURRENT (A)
0
Commanded Current Limit vs
SS Voltage
4
80
0
–50 –25
0
CLKOUT DUTY CYCLE (%)
4
SWA + SWB CURRENT (A)
100
1
3
2
0.2
0.8
0.4
0.6
SS VOLTAGE (V)
1
RT = 402k
0
25 50 75 100 125 150
TEMPERATURE (°C)
8582 G07
0
–50 –25
1.2
0
25 50 75 100 125 150
TEMPERATURE (°C)
8582 G05
8582 G06
Switching Frequency During
Soft-Start
Gate Pin Current (VSS = 2.1V)
1100
1
1000
900
GATE PIN CURRENT (μA)
RT = 31.6k
40
20
0
NORMALIZED OSCILLATOR FREQUENCY (fSW/fNOM)
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
–50 –25
CHANNEL 1
1
8582 G04
Oscillator Frequency
CHANNEL 2
60
0
25 50 75 100 125 150
TEMPERATURE (°C)
3.5
CLKOUT Duty Cycle
5
2
3
8582 G03
5
3
2.5
1.5
2
1
SWA CURRENT (A)
0.5
8582 G02
Switch Current Limit at Minimum
Duty Cycle
SWA + SWB CURRENT (A)
3.5
3
8582 G01
FREQUENCY (MHz)
0.4
0.2
0
10
0.5
0.3
100
50
0
0.6
1/2
1/3
1/4
1/5
800
700
600
500
400
300
200
INVERTING
NONINVERTING
CONFIGURATIONS CONFIGURATIONS
0
0.2
0.6
0.8
0.4
FBX VOLTAGE (V)
1
TA = –40°C
TA = 25°C
TA = 125°C
100
0
1.2
8582 G08
0
10
30
40
20
GATE PIN VOLTAGE (V)
50
60
8582 G09
8582f
5
LT8582
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Positive Feedback Voltage
Gate Pin Current (VGATE = 5V)
1000
Active/Lockout Threshold
1.220
1.40
1.38
900
1.215
600
500
400
300
200
1.36
SHDN VOLTAGE (V)
700
FBX VOLTAGE (V)
GATE PIN CURRENT (μA)
800
1.210
1.205
1.200
1.30
1.28
SHDN FALLING
1.26
1.22
0
0
0.25
0.75
1
0.5
SS VOLTAGE (V)
1.25
1.5
1.190
–50 –25
0
1.20
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
8582 G10
SHDN Pin Current
SHDN Pin Current
TA = –40°C
TA = 25°C
TA = 125°C
Internal UVLO
2.50
TA = –40°C
TA = 25°C
TA = 125°C
15
10
5
2.45
2.40
200
VIN VOLTAGE (V)
SHDN PIN CURRENT (μA)
250
20
150
100
0
2.30
2.25
2.15
0
0.25 0.50 0.75 1 1.25 1.50 1.75
SHDN VOLTAGE (V)
2.35
2.20
50
0
25 50 75 100 125 150
TEMPERATURE (°C)
8582 G12
300
25
0
8582 G11
30
SHDN PIN CURRENT (μA)
SHDN RISING
1.32
1.24
1.195
100
0
2
5
10
15 20 25 30
SHDN VOLTAGE (V)
8582 G13
35
2.10
–50 –25
40
0
25 50 75 100 125 150
TEMPERATURE (°C)
8582 G14
CLKOUT Rise and Fall Times at
1MHz
8582 G15
VIN Overvoltage Lockout
PG Threshold
1.50
28
40
27
35
1.25
26
RISE TIME
25
20
15
FALL TIME
10
25
FBX VOLTAGE (V)
30
VIN VOLTAGE (V)
CLKOUT TRANSITION TIME (ns)
1.34
24
23
22
21
20
5
1.00
0.75
0.50
0.25
19
0
0
25
50
75
100
125
CLKOUT CAPACITIVE LOAD (pF)
150
8582 G16
18
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8582 G17
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8582 G18
8582f
6
LT8582
PIN FUNCTIONS
(CH1/CH2)
FBX1, FBX2 (Pin 6/Pin 7): Positive and Negative Feedback
Pins. For an inverting or noninverting output converter,
tie a resistor from the FBX pin to VOUT according to the
following equations:
⎛V
– 1.204V ⎞
R FBX = ⎜ OUT
⎟⎠ ; Noninverting
⎝
83.3μA
Converter
|| +7mV ⎞
⎛|| V
R FBX = ⎜ OUT
; Inverting Converter
⎝ 83.3μA ⎟⎠
VC1, VC2 (Pin 5/Pin 8): Error Amplifier Output Pins. Tie
external compensation network to these pins.
GATE1, GATE2 (Pin 4/Pin 9): PMOS Gate Drive Pins. The
GATE pin is a pull-down current source and can be used
to drive the gate of an external PMOS transistor for output
short-circuit protection or output disconnect. The GATE
pin current increases linearly with the SS pin voltage,
with a maximum pull-down current of 1mA at SS voltages
exceeding 550mV. Note that if the SS voltage is greater
than 550mV and the GATE pin voltage is less than 2V, the
GATE pin looks like a 2kΩ impedance to ground. See the
Appendix for more information.
PG1, PG2 (Pin 3/Pin 10): Power Good Indication Pins.
This active high pin indicates that the FBX pin voltage for
the corresponding channel is within 4% of its regulation
voltage (VFBX > 1.15V for noninverting outputs or VFBX <
65mV for inverting outputs). For most applications, a 4%
change in VFBX corresponds to an 8% change in VOUT. This
open drain output requires a pull-up resistor to indicate
power good. Also, the status is valid only when SHDN >
1.31V and VIN > 2.3V.
VIN1, VIN2 (Pin 2/Pin 11): Input Supply Pins. Must be
locally bypassed.
SWA1, SWA2 (Pin 1/Pin 12): Master Switch Pins. This is
the collector of the internal master NPN power switch for
each channel. SWA is designed to handle a peak collector
current of 1.7A (minimum). Minimize the metal trace area
connected to this pin to minimize EMI.
SWB1, SWB2 (Pin 24/Pin 13): Slave Switch Pins. This is
the collector of the internal slave NPN power switch for
each channel. SWB is designed to handle a peak collector
current of 1.3A (minimum). Minimize the metal trace area
connected to this pin to minimize EMI.
CLKOUT1, CLKOUT2 (Pin 23/Pin 14): Clock Output Pins.
Use these pins to synchronize one or more other ICs to
either channel of the LT8582. Can also be used to synchronize channel 1 or channel 2 of the LT8582 with the
other channel of the LT8582. This pin oscillates at the same
frequency as the internal oscillator of the part or, if active,
the SYNC pin. The CLKOUT pin signal on CH1 is 180° out
of phase with the internal oscillator or SYNC pin and the
duty cycle is fixed at ~50%. The CLKOUT pin signal on
CH2 is in phase with the internal oscillator or SYNC pin
and the duty cycle varies linearly with the part’s junction
temperature. Note that CLKOUT of either channel is only
meant to drive capacitive loads up to 120pF.
SHDN1, SHDN2 (Pin 22/Pin 15): Shutdown Pins. In
conjunction with the UVLO (undervoltage lockout) circuit,
these pins are used to enable/disable the channel and
restart the soft-start sequence. Drive below 0.3V to disable the channel with very low quiescent current. Drive
above 1.31V (typical) to activate the channel and restart
the soft-start sequence. Do not float these pins.
RT1, RT2 (Pin 21/Pin 16): Timing Resistor Pins. Adjusts the
switching frequency of the corresponding channel. Place
a resistor from these pins to ground to set the frequency
to a fixed free running level. Do not float these pins.
SS1, SS2 (Pin 20/Pin 17): Soft-Start Pins. Place a softstart capacitor here. Upon start-up, the SS pins will be
charged by a (nominally) 250k resistor to ~2.1V. During
a fault, the SS pin for the corresponding channel will be
slowly charged up and discharged as part of a timeout
sequence (see the State Diagram for more information).
SYNC1, SYNC2 (Pin 19/Pin 18): Use to synchronize the
switching frequency of a channel to an outside clock. The
high voltage level of the clock must exceed 1.3V and the
low level must be less than 0.4V. Drive these pins to less
than 0.4V to revert to the internal free running clock for the
corresponding channel. See the Applications Information
section for more information.
GND (Exposed Pad Pin 25): Ground. Exposed pad must
be soldered directly to local ground plane.
8582f
7
LT8582
BLOCK DIAGRAM
RFBX
FBX1
OPTIONAL
D1
L1
M1
VIN
CIN
COUT1
RPG
GATE1
VOUT
COUT2
RGATE
PG1
1mA
SOFT-START
VC1
2.1V
+
START-UP
AND FAULT
LOGIC
–
+
1.84V
250k
–
CSS
VIN1
+
–
22.2V
(MIN)
–
+
–
–
UVLO
+
+
DRIVER
SR1
R
A3
S
Q2
SWA1
28mΩ
Q1
Q
+
A1
14.5k
RS
22mΩ
A4
–
FBX1
SWB1
7#&t
+
COMPARATOR
1.204V
REFERENCE
65mV
TD ~ 30ns
–
–
1.31V
1.15V
FBX1
+
50k
VIN1
+
2A
(MIN)
ISWA1
SHDN1
165°C
+
DRIVER
DISABLE
SS1
DIE TEMP
–
–
55mV
+
–
RAMP
GENERATOR
GND
+
14.5k
FREQUENCY ÷N
FOLDBACK
A2
ADJUSTABLE
OSCILLATOR
SS1
–
SYNC
BLOCK
VC1
SYNC1
RT1
CLKOUT**
RC
RT
CC
8582 BD
**BLOCK DIAGRAM FOR CH1 IS SHOWN. BLOCK DIAGRAM FOR CH2 IS IDENTICAL, EXCEPT CLKOUT SIGNAL FOR CH1 IS 180° OUT OF PHASE
WITH THE INTERNAL OSCILLATOR AND HAS A FIXED 50% DUTY CYCLE AND CLKOUT SIGNAL FOR CH2 IS IN PHASE WITH THE INTERNAL OSCILLATOR
AND ITS DUTY CYCLE VARIES LINEARLY WITH THE PART’S JUNCTION TEMPERATURE.
Figure 1. Block Diagram
8582f
8
LT8582
STATE DIAGRAM
SHDN17
03
7*/7
CHIP OFF
t"--48*5$)&4%*4"#-&%
t*("5&0''
t'"6-5T$-&"3&%
SHDN17
"/%
7*/7
INITIALIZE
t441*/16--&%-08
'"6-5
441*/N7
FAULT DETECTED
SOFT-START
t*("5&&/"#-&%
t441*/$)"3(&461
t48*5$)&3&/"#-&%
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8582 SD
Figure 2. State Diagram
8582f
9
LT8582
OPERATION
OPERATION – OVERVIEW
The LT8582 uses a constant frequency, current mode control
scheme to provide excellent line and load regulation. Each
channel’s undervoltage lockout (UVLO) function, together
with soft-start and frequency foldback, offer a controlled
means of starting up. Fault features are incorporated into
each channel of the LT8582 to facilitate the detection of
output shorts, overvoltage and overtemperature conditions. Please refer to the Block Diagram (Figure 1) and
the State Diagram (Figure 2) for the following description
of the part’s operation.
OPERATION – START-UP
VIN
VIN
1.31V
–
RUVLO1
ACTIVE/
LOCKOUT
+
SHDN
12.3μA
AT 1.31V
RUVLO2
(OPTIONAL)
GND
8582 F03
Figure 3. Configurable UVLO
Internal Undervoltage Lockout (UVLO)
Several functions are provided to enable a very clean
start-up of both channels of the LT8582.
Regardless of where external circuitry sets VINUVLO, the
LT8582 also has internal UVLO circuitry that disables the
chip when VIN < 2.3V (typical).
Precise Turn-On Voltage
Soft-Start of Switch Current
The SHDN pin on each channel is compared to an internal
voltage reference to give a precise turn on voltage level. Taking each SHDN pin above 1.31V enables the corresponding
channel. Taking each SHDN pin below 300mV shuts down
the channel, resulting in extremely low quiescent current
for that channel. The SHDN pin has 35mV of hysteresis
to protect against glitches and slow ramping.
Configurable Undervoltage Lockout (UVLO)
The SHDN pin can also be used to create a configurable
UVLO for each channel. This function sets the turn on/
off of each of LT8582’s channels at a desired voltage
(VINUVLO). Figure 3 shows how a resistor divider (or a
single resistor) from VIN to the SHDN pin can be used to
program VINUVLO. RUVLO2 is optional. If left out, set it to
infinite in the equation below. For increased accuracy, set
RUVLO2 ≤ 10k. Pick RUVLO1 as follows:
R UVLO1 =
VIN UVLO – 1.31V
⎛ 1.31V ⎞
⎜⎝
⎟ + 12.3μA
R UVLO2 ⎠
The soft-start circuitry provides for a gradual ramp-up of
the switch current in each channel (refer to Commanded
Current Limit vs SS Voltage in Typical Performance
Characteristics). When the channel is taken out of shutdown, the external SS capacitor is first discharged. This
resets the state of the logic circuits in the channel. Then
an integrated 250k resistor pulls the channel’s SS pin to
~1.84V. The ramp rate of the SS pin voltage is set by this
250k resistor and the external capacitor connected to this
pin. Once SS gets to ~1.84V, the CLKOUT pin is enabled
and an internal regulator pulls the pin up quickly to ~2.1V.
Typical values for the external soft-start capacitor range
from 100nF to 1μF.
Soft-Start of External PMOS (if used)
The soft-start circuitry also gradually ramps up the GATE
pin pull-down current for the corresponding channel. This
allows an external PMOS to slowly turn on (M1 in Block
Diagram). The GATE pin current increases linearly with
SS voltage, with a maximum current of 1mA when the
SS voltage gets above 550mV. Note that if the GATE pin
voltage is less than 2V for SS voltages exceeding 550mV,
then the GATE pin impedance to ground is 2kΩ. The soft
turn on of the external PMOS helps limit inrush current at
start up, making hot plugs of LT8582s feasible.
8582f
10
LT8582
OPERATION
Sample Mode
Sample mode is the mechanism used by the LT8582 to
aid in the detection of output shorts. It refers to a state of
the LT8582 where the master and slave power switches
(Q1 and Q2) are turned on for a minimum period of time
every clock cycle (or every few clock cycles in frequency
foldback) in order to sample the inductor current. If the
sampled current through Q1 exceeds the master switch
fault current limit of 2A (minimum), the LT8582 triggers
an overcurrent fault internally for that channel (see Operation – Fault section for details). Sample mode exists
when FBX for that channel is out of regulation by more
than 4% (65mV < FBX < 1.15V). During this mode, PG
will be pulled low.
Frequency Foldback
The frequency foldback circuit reduces the switching
frequency for that channel when 144mV < FBX < 1.03V
(typical). This feature lowers the minimum duty cycle that
the channel can achieve, thus allowing better control of
the inductor current during start-up. When the FBX voltage is pulled outside of the above mentioned range, the
switching frequency for that channel returns to normal.
collector current through the master switch, Q1, is ~1.3
times the collector current through the slave switch, Q2,
when the collectors of the two switches are tied together.
Q1’s emitter current flows through a current sense resistor (RS) generating a voltage proportional to the switch
current. This voltage (amplified by A4) is added to a stabilizing ramp and the resulting sum is fed into the positive
terminal of the PWM comparator A3. When the voltage on
the positive input of A3 exceeds the voltage on the negative input, the SR latch is reset, turning off the master and
slave power switches. The voltage on the negative input
of A3 (VC pin) is set by A1 (or A2), which is simply an
amplified difference between the FBX pin voltage and the
reference voltage (1.204V if the LT8582 is configured as a
noninverting converter, or 7mV if configured as an inverting converter). In this manner, the error amplifier sets the
correct peak current level to maintain output regulation.
Note that the peak inductor current at start-up is a function
of many variables including load profile, output capacitance,
target VOUT, VIN, switching frequency, etc.
As long as the channel is not in fault and the SS pin exceeds 1.84V, the LT8582 drives the CLKOUT pin for that
channel at the frequency set by the RT pin or the SYNC
pin. The CLKOUT pin can synchronize other ICs, including
additional LT8582s or the other channel of an LT8582, up
to 120pF load on CLKOUT. For channel 1, CLKOUT1 has a
fixed duty cycle and is 180° out of phase with the internal
clock. For channel 2, CLKOUT2’s duty cycle varies linearly
with channel 2’s junction temperature and may be used
as a temperature monitor.
OPERATION – REGULATION
OPERATION – FAULT
The following description of the LT8582’s operation assumes that the FBX voltage is close enough to its regulation
target so that the part is not in sample mode. Also, this
description applies equally to both channels independently
of each other. Use the Block Diagram as a reference when
stepping through the following description of the LT8582
operating in regulation.
Each of the following events can trigger a fault in the LT8582:
At the start of each oscillator cycle, the SR latch (SR1) is
set, which turns on the power switches Q1 and Q2. The
1. SW Overcurrent:
a. ISWA > 2A (minimum)
b. (ISWA + ISWB) > 3.5A (minimum)
2. VIN Voltage > 22.2V (minimum)
3. Die Temperature > 165°C
8582f
11
LT8582
OPERATION
Refer to the State Diagram (Figure 2) for the following
description of the LT8582’s operation during a fault
event. When a fault is detected on a channel, the LT8582
disables the CLKOUT pin for that channel, turns off the
power switches for that channel and the GATE pin for that
channel becomes high impedance. The external PMOS,
M1, is turned off by the external RGATE resistor (see
Block Diagram). With the external PMOS turned off, the
power path from VIN to VOUT is opened, protecting
power path components. Also, as soon as the feedback
voltage falls inside the range 65mV < FBX < 1.15V, PG
pulls low. Refer to Figure 4 for the case of an output short.
At the beginning of a fault event, a timeout sequence commences where the SS pin for that channel is charged up to
1.84V (the SS pin will continue charging up to ~2.1V and
be held there in the case of a FAULT event that still exists)
and then discharged to 55mV. This timeout period relieves
the chip, the PMOS and other power path components
from electrical and thermal stress for a minimum amount
of time set by the voltage ramp rate on the SS pin.
OPERATION – CURRENT LIMIT
The current limit operates independently of the FAULT
current limit. The current limit sets a maximum switch
current. This switch current limit is duty cycle dependent,
but for most applications will be around 3A minimum (see
the Electrical Characteristics). Once this limit is reached,
the switch duty cycle decreases, reducing the magnitude
of the output voltage. If, despite the reduced duty cycle
the switch current reaches the FAULT current limit, the part
will behave as described in the Operation – Fault section.
CLKOUT
5V/DIV
VOUT1
5V/DIV
GATE
5V/DIV
IL1
5A/DIV
20μs/DIV
8582 F04
Figure 4. Output Short-Circuit Protection of the LT8582
8582f
12
LT8582
APPLICATIONS INFORMATION
Boost Converter Component Selection
D1
30V, 2A
L1
4.7μH
VIN
5V
PARAMETERS/EQUATIONS
OPTIONAL
VOUT
12V
0.8A
M1
COUT1
10μF
SWA
Table 1. Boost Converter Design Equations
6.04k
100k
CIN
4.7μF
RT
53.6k
SWB
Step 2: DC
DC ≅
Step 3: L1
FBX
LT8582
GATE
SHDN CHx
PG
CLKOUT
RT
VC
SYNC GND
Choose VIN, VOUT and fOSC to calculate equations
below.
RFBX
130k
VIN
215k
Step 1: Inputs
SS
COUT2
10μF
47pF
0.1μF
VOUT – VIN + 0.5V
VOUT + 0.5V – 0.3V
L TYP =
(VIN – 0.3) • DC
fOSC • 1A
L MIN =
(VIN – 0.3V) • (2 • DC – 1)
1.7A • fOSC • (1– DC)
(2)
LMAX =
(VIN – 0.3V) • DC
fOSC • 0.18A
(3)
6.49k
4.7nF
8582 F05
Figure 5. Boost Converter – The Component Values Given
Are Typical Values for a 1.5MHz, 5V to 12V Boost
Each channel of the LT8582 can be configured as a boost
converter as in Figure 5. This topology allows for positive
output voltages that are higher than the input voltage. An
external PMOS (optional) driven by the GATE pin of the
LT8582 can achieve input or output disconnect during a
FAULT event, SHDN < 1.31V, or VIN < 2.3V. Figure 5 shows
the configuration for output disconnect. A single feedback
resistor sets the output voltage. For output voltages higher
than 40V, see the Charge Pump Topology in the Charge
Pump Aided Regulators section.
Table 1 is a step-by-step set of equations to calculate
component values for the LT8582 when operating as a
boost converter. Input parameters are input and output
voltage and switching frequency (VIN, VOUT and fOSC respectively). Refer to the Appendix for further information
on the design equations presented in Table 1.
Variable Definitions:
= Input Voltage
VIN
VOUT = Output Voltage
DC
= Power Switch Duty Cycle
= Switching Frequency
fOSC
= Maximum Output Current
IOUT
IRIPPLE = Inductor Ripple Current
RDSON_PMOS = RDSON of External Output PMOS (set to 0
if not using PMOS)
(1)
• Solve equations 1, 2 and 3 for a range of L
values
• The minimum of the L value range is the
higher of LTYP and LMIN
• The maximum of the L value range is LMAX
Step 4: IRIPPLE
I RIPPLE =
Step 5: IOUT
⎛
⎝
IOUT = ⎜ 3A –
Step 6: D1
Step 7: COUT
IRIPPLE ⎞
• (1– DC)
2 ⎟⎠
VR ≥ VOUT; IAVG ≥ IOUT
COUT1 " COUT2
v
IOUT tDC
fOSC (0.01t VOUT – 0.5 t IOUT t R DSON _ PMOS )
•
Step 8: CIN
(VIN – 0.3V) • DC
fOSC • L1
If PMOS is not used, then use just one
capacitor where COUT = COUT1 + COUT2
CIN v CVIN CPWR v
3A tDC
I RIPPLE
8 t fOSC t 0.005 t VIN
50 t fOSC t 0.005 t VIN
Step 9: RFBX
Step 10: RT
Step 11: PMOS
⎛V
– 1.204V ⎞
R FBX = ⎜ OUT
⎟⎠
⎝
83.3μA
RT =
81.6
–1; fOSC in MHz and RT in kΩ
fOSC
Only needed for input or output disconnect. See
PMOS Selection in the Appendix for information
on sizing the PMOS and the biasing resistor,
RGATE and picking appropriate UVLO components.
Note 1: Above equations use numbers good for many applications but
for more exact results use the equations from the appendix with numbers
from the Electrical Characteristics.
Note 2: The final values for COUT1, COUT2 and CIN may deviate from the
above equations in order to obtain desired load transient performance.
8582f
13
LT8582
APPLICATIONS INFORMATION
SEPIC Converter Component Selection – Coupled or
Uncoupled Inductors
VOUT
5V
1A(VIN >12V)
s
SWA
SWB
LT8582 FBX
CHx
SHDN
GATE
CIN
10μF
RT
107K
PG
CLKOUT
RT
VC
Step 2: DC
Choose VIN, VOUT and fOSC to calculate equations
below.
DC ≅
L2
6.8μH
Step 3: L
RFBX
45.3k
VIN
100k
PARAMETERS/EQUATIONS
Step 1: Inputs
D1
40V, 2A
s
VIN
3V TO
19V
C1
2.2μF
L1
6.8μH
Table 2. SEPIC Design Equations
COUT
22μF
×2
SYNC GND SS
47pF
0.1μF
VOUT + 0.5V
VIN + VOUT + 0.5V – 0.3V
L TYP =
(VIN – 0.3V) • DC
fOSC • 1A
(1)
L MIN =
(VIN – 0.3V) • (2 • DC – 1)
1.7A • fOSC • (1– DC)
(2)
LMAX =
(VIN – 0.3V) • DC
fOSC • 0.18A
(3)
14.7k
1.5nF
8582 F06
Figure 6. SEPIC Converter – The Component Values Given
Are Typical Values for a 700kHz, 3V - 19V to 5V SEPIC
Topology Using Coupled Inductors
Each channel of the LT8582 can also be configured as a
SEPIC as shown in Figure 6. This topology allows for positive output voltages that are lower, equal, or higher than
the input voltage. Output disconnect is inherently built into
the SEPIC topology, meaning no DC path exists between
the input and output due to capacitor C1. Therefore the
external PMOS is not required.
Table 2 is a step-by-step set of equations to calculate
component values for the LT8582 when operating as a
SEPIC converter. Input parameters are input and output
voltage and switching frequency (VIN, VOUT and fOSC
respectively). Refer to the Appendix for further information
on the design equations presented in Table 2.
Variable Definitions:
= Input Voltage
VIN
VOUT = Output Voltage
DC
= Power Switch Duty Cycle
fOSC = Switching Frequency
IOUT = Maximum Output Current
IRIPPLE = Inductor Ripple Current
Step 4: IRIPPLE
Step 5: IOUT
•
Solve equations 1, 2 and 3 for a range of L
values
•
The minimum of the L value range is the
higher of LTYP and LMIN
•
The maximum of the L value range is LMAX
•
L = L1 = L2 for coupled inductors.
•
L = L1||L2 for uncoupled inductors.
I RIPPLE =
⎛
⎝
(VIN – 0.3V) • DC
fOSC • L
IOUT = ⎜ 3A –
IRIPPLE ⎞
• (1– DC)
2 ⎟⎠
Step 6: D1
VR ≥ VIN + VOUT; IAVG ≥ IOUT
Step 7: C1
C1 ≥ 1μF; VRATING ≥ VIN
Step 8: COUT
Step 9: CIN
C OUT ≥
IOUT • DC
fOSC • 0.005 • VOUT
CIN ≥ CVIN + CPWR ≥
3A • DC
I RIPPLE
+
50 • fO sc • 0.005 • VIN 8 • fO sc • 0.005 • VIN
Step 10: RFBX
Step 11: RT
⎛V
– 1.204V ⎞
R FBX = ⎜ OUT
⎟⎠
⎝
83.3μA
RT =
81.6
–1; fOSC in MHz, RT in kΩ
fOSC
Note 1: Above equations use numbers good for many applications but
for more exact results use the equations from the appendix with numbers
from the Electrical Characteristics.
Note 2: The final values for COUT, and CIN may deviate from the above
equations in order to obtain desired load transient performance.
8582f
14
LT8582
APPLICATIONS INFORMATION
Dual Inductor Inverting Converter Component
Selection – Coupled or Uncoupled Inductors
s
PARAMETERS/EQUATIONS
Step 1: Inputs
L2
4.7μH
VOUT
–12V
550mA
s
VIN
5V
C1
2.2μF
L1
4.7μH
Table 3. Dual Inductor Inverting Design Equations
Step 2: DC
D1
30V, 2A
SWA
SWB
VIN LT8582 FBX
CHx
GATE
SHDN
100k
CIN
4.7μF
RT
53.6K
PG
CLKOUT
RT
VC
SYNC GND SS
| VOUT | + 0.5V
VIN + | VOUT | +0.5V – 0.3V
L TYP =
(VIN – 0.3V) • DC
fOSC • 1A
(1)
L MIN =
(VIN – 0.3V) • (2 • DC – 1)
1.7A • fOSC • (1– DC)
(2)
LMAX =
(VIN – 0.3V) • DC
fOSC • 0.18A
(3)
14.7k
2.2nF
8582 F07
Figure 7. Dual Inductor Inverting Converter – The Component
Values Given Are Typical Values for a 1.5MHz, 5V to –12V
Inverting Topology Using Coupled Inductors
Due to its unique FBX pin, each channel of the LT8582 can
work in a dual inductor inverting configuration as shown in
Figure 7. Changing the connections of L2 and the Schottky
diode in the SEPIC topology results in generating negative
output voltages. This configuration results in very low
output voltage ripple due to inductor L2 in series with
the output. Output disconnect is inherently built into this
topology because of capacitor C1.
Table 3 is a step-by-step set of equations to calculate
component values for the LT8582 when operating as a dual
inductor inverting converter. Input parameters are input
and output voltage and switching frequency (VIN, VOUT
and fOSC respectively). Refer to the Appendix for further
information on the design equations presented in Table 3.
Variable Definitions:
= Input Voltage
VIN
VOUT = Output Voltage
DC
= Power Switch Duty Cycle
fOSC = Switching Frequency
IOUT = Maximum Output Current
IRIPPLE = Inductor Ripple Current
DC ≅
COUT2
10μF
47pF
0.1μF
Step 3: L
RFBX
143k
Choose VIN, VOUT and fOSC to calculate equations
below.
Step 4: IRIPPLE
Step 5: IOUT
•
Solve equations 1, 2 and 3 for a range of L
values
•
The minimum of the L value range is the
higher of LTYP and LMIN
•
The maximum of the L value range is LMAX
•
L = L1 = L2 for coupled inductors.
•
L = L1||L2 for uncoupled inductors.
I RIPPLE =
⎛
⎝
(VIN – 0.3V) • DC
fOSC • L
IOUT = ⎜ 3A –
IRIPPLE ⎞
• (1– DC)
2 ⎟⎠
Step 6: D1
VR > VIN + |VOUT|; IAVG > IOUT
Step 7: C1
C1 ≥ 1μF; VRATING ≥ VIN + |VOUT|
Step 8: COUT
Step 9: CIN
C OUT ≥
IRIPPLE
8 t fOSC t 0.005 t | VOUT |
CIN ≥ CVIN + CPWR ≥
I RIPPLE
3A • DC
+
50 • fO sc • 0.005 • VIN 8 • fO sc • 0.005 • VIN
Step 10: RFBX
Step 11: RT
R FBX =
RT =
| VOUT |+ 7mV
83.3μA
81.6
–1; fOSC in MHz, RT in kΩ
fOSC
Note 1: Above equations use numbers good for many applications but
for more exact results use the equations from the appendix with numbers
from the Electrical Characteristics.
Note 2: The final values for COUT, and CIN may deviate from the above
equations in order to obtain desired load transient performance.
8582f
15
LT8582
APPLICATIONS INFORMATION
LAYOUT GUIDELINES FOR LT8582
Boost Topology Specific Layout Guidelines
General Layout Guidelines
• Keep length of loop (high speed switching path) governing switch, diode D1, output capacitor COUT1 and
ground return as short as possible to minimize parasitic
inductive spikes during switching.
• To improve thermal performance, solder the exposed
ground pad of the LT8582 to the ground plane, with
multiple vias in and around the pad connecting to additional ground planes.
• A ground plane should be used under the switcher
circuitry to prevent interplane coupling and reduce
overall noise.
• High speed switching paths (see specific topology
below for more information) must be kept as short as
possible.
SEPIC Topology Specific Layout Guidelines
• Keep length of loop (high speed switching path) governing switch, flying capacitor C1, diode D1, output
capacitor COUT1 and ground return as short as possible
to minimize parasitic inductive spikes during switching.
Inverting Topology Specific Layout Guidelines
• The VC, FBX and RT components should be placed
as close to the LT8582 as possible, while being as far
away as practically possible from the switch node. The
ground for these components should be separated from
the switch current path.
• Keep ground return path from the cathode of D2
(to chip) separated from output capacitor COUT3’s ground
return path (to chip) in order to minimize switching noise
coupling into the output. Notice the separate ground
return for D2’s cathode in Figure 8.
• Place the bypass capacitors for the VIN pins (CVIN) as
close as possible to the LT8582.
• Keep length of loop (high speed switching path) governing switch, flying capacitor C1 (in Figure 8), diode
D2 and ground return as short as possible to minimize
parasitic inductive spikes during switching.
• Place the bypass capacitors for the inductors (CPWR)
as close as possible to the inductors.
• Bypass capacitors CPWR and CVIN may be combined
into a single bypass capacitor, CIN, if the input side of
the inductor can be close to the VIN pin of the LT8582.
8582f
16
LT8582
APPLICATIONS INFORMATION
Power and Thermal Calculations
THERMAL CONSIDERATIONS
For the LT8582 to deliver its full output power, it is imperative
that a good thermal path be provided to dissipate the heat
generated within the package. This can be accomplished
by taking advantage of the thermal pad on the underside
of the chip. It is recommended that multiple vias in the
printed circuit board be used to conduct heat away from the
chip and into copper planes with as much area as possible.
s
L2
s
Power dissipation in the LT8582 chip comes from four
primary sources: switch I2R loss, NPN base drive loss
(AC + DC) and chip bias current. The following formulas
assume continuous mode operation, so they should not
be used for calculating thermal losses or efficiency in
discontinuous mode or at light load currents.
Overview
L3
D2
C1
COUT3
CPWR2
VOUT2
+
CLKOUT2
VIN
–
SYNC1
13
12
14
11
15
10
16
9
17
8
18
7
19
6
20
5
21
4
22
3
23
2
1
24
CVIN2
GND
CVIN1
25
COUT2
VOUT1
CPWR1
L1
M1
COUT1
D1
RGATE
8582 F08
Figure 8. Suggested Component Placement for Boost and Dual Inductor Inverting Topologies.
Note the Separate Ground Return for the RT, SS, and VC Components as Well as D2’s Cathode
8582f
17
LT8582
s
L3
s
APPLICATIONS INFORMATION
L4
D2
C2
COUT2
CPWR2
VOUT2
+
VIN
–
CLKOUT2
SYNC1
13
12
14
11
15
10
16
9
17
8
18
7
19
6
20
5
21
4
22
3
23
2
24
1
CVIN2
GND
CVIN1
25
VOUT1
CPWR1
COUT1
s
D1
s
C1
L1
L2
8582 F09
Figure 9. Suggested Component Placement for SEPIC and Dual Inductor Inverting Topologies.
Note the Separate Ground Return for the RT, SS, and VC Components as Well as D2’s Cathode
8582f
18
LT8582
APPLICATIONS INFORMATION
Table 4 calculates the power dissipation of one
channel of the LT8582 for a particular boost
application (VIN = 5V, VOUT = 12V, IOUT = 0.8A, fOSC = 1.5MHz,
VD = 0.5V, VCESAT = 0.270V).
From PTOTAL in Table 4, die junction temperature can be
calculated using the appropriate thermal resistance number
and worst-case ambient temperature:
TJ = TA + θJA • PTOTAL
where TJ = die junction temperature, TA = ambient temperature and θJA is the thermal resistance from the silicon
junction to the ambient air.
The published θJA value is 34°C/W for the 7mm × 4mm
24-pin DFN package package. In practice, lower θJA values
are realizable if board layout is performed with appropriate
grounding (accounting for heat sinking properties of the
board) and other considerations listed in the Board Layout
Guidelines section. For instance, a θJA value of ~16°C/W
was consistently achieved for DFN packages of the LT8582
(at VIN = 5V, VOUT = 12V, IOUT = 0.8A, fOSC = 1.5MHz) when
board layout was optimized as per the suggestions in the
Board Layout Guidelines section.
Junction Temperature Measurement
The duty cycle of CLKOUT2 is linearly proportional to die
junction temperature (TJ) near the CLKOUT2 pin. To get an
accurate reading, measure the duty cycle of the CLKOUT
signal and use the following equation to approximate the
junction temperature:
DCCLKOUT – 34.5%
0.3%
TJ =
where DCCLKOUT is the CLKOUT duty cycle in % and TJ is
the die junction temperature in °C. Although the absolute
die temperature can deviate from the above equation by
±10°C, the relationship between the CLKOUT duty cycle and
change in die temperature is well defined. A 3% increase
in CLKOUT duty cycle corresponds to ~10°C increase in
die temperature.
Note that the CLKOUT pin is only meant to drive capacitive
loads up to 120pF.
Thermal Lockout
When the die temperature exceeds 165°C (see Operation
Section), a fault condition occurs and the part goes into
thermal lockout. The fault condition ceases when the die
temperature drops to ~160°C (nominal).
Table 4. Calculations Example with VIN = 5V, VOUT = 12V, IOUT = 0.8A, fOSC = 1.5MHz, VD = 0.5V, VCESAT = 0.27V
DEFINITION OF VARIABLES
DC = Switch Duty Cycle
IIN = Average Input Current
η = Power Conversion Efficiency
(typically 88% at high currents)
PSW = Switch I2R Loss
EQUATION
DC =
VOUT – VIN + VD
VOUT + VD – VCESAT
V
•I
IIN = OUT OUT
VIN • η
DESIGN EXAMPLE
DC =
VALUE
12V – 5V + 0.5V
12V + 0.5V – 0.270V
DC = 61.3%
12V • 0.8A
5V • 0.88
IIN = 2.18A
IIN =
PSW = DC • IIN2 • RSW
PSW = 0.613 • (2.18A)2 • 95mΩ
PBAC = 13ns • IIN • VOUT • fOSC
PBAC = 13ns • 2.18A • 12V • 1.5MHz
PSW = 277mW
RSW = Switch Resistance (typically
95mΩ combined SWA and SWB)
PBAC = Base Drive Loss (AC)
PBDC = Base Drive Loss (DC)
PINP = Chip Bias Loss
V •I • DC
PBDC = IN IN
βSW _ at _IIN
PINP = 11mA • VIN
PBDC =
5V • 2.18A • 0.613
50
PINP = 11mA • 5V
PBAC = 511mW
PBDC = 134mW
PINP = 55mW
PTOTAL = 977mW
Note: These power calculations are for one channel of the LT8582. The power consumption of both channels should be taken into account when
calculating die temperature.
8582f
19
LT8582
APPLICATIONS INFORMATION
SWITCHING FREQUENCY
There are several considerations in selecting the operating frequency of the converter. The first is staying clear
of sensitive frequency bands, which cannot tolerate any
spectral noise. For example, in RF communication products with a 455kHz IF, switching above 600kHz is desired.
Communication products with sensitivity to 1.1MHz would
require to set the switching frequency to 1.5MHz or higher.
Also, like any other switching regulator, harmonics of much
higher frequency than the switching frequency are also
produced. The second consideration is the physical size
of the converter. As the operating frequency goes up, the
inductor and filter capacitors go down in value and size.
The trade-off is efficiency, since the switching losses due
to inductor AC loss, NPN base drive (see Thermal Calculations), Schottky diode charge and other capacitive loss
terms increase proportionally with frequency.
Oscillator Timing Resistor (RT)
The operating frequency of the LT8582 can be set by the
internal free running oscillator. When the SYNC pin for a
channel is driven low (< 0.4V), the oscillator frequency
for that channel is set by a resistor from the RT pin to
ground. The oscillator frequency is calculated using the
following formula:
f OSC =
81.6
RT + 1
where fOSC is in MHz and RT is in kΩ. Conversely, RT
(in kΩ) can be calculated from the desired frequency (in
MHz) using:
RT =
81.6
–1
f OSC
Clock Synchronization
The operating frequency of each channel of the LT8582
can be set by an external source by simply providing
a clock into the SYNC pin for that channel (RT resistor
still required). The LT8582 will revert to its internal free
running oscillator clock (set by the RT resistor) when the
SYNC pin is driven below 400mV for several free running
clock periods.
Driving the SYNC pin of a channel high for an extended
period of time effectively stops the oscillator for that channel. As a result, the switching operation for that channel of
the LT8582 will stop and the CLKOUT pin of that channel
will be pulled low.
The duty cycle of the SYNC signal must be between 20%
and 80% for proper operation. Also, the frequency of the
SYNC signal must meet the following two criteria:
(1) SYNC may not toggle outside the frequency range
of 200kHz to 2.5MHz.
(2) The SYNC frequency can be higher than the free running oscillator frequency (as set by the RT resistor),
fOSC, but should not be less than 25% below fOSC.
Clock Synchronization of Additional Regulators
The CLKOUT pins of the LT8582 can be used to synchronize additional switching regulators or other channels of
LT8582s, as shown in the Typical Application figure on
the front page.
The frequency of channel 1 of the LT8582 is set by the
external RT resistor. The SYNC pin of channel 2 of the
LT8582 is driven by the CLKOUT pin of channel 1 of the
LT8582. Channel 1’s CLKOUT pin has a 50% duty cycle
intended for driving SYNC2 and is 180° out of phase for
reduced input ripple or multiphase topologies.
Note that the RT pin of channel 2 of the LT8582 must have
a resistor tied to ground. It takes a few clock cycles for the
CLKOUT signal to begin oscillating and it is preferable for
all LT8582 channels to have the same internal free running
frequency. Therefore, in general, use the same value RT
resistor for all of the synchronized LT8582s.
EVENT BASED SEQUENCING
The PG pin may be used to sequence other ICs since it
is pulled low as long as the LT8582 is enabled and the
magnitude of the output voltage is below regulation (refer
to the Block Diagram). Since the PG pin is an open drain
output, it can be used to pull the SHDN pin of another IC
low until the output of one of the channels of the LT8582
8582f
20
LT8582
APPLICATIONS INFORMATION
is close to its regulation voltage. This method allows the
PG pin to disable multiple ICs. Refer to Figure 10 for the
necessary connections. Alternatively, the PG pin may be
used to pull the SS pin of another switching regulator low,
preventing the other regulator from switching.
LT8582
CH1
MASTER
SHDN1
CH2
SLAVE
PG1
SHDN2
• The master switch, immune from the flying capacitor current spike (seen only by the slave switch), can
therefore sense the inductor current more accurately.
• Since the slave switch can sustain large current spikes,
the diodes that feed current into the flying capacitors do
not need current limiting resistors, leading to efficiency
and thermal improvements, as well as a smaller solution
size.
High VOUT Charge Pump Topology
VIN
RUVLO1
RUVLO2
SHDNSYS
10k
8582 F10
SET RUVLO1 AND RUVLO2 SUCH THAT
VIN1UVLO < VIN2UVLO
SEE CONFIGURABLE UNDERVOLTAGE LOCKOUT
SECTION FOR DETAILS
The LT8582 can be used in a charge pump topology as
shown in Figure 11, multiplying the output of a boost
converter. The master switch (SWA) can be used to drive
the boost converter, while the slave switch (SWB) can
be used to drive one or more charge pump stages. This
topology is useful for high voltage applications including
VFD bias supplies.
Figure 10. Using the Two LT8582 Channels, with Power
Supply Sequencing
VOUT1
100V
80mA
2.2μF
CHARGE PUMP AIDED REGULATORS
Designing charge pumps with the LT8582 can offer efficient
solutions with fewer components than traditional circuits
because of the master/slave switch configuration on the
IC. Although the slave switch, SWB, operates in phase
with the master switch, SWA, only the current through the
master switch (SWA) is sensed by the current comparator
(A4 in the Block Diagram). This method of operation by
the master/slave switches can offer the following benefits
to charge pump designs:
• The slave switch, by not performing a current sense
operation like the master switch, can sustain fairly
large current spikes without falsely tripping the current
comparator. In a charge pump, these spikes occur when
the flying capacitors charge up. Since this current spike
flows through SWB, it does not affect the operation of
the current comparator (A4 in the Block Diagram).
2.2μF
VOUT2
66V
120mA
2.2μF
2.2μF
22μH
VIN
9V TO 16V
2.2μF
SWA SWB
VIN
576k
100k
4.7μF
80.6K
SHDN
LT8582
CHx
8.06k
383k
FBX
GATE
PG
CLKOUT
RT
VC
SYNC GND
SS
2.2μF
47pF
2.2μF
21k
1.5nF
8582 F11
Figure 11. High VOUT Charge Pump Topology
8582f
21
LT8582
APPLICATIONS INFORMATION
Single Inductor Inverting Topology
HOT-PLUG
If there is a need to use just one inductor to generate a
negative output voltage whose magnitude is greater than
VIN, the single inductor inverting topology (shown in
Figure 12) can be used. Since the master and slave switches
are isolated by a Schottky diode, the current spike through
C1 will flow only through the slave switch, preventing the
current comparator, (A4 in the Block Diagram) from false
tripping. Output disconnect is inherently built into the
single inductor topology.
High inrush currents associated with hot-plugging VIN can
largely be rejected with the use of an external PMOS. A
simple hot-plug controller can be designed by connecting
an external PMOS in series with VIN, with the gate of the
PMOS being driven by the GATE pin of the LT8582. The
GATE pin pull-down current is linearly proportional to the
SS voltage. Since the SS charge up time is relatively slow,
the GATE pin pull-down current will increase gradually,
thereby turning on the external PMOS slowly. Controlled
in this manner, the PMOS acts as an input current limiter
when VIN hot-plugs or ramps up sharply.
C1
D1
L1
D3
VOUT < 0V
AND
|VOUT| > VIN
VIN
D2
SWA
VIN
SHDN
100k
CIN
RT
SWB
LT8582
CHx
RFBX
FBX
COUT
GATE
PG
CLKOUT
RT
VC
SYNC GND
SS
CF
CSS
RC
Likewise, when the PMOS is connected in series with the
output, inrush current into the output capacitor can be
limited during a hot-plug event. To illustrate this, the circuit
in Figure 5 was reconfigured by adding a large 1500μF
capacitor to the output. An 18Ω resistive load was used
and CSS was increased to 10μF. Figure 13 shows the results
of hot-plugging this reconfigured circuit. Notice how the
inductor current is well behaved.
CC
8582 F12
VIN
5V/DIV
Figure 12. Single Inductor Inverting Topology
VOUT1
10V/DIV
SS1
1V/DIV
IL1
2A/DIV
2s/DIV
8582 F13
Figure 13. VIN Hot-Plug Control. Inrush Current Is Well Controlled
8582f
22
LT8582
APPENDIX
INDEPENDENT CHANNELS
Either channel may be used independently of the other
channel. To disable one channel, drive SHDN of that channel
low. Activating or deactivating one channel will not alter
the functionality of the other channel.
Duty cycle equations for several common topologies are
given below where VD is the diode forward voltage drop
and VCESAT is the collector to emitter saturation voltage
of the switch. VCESAT, with SWA and SWB tied together, is
typically 270mV when the combined switch current (ISWA
+ ISWB) is 2.75A.
SETTING THE OUTPUT VOLTAGE
For the boost topology (see Figure 5):
The output voltage is set by connecting a resistor (RFBX)
from VOUT to the FBX pin. RFBX is determined by using
the following equation:
|V
– VFBX |
R FBX = OUT
83.3μA
where VFBX is 1.204V (typical) for noninverting topologies
(i.e. boost and SEPIC regulators) and 7mV (typical) for
inverting topologies (see the Electrical Characteristics).
POWER SWITCH DUTY CYCLE
In order to maintain loop stability and deliver adequate
current to the load, the power NPNs (Q1 and Q2 in the
Block Diagram) cannot remain on for 100% of each clock
cycle. The maximum allowable duty cycle is given by:
DC MA X =
(TP – MinOffTime)
• 100%
TP
where TP is the clock period and MinOffTime (found in the
Electrical Characteristics) is typically 45ns.
Conversely, the power NPNs (Q1 and Q2 in the Block
Diagram) cannot remain off for 100% of each clock cycle
and will turn on for a minimum on time (MinOnTime) when
in regulation. This MinOnTime governs the minimum allowable duty cycle given by:
DC MIN =
MinOnTime
• 100%
TP
Where TP is the clock period and MinOnTime (found in
the Electrical Characteristics) is typically 55ns.
The application should be designed such that the operating
duty cycle is between DCMIN and DCMAX.
DCBOOST ≅
VOUT – VIN + VD
VOUT + VD – VCESAT
For the SEPIC or dual inductor inverting topology (see
Figure 6 and Figure 7):
DCSEPIC _& _ INVERT ≅
| VOUT | +VD
VIN +| VOUT | +VD – VCESAT
For the single inductor inverting topology (see Figure 12):
DCSI _ INVERT ≅
| VOUT | –VIN + VCESAT + 3 • VD
| VOUT | +3 • VD
The LT8582 can be used in configurations where the duty
cycle is higher than DCMAX, but it must be operated in the
discontinuous conduction mode so that the effective duty
cycle is reduced.
INDUCTOR SELECTION
General Guidelines
The high frequency operation of the LT8582 allows for the
use of small surface mount inductors. For high efficiency,
choose inductors with high frequency core material,
such as ferrite, to reduce core losses. Also to improve
efficiency, choose inductors with more volume for a given
inductance. The inductor should have low DCR (copperwire resistance) to reduce I2R losses and must be able to
handle the peak inductor current without saturating. Note
that in some applications, the current handling requirements of the inductor can be lower, such as in the SEPIC
topology where each inductor only carries one half of the
total switch current. Multilayer chip inductors usually do
not have enough core volume to support peak inductor
currents in the 2A to 6A range. To minimize radiated noise,
8582f
23
LT8582
APPENDIX
use a toroidal or shielded inductor. See Table 5 for a list
of inductor manufacturers.
Table 5. Inductor Manufacturers
where
LBOOST = L1 for boost topologies (see Figure 5)
LDUAL = L1 = L2 for coupled dual inductor topologies
(see Figures 6 and 7)
Coilcraft
MSD7342
XAL6060 Series
www.coilcraft.com
Vishay
IHLP-2020BZ-01
IHLP-2525CZ-01
Series
www.vishay.com
LDUAL = L1 || L2 for uncoupled dual inductor
topologies (see Figures 6 and 7)
WÜRTH
WE-PD
WE-DD
WE-TDC Series
www.we-online.com
DC
= Switch duty cycle (see Power Switch Duty
Cycle section in Appendix)
Cooper Bussman
Octa-Pac Plus
DRQ-125
DRQ-74 Series
www.cooperbussmann.com
IPK
Sumida
CDR6D28MN
CDR7D28MN
Series
www.sumida.com
= Maximum Peak Switch Current; should not
exceed 3A for a combined SWA + SWB
current, or 1.7A if only SWA is being used.
η
Taiyo Yuden
NR Series
www.t-yuden.com
TDK
VLF, SLF, RLF
Series
www.tdk.com
= Power conversion efficiency (typically 88%
for boost and 82% for dual inductor
topologies at high currents)
fOSC
= Switching frequency
IOUT
= Maximum load current
Minimum Inductance
Although there can be a trade-off with efficiency, it is
often desirable to minimize board space by choosing
smaller inductors. When choosing an inductor, there are
three conditions that limit the minimum inductance: (1)
providing adequate load current, (2) avoiding subharmonic
oscillation and (3) supplying a minimum ripple current to
avoid false tripping of the current comparator.
Adequate Load Current
Small value inductors result in increased ripple currents
and thus, due to the limited peak switch current, decrease
the average current that can be provided to the load. In
order to provide adequate load current, L should be at least:
LBOOST #
DC t (VIN – VCESAT)
©
V
tI ¹
2 t fOSC t ª IPK – OUT OUTº
VIN t M »
«
Boost
Topology
Avoiding Subharmonic Oscillations
Subharmonic oscillations can occur when the duty cycle is
greater than 50%. The LT8582’s internal slope compensation circuit will avoid this, provided that the inductance
exceeds a certain minimum value. In applications that
operate with duty cycles greater than 50%, the inductance
must be at least:
LMIN >
(VIN – VCESAT) • (2 • DC – 1)
1.7A • fOSC • (1– DC)
where
LMIN = L1 for boost topologies (see Figure 5)
LMIN = L1 = L2 for coupled dual inductor topologies
(see Figures 6 and 7)
or
L DUAL #
Negative values of LBOOST or LDUAL indicate that the
output load current IOUT exceeds the switch current limit
capability of the LT8582.
DC t (V IN – V CESAT )
¹
©
|V | t I
2tf OSC t ªIPK – OUT OUT I OUTº
»
«
V tM
IN
SEPIC or
Inverting
Topologies
LMIN = L1 || L2 for uncoupled dual inductor topologies
(see Figures 6 and 7)
8582f
24
LT8582
APPENDIX
Maximum Inductance
Excessive inductance can reduce current ripple to levels
that are difficult for the current comparator (A4 in the
Block Diagram) to easily distinguish the peak current.
This causes duty cycle jitter and/or poor regulation. The
maximum inductance can be calculated by:
Note that these equations offer conservative results for
the required inductor current ratings. The current ratings
could be lower for applications with light loads and small
transients if the SS capacitor is sized appropriately to limit
inductor currents at start-up.
DIODE SELECTION
V –V
DC
LMAX = IN CESAT •
180mA
fOSC
where
LMAX = L1 for boost topologies (see Figure 5)
LMAX = L1 = L2 for coupled dual inductor topologies
(see Figures 6 and 7)
LMAX = L1 || L2 for uncoupled dual inductor topologies
(see Figures 6 and 7)
Inductor Current Rating
Inductors must have a rating greater than their peak
operating current to prevent saturation, which results in
efficiency losses. The maximum inductor current (considering start-up, transient, and steady-state conditions)
is given by:
V •T
IL _ PEAK = ILIM + IN MIN _ PROP
L
where
IL_PEAK = Peak of Inductor Current in L1 for boost
topology, or peak of the sum of inductor
currents in L1 and L2 for dual inductor
topologies.
ILIM
= For hard saturation inductors, 5.4A when SWA
and SWB are tied together, or 3A when only
SWA is being used. For soft saturation
inductors, 3.3A when SWA and SWB are tied
together, or 1.8A when only SWA is being
used.
TMIN_PROP = 55ns (propagation delay through the
current feedback loop)
Schottky diodes, with their low forward voltage drops
and fast switching speeds, are recommended for use with
the LT8582. Choose a Schottky diode with low parasitic
capacitance to reduce reverse current spikes through the
power switch of the LT8582. The Diodes Inc. PD3S230H
diode is a very good choice with a 30V reverse voltage
rating and an average forward current of 2A.
OUTPUT CAPACITOR SELECTION
Low ESR (equivalent series resistance) capacitors should
be used at the output to minimize the output ripple voltage. Multilayer ceramic capacitors are an excellent choice,
as they have an extremely low ESR and are available in
very small packages. X5R or X7R types are preferred,
as these retain their capacitance over wide voltage and
temperature ranges. A 10μF to 22μF output capacitor is
sufficient for most applications, but systems with very
low output currents may need only 2.2μF to 10μF. Always
use a capacitor with a sufficient voltage rating. Many
ceramic capacitors, particularly 0805 or 0603 case sizes,
have greatly reduced capacitance at the desired output
voltage. Tantalum polymer or OS-CON capacitors can be
used, but it is likely that these capacitors will occupy more
board area than ceramics and will have a higher ESR with
greater output ripple.
INPUT CAPACITOR SELECTION
Ceramic capacitors make a good choice for the input bypass capacitor and should be placed as close as possible
to the VIN pin of the chip as well as to the inductor connected to the input of the power path. If it is not possible
to optimally place a single input capacitor, then use two
separate capacitors—use one at the VIN pin of the chip
(see the equation for CVIN in Table 1, Table 2 and Table 3)
8582f
25
LT8582
APPENDIX
and one at the input to the power path (see the equation
for CPWR in Table 1, Table 2 and Table 3). A 4.7μF to 20μF
input capacitor is sufficient for most applications.
Table 6 shows a list of several ceramic capacitor manufacturers. Consult the manufacturers for detailed information
on their entire selection of ceramic parts.
Table 6. Ceramic Capacitor Manufacturers
TDK
www.tdk.com
Murata
www.murata.com
Taiyo Yuden
www.t-yuden.com
Kemet
www.kemet.com
PMOS SELECTION
An external PMOS, controlled by the LT8582’s GATE pin,
can be used to facilitate input or output disconnect. The
GATE pin turns on the PMOS gradually during start-up
(see soft-start of external PMOS in the Operation section)
and turns the PMOS off when the LT8582 is in shutdown
or in fault.
The use of the external PMOS, controlled by the GATE pin,
is particularly beneficial when dealing with unintended
output shorts in a boost regulator. In a conventional boost
regulator, the inductor, Schottky diode and power switches
are susceptible to damage in the event of an output short.
Using an external PMOS in the boost regulator’s power
path (path from VIN to VOUT) controlled by the GATE pin,
will serve to disconnect the input from the output when
the output has a short. This helps to save the chip and
the other components in the power path from damage.
Ensure that both the diode and the inductor can survive
low duty cycle current pulses of 5 to 6 times their steady
state levels.
The PMOS chosen must be capable of handling the maximum input or output current depending on whether it is
used at the input or the output (see Figure 5).
Ensure that the PMOS is biased with enough source to
gate voltage (VSG) to enhance the device into the triode
mode of operation. The higher the VSG voltage that biases
the PMOS into triode, the lower the RDSON of the PMOS,
thereby lowering power dissipation in the device during
normal operation, as well as improving the efficiency of
the application. The following equations show the relationship between RGATE (see Block Diagram) and the desired
VSG that the PMOS is biased with, where VS is the PMOS
source voltage:
VSG =
VS
RGATE
if VGATE < 2V
RGATE + 2kΩ
1mA t RGATE if VGATE ≥ 2V
When using a PMOS, it is advisable to configure the specific
application for undervoltage lockout (see the Operations
section). The goal is to have VIN get to a certain minimum
voltage where the PMOS has sufficient VSG.
Figure 5 shows the PMOS connected in series with the
output to act as an output disconnect during a fault condition. Using a PMOS with a high VT (~2V) can help to
reduce extraneous current spikes during hot-plug. The
resistor divider from VIN to the SHDN pin sets UVLO at
4V for this application.
Connecting the PMOS in series with the output offers certain advantages over connecting it in series with the input:
• Since the load current is always less than the input
current for a boost converter, the current rating of
the PMOS will be reduced.
• A PMOS in series with the output can be biased with
a higher overdrive voltage than a PMOS used in series
with the input, since VOUT > VIN. This higher overdrive
results in a lower RDSON rating for the PMOS, thereby
improving the efficiency of the regulator.
In contrast, an input connected PMOS works as a simple
hot-plug controller (covered in more detail in the Hot-Plug
section). The input connected PMOS also functions as an
inexpensive means of protecting against multiple output
shorts in boost applications that synchronize the LT8582
with other compatible chips.
8582f
26
LT8582
APPENDIX
Table 7 shows a list of several discrete PMOS manufacturers. Consult the manufacturers for detailed information
on their entire selection of PMOSs.
Table 7. Discrete PMOS Manufacturers
Vishay
www.vishay.com
ON Semiconductor
www.onsemi.com
Fairchild Semiconductor
www.fairchildsemi.com
Diodes Incorporated
www.diodes.com
VOUT
AC-COUPLED
500mV/DIV
IL
1A/DIV
ILOAD
400mA/DIV
100μs/DIV
8582 F14b
Figure 14b. Transient Response Is Better
COMPENSATION – ADJUSTMENT
To compensate the feedback loop of the LT8582, a series
resistor capacitor network in parallel with an optional
single capacitor should be connected from the VC pin to
GND. For most applications, choose a series capacitor in
the range of 1nF to 10nF with 2.2nF being a good starting value. The optional parallel capacitor should range in
value from 22pF to 220pF with 47pF being a good starting
value. The compensation resistor, RC, is usually in the
range of 5k to 50k with 10k being a good starting value.
A good technique to compensate a new application is to
use a 100k potentiometer in place of the series resistor
RC. With the series and parallel capacitors at 4.7nF and
47pF respectively, adjust the potentiometer while observing the transient response and the optimum value for RC
can be found. Figures 14a to Figure 14c illustrate this
process for the circuit of Figure 17 with a load current
stepped between 300mA and 800mA. Figure 14a shows
the transient response with RC equal to 1k. The phase
margin is poor as evidenced by the excessive ringing in
the output voltage and inductor current. In Figure 14b, the
value of RC is increased to 3.15k, which results in a more
damped response. Figure 14c shows the results when RC is
increased further to 6.49k. The transient response is nicely
damped and the compensation procedure is complete.
VOUT1
AC-COUPLED
500mV/DIV
IL1
1A/DIV
ILOAD
400mA/DIV
100μs/DIV
8582 F14a
VOUT
AC-COUPLED
500mV/DIV
IL
1A/DIV
ILOAD
400mA/DIV
100μs/DIV
8582 F14c
Figure 14c. Transient Response Is Well Damped
Compensation – Theory
Like all other current mode switching regulators, the
LT8582 needs to be compensated for stable and efficient
operation. Two feedback loops are used in the LT8582: a
fast current loop which does not require compensation
and a slower voltage loop which does. Standard bode plot
analysis can be used to understand and adjust the voltage
feedback loop.
As with any feedback loop, identifying the gain and phase
contribution of the various elements in the loop is critical.
Figure 15 shows the key equivalent elements of a boost
converter. Because of the fast current control loop, the
power stage of the chip, inductor and diode have been
replaced by a combination of the equivalent transconductance amplifier gmp and the current controlled current
source (which converts IVIN to (ηVIN/VOUT) • IVIN). gmp
acts as a current source where the peak input current,
IVIN, is proportional to the VC voltage. η is the efficiency
of the switching regulator and is typically about 88% at
higher currents.
Figure 14a. Transient Response Shows Excessive Ringing
8582f
27
LT8582
APPENDIX
Error Amp Pole:
–
+
VOUT
gmp
IVIN
Mt7IN
VOUT
RESR
t*VIN
CPL
+
CF
RC
RO
R1
R2
FBX
–
8582 F15
Error Amp Zero:
1
Z1=
2 • π • R C • CC
ESR Zero:
R2
CC
Z2 =
CC: COMPENSATION CAPACITOR
COUT: OUTPUT CAPACITOR
CPL: PHASE LEAD CAPACITOR
CF: HIGH FREQUENCY FILTER CAPACITOR
gma: TRANSCONDUCTOR ERROR AMPLIFIER INSIDE THE CHIP
gmp: POWER STAGE TRANSCONDUCTANCE AMPLIFIER
RC: COMPENSATION RESISTOR
RL: OUTPUT RESISTANCE DEFINED AS VOUT/ILOADMAX
RO: OUTPUT RESISTANCE OF gma
R1, R2: OUTPUT VOLTAGE FEEDBACK RESISTOR DIVIDER
RESR: OUTPUT CAPACITOR ESR
M: CONVERTER EFFICIENCY (~88% AT HIGHER CURRRENTS)
Figure 15. Boost Converter Equivalent Model
Note that the maximum output currents of gmp and gma
are finite. The output current of the gmp stage is limited
by the minimum switch current limit (see the Electrical
Specifications) and the output of the gma stage is nominally
limited to about ±12μA.
From Figure 15, the DC gain, poles and zeros can be
calculated as follows:
0.5R2
V
R ⎞
⎛
ADC = (gma • RO)• gmp • ⎜ η • IN • L ⎟ •
⎝
VOUT 2 ⎠ R1 + 0.5R2
Output Pole:
2
2 • π • RL + COUT
1
2 • π • R ESR • COUT
RHP Zero:
Z3 =
VIN2 • RL
2 • π • VOUT2 • L
High Frequency Pole:
f
P3 > s
3
Phase Lead Zero:
Z4 =
1
2 • π • R1• CPL
Phase Lead Pole:
P4 =
DC GAIN:
P1 =
1
2 • π • (RO + RC) CC
COUT
1.204V
REFERENCE
gma
RL
P2 =
1
0.5 • R1 • R2
2•π
• CPL
R1 + 0.5R2
Error Amp Filter Pole:
P5 =
1
C
,C F < C
R •R
10
2 • π • C O • CF
RC + RO
8582f
28
LT8582
APPENDIX
The current mode zero (Z3) is a right half plane zero
which can be an issue in feedback control design, but is
manageable with proper external component selection.
0
140
120
GAIN (dB)
100
–90
80
–135
–180
60
50° AT
5kHz
40
GAIN
20
Table 8. Bode Plot Parameters
PARAMETER
VALUE
UNITS
COMMENT
RL
20
Ω
Application Specific
COUT
22
μF
Application Specific
RESR
1
mΩ
Application Specific
RO
305
kΩ
Not Adjustable
CC
4700
pF
Adjustable
CF
47
pF
Optional/Adjustable
CPL
0
pF
Optional/Adjustable
–270
–315
0
–20
10
100
10k
1k
FREQUENCY (Hz)
100k
–360
1M
8582 F16
Figure 16. Bode Plot for Example Boost Converter
L1
4.7μH
VIN
5V
RC
6.49
kΩ
Adjustable
R1
130
kΩ
Adjustable
R2
14.5
kΩ
Not Adjustable
VREF
1.204
V
Not Adjustable
215k
VOUT
12
V
Application Specific
100k
VIN
5
V
Application Specific
gma
270
μmho
Not Adjustable
gmp
15.1
mho
Not Adjustable
L
4.7
μH
Application Specific
fOSC
1.5
MHz
Adjustable
From Figure 16, the phase is –130° when the gain reaches
0dB, giving a phase margin of 50°. The crossover frequency
is 5kHz, which is many times lower than the frequency of
the RHP zero Z3, thus providing for adequate phase margin.
–225
PHASE (DEG)
Using the circuit in Figure 17 as an example, Table 8 shows
the parameters used to generate the bode plot shown in
Figure 16.
–45
PHASE
D1
VOUT
12V
SWA
SWB
CIN
4.7μF
RT
53.6K
SHDN
130k
FBX
VIN
PG
GATE
LT8582
CHx CLKOUT
RT
VC
SYNC
GND
SS
COUT
22μF
47pF
0.1μF
6.49k
4.7nF
8582 F17
Figure 17. 5V to 12V Boost Converter
8582f
29
LT8582
TYPICAL APPLICATIONS
1.5MHz, 5V to ±12V Boost and Inverting Converter Can Survive Output Shorts
L1
4.7μH
D1
M1
CIN1
4.7μF
COUT1
10μF
SWA1
SWB1
100k
SHDN1
PG1
130k
GATE1
LT8582
COUT2
10μF
VC1
SS1
CLKOUT1
RT1
6.49k
47pF
0.1μF
53.6k
4.7nF
53.6k
2.2nF
GND
SYNC2
215k
PG2
RT2
SHDN2
SS2
VIN2
VC2
0.1μF
47pF
14.7k
100
3.2
90
2.8
80
2.4
70
2.0
60
1.6
50
1.2
40
0.8
30
0.4
20
0
COUT3
10μF
GATE2
143k
0.1
0.4
0.3
0.2
LOAD CURRENT (A)
L2
4.7μH
0
0.6
8582 TA02b
FBX2
SWA2
0.5
POWER LOSS (W)
SYNC1
CLKOUT2
100k
Efficiency and Power Loss
(Load Between 12V and –12V Outputs)
6.04k
FBX1
VIN1
215k
VOUT1
12V
0.8A*
EFFICIENCY (%)
VIN
5V
SWB2
C1
2.2μF
L3
4.7μH
s
s
CIN2
4.7μF
VOUT2
–12V
550mA*
D2
8582 TA02a
CIN1, CIN2: 4.7μF, 16V, X7R, 1206
COUT1, COUT2, COUT3: 10μF, 25V, X7R, 1206
C1: 2.2μF, 25V, X7R, 1206
D1, D2: DIODES INC. PD3S230H
L1: COILCRAFT XAL6060-472ML
L2, L3: COILCRAFT MSD7342-472
M1: FAIRCHILD FDMC510P
*MAX TOTAL OUTPUT POWER: 14.4W
Output Short from 12V Output to Ground
CLKOUT1
5V/DIV
VOUT1
5V/DIV
Transient Response with 0.15A to 0.45A to 0.15A
Output Load Step Between Rails
VOUT1
500mV/DIV
AC-COUPLED
VOUT2
500mV/DIV
AC-COUPLED
GATE
5V/DIV
IL1
1A/DIV
IL1
5A/DIV
IL2 + IL3
1A/DIV
20μs/DIV
8582 TA02c
100μs/DIV
8582 TA02d
8582f
30
LT8582
TYPICAL APPLICATIONS
VFD (Vacuum Fluorescent Display) and Filament Power Supply Switches at 1MHz
D6
VOUT1
100V
C6
80mA*
2.2μF
D5
C4
2.2μF
D4
VOUT2
66V
C5
120mA*
2.2μF
D3
C3
2.2μF
L1
22μH
VIN
9V TO 16V
D2
CIN1
4.7μF
D1
CIN1, CIN2: 4.7μF, 25V, X7R, 1206
C1 TO C6: 2.2μF, 50V, X7R, 1206
C7: 2.2μF, 25V, X7R, 0805
C8: 10μF, 25V, X7R, 1210
D1 TO D6: CENTRAL SEMI CMMSH2-40
D7: CENTRAL SEMI CMHZ5240B
D8: CENTRAL SEMI CTLSH5-40M833
D9: CENTRAL SEMI CTLSH2-40M832
L1: WÜRTH 744771122
L2, L3: WÜRTH 744870100
M1: VISHAY SI7611DN
M1**
D7**
C1
2.2μF
D8**
8.06k**
SWA1 SWB1
FBX1
VIN1
576k
100k
SHDN1
PG1
383k
GATE1
LT8582
C2
2.2μF
VC1
SYNC1
SS1
CLKOUT1
RT1
21k
47pF
*CHANNEL 1 MAX OUTPUT POWER 8W
**OPTIONAL FOR OUTPUT SHORT PROTECTION
2.2μF
80.6k
CLKOUT2
1.5nF
GND
SYNC2
100k
576k
80.6k
PG2
1.5nF
RT2
SHDN2
SS2
VIN2
VC2
2.2μF
47pF
11.8k
C8
10μF
×2
GATE2
113k
FBX2
SWA2
C7
2.2μF
SWB2
D9
VOUT3
10.5V
0.85A
s
L2
10μH
CIN2
4.7μF
s
8582 TA03a
L3
10μH
Efficiency and Power Loss
(VIN = 12V with Load on 100V Output)
2.0
90
0.8
50
0
2
6
4
OUTPUT POWER (W)
8
0.4
10
8582 TA03b
100
1.6
90
1.4
80
1.2
70
1.0
60
0.8
50
0.6
40
0.4
30
0.2
20
0
0.2
0.6
0.4
LOAD CURRENT (A)
0.8
POWER LOSS (W)
60
POWER LOSS (W)
1.2
70
EFFICIENCY (%)
1.6
80
EFFICIENCY (%)
Efficiency and Power Loss
(VIN = 12V with Load on 10.5V Output)
0
1
8582 TA03c
8582f
31
LT8582
TYPICAL APPLICATIONS
Tracking ±15V Supplies from a 2.7V to 5.5V Input
L1
10μH
VIN
2.7V TO 5.5V
D1
CIN1
10μF
49.9k
SWA1
SWB1
6.04k
FBX1
VIN1
SHDN1
100k
VOUT1
15V
0.3A(VIN = 2.7V)
0.42A(VIN = 3.6V)
0.56A(VIN = 4.5V)
0.69A(VIN = 5.5V)
PG1
FBX2
GATE1
LT8582
COUT1
10μF
×2
VC1
SYNC1
SS1
CLKOUT1
RT1
6.65k
0.1μF
107k
CLKOUT2
CIN1, CIN2: 10μF, 16V, X7R, 1206
COUT1, COUT2: 10μF, 25V, X7R, 1210
C1: 4.7μF, 50V, X7R, 1206
D1, D2: DIODES INC. PD3S230H
L1: COILCRAFT XAL6060-103ME
L2, L3: COILCRAFT MSD1260-153
100pF
6.8nF
GND
SYNC2
107k
PG2
RT2
SHDN2
6.8nF
0.1μF
SS2
VIN2
100pF
6.65k
VC2
COUT2
10μF
×2
GATE2
53.6k
FBX2
SWA2
SWB2
C1
4.7μF
L2
15μH
L3
15μH
VOUT2
–15V
0.27A(VIN = 2.7V)
0.37A(VIN = 3.6V)
0.46A(VIN = 4.5V)
0.54A(VIN = 5.5V)
s
s
CIN2
10μF
D2
8582 TA04a
15V and –15V Outputs vs Load Current
(VIN = 3.6V, Load on 15V Output)
3.2
15.30
90
2.8
15.25
80
2.4
15.20
70
2.0
60
1.6
MAGNITUDE VOUT (V)
100
POWER LOSS (W)
EFFICIENCY (%)
Efficiency and Power Loss
(VIN = 3.6V with Load Between 15V and –15V Outputs)
15.10
15.05
50
1.2
0.8
15.10
30
0.4
14.95
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
LOAD CURRENT (A)
–15V
15.15
40
20
15V
14.90
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
LOAD CURRENT (A)
8582 TA04c
8582 TA04b
15V and –15V Outputs vs Load Current
(VIN = 3.6V, Load on –15V Output)
15V and –15V Outputs vs Load Current
(VIN = 3.6V, Load Between 15V and –15V Outputs)
15.30
15.30
15V
15.25
15.20
15.15
MAGNITUDE VOUT (V)
MAGNITUDE VOUT (V)
15.25
–15V
15.10
15.05
15.15
15.10
15.10
14.95
14.95
14.90
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
LOAD CURRENT (A)
8582 TA04d
–15V
15.05
15.00
14.90
15V
15.20
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
LOAD CURRENT (A)
8582 TA04e
8582f
32
LT8582
TYPICAL APPLICATIONS
SuperCap Backup Power
VOUT
VIN (VIN > 11.4V)
11V (VIN < 11.4V)
M1
C1
2.2μF
L1
5μH
6.04k
D1
VOUT1
10V
s
VIN
12V ±5%
CIN1
4.7μF
L2
5μH
s
SWA1
100k
73.2k
SWB1
VIN1
FBX1
PG1
GATE1
SHDN1
COUT1
4.7μF
130k
COUT2
10μF
VC1
LT8582
11k
SS1
SYNC1
15.4k
80.6k
CLKOUT1
100pF
0.47μF
RT1
1.2k
1/4W
CS1
60F
1.2k
1/4W
CS2
60F
1.2k
1/4W
CS3
60F
1.2k
1/4W
CS4
60F
1nF
GND
CLKOUT2
80.6k
SYNC2
VOUT1
100k
3.3nF
RT2
PG2
SS2
SHDN2
VC2
VIN2
0.47μF
100pF
12.7k
CIN1, CIN2: 4.7μF, 16V, X7R, 1206
COUT1: 4.7μF, 25V, X7R, 1206
COUT2: 10μF, 25V, X7R, 1210
COUT3: 22μF, 16V, X7R, 1210
C1: 2.2μF, 25V, X7R, 0805
CS1 TO CS4: 60F, 2.5V, COOPER HB1840-2R5606-R
D1, D2: CENTRAL SEMI CTLSH5-40M833
L1, L2: COOPER CTX5-1A
L3: COOPER HCM0703-2R2
M1: VISHAY SI7123DN
COUT3
22μF
×2
GATE2
105k
FBX2
L3
2.2μH
SWA2
SWB2
D2
8582 TA05a
CIN2
4.7μF
System Level Diagram
GATE
VIN
VIN1
SEPIC
VOUT1
VIN2
BOOST
VOUT2
VOUT
8582 TA05b
SUPERCAPS
Charging SuperCaps
Input Removed, Holdup for ~110s with 500mA Load
IL1 + IL2
2A/DIV
IL1 + IL2
2A/DIV
IL3
2A/DIV
VOUT ≈ 11V
5V/DIV
VOUT1
5V/DIV
IL3
2A/DIV
VOUT ≈ VIN
5V/DIV
VOUT1
5V/DIV
25s/DIV
8582 TA05c
25s/DIV
8582 TA05d
8582f
33
LT8582
TYPICAL APPLICATIONS
12V and 5V Sequenced Outputs from a 3V to 19V Input*
C1
2.2μF
L1
8.2μH
D1
CIN1
10μF
SWA1
SWB1
s
L2
8.2μH
VIN1
SHDNSYS
130k
*FOR SYSTEM LEVEL DIAGRAM,
SEE FIGURE 10
FBX1
10k
10k
SHDN1
M1
VOUT1
12V
0.3A (VIN = 3V)
0.5A (VIN = 5V)
1A (VIN = 12V)
s
VIN
3V to 19V
115k
PG1
M2
GATE1
LT8582
COUT1
10μF
×2
VC1
SYNC1
SS1
CLKOUT1
RT1
CLKOUT2
47pF
20k
0.1μF
107k
1.5nF
107k
1.5nF
GND
SYNC2
100k
PG2
RT2
SHDN2
VIN2
47pF
0.1μF
14.7k
SS2
VC2
COUT2
22μF
×2
GATE2
45.3k
CIN1, CIN2: 10μF, 25V, X7R, 1210
COUT1: 10μF, 25V, X7R, 1210
COUT2: 22μF, 16V, X7R, 1210
C1,C2 : 2.2μF, 25V, X7R, 0805
D1, D2: CENTRAL SEMI CTLSH2-40M832
L1, L2: COOPER DRQ125-8R2
L3, L4: COOPER DRQ125-6R8
M1, M2: 2N7002
FBX2
SWA2
SWB2
C2
2.2μF
VOUT2
5V
0.7A (VIN = 3V)
1A (VIN = 5V)
1.45A (VIN = 12V)
D2
s
L3
6.8μH
CIN2
10μF
s
L4
6.8μH
8582 TA06a
Start-Up Waveforms (VIN = 12V)
Cycle-to-Cycle (5V Output)
CLKOUT2
2V/DIV
VOUT1
5V/DIV
SWA2, SWB2
10V/DIV
IL1 + IL2
2A/DIV
VOUT2
50mV/DIV
AC-COUPLED
IL3 + IL4
1A/DIV
VOUT2
2V/DIV
IL3 + IL4
2A/DIV
8582 TA06b
2ms/DIV
Efficiency and Power Loss
(VIN = 12V with Load on 12V Output)
70
1.5
60
1.2
0.9
50
40
0.6
30
0.3
20
0
0
0.2
0.6
0.4
LOAD CURRENT (A)
0.8
1
8582 TA06d
100
2.50
90
2.25
80
2.00
70
1.75
60
1.50
50
1.25
40
1.00
30
0.75
20
0.50
POWER LOSS (W)
1.8
POWER LOSS (W)
80
EFFICIENCY (%)
2.1
90
EFFICIENCY (%)
Efficiency and Power Loss
(VIN = 12V with Load on 5V Output)
2.4
100
8582 TA06c
500ns/DIV
0.25
10
0
0
0.2
0.4
0.6 0.8 1
1.2
LOAD CURRENT (A)
1.4
0
1.6
8582 TA06e
8582f
34
LT8582
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DKD Package
24-Lead Plastic DFN (7mm × 4mm)
(Reference LTC DWG # 05-08-1864 Rev Ø)
0.70 p 0.05
4.50 p 0.05
6.43 p0.05
2.64 p0.05
3.10 p 0.05
PACKAGE
OUTLINE
0.50 BSC
0.25 p 0.05
5.50 REF
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
7.00 p0.10
13
R = 0.115
TYP
24
R = 0.05
TYP
0.40 p 0.10
6.43 p0.10
4.00 p0.10
2.64 p0.10
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 s 45o CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
12
0.75 p0.05
0.50 BSC
0.25 p 0.05
BOTTOM VIEW—EXPOSED PAD
0.200 REF
1
5.50 REF
(DKD24) QFN 0210 REV Ø
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX)
IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
8582f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LT8582
TYPICAL APPLICATION
700kHz SEPIC and Inverting Converter Generates ±5V
Outputs from a 3V to 19V Input
C1
2.2μF
L1
4.7μH
VOUT1
5V
0.7A (VIN = 3V)
1.4A (VIN = 9V)
1.5A (VIN = 16V)
D1
s
VIN
3V to 19V
CIN1
22μF
SWA1
SWB1
s
L2
4.7μH
SHDN1
100k
PG1
EFFICIENCY (%)
FBX1
LT8582
GATE1
COUT1
22μF
×2
VC1
SYNC1
SS1
CLKOUT1
RT1
11.8k
47pF
0.1μF
115k
CLKOUT2
VIN2
115k
2.2nF
RT2
0.1μF
3.5
60
3.0
50
2.5
40
2.0
30
1.5
20
1.0
10
0.5
0.2
0.4
0.6 0.8
1 1.2
LOAD CURRENT (A)
47pF
1.4
0
1.6
8582 TA07b
18.7k
SS2
VC2
COUT2
22μF
×2
60.4k
FBX2
C2
2.2μF
L4
4.7μH
s
s
SWA2 SWB2
70
0
GATE2
L3
4.7μH
4.0
0
100k
SHDN2
4.5
2.2nF
GND
SYNC2
PG2
90
80
POWER LOSS (W)
45.3k
VIN1
Efficiency and Power Loss
(VIN = 12V with Load Between 5V
and –5V Outputs)
CIN2
22μF
D2
VOUT2
–5V
0.7A (VIN = 3V)
1.4A (VIN = 9V)
1.5A (VIN = 16V)
CIN1, CIN2: 22μF, 25V, X7R, 1210
COUT1, COUT2: 22μF, 16V, X7R, 1210
C1, C2: 2.2μF, 50V, X7R, 1206
D1, D2: VISHAY MSS2P3
L1, L2: WÜRTH WE TDC 74489440047
L3, L4: WÜRTH WE TDC 74489440047
8582 TA07a
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT3581
3.3A (ISW), 42V, 2.5MHz, High Efficiency
Step-Up DC/DC Converter
VIN: 2.5V to 22V, VOUT(MAX) = 42V, IQ = 1.9mA, ISD = < 1μA, 4mm × 3mm DFN-14,
MSOP-16E
LT3579
6A (ISW), 42V, 2.5MHz, High Efficiency
Step-Up DC/DC Converter
VIN: 2.5V to 16V, VOUT(MAX) = 42V, IQ = 1.9mA, ISD = < 1μA, 4mm × 5mm QFN-20, TSSOP-20
LT3580
2A (ISW), 42V, 2.5MHz, High Efficiency
Step-Up DC/DC Converter
VIN: 2.5V to 32V, VOUT(MAX) = 42V, IQ = 1mA, ISD = < 1μA, 3mm × 3mm DFN-8, MSOP-8E
LT3471
Dual Output 1.3A (ISW), 1.2MHz, High
Efficiency Step-Up DC/DC Converter
VIN = 2.4V to 16V, VOUT(MAX) = ±40V, IQ = 2.5mA, ISD < 1μA, 3mm × 3mm DFN-10 Package
LT3479
3A (ISW), 40V, 3.5MHz, High Efficiency
Step-Up DC/DC Converter
VIN: 2.5V to 24V, VOUT(MAX) = 40V, IQ = 5mA, ISD = < 1μA, 4mm × 3mm DFN-14, TSSOP-16E
LT3477
40V, 3A, Full Featured DC/DC Converter
VIN = 2.5V to 25V, VOUT(MAX) = 40V, IQ = 5mA, ISD < 1μA, QFN, TSSOP-20E Packages
LT1946/LT1946A 1.5A (ISW), 1.2MHz/2.7MHz, High
Efficiency Step-Up DC/DC Converter
VIN = 2.6V to 16V, VOUT(MAX) = 34V, IQ = 3.2mA, ISD < 1μA, MS8E Package
LT1935
2A (ISW), 40V, 1.2MHz, High Efficiency
Step-Up DC/DC Converter
VIN = 2.3V to 16V, VOUT(MAX) = 40V, IQ = 3mA, ISD < 1μA, ThinSOT™ Package
LT1310
2A (ISW), 40V, 1.2MHz, High Efficiency
Step-Up DC/DC Converter
VIN = 2.3V to 16V, VOUT(MAX) = 40V, IQ = 3mA, ISD < 1μA, ThinSOT Package
LT3436
3A (ISW), 800kHz, 34V Step-Up DC/DC
Converter
VIN = 3V to 25V, VOUT(MAX) = 34V, IQ = 0.9mA, ISD < 6μA, TSSOP-16E Package
8582f
36 Linear Technology Corporation
LT 0112 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
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