10 MHz, 20 V/μs, G = 1, 10, 100, 1000 iCMOS Programmable Gain Instrumentation Amplifier AD8253 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM DGND WR Small package: 10-lead MSOP Programmable gains: 1, 10, 100, 1000 Digital or pin-programmable gain setting Wide supply: ±5 V to ±15 V Excellent dc performance High CMRR: 100 dB (minimum), G = 100 Low gain drift: 10 ppm/°C (maximum) Low offset drift: 1.2 μV/°C (maximum), G = 1000 Excellent ac performance Fast settling time: 780 ns to 0.001% (maximum) High slew rate: 20 V/μs (minimum) Low distortion: −110 dB THD at 1 kHz,10 V swing High CMRR over frequency: 100 dB to 20 kHz (minimum) Low noise: 10 nV/√Hz, G = 1000 (maximum) Low power: 4 mA 2 A0 5 4 LOGIC –IN 1 7 OUT +IN 10 8 3 9 +VS –VS REF 06983-001 AD8253 Figure 1. 80 70 APPLICATIONS 60 Data acquisition Biomedical analysis Test and measurement G = 1000 GAIN (dB) 50 GENERAL DESCRIPTION The AD8253 is an instrumentation amplifier with digitally programmable gains that has gigaohm (GΩ) input impedance, low output noise, and low distortion, making it suitable for interfacing with sensors and driving high sample rate analog-todigital converters (ADCs). The AD8253 user interface consists of a parallel port that allows users to set the gain in one of two different ways (see Figure 1 for the functional block diagram). A 2-bit word sent via a bus can be latched using the WR input. An alternative is to use transparent gain mode, where the state of logic levels at the gain port determines the gain. 40 G = 100 30 20 G = 10 10 0 G=1 –10 –20 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 006983-023 It has a high bandwidth of 10 MHz, low THD of −110 dB, and fast settling time of 780 ns (maximum) to 0.001%. Offset drift and gain drift are guaranteed to 1.2 μV/°C and 10 ppm/°C, respectively, for G = 1000. In addition to its wide input common voltage range, it boasts a high common-mode rejection of 100 dB at G = 1000 from dc to 20 kHz. The combination of precision dc performance coupled with high speed capabilities makes the AD8253 an excellent candidate for data acquisition. Furthermore, this monolithic solution simplifies design and manufacturing and boosts performance of instrumentation by maintaining a tight match of internal resistors and amplifiers. Rev. B A1 6 Figure 2. Gain vs. Frequency Table 1. Instrumentation Amplifiers by Category General Purpose AD82201 AD8221 AD8222 AD82241 AD8228 1 Zero Drift AD82311 AD85531 AD85551 AD85561 AD85571 Mil Grade AD620 AD621 AD524 AD526 AD624 Low Power AD6271 AD6231 AD82231 High Speed PGA AD8250 AD8251 AD8253 Rail-to-rail output. The AD8253 is available in a 10-lead MSOP package and is specified over the −40°C to +85°C temperature range, making it an excellent solution for applications where size and packing density are important considerations. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2008–2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8253 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Supply Regulation and Bypassing ................................ 18 Applications ....................................................................................... 1 Input Bias Current Return Path ............................................... 18 General Description ......................................................................... 1 Input Protection ......................................................................... 18 Functional Block Diagram .............................................................. 1 Reference Terminal .................................................................... 19 Revision History ............................................................................... 2 Common-Mode Input Voltage Range ..................................... 19 Specifications..................................................................................... 3 Layout .......................................................................................... 19 Timing Diagram ........................................................................... 5 RF Interference ........................................................................... 19 Absolute Maximum Ratings............................................................ 6 Driving an Analog-to-Digital Converter ................................ 20 Maximum Power Dissipation ..................................................... 6 Applications Information .............................................................. 21 ESD Caution .................................................................................. 6 Differential Output .................................................................... 21 Pin Configuration and Function Descriptions ............................. 7 Setting Gains with a Microcontroller ...................................... 21 Typical Performance Characteristics ............................................. 8 Data Acquisition ......................................................................... 22 Theory of Operation ...................................................................... 16 Outline Dimensions ....................................................................... 23 Gain Selection ............................................................................. 16 Ordering Guide .......................................................................... 23 REVISION HISTORY 10/12—Rev. A to Rev. B Changed Digital Input Voltage Low Maximum Parameter from 1.2 V to 2.1 V and Changed Digital Input Voltage High Typical Parameter from 1.5 V to 2.8 V ........................................................ 4 Updated Outline Dimensions ....................................................... 23 8/08—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 23 7/08—Revision 0: Initial Version Rev. B | Page 2 of 24 Data Sheet AD8253 SPECIFICATIONS +VS = +15 V, −VS = −15 V, VREF = 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted. Table 2. Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR to 60 Hz with 1 kΩ Source Imbalance G=1 G = 10 G = 100 G = 1000 CMRR to 20 kHz1 G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz, RTI G=1 G = 10 G = 100 G = 1000 0.1 Hz to 10 Hz, RTI G=1 G = 10 G = 100 G = 1000 Current Noise, 1 kHz Current Noise, 0.1 Hz to 10 Hz VOLTAGE OFFSET Offset RTI VOS Over Temperature Average TC Offset Referred to the Input vs. Supply (PSR) INPUT CURRENT Input Bias Current Over Temperature2 Average TC Input Offset Current Over Temperature Average TC DYNAMIC RESPONSE Small-Signal −3 dB Bandwidth G=1 G = 10 G = 100 G = 1000 Settling Time 0.01% G=1 G = 10 G = 100 G = 1000 Conditions Min Typ 80 96 100 100 100 120 120 120 Max Unit +IN = −IN = −10 V to +10 V dB dB dB dB +IN = −IN = −10 V to +10 V 80 96 100 100 dB dB dB dB 45 12 11 10 nV/√Hz nV/√Hz nV/√Hz nV/√Hz 2.5 1 0.5 0.5 μV p-p μV p-p μV p-p μV p-p pA/√Hz pA p-p ±150 + 900/G ±210 + 900/G ±1.2 + 5/G ±5 + 25/G μV μV μV/°C μV/V 50 60 400 40 40 160 nA nA pA/°C nA nA pA/°C 5 60 G = 1, 10, 100, 1000 T = −40°C to +85°C T = −40°C to +85°C VS = ±5 V to ±15 V 5 T = −40°C to +85°C T = −40°C to +85°C 40 5 T = −40°C to +85°C T = −40°C to +85°C 10 4 550 60 MHz MHz kHz kHz ΔOUT = 10 V step 700 680 1.5 14 Rev. B | Page 3 of 24 ns ns μs μs AD8253 Parameter Settling Time 0.001% G=1 G = 10 G =100 G = 1000 Slew Rate G=1 G = 10 G = 100 G = 1000 Total Harmonic Distortion + Noise GAIN Gain Range Gain Error G=1 G = 10, 100, 1000 Gain Nonlinearity G=1 G = 10 G = 100 G = 1000 Gain vs. Temperature INPUT Input Impedance Differential Common Mode Input Operating Voltage Range Over Temperature3 OUTPUT Output Swing Over Temperature4 Short-Circuit Current REFERENCE INPUT RIN IIN Voltage Range Gain to Output DIGITAL LOGIC Digital Ground Voltage, DGND Digital Input Voltage Low Digital Input Voltage High Digital Input Current Gain Switching Time5 tSU tHD t WR -LOW t WR -HIGH Data Sheet Conditions ΔOUT = 10 V step Min Typ Max Unit 780 880 1.8 1.8 ns ns μs μs 20 20 12 2 −110 f = 1 kHz, RL = 10 kΩ, ±10 V, G = 1, 10 Hz to 22 kHz bandpass filter G = 1, 10, 100, 1000 OUT = ±10 V V/μs V/μs V/μs V/μs dB 1 OUT = −10 V to +10 V RL = 10 kΩ, 2 kΩ, 600 Ω RL = 10 kΩ, 2 kΩ, 600 Ω RL = 10 kΩ, 2 kΩ, 600 Ω RL = 10 kΩ, 2 kΩ, 600 Ω All gains 3 1000 V/V 0.03 0.04 % % 5 3 18 110 10 ppm ppm ppm ppm ppm/°C GΩpF GΩpF V V 4||1.25 1||5 VS = ±5 V to ±15 V T = −40°C to +85°C −VS + 1 −VS + 1.2 +VS − 1.5 +VS − 1.7 T = −40°C to +85°C −13.7 −13.7 +13.6 +13.6 37 20 +IN, −IN, REF = 0 1 +VS −VS 1 ± 0.0001 Referred to GND Referred to GND Referred to GND −VS + 4.25 DGND 2.8 0 +VS − 2.7 2.1 +VS 1 325 See Figure 3 timing diagram Rev. B | Page 4 of 24 15 30 20 15 V V mA kΩ μA V V/V V V V μA ns ns ns ns ns Data Sheet AD8253 Parameter POWER SUPPLY Operating Range Quiescent Current, +IS Quiescent Current, −IS Over Temperature TEMPERATURE RANGE Specified Performance Conditions Min Typ Max Unit 4.6 4.5 ±15 5.3 5.3 6 V mA mA mA +85 °C ±5 T = −40°C to +85°C −40 1 See Figure 20 for CMRR vs. frequency for more information on typical performance over frequency. Input bias current over temperature: minimum at hot and maximum at cold. 3 See Figure 30 for input voltage limit vs. supply voltage and temperature. 4 See Figure 32, Figure 33, and Figure 34 for output voltage swing vs. supply voltage and temperature for various loads. 5 Add time for the output to slew and settle to calculate the total time for a gain change. 2 TIMING DIAGRAM tWR-HIGH tWR-LOW WR tSU tHD 06983-003 A0, A1 Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section) Rev. B | Page 5 of 24 AD8253 Data Sheet ABSOLUTE MAXIMUM RATINGS power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some of which is dissipated in the load (VOUT × IOUT). Table 3. Rating ±17 V See Figure 4 Indefinite1 ±VS ±VS ±VS –65°C to +125°C –40°C to +85°C 300°C 140°C 112°C/W 140°C The difference between the total drive power and the load power is the drive power dissipated in the package. PD = Quiescent Power + (Total Drive Power − Load Power) V V PD VS I S S OUT 2 RL VOUT 2 – RL In single-supply operation with RL referenced to −VS, the worst case is VOUT = VS/2. Assumes the load is referenced to midsupply. 2 Temperature for specified performance is −40°C to +85°C. For performance to +125°C, see the Typical Performance Characteristics section. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8253 package is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 140°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8253. Exceeding a junction temperature of 140°C for an extended period can result in changes in silicon devices, potentially causing failure. The still-air thermal properties of the package and PCB (θJA), the ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature is calculated as Airflow increases heat dissipation, effectively reducing θJA. In addition, more metal directly in contact with the package leads from metal traces through holes, ground, and power planes reduces the θJA. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature on a 4-layer JEDEC standard board. 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 –40 –20 0 20 40 60 80 100 120 AMBIENT TEMPERATURE (°C) Figure 4. Maximum Power Dissipation vs. Ambient Temperature ESD CAUTION TJ TA PD θ JA The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent Rev. B | Page 6 of 24 06983-004 1 MAXIMUM POWER DISSIPATION (W) Parameter Supply Voltage Power Dissipation Output Short-Circuit Current Common-Mode Input Voltage Differential Input Voltage Digital Logic Inputs Storage Temperature Range Operating Temperature Range2 Lead Temperature (Soldering 10 sec) Junction Temperature θJA (4-Layer JEDEC Standard Board) Package Glass Transition Temperature Data Sheet AD8253 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –IN 1 DGND 2 10 +IN AD8253 9 REF 8 +VS TOP VIEW A0 4 (Not to Scale) 7 OUT A1 5 6 WR 06983-005 –VS 3 Figure 5. 10-Lead MSOP (RM-10) Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic −IN DGND −VS A0 A1 WR OUT +VS REF +IN Description Inverting Input Terminal. True differential input. Digital Ground. Negative Supply Terminal. Gain Setting Pin (LSB). Gain Setting Pin (MSB). Write Enable. Output Terminal. Positive Supply Terminal. Reference Voltage Terminal. Noninverting Input Terminal. True differential input. Rev. B | Page 7 of 24 AD8253 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS TA @ 25°C, +VS = +15 V, −VS = −15 V, RL = 10 kΩ, unless otherwise noted. 210 240 180 150 NUMBER OF UNITS NUMBER OF UNITS 210 120 90 180 150 120 90 60 60 30 –60 –40 –20 0 0 06983-006 0 20 CMRR (µV/V) –60 –40 –20 0 20 40 60 INPUT OFFSET CURRENT (nA) Figure 6. Typical Distribution of CMRR, G = 1 06983-009 30 Figure 9. Typical Distribution of Input Offset Current 90 180 80 70 120 NOISE (nV/√Hz) NUMBER OF UNITS 150 90 60 60 50 G=1 G = 100 40 30 G = 10 20 30 10 0 –100 100 200 INPUT OFFSET VOLTAGE, VOSI , RTI (µV) 0 G = 1000 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 10. Voltage Spectral Density Noise vs. Frequency Figure 7. Typical Distribution of Offset Voltage, VOSI 250 200 150 50 2µV/DIV 0 –90 –60 –30 0 30 60 INPUT BIAS CURRENT (nA) 90 1s/DIV Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1 Figure 8. Typical Distribution of Input Bias Current Rev. B | Page 8 of 24 06983-011 100 06983-008 NUMBER OF UNITS 300 06983-010 –200 06983-007 0 Data Sheet AD8253 18 16 14 12 10 8 6 4 2 0 0.01 0.1 1 WARM-UP TIME (Minutes) Figure 15. Change in Input Offset Voltage vs. Warm-Up Time, G = 1000 Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1000 140 18 16 120 G = 1000 G = 100 14 100 PSRR (dB) 12 10 8 6 80 G=1 60 G = 10 40 4 10 100 1k 10k 100k FREQUENCY (Hz) 0 10 100 1k 10k 100k 1M 06983-016 1 06983-013 0 1M 06983-017 20 2 FREQUENCY (Hz) Figure 16. Positive PSRR vs. Frequency, RTI Figure 13. Current Noise Spectral Density vs. Frequency 140 G = 100 120 G = 1000 PSRR (dB) 100 80 G = 10 60 40 140pA/DIV 1s/DIV G=1 20 06983-014 NOISE (pA/√Hz) 10 06983-015 06983-012 1s/DIV 500nV/DIV CHANGE IN INPUT OFFSET VOLTAGE (µV) 20 0 10 100 1k 10k 100k FREQUENCY (Hz) Figure 17. Negative PSRR vs. Frequency, RTI Figure 14. 0.1 Hz to 10 Hz Current Noise Rev. B | Page 9 of 24 AD8253 Data Sheet 10.5 IB– 7.5 –20 6.0 –30 4.5 IOS –40 3.0 –50 1.5 –60 –15 –10 –5 0 5 COMMON-MODE VOLTAGE (V) 0 15 10 G = 100 60 G = 10 40 20 G=1 0 10 100 1k 10k 100k 1M 130 FREQUENCY (Hz) Figure 21. CMRR vs. Frequency, 1 kΩ Source Imbalance Figure 18. Input Bias Current and Offset Current vs. Common-Mode Voltage 15 30 25 10 20 5 CMRR (µV/V) 15 10 IB– 5 0 IB+ –5 IOS –10 0 –5 –10 –60 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 –15 –50 06983-019 INPUT BIAS CURRENT AND OFFSET CURRENT (nA) G = 1000 80 06983-018 –10 100 06983-021 9.0 CMRR (dB) 0 INPUT OFFSET CURRENT (nA) IB+ 06983-022 10 –30 10 30 50 70 90 110 TEMPERATURE (°C) Figure 19. Input Bias Current and Offset Current vs. Temperature 120 –10 Figure 22. CMRR vs. Temperature, G = 1 80 G = 1000 70 G = 100 100 60 50 80 GAIN (dB) G=1 60 G = 10 40 40 G = 100 30 20 G = 10 10 0 20 G=1 –10 0 10 100 1k 10k FREQUENCY (Hz) 100k 1M –20 1k 06983-020 CMRR (dB) G = 1000 Figure 20. CMRR vs. Frequency 10k 100k 1M FREQUENCY (Hz) Figure 23. Gain vs. Frequency Rev. B | Page 10 of 24 10M 100M 006983-023 INPUT BIAS CURRENT (nA) 120 12.0 20 AD8253 40 400 30 300 NONLINEARITY (10 ppm/DIV) 20 10 0 –10 –20 –6 –4 –2 0 2 4 6 8 10 –200 –400 –10 30 12 INPUT COMMON-MODE VOLTAGE (V) 16 20 10 0 –10 –20 –6 –4 –2 0 2 4 6 8 10 OUTPUT VOLTAGE (V) Figure 25. Gain Nonlinearity, G = 10, RL = 10 kΩ, 2 kΩ, 600 Ω 8 0 –20 –40 4 6 8 10 –8 10 OUTPUT VOLTAGE (V) Figure 26. Gain Nonlinearity, G = 100, RL = 10 kΩ, 2 kΩ, 600 Ω VS, ±15V –14.1V, +7.3V +13.8V, +7.3V 0V, +3.8V +3.8V, +1.9V VS = ±5V +3.8V, –1.9V 0V, –4.2V –14.1V, –7.3V +13.8V, –7.3V –12 0V, –14.2V –12 –8 –4 0 4 8 12 16 0V, +13.7V VS ±15V 8 –14.4V, +6V 0V, +3.8V +14.1V, +6V 4 –4.3V, +2V +4.3V, +2V VS = ±5V 0 –4.3V, –2V +4.3V, –2V –4 +14.1V, –6V 0V, –4.2V –14.4V, –6V –8 –12 –16 –16 06983-026 –60 2 8 OUTPUT VOLTAGE (V) INPUT COMMON-MODE VOLTAGE (V) 20 0 6 Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, G = 1 40 –2 4 0V, +13.9V –4V, –1.9V 12 –4 2 –4 60 –6 0 –4V, +1.9V 16 –8 –2 0 80 –80 –10 –4 4 –16 –16 06983-025 –30 –8 –6 Figure 27. Gain Nonlinearity, G = 1000, RL = 10 kΩ, 2 kΩ, 600 Ω 40 –40 –10 –8 OUTPUT VOLTAGE (V) Figure 24. Gain Nonlinearity, G = 1, RL = 10 kΩ, 2 kΩ, 600 Ω NONLINEARITY (10ppm/DIV) –100 06983-028 –8 OUTPUT VOLTAGE (V) NONLINEARITY (10ppm/DIV) 0 –300 06983-024 –40 –10 100 06983-027 –30 200 0V, –14.1V –12 –8 –4 0 4 OUTPUT VOLTAGE (V) 8 12 16 06983-029 NONLINEARITY (10ppm/DIV) Data Sheet Figure 29. Input Common-Mode Voltage Range vs. Output Voltage, G = 1000 Rev. B | Page 11 of 24 AD8253 Data Sheet +VS +85°C –0.2 –2 +25°C –40°C +2 +25°C –40°C +1 +125°C –VS 4 8 10 12 16 14 Figure 30. Input Voltage Limit vs. Supply Voltage, G = 1, VREF = 0 V, RL = 10 kΩ 25 +IN –IN –IN –40°C –40°C +25°C +85°C +0.8 +0.6 +0.4 +125°C –VS 4 6 8 10 12 16 14 SUPPLY VOLTAGE (±VS) Figure 33. Output Voltage Swing vs. Supply Voltage, G =1000, RL = 10 kΩ +25°C 10 5 +IN +25°C +1.0 OUTPUT VOLTAGE SWING (V) CURRENT (mA) +85°C +85°C +Vs –5 –10 –1.0 15 FAULT CONDITION (OVER-DRIVEN INPUT) G=1000 FAULT CONDITION (OVER-DRIVEN INPUT) 15 G=1000 20 0 –0.8 +0.2 SUPPLY VOLTAGE (±VS) 10 –0.6 +85°C 6 +125°C –0.4 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES –1 06983-033 +125°C 06983-030 INPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES +VS –Vs –15 –40°C 5 +125°C 0 +85°C –5 +125°C +25°C –10 Figure 34. Output Voltage Swing vs. Load Resistance +VS +VS –0.2 –40°C +25°C +85°C +125°C –0.4 –0.4 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES +125°C –0.6 –0.8 –1.0 –1.2 +85°C +25°C –40°C +1.2 –40°C +85°C +25°C +1.0 +0.8 +0.6 +125°C +0.4 –0.8 –1.2 –1.6 –2.0 +2.0 +1.6 +1.2 +0.8 +0.4 4 6 8 10 12 SUPPLY VOLTAGE (±VS) 14 16 06983-032 +0.2 Figure 32. Output Voltage Swing vs. Supply Voltage, G = 1000, RL = 2 kΩ Rev. B | Page 12 of 24 –VS 4 6 8 10 12 14 OUTPUT CURRENT (mA) Figure 35. Output Voltage Swing vs. Output Current 16 06983-035 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES 10k 1k LOAD RESISTANCE (Ω) Figure 31. Fault Current Draw vs. Input Voltage, G = 1000, RL = 10 kΩ –VS –40°C 06983-034 10 –15 100 06983-031 DIFFERENTIAL INPUT VOLTAGE (V) 1 100m 10m 1m 100µ –10µ/ 10µ –100µ –1m –10m –100m –10 –25 –1 –20 Data Sheet AD8253 5V/DIV NO LOAD 47pF 100pF 1392ns TO 0.01% 1712ns TO 0.001% 2µs/DIV 2µs/DIV TIME (µs) Figure 36. Small-Signal Pulse Response for Various Capacitive Loads, G = 1 06983-039 20mV/DIV 06983-036 0.002%/DIV Figure 39. Large-Signal Pulse Response and Settling Time, G = 100, RL = 10 kΩ 5V/DIV 664ns TO 0.01% 744ns TO 0.001% 0.002%/DIV 0.002%/DIV TIME (µs) 10µs/DIV 06983-037 2µs/DIV 12.88µs TO 0.01% 16.64µs TO 0.001% TIME (µs) Figure 37. Large-Signal Pulse Response and Settling Time, G = 1, RL = 10 kΩ 06983-040 5V/DIV Figure 40. Large-Signal Pulse Response and Settling Time, G = 1000, RL = 10 kΩ 5V/DIV 656ns TO 0.01% 840ns TO 0.001% TIME (µs) 20mV/DIV 06983-038 2µs/DIV 2µs/DIV Figure 41. Small-Signal Response, G = 1, RL = 2 kΩ, CL = 100 Figure 38. Large-Signal Pulse Response and Settling Time, G = 10, RL = 10 kΩ Rev. B | Page 13 of 24 06983-041 0.002%/DIV AD8253 Data Sheet 1400 1200 1000 TIME (ns) SETTLED TO 0.001% 800 600 SETTLED TO 0.01% 400 2 4 6 8 10 12 14 16 18 20 06983-045 0 20 06983-046 200 20 06983-047 2µs/DIV 06983-042 20mV/DIV STEP SIZE (V) Figure 42. Small-Signal Response, G = 10, RL = 2 kΩ, CL = 100 pF Figure 45. Settling Time vs. Step Size, G = 1, RL = 10 kΩ 1400 1200 TIME (ns) 1000 SETTLED TO 0.001% 800 SETTLED TO 0.01% 600 400 20µs/DIV 200 06983-043 20mV/DIV 0 2 4 6 8 10 12 14 16 18 STEP SIZE (V) Figure 43. Small-Signal Response, G = 100, RL = 2 kΩ, CL = 100 pF Figure 46. Settling Time vs. Step Size, G = 10, RL = 10 kΩ 2000 SETTLED TO 0.001% 1800 1600 1400 TIME (ns) SETTLED TO 0.01% 1200 1000 800 600 20mV/DIV 20µs/DIV 06983-044 400 200 0 2 4 6 8 10 12 14 16 18 STEP SIZE (V) Figure 44. Small-Signal Response, G = 1000, RL = 2 kΩ, CL = 100 pF Figure 47. Settling Time vs. Step Size, G = 100, RL = 10 kΩ Rev. B | Page 14 of 24 Data Sheet AD8253 0 20 18 –10 SETTLED TO 0.001% –20 16 –30 –40 12 THD + N (dB) SETTLED TO 0.01% 10 8 –50 G = 1000 –60 G = 100 –70 G = 10 –80 6 –90 4 –110 0 –120 10 2 4 6 8 10 12 14 16 18 20 06983-048 2 STEP SIZE (V) 0 –20 –30 –40 –50 G = 1000 –70 G = 100 –80 G = 10 –90 –100 G=1 100 1k 10k 100k FREQUENCY (Hz) 1M 06983-049 –110 –120 10 1k 10k 100k Figure 50. Total Harmonic Distortion vs. Frequency, 10 Hz to 500 kHz Band-Pass Filter, 2 kΩ Load –10 –60 100 FREQUENCY (Hz) Figure 48. Settling Time vs. Step Size, G = 1000, RL = 10 kΩ THD + N (dB) G=1 –100 Figure 49. Total Harmonic Distortion vs. Frequency, 10 Hz to 22 kHz Band-Pass Filter, 2 kΩ Load Rev. B | Page 15 of 24 1M 06983-050 TIME (µs) 14 AD8253 Data Sheet THEORY OF OPERATION +VS +VS A0 A1 2.2kΩ +VS –VS –VS 1.2kΩ –IN 10kΩ A1 10kΩ –VS +VS DIGITAL GAIN CONTROL OUT A3 –VS +VS +VS +IN 10kΩ A2 +VS –VS 10kΩ REF –VS +VS 2.2kΩ DGND WR –VS 06983-061 1.2kΩ –VS Figure 51. Simplified Schematic The AD8253 is a monolithic instrumentation amplifier based on the classic 3-op-amp topology, as shown in Figure 51. It is fabricated on the Analog Devices, Inc., proprietary iCMOS® process that provides precision linear performance and a robust digital interface. A parallel interface allows users to digitally program gains of 1, 10, 100, and 1000. Gain control is achieved by switching resistors in an internal precision resistor array (as shown in Figure 51). All internal amplifiers employ distortion cancellation circuitry and achieve high linearity and ultralow THD. Laser-trimmed resistors allow for a maximum gain error of less than 0.03% for G = 1 and a minimum CMRR of 100 dB for G = 1000. A pinout optimized for high CMRR over frequency enables the AD8253 to offer a guaranteed minimum CMRR over frequency of 80 dB at 20 kHz (G = 1). The balanced input reduces the parasitics that in the past had adversely affected CMRR performance. Transparent Gain Mode The easiest way to set the gain is to program it directly via a logic high or logic low voltage applied to A0 and A1. Figure 52 shows an example of this gain setting method, referred to throughout the data sheet as transparent gain mode. Tie WR to the negative supply to engage transparent gain mode. In this mode, any change in voltage applied to A0 and A1 from logic low to logic high, or vice versa, immediately results in a gain change. Table 5 is the truth table for transparent gain mode, and Figure 52 shows the AD8253 configured in transparent gain mode. +15V 10μF 0.1µF WR A1 A0 +IN –15V +5V +5V G = 1000 AD8253 GAIN SELECTION REF Rev. B | Page 16 of 24 –IN DGND 10μF DGND 0.1µF –15V NOTE: 1. IN TRANSPARENT GAIN MODE, WR IS TIED TO −VS. THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE SET TO LOGIC HIGH, RESULTING IN A GAIN OF 1000. 06983-051 This section describes how to configure the AD8253 for basic operation. Logic low and logic high voltage limits are listed in the Specifications section. Typically, logic low is 0 V and logic high is 5 V; both voltages are measured with respect to DGND. Refer to the specifications table (Table 2) for the permissible voltage range of DGND. The gain of the AD8253 can be set using two methods: transparent gain mode and latched gain mode. Regardless of the mode, pull-up or pull-down resistors should be used to provide a well-defined voltage at the A0 and A1 pins. Figure 52. Transparent Gain Mode, A0 and A1 = High, G = 1000 Data Sheet AD8253 Table 5. Truth Table Logic Levels for Transparent Gain Mode Table 6. Truth Table Logic Levels for Latched Gain Mode WR WR A1 Low Low High High −VS −VS −VS −VS A0 Low High Low High Gain 1 10 100 1000 Latched Gain Mode Some applications have multiple programmable devices such as multiplexers or other programmable gain instrumentation amplifiers on the same PCB. In such cases, devices can share a data bus. The gain of the AD8253 can be set using WR as a latch, allowing other devices to share A0 and A1. Figure 53 shows a schematic using this method, known as latched gain mode. The AD8253 is in this mode when WR is held at logic high or logic low, typically 5 V and 0 V, respectively. The voltages on A0 and A1 are read on the downward edge of the WR signal as it transitions from logic high to logic low. This latches in the logic levels on A0 and A1, resulting in a gain change. See the truth table listing in Table 6 for more on these gain changes. +15V WR 10μF 0.1µF A1 A1 A0 +IN +5V 0V +5V 0V WR + A0 G = PREVIOUS STATE +5V 0V G = 1000 AD8253 REF – –IN DGND 0.1µF –15V NOTE: 1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0 AND A1 ARE READ AND LATCHED IN, RESULTING IN A GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 1000. 1 A0 Low High Low High X1 X1 X1 Gain Change to 1 Change to 10 Change to 100 Change to 1000 No change No change No change X = don’t care. On power-up, the AD8253 defaults to a gain of 1 when in latched gain mode. In contrast, if the AD8253 is configured in transparent gain mode, it starts at the gain indicated by the voltage levels on A0 and A1 on power-up. Timing for Latched Gain Mode In latched gain mode, logic levels at A0 and A1 must be held for a minimum setup time, tSU, before the downward edge of WR latches in the gain. Similarly, they must be held for a minimum hold time, tHD, after the downward edge of WR to ensure that the gain is latched in correctly. After tHD, A0 and A1 may change logic levels, but the gain does not change until the next downward edge of WR. The minimum duration that WR can be held high is t WR -HIGH, and t WR -LOW is the minimum duration that WR can be held low. Digital timing specifications are listed in Table 2. The time required for a gain change is dominated by the settling time of the amplifier. A timing diagram is shown in Figure 54. When sharing a data bus with other devices, logic levels applied to those devices can potentially feed through to the output of the AD8253. Feedthrough can be minimized by decreasing the edge rate of the logic signals. Furthermore, careful layout of the PCB also reduces coupling between the digital and analog portions of the board. DGND 06983-052 10μF High to Low High to Low High to Low High to Low Low to Low Low to High High to High A1 Low Low High High X1 X1 X1 Figure 53. Latched Gain Mode, G = 1000 tWR-HIGH tWR-LOW WR tSU tHD 06983-053 A0, A1 Figure 54. Timing Diagram for Latched Gain Mode Rev. B | Page 17 of 24 AD8253 Data Sheet INCORRECT POWER SUPPLY REGULATION AND BYPASSING The AD8253 has high PSRR. However, for optimal performance, a stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. As in all linear circuits, bypass capacitors must be used to decouple the amplifier. REF –VS –VS TRANSFORMER TRANSFORMER +VS +VS 10µF WR A1 A0 AD8253 AD8253 REF VOUT 10MΩ LOAD –VS REF –IN –VS THERMOCOUPLE DGND THERMOCOUPLE +VS 10µF –VS +VS C 06983-054 0.1µF REF C 1 fHIGH-PASS = 2πRC AD8253 Figure 55. Supply Decoupling, REF, and Output Referred to Ground C REF INPUT BIAS CURRENT RETURN PATH The AD8253 input bias current must have a return path to its local analog ground. When the source, such as a thermocouple, cannot provide a return current path, one should be created (see Figure 56). R AD8253 C REF R –VS –VS CAPACITIVELY COUPLED CAPACITIVELY COUPLED 06983-055 AD8253 DGND AD8253 REF +VS +IN +VS AD8253 Place a 0.1 μF capacitor close to each supply pin. A 10 μF tantalum capacitor can be used farther away from the part (see Figure 55) and, in most cases, it can be shared by other precision integrated circuits. 0.1µF CORRECT +VS Figure 56. Creating an IBIAS Path INPUT PROTECTION All terminals of the AD8253 are protected against ESD. An external resistor should be used in series with each of the inputs to limit current for voltages greater than 0.5 V beyond either supply rail. In such a case, the AD8253 safely handles a continuous 6 mA current at room temperature. For applications where the AD8253 encounters extreme overload voltages, external series resistors and low leakage diode clamps such as BAV199Ls, FJH1100s, or SP720s should be used. Rev. B | Page 18 of 24 Data Sheet AD8253 REFERENCE TERMINAL Coupling Noise The reference terminal, REF, is at one end of a 10 kΩ resistor (see Figure 51). The instrumentation amplifier output is referenced to the voltage on the REF terminal; this is useful when the output signal needs to be offset to voltages other than its local analog ground. For example, a voltage source can be tied to the REF pin to level shift the output so that the AD8253 can interface with a single-supply ADC. The allowable reference voltage range is a function of the gain, common-mode input, and supply voltages. The REF pin should not exceed either +VS or −VS by more than 0.5 V. To prevent coupling noise onto the AD8253, follow these guidelines: For best performance, especially in cases where the output is not measured with respect to the REF terminal, source impedance to the REF terminal should be kept low because parasitic resistance can adversely affect CMRR and gain accuracy. INCORRECT CORRECT AD8253 Do not run digital lines under the device. Run the analog ground plane under the AD8253. Shield fast-switching signals with digital ground to avoid radiating noise to other sections of the board, and never run them near analog signal paths. Avoid crossover of digital and analog signals. Connect digital and analog ground at one point only (typically under the ADC). Power supply lines should use large traces to ensure a low impedance path. Decoupling is necessary; follow the guidelines listed in the Power Supply Regulation and Bypassing section. Common-Mode Rejection The AD8253 has high CMRR over frequency, giving it greater immunity to disturbances, such as line noise and its associated harmonics, in contrast to typical in amps whose CMRR falls off around 200 Hz. They often need common-mode filters at the inputs to compensate for this shortcoming. The AD8253 is able to reject CMRR over a greater frequency range, reducing the need for input common-mode filtering. AD8253 VREF VREF + 06983-056 OP1177 – Figure 57. Driving the Reference Pin COMMON-MODE INPUT VOLTAGE RANGE The 3-op-amp architecture of the AD8253 applies gain and then removes the common-mode voltage. Therefore, internal nodes in the AD8253 experience a combination of both the gained signal and the common-mode signal. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. Figure 28 and Figure 29 show the allowable common-mode input voltage ranges for various output voltages, supply voltages, and gains. LAYOUT Grounding In mixed-signal circuits, low level analog signals need to be isolated from the noisy digital environment. Designing with the AD8253 is no exception. Its supply voltages are referenced to an analog ground. Its digital circuit is referenced to a digital ground. Although it is convenient to tie both grounds to a single ground plane, the current traveling through the ground wires and PC board can cause an error. Therefore, use separate analog and digital ground planes. Only at one point, star ground, should analog and digital ground meet. Careful board layout maximizes system performance. To maintain high CMRR over frequency, lay out the input traces symmetrically. Ensure that the traces maintain resistive and capacitive balance; this holds for additional PCB metal layers under the input pins and traces. Source resistance and capacitance should be placed as close to the inputs as possible. Should a trace cross the inputs (from another layer), it should be routed perpendicular to the input traces. RF INTERFERENCE RF rectification is often a problem when amplifiers are used in applications where there are strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 58. The filter limits the input signal bandwidth according to the following relationship: FilterFreq DIFF FilterFreq CM where CD ≥ 10 CC. The output voltage of the AD8253 develops with respect to the potential on the reference terminal. Take care to tie REF to the appropriate local analog ground or to connect it to a voltage that is referenced to the local analog ground. Rev. B | Page 19 of 24 1 2 π R( 2C D C C ) 1 2 π RC C AD8253 Data Sheet +15V 10µF CC R +IN VOUT AD8253 CD R REF –IN CC 0.1µF –15V 06983-057 10µF +15V Figure 58. RFI Suppression 10μF Values of R and CC should be chosen to minimize RFI. Mismatch between the R × CC at the positive input and the R × CC at negative input degrades the CMRR of the AD8253. By using a value of CD that is 10 times larger than the value of CC, the effect of the mismatch is reduced and performance is improved. DRIVING AN ANALOG-TO-DIGITAL CONVERTER 0.1µF WR A1 +12V –12V A0 +IN 0.1μF 0.1μF 49.9Ω AD8253 REF AD7612 1nF +5V –IN ADR435 DGND 10μF An instrumentation amplifier is often used in front of an analogto-digital converter to provide CMRR. Usually, instrumentation amplifiers require a buffer to drive an ADC. However, the low output noise, low distortion, and low settle time of the AD8253 make it an excellent ADC driver. Rev. B | Page 20 of 24 DGND 0.1µF 06983-058 0.1µF In this example, a 1 nF capacitor and a 49.9 Ω resistor create an antialiasing filter for the AD7612. The 1 nF capacitor also serves to store and deliver necessary charge to the switched capacitor input of the ADC. The 49.9 Ω series resistor reduces the burden of the 1 nF load from the amplifier and isolates it from the kickback current injected from the switched capacitor input of the AD7612. Selecting too small a resistor improves the correlation between the voltage at the output of the AD8253 and the voltage at the input of the AD7612 but may destabilize the AD8253. A tradeoff must be made between selecting a resistor small enough to maintain accuracy and large enough to maintain stability. –15V Figure 59. Driving an ADC Data Sheet AD8253 APPLICATIONS INFORMATION DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER +15V In certain applications, it is necessary to create a differential signal. High resolution analog-to-digital converters often require a differential input. In other cases, transmission over a long distance can require differential signals for better immunity to interference. 10μF 0.1µF WR A1 A0 +IN Figure 61 shows how to configure the AD8253 to output a differential signal. An op amp, the AD8675, is used in an inverting topology to create a differential voltage. VREF sets the output midpoint according to the equation shown in the figure. Errors from the op amp are common to both outputs and are thus common mode. Likewise, errors from using mismatched resistors cause a common-mode dc offset error. Such errors are rejected in differential signal processing by differential input ADCs or instrumentation amplifiers. MICROCONTROLLER + AD8253 REF – –IN DGND DGND 0.1µF 06983-059 10μF –15V Figure 60. Programming Gain Using a Microcontroller When using this circuit to drive a differential ADC, VREF can be set using a resistor divider from the ADC reference to make the output ratiometric with the ADC. +15V 0.1μF AMPLITUDE WR +5V A1 A0 +IN –5V AMPLITUDE + VOUTA = VIN + VREF 2 AD8253 VIN G=1 – 0.1μF +2.5V 0V –2.5V REF TIME 4.99kΩ DGND – –15V 4.99kΩ –15V 56pF + AD8675 +15V VREF 0V AMPLITUDE 10μF 0.1µF –15V 0.1µF 10μF DGND VOUTB = –VIN + VREF 2 Figure 61. Differential Output with Level Shift Rev. B | Page 21 of 24 +2.5V 0V –2.5V TIME 06983-060 +15V Data Sheet DATA ACQUISITION AMPLITUDE (dB) The AD8253 makes an excellent instrumentation amplifier for use in data acquisition systems. Its wide bandwidth, low distortion, low settling time, and low noise enable it to condition signals in front of a variety of 16-bit ADCs. Figure 63 shows the AD825x as part of a total data acquisition system. The quick slew rate of the AD8253 allows it to condition rapidly changing signals from the multiplexed inputs. An FPGA controls the AD7612, AD8253, and ADG1209. In addition, mechanical switches and jumpers allow users to pin strap the gains when in transparent gain mode. This system achieved −116 dB of THD at 1 kHz and a signal-tonoise ratio of 91 dB during testing, as shown in Figure 62. 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (kHz) Figure 62. FFT of the AD825x in a Total Data Acquisition System Using the AD8253 1 kHz Signal JMP +12V + +12V 0.1µF 10µF +CH2 +CH3 +CH4 –CH4 –CH3 –CH2 –CH1 806Ω 806Ω 806Ω 806Ω 806Ω 806Ω 806Ω 4 S1A +5V 2kΩ 10µF 2 EN DGND DGND JMP +5V DGND 5 S2A 2kΩ 2 6 S3A ALTERA EPF6010ATC144-3 DGND 6 7 S4A 0Ω DA 8 0Ω CC +IN 10 ADG1209 10 S4B 11 S3B DB 9 12 S2B GND 15 A0 13 –VS S1B A1 VSS 16 0Ω 0Ω CD –IN CC 1 + 5 WR A1 4 A0 AD8253 REF – +VS –VS 9 3 VOUT +IN 0Ω 49.9Ω AD7612 1nF C4 0.1µF C3 0.1µF 3 7 ADR435 8 1 DGND +12V –12V JMP 0.1µF –12V +5V 2kΩ DGND JMP +5V R8 2kΩ 06983-067 +CH1 VDD JMP –12V GND 14 806Ω + DGND Figure 63. Schematic of ADG1209, AD8253, and AD7612 Used with the AD825x in a Total Data Acquisition System Rev. B | Page 22 of 24 06983-062 AD8253 Data Sheet AD8253 OUTLINE DIMENSIONS 3.10 3.00 2.90 3.10 3.00 2.90 10 5.15 4.90 4.65 6 1 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 6° 0° 0.70 0.55 0.40 0.23 0.13 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 64. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model1 AD8253ARMZ AD8253ARMZ-RL AD8253ARMZ-R7 AD8253-EVALZ 1 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board Z = RoHS Compliant Part. Rev. B | Page 23 of 24 Package Option RM-10 RM-10 RM-10 Branding Y0K Y0K Y0K AD8253 Data Sheet NOTES ©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06983-0-10/12(B) Rev. B | Page 24 of 24