doc7832

AT65609EHV
Rad Hard, 5V, 128K x 8 Very Low Power CMOS SRAM
DATASHEET
Features
z Asynchronous SRAM
z Operating Voltage: 5V
z Read Access Time: 40 ns
z Write Cycle Time: 30 ns
z Very Low Power Consumption (Pre-RAD)
z
z
Active: 275 mW (Max)
Standby: 44 mW (Max)
z Wide Temperature Range: -55°C to +125°C
z 400 Mils Width Packages: FP32 and SB32
z TTL Compatible Inputs and Outputs
z No Single Event Latch-up below a LET Threshold of 80 [email protected]°C
z Radiation Tolerance(1)
z
z
Tested up to a Total Dose of 300 krads (Si)
RHA capability of 100 krad (Si) according to MIL STD 883 Method 1019
z ESD better than 4000V
z Deliveries at least equivalent to QML procurement according to MIL-PRF38535
z Pin to pin compatible with M65608E
Note:
1.
tolerance to MBU’s may need to be enhanced by the application
Description
The AT65609EHV is a very low power CMOS static RAM organized as 131072 x 8 bits.
Utilizing an array of six transistors (6T) memory cells, the AT65609EHV combines an
extremely low standby supply current with a fast access time over the full military
temperature range. The high stability of the 6T cell provides an excellent protection
against soft errors due to noise.
The AT65609EHV is processed according to the methods of the latest revision of the
MIL PRF 38535 or ESCC 9000.
It is manufactured on the same process as the MH1RT Rad-Hard sea of gates series.
7832E–AERO–09/14
Table of Contents
1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.1
4.2
4.3
4.4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Military Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5
5
5
5. DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5.1
5.2
DC Test Conditions (Pre and Post-Radiation) . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6. AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.1
6.2
6.3
6.4
6.5
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Test Loads Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.3.1
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
6.3.2
Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Write Cycle (Pre and Post-Radiation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.4.1
Write Cycle 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
6.4.2
Write Cycle 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
6.4.3
Write Cycle 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Read Cycle (Pre and Post-Radiation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.5.1
Read Cycle 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6.5.2
Read Cycle 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
6.5.3
Read Cycle 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8. Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.1
8.2
32-lead Flat Pack 400 Mils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
32-lead Side Brazed 400 Mils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AT65609EHV [DATASHEET]
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1.
Block Diagram
Vcc
I/O0
GND
1024 ROWS
COLUMN DECODER
A5
A6
A7
A8
A9
A11
A13
A14
A15
A16
MEMORY ARRAY
1024x128x8
INPUT
DATA
CIRCUIT
I/O7
128 COLUMNS
COLUMN DECODER
A0
A1
A2
A3
A4
A10
A12
CS1
OE
CONTROL
CIRCUIT
WE
CS2
2.
Pin Assignment
Figure 2-1. 32-lead DIL side-brazed or 32-lead Flat Pack - 400 Mils
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
Note:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
NC pin is not bonded internally and can be connected to GND or VCC.
AT65609EHV [DATASHEET]
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3.
Pin Description
Table 3-1.
Pin Names
Names
Description
A0 - A16
Address inputs
I/O0 - I/O7
Data Inputs/Outputs
CS1
Chip select 1
CS2
Chip select 2
WE
Write Enable
OE
Output Enable
VCC
Power
GND
Power
Table 3-2.
Truth Table
CS1
CS2
WE
OE
Inputs/ Outputs
H
X
X
X
Z
Deselect/Power-down
X
L
X
X
Z
Deselect/Power-down
L
H
H
L
Data Out
Read
L
H
L
X
Data In
Write
L
H
H
H
Z
Note:
Mode
Output Disable
L = low, H = high, X = H or L, Z = high impedance.
AT65609EHV [DATASHEET]
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4.
Electrical Characteristics
4.1
Absolute Maximum Ratings
*NOTE: Stresses beyond those listed under "Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions beyond those
indicated in the operational sections of this
specification is not implied. Exposure
between recommended DC operating and
absolute maximum rating conditions for
extended periods may affect device
reliability.
Supply voltage to GND potential:-0.5V + 7.0V
DC input voltage:GND - 0.5V to VCC + 0.5
DC output voltage high Z state:GND - 0.5V to VCC + 0.5
Storage temperature:-65°C to +150°C
Output current from output pins (low):20 mA
Electro Static Discharge voltage with HBM method
(MIL STD 883D method 3015): > 4000V
Electro Static Discharge voltage with Socketed CDM
method (ANSI/ESD SP5.3.2-2004): > 1000V
4.2
4.3
4.4
Military Operating Range
Operating Voltage
Operating Temperature
5V + 10%
-55°C to + 125°C°
Recommended DC Operating Conditions
Parameter
Description
Min
Typ
Max
Unit
VCC
Supply voltage
4.5
5.0
5.5
V
Gnd
Ground
0.0
0.0
0.0
V
VIL
Input low voltage
GND - 0.5
0.0
0.8
V
VIH
Input high voltage
2.2
–
VCC + 0.5
V
Capacitance
Parameter
Description
Cin(1)
Cout(1)
Note:
Max
Unit
Input low voltage
8
pF
Output high voltage
8
pF
1. Guaranteed but not tested.
AT65609EHV [DATASHEET]
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5.
DC Parameters
5.1
DC Test Conditions (Pre and Post-Radiation)
TA = -55°C to + 125°C; GND = 0V; VCC = 4.5V to 5.5V
5.2
Symbol
Description
Test Conditions
Min
Max
Unit
IIX
Input leakage current
-3
3
µA
IOZ
Output leakage current
GND <= Vin <= VCC,
GND <= Vout <= VCC,
Output Disabled.
-3
3
µA
VOL
Output low voltage
VCC min. IOL = 8 mA
–
0.4
V
VOH
Output high voltage
VCC min. IOH = -4 mA.
2.4
–
V
Power Consumption
Symbol
ICCSB
Description
Standby supply current
(SMD Conditions)
Test Conditions
TAVAV/
TAVAW
Max
Unit
Pre-RAD
Post-RAD
8
70
mA
7
65
mA
2
60 (2)
mA
VCC max, F=0 Hz,
CS1 >= VIH ,
CS2 <= VIL ,
VCC max, F=0 Hz,
ICCSB1
Standby supply current
(SMD Conditions)
CS1 >= VCC - 0.2V,
CS2 <= GND + 0.2V,
Inputs=VIH or VIL,
VCC max, F=0 Hz,
ICCSB1
Standby supply current
(Standard Conditions)
CS1 >= VCC - 0.2V,
CS2 <= GND + 0.2V,
Inputs=GND or VCC
ICCOPR
Dynamic operating current
(READ)
VCC max,
40 ns(1)
50
115
mA
F = 1/TAVAV,
Iout = 0 mA,
CS1=VIL,
50 ns(2)
45
110
mA
100 ns(2)
40
105
mA
OE=WE=CS2=VIH
250 ns(2)
25
90
mA
35 ns(2)
50
115
mA
40 ns(1)
45
110
mA
50 ns(2)
40
105
mA
100 ns(2)
30
95
mA
250 ns(2)
25
90
mA
VCC max,
ICCOPW
Note:
Dynamic operating current
(WRITE)
F = 1/TAVAW,
Iout = 0 mA,
OE=CS2=VIH
WE=CS1=VIL
1.
Parameters guaranteed and tested
2.
Parameters guaranteed but not tested.
AT65609EHV [DATASHEET]
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6.
AC Parameters
6.1
Test Conditions
Input Pulse Levels: ............................................................................................................................. GND to 3.0V
Supply Voltage: ............................................................................................................................................5 +0.5V
Input Timing Reference Levels: ........................................................................................................................1.5V
6.2
Test Loads Waveforms
Figure 6-1. Test Loads
View A
View B
Figure 6-2. CMOS Input pulses
6.3
Data Retention Mode
Atmel CMOS RAM’s are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention:
1. During data retention chip select CS1 must be held high within VCC to VCC -0.2V or, chip select CS2 must
be held down within GND to GND +0.2V.
2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, minimizing power
dissipation.
3. During power up and power-down transitions CS1 and OE must be kept between VCC + 0.3V and 70% of
VCC, or with CS2 between GND and GND -0.3V.
4. The RAM can begin operation > TR ns after VCC reaches the minimum operation voltages (4.5V).
AT65609EHV [DATASHEET]
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6.3.1
Timing
6.3.2
Data Retention Characteristics
Parameter
Description
Conditions
Min
Typ
TA = 25 °C
Max
Pre-RAD
Post-RAD
Unit
VCCDR
VCC for data retention
2.0
–
–
V
TCDR
Chip deselect to data retention
time
0.0
–
–
ns
TR
Operation recovery time
TAVAV(1)
–
–
ns
ICCDR1
Data retention current at 2.0V
–
0.1
1
40
mA
–
0.2
1.5
55
mA
CS1 >= VCC-0.2V
CS2 <= 0.2V
ICCDR2
Note:
Data retention current at 3.0V(2)
F= 0 Hz,
All other inputs =
0.2V or VCC-0.2V
1.
TAVAV = Read Cycle Time
2.
Parameters guaranteed, not tested.
AT65609EHV [DATASHEET]
7832E–AERO–09/14
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6.4
Write Cycle (Pre and Post-Radiation)
Symbol
Parameter
TAVAW
Write cycle time
30
ns
TAVWL
Address set-up time
0
ns
TAVWH
Address valid to end of write
28
ns
TDVWH
Data set-up time
15
ns
TE1LWH
CS1 low to write end
28
ns
TE2HWH
CS2 high to write end
28
ns
TWLQZ
Write low to high Z(1)
TWLWH
Write pulse width
26
ns
TWHAX
Address hold from to end of write
3
ns
TWHDX
Data hold time
0
ns
TWHQX
Write high to low Z(1)
5
ns
Note:
6.4.1
1.
Min
Max
Unit
8
ns
Parameters guaranteed, not tested, with output loading 5 pF (see view B on Figure 6-1 on page 7).
Write Cycle 1
WE Controlled, OE High During Write
AT65609EHV [DATASHEET]
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6.4.2
Write Cycle 2
WE Controlled, OE Low
6.4.3
Write Cycle 3
CS1 or CS2 Controlled
Note:
The internal write time of the memory is defined by the overlap of CS1 Low and CS2 HIGH and WE LOW. Both signals
must be actived to initiate a write and either signal can terminate a write by going in actived. The data input setup and
hold timing should be referenced to the actived edge of the signal that terminates the write. Data out is high impedance
if OE = VIH.
AT65609EHV [DATASHEET]
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6.5
Read Cycle (Pre and Post-Radiation)
Symbol
Parameter
TAVAV
Read cycle time
TAVQV
Address access time
TAVQX
Address valid to low Z
TE1LQV
Chip-select1 access time
TE1LQX
CS1 low to low Z(1)
TE1HQZ
CS1 high to high Z(1)
12
ns
TE2HQV
Chip-select2 access time
40
ns
TE2HQX
CS2 high to low Z(1)
TE2LQZ
CS2 low to high Z(1)
12
ns
TGLQV
Output Enable access time
10
ns
TGLQX
OE low to low Z(1)
TGHQZ
OE high to high Z(1)
Note:
6.5.1
1.
Min
Max
40
Unit
ns
40
3
ns
ns
40
3
ns
ns
3
ns
0
ns
10
ns
Parameters guaranteed, not tested, with output loading 5 pF (see view B on Figure 6-1 on page 7).
Read Cycle 1
Address Controlled (CS1 = OE Low, CS2 = WE High)
AT65609EHV [DATASHEET]
7832E–AERO–09/14
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6.5.2
Read Cycle 2
CS1 Controlled (CS2 = WE High)
6.5.3
Read Cycle 3
CS2 Controlled (WE High, CS1 Low)
AT65609EHV [DATASHEET]
7832E–AERO–09/14
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7.
Ordering Information
Part Number
Temperature Range
Speed
Package
AT65609EHV-C940-E
25°C
40 ns
SB32.4
AT65609EHV-DJ40-E
25°C
40 ns
FP32.4
5962-8959849QZC
-55° to +125°C
40 ns
SB32.4
5962-8959849QTC
-55° to +125°C
40 ns
FP32.4
5962-8959849VZC
-55° to +125°C
40 ns
SB32.4
5962-8959849VTC
-55° to +125°C
40 ns
FP32.4
5962R8959849VZC
-55° to +125°C
40 ns
SB32.4
5962R8959849VTC
-55° to +125°C
40 ns
FP32.4
Test Flow
Engineering Samples
QML Q
QML V
QML V RHA
AT65609EHV [DATASHEET]
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8.
Package Drawings
8.1
32-lead Flat Pack 400 Mils
AT65609EHV [DATASHEET]
7832E–AERO–09/14
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8.2
32-lead Side Brazed 400 Mils
AT65609EHV [DATASHEET]
7832E–AERO–09/14
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9.
Revision History
Doc. Rev.
Date
Comments
Update: SMD part-numbers added in ordering information section
E
09/2014
Update: Footnote of 40 ns item changed in ICCOPW parameter in Power Consumption
Section 5.2
Add-on: MBU’s note in features section
D
11/2013
Update: radiation tolerance specifications in features section
Update: Block Diagram
Update: AC Test conditions section
Update: final datasheet release including characterization data
C
09/2013
Add-on: pre and post-RAD specifications
Update: document template
Update: total dose value in features section
Add-on: ESD item in features section
B
11/2009
Add-on: ESD HBM improved and ESD Socketed CDM in Absolute Maximum Ratings
Update: note 3 of Consumption Table
Update: ordering information section
A
03/2009
Initial document release.
FunctionZZ_Summary Notes
AT65609EHV [DATASHEET]
7832E–AERO–09/14
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