doc7791

Features
• Operating Voltage: 5V
• Access Time: 40ns
• Very Low Power Consumption
– Active: 440mW (Max)
– Standby: 10mW (Typ)
• Wide Temperature Range: -55°C to +125°C
• 600 Mils Width Package: SB28
• TTL Compatible Inputs and Outputs
• Asynchronous
• No Single Event Latch-up below a LET Threshold of 80 [email protected]°C
• Radiation Tolerance(1)
– Tested up to a Total Dose of 300 krads (Si)
– RHA capability of 100 krad (Si) according to MIL STD 883 Method 1019
• ESD better than 4000V
• Deliveries at least equivalent to QML procurement according to MIL-PRF38535
• AT65609EHW is pin to pin compatible with MA9264 device from DYNEX
Note:
1. tolerance to MBU’s may need to be enhanced by the application
Description
The AT65609EHW is a very low power CMOS static RAM organized as 8192 x 8 bits.
Rad. Tolerant
8K x 8 - 5 volts
Very Low Power
CMOS SRAM
AT65609EHW
Using an array of six transistors (6T) memory cells, the AT65609EHW combines an
extremely low standby supply current with a fast access time at 40 ns over the full military temperature range. The high stability of the 6T cell provides excellent protection
against soft errors due to noise.
The AT65609EHW is processed according to the methods of the latest revision of the
MIL PRF 38535.
It is manufactured on the same process as the MH1RT RAD-hard sea of gates series.
7791D–AERO–11/13
Block Diagram
Vcc
A4
A5
A7
A8
A9
A11
A12
COLUMN DECODER
I/O0
INPUT
DATA
CIRCUIT
128 ROWS
I/O7
GND
MEMORY ARRAY
128x64x8
64 COLUMNS
COLUMN DECODER
A0
A1
A2
A3
A6
A10
CS1
OE
CONTROL
CIRCUIT
WE
CE
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
Note:
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-lead DIL side-brazed 600 Mils
Pin Assignment
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE
CE
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
NC pin is not bonded internally. So, it can be connected to GND or VCC.
AT65609EHW
7791D–AERO–11/13
AT65609EHW
Pin Description
Table 1. Pin Names
Names
Description
A0 - A12
Address inputs
I/O0 - I/O7
Data Input/Output
CS1
Chip select
CE
Chip Enable
WE
Write Enable
OE
Output Enable
VCC
Power
GND
Ground
Table 2. Truth Table
CS1
CE
WE
OE
Inputs/ Outputs
H
X
X
X
Z
Deselect / Power-down
X
L
X
X
Z
Deselect / power-down
L
H
H
L
Data Out
Read
L
H
L
X
Data In
Write
L
H
H
H
Z
Note:
Mode
Output Disable
L = low, H = high, X = H or L, Z = high impedance.
3
7791D–AERO–11/13
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential:..........................-0.5V + 7.0V
*NOTE:
DC input voltage: ..............................GND - 0.3V to VCC + 0.3
DC output voltage high Z state: ........GND - 0.3V to VCC + 0.3
Storage temperature: .......................................-65⋅C to +150⋅C
Output current into outputs (low): .................................. 20 mA
Electro Static Discharge voltage with HBM method
(MIL STD 883D method 3015):................................... > 4000V
Stresses beyond those listed under "Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the
device at these or any other conditions
beyond those indicated in the operational
sections of this specification is not implied.
Exposure between recommended DC
operating and absolute maximum rating conditions for extended periods
may affect device reliability.
Electro Static Discharge voltage with Socketed CDM method
(ANSI/ESD SP5.3.2-2004) :........................................ > 1000V
Military Operating Range
Operating Voltage
Operating Temperature
5V + 10%
-55°C to + 125°C
Recommended DC Operating Conditions
Parameter
Description
Minimum
Typical
Maximum
Unit
VCC
Supply voltage
4.5
5.0
5.5
V
GND
Ground
0.0
0.0
0.0
V
VIL
Input low voltage
GND - 0.3
0.0
0.8
V
VIH
Input high voltage
2.2
–
VCC + 0.3
V
Parameter
Description
Minimum
Typical
Maximum
Unit
Cin(1)
Input low voltage
–
–
8
pF
Cout(1)
Output high voltage
–
–
8
pF
Capacitance
Note:
4
1. Guaranteed but not tested.
AT65609EHW
7791D–AERO–11/13
AT65609EHW
DC Parameters
DC Test Conditions
TA = -55°C to + 125°C; Vss = 0V; VCC = 4.5V to 5.5V
Symbol
Description
Minimum
Typical
Maximum
Unit
IIX (1)
Input leakage current
-10
–
10
µA
IOZ (1)
Output leakage current
-10
–
10
µA
VOL (2)
Output low voltage
–
–
0.4
V
VOH (3)
Output high voltage
2.4
–
–
V
1.
GND < Vin < VCC, GND < Vout < VCC Output Disabled.
2.
3.
VCC min. IOL = 8 mA
VCC min. IOH = -4 mA.
Consumption
Symbol
Description
AT65609EHW
Unit
Value
ICCSB (1)
Standby supply current
5
mA
max
ICCSB1 (2)
Standby supply current
3
mA
max
ICCOP (3)
Dynamic operating current
80
mA
max
1.
2.
3.
CS1 > VIH or CE < VIL and CS1 < VIL.
CS1 > VCC - 0.3V or, CE < GND + 0.3V and CS1 < 0.2V.
F = 1/TAVAV, Iout = 0 mA, WE = OE = Vcc, Vin = GND or VCC, VCC max, CS1=Vil, CE=Vih
5
7791D–AERO–11/13
AC Parameters
Test Conditions
Temperature Range................................................................................................. -55 +125 °C
Supply Voltage: .............................................................................................................. 5 +0.5V
Input and Output Timing Reference Levels ......................................................................... 1.5V
Test Loads and Waveforms
Figure 1. Test Loads
View A
View B
Figure 2. CMOS Input Pulses
6
AT65609EHW
7791D–AERO–11/13
AT65609EHW
Data Retention Mode
Atmel CMOS RAM’s are designed with battery backup in mind. Data retention voltage and
supply current are guaranteed over temperature. The following rules ensure data retention:
1. During data retention chip select CS1 must be held high within VCC to VCC -0.2V or,
chip select CE must be held down within GND to GND +0.2V.
2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, minimizing power dissipation.
3. During power up and power-down transitions CS1 and OE must be kept between VCC +
0.3V and 70% of VCC, or with CE between GND and GND -0.3V.
4. The RAM can begin operation > TR ns after VCC reaches the minimum operation voltages (4.5V).
Timing
Data Retention Characteristics
Minimum
Typical
TA = 25 °C
Maximum
Unit
VCC for data retention
2.0
–
–
V
TCDR
Chip deselect to data retention time
0.0
–
–
ns
TR
Operation recovery time
TAVAV(1)
–
–
ns
ICCDR1(2) Data retention current at 2.0V
–
1
1.5
mA
ICCDR2(2) Data retention current at 3.0V
–
1.5
2
mA
Parameter
Description
VCCDR
Notes:
1. TAVAV = Read Cycle Time
2. CS1 = VCC or CE = CS1 = GND, Vin = GND/VCC, this parameter is only tested at
VCC = 2V.
7
7791D–AERO–11/13
Write Cycle
Symbol
Parameter
AT65609EHW
Unit
Value
TAVAW
Write cycle time
40
ns
min
TAVWL
Address set-up time
0
ns
min
TAVWH
Address valid to end of write
35
ns
min
TDVWH
Data set-up time
22
ns
min
TE1LWH
CS1 low to write end
35
ns
min
TE2HWH
CE high to write end
35
ns
min
TWLQZ
Write low to high Z(1)
17
ns
max
TWLWH
Write pulse width
35
ns
min
TWHAX
Address hold from to end of write
3
ns
min
TWHDX
Data hold time
0
ns
min
TWHQX
Write high to low Z(1)
0
ns
min
Note:
Write Cycle 1
8
1. Parameters guaranteed, not tested, with output loading 5 pF (See view B on Figure 1 on page
6)
WE Controlled, OE High During Write
AT65609EHW
7791D–AERO–11/13
AT65609EHW
Write Cycle 2
WE Controlled, OE Low
Write Cycle 3
CS1 or CE Controlled
Note:
The internal write time of the memory is defined by the overlap of CS1 Low and CE HIGH and WE
LOW. Both signals must be actived to initiate a write and either signal can terminate a write by
going in actived. The data input setup and hold timing should be referenced to the actived edge of
the signal that terminates the write. Data out is high impedance if OE = VIH.
9
7791D–AERO–11/13
Read Cycle
Symbol
Parameter
AT65609EHW
Unit
Value
TAVAV
Read cycle time
40
ns
min
TAVQV
Address access time
40
ns
max
TAVQX
Address valid to low Z(1)
3
ns
min
TE1LQV
Chip-select1 access time
40
ns
max
TE1LQX
CS1 low to low Z(1)
3
ns
min
TE1HQZ
CS1 high to high Z(1)
15
ns
max
TE2HQV
Chip-select2 access time
40
ns
max
TE2HQX
CE high to low Z(1)
3
ns
min
TE2LQZ
CE low to high Z(1)
15
ns
max
TGLQV
Output Enable access time
15
ns
max
TGLQX
OE low to low Z(1)
0
ns
min
TGHQZ
OE high to high Z(1)
10
ns
max
Note:
10
1. Parameters Guaranteed, not tested, with output loading 5 pF (See view B on Figure 1 on page
6)
AT65609EHW
7791D–AERO–11/13
AT65609EHW
Read Cycle 1
Address Controlled (CS1 = OE Low, CE = WE High)
Read Cycle 2
CS1 Controlled (CE = WE High)
Read Cycle 3
CE Controlled (WE High, CS1 Low)
11
7791D–AERO–11/13
Ordering Information
Atmel Reference
Part Number
Temperature Range
Speed
Package
25⋅C
40ns
SB28.6
Engineering Samples
AT65609EHW-CI40MQ
-55⋅ to +125⋅C
40ns
SB28.6
Mil Level B
AT65609EHW-CI40SV
-55⋅ to +125⋅C
40ns
SB28.6
Space Level B
AT65609EHW-CI40SR
-55⋅ to +125⋅C
40ns
SB28.6
Space Level B RHA
AT65609EHW-CI40-E
12
Flow
AT65609EHW
7791D–AERO–11/13
AT65609EHW
Package Drawing
28-lead Side Braze 600 Mils
D
28
15
M
LEAD N°1
14
INDEX MARK
A2
A
A1
H
c
b
e
Ref
A
A1
A2
b
c
D
D1
e
e1
H
M
Min.
3.73
1.02
2.47
0.41
0.23
35.20
32.89
2.41
14.99
14.86
Millimeters
Nom.
3.99
1.27
2.73
0.46
0.25
35.56
33.02
2.54
15.24
15.11
e1
(AT STAND OFF)
D1
Inches
Max.
Min.
Nom.
Max.
0.157
0.167
4.24 0.147
0.050
0.060
1.52 0.040
2.98 0.0974 0.1074 0.1174
0.018
0.020
0.51 0.016
0.010
0.012
0.30 0.009
1.400
1.414
35.92 1.386
1.300
1.305
33.15 1.295
0.100
0.105
2.67 0.095
0.600
0.610
15.49 0.590
0.217
5.51
0.595
0.605
15.37 0.585
13
7791D–AERO–11/13
Document Revision History
Changes from 7791A to 7791B
1. Update: total dose value in features section
2. Update: note 3 of consumption table
Changes from 7791B to 7791C
1. Add-on: ESD item in features section
2. Update: ESD HBM in Absolute Maximum Ratings
3. Add-on: ESD Socketed CDM in Absolute Maximum Ratings
4. Update: ordering Information section
5. Update: package drawing
Changes from 7791C to 7791D
1. Add-on: MBU’s note in features section
2. Update: radiation tolerance in features section
3. Update: block diagram
4. Update: AC Test conditions section
14
AT65609EHW
7791D–AERO–11/13
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7791D–AERO–11/13
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