doc7842

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16 Mbit SRAM Multi Chip Module
Allows 32-, 16- or 8-bit access configuration
Operating Voltage: 3.3V + 0.3V
Access Time
– 20 ns
– 18 ns
Power Consumption
– Active: 620 mW per byte (Max) @ 18ns - 415 mW per byte (Max) @ 50ns (1)
– Standby: 13 mW (Typ)
Military Temperature Range: -55 to +125⋅C
TTL-Compatible Inputs and Outputs
Asynchronous
Die manufactured on Atmel 0.25 µm Radiation Hardened Process
No Single Event Latch Up below LET Threshold of 80 [email protected]°C
Tested up to a Total Dose of 300 krads (Si) according to MIL-STD-883 Method 1019
ESD better than 4000V
Quality Grades:
– QML-Q or V
– ESCC
950 Mils Wide MQFPT68 Package
Mass : 8.5 grams
Note:
Rad Hard
16 MegaBit 3.3V
SRAM MultiChip Module
AT68166H
1. Only for AT68166H-18. 450mW for AT68166H-20.
Description
The AT68166H is a 16Mbit SRAM packaged in a hermetic Multi Chip Module
(MCM) for space applications.
The AT68166H MCM incorporates four 4Mbit AT60142H SRAM dice. It can be organized as either one bank of 512Kx8, two banks of 512Kx16 or four banks of 512Kx8. It
combines rad-hard capabilities, a latch-up threshold of 80MeV.cm²/mg, a Multiple Bit
Upset immunity and a total dose tolerance of 300Krads, with a fast access time.
The MCM packaging technology allows a reduction of the PCB area by 50% with a
weight savings of 75% compared to four 4Mbit packages.
Thanks to the small size of the 4Mbit SRAM die, Atmel has been able to accommodate the assembly of the four dice on one side of the package which facilitates the
power dissipation.
The compatibility with other products allows designers to easily migrate to the Atmel
AT68166H memory.
The AT68166H is powered at 3.3V.
The AT68166H is processed according to the test methods of the latest revision of the
MIL-PRF-38535 or the ESCC 9000.
7842D–AERO–11/13
Block Diagram
AT68166H Block Diagram
A[18:0]
CS3
WE3
CS2
WE2
CS1
WE1
CS0
WE0
OE
BANK3
BANK2
BANK1
BANK0
512k x 8
512k x 8
512k x 8
512k x 8
I/O[31:24]
or
I/O1[31:24]
or
I/O3[31:24]
I/O[23:16]
or
I/O1[23:16]
or
I/O2[31:24]
I/O[15:8]
or
I/O0[31:24]
or
I/O1[31:24]
I/O[7:0]
or
I/O0[23:16]
or
I/O0[31:24]
512K x 8 Bank Block Diagram (AT60142H)
I/Ox0
I/Ox7
CSx
OE
WEx
2
AT68166H
7842D–AERO–11/13
AT68166H
Pin Configuration
AT68166H is packaged in a MQFPT68. The pin assignment depends on the access time.
There are 2 versions as described in the table below :
Access Time
Package Version
18 ns
20 ns
YS
YM
Table 1. Pin assignment for YS & YM versions
Lead
Signal
Lead
Signal
Lead
Signal
Lead
Signal
1
I/O0[0]
18
VCC
35
I/O3[7]
52
VCC
2
I/O0[1]
19
A11
36
I/O3[6]
53
A10
3
I/O0[2]
20
A12
37
I/O3[5]
54
A9
4
I/O0[3]
21
A13
38
I/O3[4]
55
A8
5
I/O0[4]
22
A14
39
I/O3[3]
56
A7
6
I/O0[5]
23
A15
40
I/O3[2]
57
A6
7
I/O0[6]
24
A16
41
I/O3[1]
58
WE0
8
I/O0[7]
25
CS0
42
I/O3[0]
59
CS3
9
GND
26
OE
43
GND
60
GND
10
I/O1[0]
27
CS1
44
I/O2[7]
61
CS2
11
I/O1[1]
28
A17
45
I/O2[6]
62
A5
12
I/O1[2]
29
WE1
46
I/O2[5]
63
A4
13
I/O1[3]
30
WE2
47
I/O2[4]
64
A3
14
I/O1[4]
31
WE3
48
I/O2[3]
65
A2
15
I/O1[5]
32
A18
49
I/O2[2]
66
A1
50
I/O2[1]
67
A0
51
I/O2[0]
16
I/O1[6]
33
17
I/O1[7]
34
YS
GND
YM
NC
YS
VCC
YM
NC
68
YS
VCC
YM
NC
3
7842D–AERO–11/13
AT68166H
(top view)
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
I/O2[0]
I/O2[1]
I/O2[2]
I/O2[3]
I/O2[4]
I/O2[5]
I/O2[6]
I/O2[7]
GND
I/O3[0]
I/O3[1]
I/O3[2]
I/O3[3]
I/O3[4]
I/O3[5]
I/O3[6]
I/O3[7]
VCC
A11
A12
A13
A14
A15
A16
CS0
OE
CS1
A17
WE1
WE2
WE3
A18
NC
NC
I/O0[0]
I/O0[1]
I/O0[2]
I/O0[3]
I/O0[4]
I/O0[5]
I/O0[6]
I/O0[7]
GND
I/O1[0]
I/O1[1]
I/O1[2]
I/O1[3]
I/O1[4]
I/O1[5]
I/O1[6]
I/O1[7]
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
NC
A0
A1
A2
A3
A4
A5
CS2
GND
CS3
WE0
A6
A7
A8
A9
A10
VCC
Figure 1. YM package pin assignment
Note:
NC pins are not bonded internally. So, they can be connected to GND or Vcc.
AT68166H
(top view)
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
I/O2[0]
I/O2[1]
I/O2[2]
I/O2[3]
I/O2[4]
I/O2[5]
I/O2[6]
I/O2[7]
GND
I/O3[0]
I/O3[1]
I/O3[2]
I/O3[3]
I/O3[4]
I/O3[5]
I/O3[6]
I/O3[7]
VCC
A11
A12
A13
A14
A15
A16
CS0
OE
CS1
A17
WE1
WE2
WE3
A18
GND
VCC
I/O0[0]
I/O0[1]
I/O0[2]
I/O0[3]
I/O0[4]
I/O0[5]
I/O0[6]
I/O0[7]
GND
I/O1[0]
I/O1[1]
I/O1[2]
I/O1[3]
I/O1[4]
I/O1[5]
I/O1[6]
I/O1[7]
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
VCC
A0
A1
A2
A3
A4
A5
CS2
GND
CS3
WE0
A6
A7
A8
A9
A10
VCC
Figure 2. YS package pin assignment
4
AT68166H
7842D–AERO–11/13
AT68166H
Pin Description
Table 2. Pin Names
Name
Description
A0 - A18
Address Inputs
I/O0 - I/O31
Data Input/Output
CS0 - CS3
Chip Select
WE0 - WE3
Write Enable
OE
Output Enable
VCC
Power Supply
GND(1)
Note:
Ground
1. The package lid is connected to GND
Table 3. Truth Table(1)
CSx
WEx
OE
Inputs/Outputs
Mode
H
X
X
Z
Standby
L
H
L
Data Out
Read
L
L
X
Data In
Write
L
H
H
Z
Output Disable
Note:
1. L=low, H=high, X= H or L, L=high impedance.
5
7842D–AERO–11/13
Electrical Characteristics
Absolute Maximum Ratings*
Supply Voltage to GND Potential: ....................... -0.5V + 4.6V
Stresses beyond those listed under "Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the
device at these or any other conditions
beyond those indicated in the operational
sections of this specification is not implied.
Exposure between recommended DC
operating and absolute maximum rating
conditions for extended periods may
affect device reliability.
*NOTE:
Voltage range on any input: ...................... GND -0.5V to 4.6V
Voltage range on any ouput: ..................... GND -0.5V to 4.6V
Storage Temperature: ................................... -65⋅C to + 150⋅C
Output Current from Output Pins: ................................ 20 mA
Electrostatic Discharge Voltage: ............................... > 4000V
(MIL STD 883D Method 3015)
Military Operating Range
Operating Voltage
Operating Temperature
3.3 + 0.3V
-55⋅°C to + 125⋅°C
Recommended DC Operating Conditions
Parameter
Description
Min
Typ
Max
Unit
Vcc
Supply voltage
3.0
3.3
3.6
V
GND
Ground
0.0
0.0
0.0
V
VIL
Input low voltage
GND - 0.3
0.0
0.8
V
VIH
Input high voltage
2.2
–
VCC + 0.3
V
Capacitance
Parameter
Description
Min
Typ
Max
Unit
Cin(1) (OE and Ax)
Input capacitance
–
–
48
pF
Cin(1) (CSx and WEx)
Input capacitance
–
–
12
pF
Cio(1)
I/O capacitance
–
–
12
pF
Note:
6
1. Guaranteed but not tested.
AT68166H
7842D–AERO–11/13
AT68166H
DC Parameters
DC Test Conditions
TA = -55°C to + 125°C; Vss = 0V; VCC = 3.0V to 3.6V
Parameter
Minimum
Typical
Maximum
Unit
Input leakage current
-1
–
1
μA
Output leakage current
-1
–
1
μA
VOL(2)
Output low voltage
–
–
0.4
V
VOH(3)
Output high voltage
2.4
–
–
V
IIX(1)
IOZ
Notes:
(1)
Description
1. GND < VIN < VCC, GND < VOUT < VCC Output Disabled.
2. VCC min, -IOL = 8 mA
3. VCC min, IOH = -4 mA
Consumption
TAVAV/TAVAW
Test Condition
AT68166H-20
AT68166H-18
Unit
Value
Standby Supply Current
–
10
7
mA
max
Standby Supply Current
–
8
6
mA
max
Dynamic Operating Current
18 ns
20 ns
50 ns
1 µs
–
170
85
15
170
165
80
12
mA
max
Dynamic Operating Current
18 ns
20 ns
50 ns
1 µs
–
150
125
110
145
140
115
105
mA
max
Symbol
Description
ICCSB(1)
ICCSB1(2)
ICCOP(3) Read per byte
ICCOP(4) Write per byte
Notes:
1.
2.
3.
4.
All CSx >VIH
All CSx > VCC - 0.3V
F = 1/TAVAV, Iout = 0 mA, WEx = OE = VIH, VIN = GND/VCC, VCC max.
F = 1/TAVAW, Iout = 0 mA, WEx = VIL, OE = VIH , VIN = GND/VCC, VCC max.
7
7842D–AERO–11/13
Data Retention Mode
Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention:
1. During data retention chip select CSx must be held high within VCC to VCC -0.2V.
2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, minimizing power dissipation.
3. During power-up and power-down transitions CSx and OE must be kept between VCC +
0.3V and 70% of VCC.
4. The RAM can begin operation > tR ns after VCC reaches the minimum operation voltages
(3V).
Figure 3. Data Retention Timing
vcc
CSx
Data Retention Characteristics
Parameter Description
Min
Typ TA = 25⋅C
Max
Unit
VCCDR
VCC for data retention
2.0
–
–
V
tCDR
Chip deselect to data retention time
0.0
–
–
ns
–
–
ns
tR
ICCDR (2)
1.
2.
8
Operation recovery time
Data retention current
tAVAV
–
(1)
3
6
(AT68166H-20)
4.5
(AT68166H-18)
mA
TAVAV = Read cycle time.
All CSx = VCC, VIN = GND/VCC.
AT68166H
7842D–AERO–11/13
AT68166H
AC Characteristics
Test Conditions
Temperature Range:................................................................................................ -55 +125 °C
Supply Voltage: ........................................................................................................... 3.3 +0.3V
Input and Output Timing Reference Levels: ........................................................................ 1.5V
Test Loads and Waveforms
Figure 4. Test Loads
VCC
R L = 50 Ω
DUT
ZO = 50 Ω
VL = 1.5V
30pF
Figure 5. Test Loads specific to TWLQZ, TWHQX, TELQX, TEHQZ, TGLQX, TGHQZ
VCC
V CC
R 1 = 319 Ω
V L = 1.5V
DUT
R 2 = 353 Ω
5pF
Figure 6. CMOS Input Pulses
3.0V
GND
90%
10%
Rise time > 3 ns
90%
10%
Fall time > 3 ns
9
7842D–AERO–11/13
Write Cycle
Table 4. Write cycle timings(1)
AT68166H-18
min
max
min
max
Unit
Symbol
Parameter
TAVAW
Write cycle time
20
-
18
-
ns
TAVWL
Address set-up time
2
-
2
-
ns
TAVWH
Address valid to end of write
14
-
11
-
ns
TDVWH
Data set-up time
9
-
8
-
ns
TELWH
CS low to write end
12
-
12
-
ns
TWLQZ
Write low to high Z(2)
-
10
-
8
ns
TWLWH
Write pulse width
12
-
9
-
ns
TWHAX
Address hold from end of write
0
-
0
-
ns
TWHDX
Data hold time
2
-
1
-
ns
TWHQX
Write high to low Z(2)
5
-
3
-
ns
Notes:
Write Cycle 1.
AT68166H-20
1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode.
2. Parameters guaranteed, not tested, with output loading 5 pF. (See “Test Loads and Waveforms” on page 9.)
WE Controlled, OE High During Write
ADDRESS
CSx
E
WEx E
OE
I/Os
10
AT68166H
7842D–AERO–11/13
AT68166H
Write Cycle 2.
WE Controlled, OE Low
ADDRESS
CSx
WEx E
E
I/Os
Write Cycle 3.
CS Controlled
ADDRESS
CSx
WEx E
I/Os
Note:
The internal write time of the memory is defined by the overlap of CS Low and WE LOW. Both signals must be activated to initiate a write and either signal can terminate a write by going in active
mode. The data input setup and hold timing should be referenced to the active edge of the signal
that terminates the write.
Data out is high impedance if OE= VIH.
11
7842D–AERO–11/13
Read Cycle
Table 5. Read cycle timings(1)
AT68166H-18
min
max
min
max
Unit
20
-
18
-
ns
Symbol
Parameter
TAVAV
Read cycle time
TAVQV
Address access time
-
20
-
18
ns
TAVQX
Address valid to low Z
5
-
5
-
ns
TELQV
Chip-select access time
-
20
-
18
ns
TELQX
CS low to low Z(2)
5
-
5
-
ns
TEHQZ
CS high to high Z(2)
-
9
-
8
ns
TGLQV
Output Enable access time
-
11
-
8
ns
TGLQX
OE low to low Z(2)
2
-
2
-
ns
TGHQZ
OE high to high Z (2)
-
9
-
8
ns
Notes:
Read Cycle 1
AT68166H-20
1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode.
2. Parameters guaranteed, not tested, with output loading 5 pF. (See “Test Loads and Waveforms” on page 9.)
Address Controlled (CS = OE = VIL, WE = VIH)
ADDRESS
DOUT
Read Cycle 2
Chip Select Controlled (WE = VIH)
CSx
OE
DOUT
12
AT68166H
7842D–AERO–11/13
AT68166H
Typical Applications
This section shows standard implementations of the AT68166H in applications.
32-bit mode
application
When used on a 32-bit (word) application, the module shall be connected as follow :
•
The 32 lines of data are connected to distinct data lines
•
The four CSx are connected together and linked to a single host CS output
•
Each of the four WEx is connected to a dedicated WE line on the host to allow byte, half
word and word format write.
Figure 7. 32-bit typical application (one SRAM bank)
AT68166H
RAMS0*
RAMOE0*
CS[3:0]
OE
A
A[17:0]
I/O3[7:0]
RWE0*
WE3
RWE1*
WE2
I/O2[7:0]
RWE2*
WE1
I/O1[7:0]
WE0
I/O0[7:0]
RWE3*
TSC695F
D[31:24]
D[23:16]
D[15:8]
D[7:0]
A[19:2]
A[27:0]
D[31:0]
D[31:0]
16-bit mode
application
D
A[19:2]
When used on a 16-bit (half word) application, the module can be connected as presented in the
following figure. This allows the use of a single AT68166H part for two SRAM memory banks.
All input controls of the AT68166H not used in the application shall be pulled-up.
Figure 8. 16-bit typical application (two SRAM banks)
RAMOE[1:0]*
RAMS1*
RWE0*
RAMS0*
RWE1*
TSC695F
OE
AT68166H
A
A[17:0]
CS[3:2]
I/O3[7:0]
WE3
WE1
CS[1:0]
I/O2[7:0]
I/O1[7:0]
I/O0[7:0]
WE2
WE0
D[31:24]
D[23:16]
D[31:24]
D[23:16]
A[18:1]
A[27:0]
D[31:0]
D[31:0]
8-bit mode
application
D
A[18:1]
When used on a 8-bit (byte) application, the module can be connected as presented in the following figure. This allows the use of a single AT68166H part for up to four SRAM memory banks.
All input controls of the AT68166H not used in the application shall be pulled-up.
Figure 9. 8-bit typical application (four SRAM banks)
AT68166H
RAMOE[3:0]*
RWE0*
TSC695F
OE
A
A[17:0]
WE[3:0]
RAMS3*
CS3
I/O3[7:0]
RAMS2*
CS2
I/O2[7:0]
RAMS1*
CS1
I/O1[7:0]
RAMS0*
CS0
I/O0[7:0]
A[27:0]
D[31:0]
D
A[17:0]
D[31:24]
D[31:24]
D[31:24]
D[31:24]
A[17:0]
D[31:0]
13
7842D–AERO–11/13
Ordering Information
Part Number
Temperature Range
Speed
Package
Flow
AT68166H-YM20-E
25⋅C
20 ns
MQFPT68
Engineering Samples
5962-0622908QXC
-55⋅ to +125⋅C
20 ns
MQFPT68
QML Q
5962-0622908VXC
-55⋅ to +125⋅C
20 ns
MQFPT68
QML V
5962R0622908VXC
-55⋅ to +125⋅C
20 ns
MQFPT68
QML V RHA
AT68166H-YM20-SCC(1)
-55⋅ to +125⋅C
20 ns
MQFPT68
ESCC
AT68166H-YS18-E
25⋅C
18 ns
MQFPT68
Engineering Samples
5962-0622906QYC
-55⋅ to +125⋅C
18 ns
MQFPT68
QML Q
5962-0622906VYC
-55⋅ to +125⋅C
18 ns
MQFPT68
QML V
-55⋅ to +125⋅C
18 ns
MQFPT68
QML V RHA
-55⋅ to +125⋅C
18 ns
MQFPT68
ESCC
5962R0622906VYC
AT68166H-YS18-SCC
Notes:
14
(1)
1. Will be replaced by ESCC part number when available.
AT68166H
7842D–AERO–11/13
AT68166H
Package Drawing
68-lead Quad Flat Pack (950 Mils) with non conductive tie bar
Note:
1. Lid is connected to Ground.
2. YM and YS package drawings are identical.
15
7842D–AERO–11/13
Document Revision History
Creation from AT66168F without any change.
Changes from Rev. A to Rev. B
Update: “AT68166H Block Diagram” section : updated
Update: “Package drawings” section : updated
Update: “Typical applications” section : figures updated
Addition: SMD part-numbers for 18 ns versions (YS package) in “Ordering Information” section
Changes from Rev. B to Rev. C
Update: “Block Diagram” section
Update: Figures in “Typical applications” section
Addition: SMD part-numbers for 20 ns versions (YM package) in “Ordering Information” section
Changes from Rev. C to Rev. D
Update: Test Conditions, Test Loads and Waveforms in “AC Characteristics” section
16
AT68166H
7842D–AERO–11/13
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International
Atmel Corporation
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