CN-0200: 18-Bit, Linear, Low Noise, Precision Bipolar ±10 V DC Voltage Source

Circuit Note
CN-0200
Devices Connected/Referenced
AD5780
Circuits from the Lab™ reference circuits are engineered and
tested for quick and easy system integration to help solve today’s
analog, mixed-signal, and RF design challenges. For more
information and/or support, visit www.analog.com/CN0200.
True 18-Bit, Voltage Output DAC
Ultraprecision, 36 V, 2.8 nV√Hz,
Rail-to-Rail Output Op Amp
Ultraprecision, 36 V, 2.8 nV√Hz, Dual
Rail-to-Rail Output Op Amp
Ultralow Noise 5V LDO XFET® Voltage
Reference
AD8675
AD8676
ADR445
18-Bit, Linear, Low Noise, Precision Bipolar ±10 V DC Voltage Source
EVALUATION AND DESIGN SUPPORT
amount of external components. The AD5780 DAC is an 18-bit,
unbuffered voltage output DAC operating from a bipolar supply
of up to 33 V. The AD5780 accepts a positive reference input
range of 5 V to VDD − 2.5 V, and a negative reference input
range of VSS + 2.5 V to 0 V. Both reference inputs are buffered
on the chip, and external buffers are not required. The AD5780
offers a relative accuracy specification of ±1 LSB maximum, and
operation is guaranteed monotonic, with a ±1 LSB maximum
DNL specification.
Circuit Evaluation Boards
AD5780 Circuit Evaluation Board (EVAL-AD5780SDZ)
System Demonstration Platform (EVAL-SDP-CB1Z)
Design and Integration Files
Schematics, Layout Files, Bill of Materials
CIRCUIT FUNCTION AND BENEFITS
The circuit shown in Figure 1 is an 18-bit linear, low noise,
precision bipolar (±10 V) voltage source with a minimum
+15V
10µF
+
+15V
0.1µF
VIN VOUT
ADR445
GND
R1
1.5kΩ
0.1µF
+ C1
10µF
AD8675
+3.3V +15V
R2*
R3*
1kΩ
+10V
A1
1kΩ
–15V
10µF
+
10µF
+
0.1µF
0.1µF
9
SPI INTERFACE
AND DIGITAL
COTNROL
8
3
2
IOVCC VCC VDD
6
CLR
7
LDAC
11
SDO
14
SYNC
13
SCLK
12
SDIN
4
RESET
VREFP
20
RFB
BUFFERED
VREFP 6.8kΩ
+15V
6.8kΩ
INV
AD8675
24
A2
VOUT 1
AD5780
–10V TO +10V
OUTPUT
VOLTAGE
–15V
DGND
VSS
VREFN
AGND
15
17
16
19
0V TO +10V
0.1µF
+
09697-001
*FOR OPTIMUM PERFORMANCE OVER TEMPERATURE,
R2 AND R3 SHOULD BE IN A SINGLE PACKAGE.
10µF
–15V
Figure 1. 18-Bit Accurate, +10 V Voltage Source (Simplified Schematic: All Connections and Decoupling Not Shown)
Rev.0
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©2011 Analog Devices, Inc. All rights reserved.
CN-0200
Circuit Note
This combination of parts provides industry-leading 18-bit
integral nonlinearity (INL) of ±1 LSB and differential
nonlinearity (DNL) of ±0.75 LSB, with guaranteed
monotonicity, as well as low power, small PCB area, and
cost effectiveness in an LFCSP package.
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
0
50000
100000
150000
200000
250000
DAC CODE
09697-002
The digital input to the circuit is serial and is compatible with
standard SPI, QSPI, MICROWIRE®, and DSP interface standards.
For high accuracy applications, the compact circuit offers high
precision, as well as low noise—this is ensured by the
combination of the AD5780, ADR445, and AD8675 precision
components.
0.6
INL (LSB)
The AD8675 precision op amp has low offset voltage (75 µV
maximum), low noise (2.8 nV/√Hz typical), and is an optimum
output buffer for the AD5780. The AD5780 has two internal
matched feedforward and feedback resistors, which are
connected to the AD8675 op amp and provide the 10 V offset
voltage. This allows an output voltage swing of ±10 V with a
single external 10 V reference.
Figure 2. Integral Nonlinearity vs. DAC Code
Figure 3 shows that the differential nonlinearity as a function of
DAC code is within the −0.25 LSB to +0.75 LSB specification.
The digital-to-analog converter (DAC) shown in Figure 1 is the
AD5780, a high voltage, 18-bit converter with SPI interface,
offering ±1 LSB INL, ±0.75 LSB DNL, and 7.5 nV/√Hz noise
spectral density. The AD5780 also exhibits an extremely low
temperature drift of 0.005 LSB/°C.
Linearity Measurements
The precision performance of the circuit shown in Figure 1 is
demonstrated on the EVAL-AD5780SDZ evaluation board
using an Agilent 3458A Multimeter. Figure 2 shows the integral
nonlinearity as a function of DAC code is within specifications
of ±1 LSB.
0.4
0.3
DNL (LSB)
Figure 1 shows the AD5780 configured in a gain-of-two mode
such that a single reference source can be used to generate a
symmetrical bipolar output voltage range. This mode of
operation uses an external op amp (A2), as well as on-chip
resistors (see AD5780 data sheet), to provide the gain of 2.
These internal resistors are thermally matched to each other
and to the DAC ladder resistance, resulting in ratiometric
thermal tracking. The output buffer is again the AD8675, used
for its low noise and low drift. This amplifier is also used (A1)
to amplify the +5 V reference voltage from the low noise
ADR445 to +10 V. R2 and R3 in this gain circuit are precision
metal foil resistors with 0.01% tolerance and a temperature
coefficient resistance of 0.6 ppm/°C. For optimum performance
over temperature, R1 and R2 should be in a single package, such
as the Vishay 300144 or VSR144 series. R2 and R3 are selected
to be 1 kΩ to keep noise in the system low. R1 and C1 form a
low-pass filter with a cutoff frequency of approximately 10 Hz.
The purpose of this filter is to attenuate voltage reference noise.
0.5
0.2
0.1
0
–0.1
–0.2
0
50000
100000
150000
200000
DAC CODE
250000
09697-003
CIRCUIT DESCRIPTION
Figure 3. Differential Nonlinearity vs. DAC Code
Noise Drift Measurements
To be able to realize high precision, the peak-to-peak noise at
the circuit output must be maintained below 1 LSB, which is
76.29 µV for 18-bit resolution and a 20 V peak-to-peak voltage
range.
A real-time noise application will not have a high-pass cutoff at
0.1 Hz to attenuate 1/f noise but will include frequencies down
to dc in its pass band. With this in mind, the measured peak-topeak noise is realistically shown in Figure 4. In this case, the
noise at the output of the circuit was measured over a period of
100 seconds, effectively including frequencies as low as 0.01 Hz
in the measurement. The upper frequency cutoff is at approximately 14 Hz and is limited by the measurement setup.
Rev. 0 | Page 2 of 6
Circuit Note
CN-0200
4
Figure 4 shows the peak-to-peak values are 1.2 µV for zero-scale
output, 32 µV for half-scale output, and 64 µV for full-scale
output.
3
40
2
NOISE (µV)
The zero-scale output voltage exhibits the lowest noise because
it represents the noise from the DAC core only. The noise
contribution from each voltage reference path is attenuated by
the DAC when the zero-scale code is selected.
FULL SCALE
0
–3
10
ZERO SCALE
0
20
40
60
80
100
TIME (Seconds)
0
Figure 5. DAC Output Voltage Noise Measured Over 100 Second Period for
Full Scale (Red), Half Scale (Green), and Zero Scale (Blue) with Precision
Reference Source
–10
HALF SCALE
–20
VDD = +15V
VSS = –15V
VREFP = +10V
VREFN = 0V
–30
–40
HALF SCALE
0
20
40
60
09697-005
–2
ZERO SCALE
80
TIME (Seconds)
COMMON VARIATIONS
100
09697-004
NOISE (µV)
1
–1
30
20
FULL SCALE
VDD = +15V
VSS = –15V
VREFP = +10V
VREFN = 0V
Figure 4. DAC Output Voltage Noise Measured Over 100 Second Period for
Full Scale (Red), Half Scale (Green), and Zero Scale (Blue)
As the time period over which the measurement is taken is
increased, lower frequencies will be included, and the peak-topeak value will increase. At low frequencies, temperature drift
and thermocouple effects become contributors to noise. These
effects can be minimized by choosing components with low
thermal coefficients. In this circuit, the main contributor to low
frequency 1/f noise is the voltage reference. It also exhibits the
greatest temperature coefficient value in the circuit of 3 ppm/°C.
A temperature controlled ultralow noise reference would be
required to improve the half-scale and full-scale DAC output
noise.
The AD5780 will support a wide variety of output ranges from
0 V to +5 V up to ±10 V, and values in between. The gain-of-2
configuration, as shown in Figure 1, can be used if a
symmetrical output range is required. This mode is selected by
setting the RBUF bit of the AD5780 internal control register to
a Logic 0. If an asymmetrical range is required, individual
references can be applied at VREFP and VREFN, and the output
buffer should be configured for unity gain as described in the
AD5780 data sheet. This is done by setting the RBUF bit of the
AD5780 internal control register to a Logic 1.
The AD8676 is a dual version of the AD8675 op amp and can be
used in the circuit if desired.
CIRCUIT EVALUATION AND TEST
Equipment Required
Figure 5 shows the performance of the signal chain by replacing
the ADR445 with a Krohn Hite Model 523 Precision Reference
set for +5 V.
Complete schematics and layout of the printed circuit board
can be found in the CN-0200 Design Support Package:
www.analog.com/CN0200-DesignSupport .
•
System Demonstration Platform (EVAL-SDP-CB1Z)
•
EVAL-AD5780SDZ Evaluation Board and Software
•
Agilent 3458A multimeter
•
PC (Windows 32-bit or 64-bit)
•
National Instruments GPIB to USB-B interface cable
•
SMB cable (1)
Software Installation
The AD5780 evaluation kit includes self-installing software on
a CD. The software is compatible with Windows XP (SP2) and
Vista (32-bit and 64-bit). If the setup file does not run
automatically, you can run the setup.exe file from the CD.
Rev. 0 | Page 3 of 6
CN-0200
Circuit Note
Install the evaluation software before connecting the evaluation
board and SDP board to the USB port of the PC to ensure that
the evaluation system is correctly recognized when connected to
the PC.
After installation from the CD is complete, power up
the AD5780 evaluation board as described in the
Power Supplies section of UG-256. Connect the SDP
board (via either Connector A or Connector B) to the
AD5780 evaluation board and then to the USB port of
your PC using the supplied cable.
2.
When the evaluation system is detected, proceed
through any dialog boxes that appear. This completes
the installation.
A functional diagram of the test setup is shown in Figure 7.
Power Supply Configuration
The following supplies must be provided:
•
•
•
3.3 V between the VCC and DGND on Connector J1
for the digital supply of the AD5780. Alternatively,
place Link 1 in Position A to power the digital
circuitry from the USB port via the SDP board
(default setting).
+12 V to +16.5 V between the VDD and AGND inputs
of J2 for the positive analog supply of the AD5780.
−12 V to −16.5 V between the VSS and AGND inputs
of J2 for the negative analog supply of the AD5780.
09697-006
1.
Functional Diagram
Figure 6. Evaluation Software Main Window
Rev. 0 | Page 4 of 6
Circuit Note
CN-0200
GPIB
DUAL POWER SUPPLY
COM
+15V
AGILENT
3458A MULTIMETER
USB
PC
USB
−15V
+VDD
AGND
−VSS
J2-3
J2-2
J2-1
USB
SMB
VOUT_BUF
SDP
CON A
OR
CON B
09697-007
J4
120-PIN SDP
EVAL-AD5780SDZ
Figure 7. Functional Block Diagram of Test Setup
Link Configuration Setup
Test
The default link options are listed in Table 1. By default, the
board is configured with VREFP = +10 V and VREFN = −10 V
for a ±10 V output range.
The VOUT_BUF SMB connector is connected to the Agilent
3458A multimeter. The linearity measurements are run using
the Measure DAC Output Tab on the AD5780 GUI.
Table 1. Default Link Options
The noise drift measurement is measured on the VOUT_BUF
SMB connector also. The output voltage is set using the Prgram
Voltage tab in the AD5780 GUI. The peak-to-peak noise drift is
measured over 100 seconds.
Link No.
LK1
LK2
LK3
LK4
LK5
LK6
LK7
LK8
LK9
LK11
Option
A
B
A
Removed
Removed
Removed
Removed
C
Inserted
Inserted
For more details on the definitions and how to calculate the
INL, DNL, and noise from the measured data, see the
"TERMINOLOGY" section of the AD5780 data sheet and also
the following reference: Data Conversion Handbook, "Testing
Data Converters," Chapter 5, Analog Devices.
LEARN MORE
CN-0200 Design Support Package:
www.analog.com/CN0200-DesignSupport
To configure the board for the circuit shown in Figure 1,
the following changes must be made to the default link
configuration in Table 1:
1.
2.
3.
Egan, Maurice. "The 20-Bit DAC Is the Easiest Part of a 1-ppmAccurate Precision Voltage Source," Analog Dialogue, Vol.
44, April 2010.
Place LK3 in position B.
Insert LK4.
Place LK8 in position B.
Kester, Walt. 2005. The Data Conversion Handbook. Analog
Devices. Chapters 3, 5, and 7.
These changes configure the output buffer amplifier for a gain
of 2 and connect the VREFN pin of the AD5780 to ground.
MT-015 Tutorial, Basic DAC Architectures II: Binary DACs.
Analog Devices.
Please refer to User Guide UG-256 for more information on the
EVAL-AD5780SDZ test setup.
MT-016 Tutorial, Basic DAC Architectures III: Segmented DACs.
Analog Devices.
Rev. 0 | Page 5 of 6
CN-0200
MT-031 Tutorial, Grounding Data Converters and Solving the
Mystery of AGND and DGND. Analog Devices.
MT-035 Tutorial, Op Amp Inputs, Outputs, Single-Supply, and
Rail-to-Rail Issues. Analog Devices.
Circuit Note
REVISION HISTORY
11/11—Revision 0: Initial Version
MT-101 Tutorial, Decoupling Techniques. Analog Devices.
Voltage Reference Wizard Design Tool.
CN-0177 Circuit Note, 18-Bit, Linear, Low Noise, Precision
Bipolar ±10 V DC Voltage Source.
CN-0191 Circuit Note, 20-Bit, Linear, Low Noise, Precision,
Bipolar ±10 V DC Voltage Source.
User Guide UG-256 for EVAL-AD5780SDZ.
Data Sheets and Evaluation Boards
AD5780 Data Sheet and Evaluation Board
AD8676 Data Sheet
ADR445 Data Sheet
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CN09697-0-11/11(0)
Rev. 0 | Page 6 of 6
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