AN594

M
Author:
AN594
Using the CCP Module(s)
CCP OPERATION
Mark Palmer
Microchip Technology Inc.
This application note discusses the operation of a
Capture/Compare/PWM (CCP) module, and the
interaction of multiple CCP modules with the timer
resources.
The (CCP) module is software programmable to operate in one of three modes:
1.
2.
3.
A Capture input
A Compare output
A Pulse Width Modulation (PWM) output
For the CCP module to function, Timer resources must
be used in conjunction with the CCP module. The
desired CCP mode of operation determines which
timer resources are required. Table 1 shows the CCP
mode with the corresponding timer resource required.
Both the Capture and Compare modes require that
Timer1 be operating in timer mode or synchronized
counter mode.
Note:
Capture and Compare modes may not
operate if Timer1 is operated in the
asynchronous counter mode.
TABLE 1:
CCP MODE - TIMER RESOURCE
CCP MODE
Timer Resource
Capture
Timer1
Compare
Timer1
PWM
Timer2
The following three sections discuss the operation of
the CCP module in each of its modes of operation.
There is a simple example program for each mode of
operation. The software example for the Capture mode,
also uses a second CCP module in Compare mode to
generate the signal to capture.
PWM Mode
A Pulse Width Modulation output (Figure 1) is a signal
that has a time-base (period) and a time that the output
stays high (duty cycle). The period is the duration after
which the PWM rising edge repeats itself. The
resolution of the PWM output is the granularity with
which the duty cycle can be varied. The frequency of a
PWM is simply the inverse of the period (1/ period).
FIGURE 2:
PWM MODE BLOCK DIAGRAM
Duty cycle registers
CCPxCON<5:4>
CCPRxL
CCPRxH (Slave)
Q
R
Comparator
RCy/CCPx
TMR2
(Note 1)
S
TRISC<y>
Comparator
PR2
Clear Timer,
CCPx pin and
latch D.C.
Note: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
FIGURE 1:
PWM OUTPUT
Period
Duty Cycle
PWM frequency = 1/period
TMR2 = PR2
TMR2 = PR2
TMR2 = CCPR1H
 1997 Microchip Technology Inc.
DS00594B-page 1
AN594
Appendix A is a program which generates up to a 10-bit
PWM output. The PWM period and duty cycle are
updated after the overflow of Timer1. Upon the overflow
of Timer1, ports A, B and D are read. The 10-bit duty
cycle
is
specified
by
the
value
on
PORTB:PORTA<1:0>, while the period is specified by
the value on PORTD. By setting the conditional
assemble flag PICMaster to TRUE, these values are
read from internal registers which are dummy registers
for the ports (DUMMY_Px). This allows the software to
be verified without the use of hardware and
external stimulus.
Each CCP module can support one Pulse Width
Modulation (PWM) output signal, with minimal software
overhead. This PWM signal can attain a resolution of
up to 10-bits, from the 8-bit Timer2 module. This gives
1024 steps of variance from an 8-bit overflow counter.
This gives a maximum accuracy of Tosc (50 ns, when
the device is operated at 20 MHz). Figure 2 shows a
block diagram of the CCP module in PWM mode. When
the Timer2 overflows (timer = period register), the value
in the duty cycle registers (CCPRxL:CCPRxCON<5:4>) is latched into the 10-bit slave latch. A new
duty cycle value can be loaded into the duty cycle
register(s) at any time, but is only latched into the slave
latch when Timer2 = Timer2 Period Register (PR2).
Since the PWM duty cycle is double buffered, the duty
cycle registers are only loaded when there is sufficient
time to complete the update of the 10-bit value before
the Timer2 = PR2 match occurs. After the duty cycle
has been updated and the Timer2 = PR2 match has
occurred, the period (stored in the PR2 register) is
updated. The operation of the CCP module in PWM
mode is similar to the PIC17C42’s PWM. Additional
concepts of PWM operation can be found in Application
Notes AN564 and AN539.
The period of Timer 2 (and PWM) is determined by the
frequency of the device, the Timer2 prescaler value (1, 4
or 16), and the Timer2 Period Register. Equation 1
shows the calculation of the PWM period, duty cycle,
and the minimum and maximum frequencies.
EQUATION 1:
PWM PERIOD, DUTY CYCLE, AND FREQUENCIES
PWM Period = [(PR2) + 1] • 4 TOSC • (Timer 2 prescale value)
PWM Duty Cycle = [CCPRxL:CCPRxCON<5:4>] • 4 TOSC • (Timer2 prescale value)
PWM maximum frequency
(High Resolution mode) = 4/(PR2 • TCY)
(Low Resolution mode) = 1/(PR2 • TCY)
PWM minimum frequency
(High Resolution mode) = 4/(PR2 • TCY)
(Low Resolution mode) = 1/(PR2 • TCY)
Table 2 shows the minimum and maximum PWM frequency for different device frequencies. The Timer2 prescaler
will be selected to give either the minimum or maximum frequencies as shown.
TABLE 2:
PWM FREQUENCY FOR DIFFERENT DEVICE FREQUENCIES
20 MHz
10 MHz
2 MHz
PWM Resolution
Min
Max
Min
Max
Min
Max
Units
10-bit
1.22
19.53
0.613
9.77
0.123
1.96
kHz
9-bit
1.22
39.06
0.613
9.77
0.123
3.92
kHz
10-bit
1.22
19.53
0.613
9.77
0.123
1.96
kHz
9-bit
1.22
39.06
0.613
9.77
0.123
3.92
kHz
10-bit
1.22
19.53
0.613
9.77
0.123
1.96
kHz
9-bit
1.22
39.06
0.613
9.77
0.123
3.92
kHz
10-bit
1.22
19.53
0.613
9.77
0.123
1.96
kHz
9-bit
1.22
39.06
0.613
9.77
0.123
3.92
kHz
DS00594B-page 2
 1997 Microchip Technology Inc.
AN594
Compare Mode
When the CCP module is in the OFF state
(CCPxM3:CCPxM0 = 0h), the CCPx output latch is
forced to a low level, though the level on the CCPx pin
will be determined by the value in the data latch of the
port. Figure 3 shows the block diagram of the CCP
module in Compare mode.
In Compare mode, the 16-bit value of Timer1 is
compared to the CCPRxH:CCPRxL registers. When
these registers match, the S/W configured event
occurs on the CCPx pin. The events that can be S/W
selected are:
•
•
•
•
Appendix B is a program which uses the CCP module
to transmit a pulse train dependent on the data byte.
Timer1 is used as a free running timer, with each “new”
compare value being an offset added to the present
CCP compare latch value. The data is transmitted
every 600 µs. Each data bit has a sync pulse (High
level) of 8.8 µs. Then the data is transmitted as a low
pulse. The time duration of the low pulse determines
the value of the data bit. A ‘0’ bit is low for 18.8 µs while
a ‘1’ bit is low for 37.6 µs. After the last data bit has
been transmitted, another sync pulse is transmitted
and the output remains low (idle time) until the 600 µs
data period has completed. An example of the pulse
train for the a data byte of 0x0CA is shown in Figure 4,
and has an idle time of 224 µs. These pulse times are
based off the device operational frequency. The
program header file, COMP.H, calculates the values to
be loaded into the compare registers from the specified
Device_freq. The data to be transmitted is read from
PORTB, during the idle time. By setting the conditional
assemble flag PICMaster to TRUE, these values are
read from internal registers which are dummy registers
for the ports (DUMMY_Px). This allows the software to
be verified without the use of hardware and external
stimulus.
Clear CCPx pin on match
Set CCPx pin on match
Generate S/W interrupt (CCPx pin unchanged)
Trigger special event (CCPx pin unchanged)
- CCP1 clears Timer1
- CCP2 clears Timer1 and sets the A/D’s
GO/DONE bit
The CCPxM3:CCPxM0 control bits, in register
CCPxCON, configures the operation of the CCP
module. The compare function must have the data
direction of the CCPx pin configured as an output, if the
compare event is to control the state of the CCPx pin.
COMPARE MODE BLOCK
DIAGRAM
Trigger
Special Event
FIGURE 3:
Q
RCy/CCPx
R
TRISC<y>
Output Enable
FIGURE 4:
S
Set CCPxIF Interrupt
PIR<b>
CCPRxH CCPRxL
Output
Logic
match
Comparator
TMR1H
CCPxCON<3:0>
Mode Select
TMR1L
TRANSMIT PULSE TRAIN (DATA = 0x0CA)
CCPx Pin
1
1
 1997 Microchip Technology Inc.
0
0
1
0
1
0
IDLE TIME
DS00594B-page 3
AN594
Capture Mode
In Capture mode, the 16-bit value of Timer1 is latched
into the CCPRxH:CCPRxL registers, when the S/W
configured event occurs on the CCPx pin. The events
that can cause a capture are:
•
•
•
•
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
The CCPxM3:CCPxM0 control bits, in register
CCPxCON, configures the operation of the CCP
module. The capture function works regardless of the
data direction of the CCPx pin (input or output). With
the CCPx pin is configured as an output, a write to the
CCPx pin (in PORTC) will cause a capture when the
capture requirement is met.
FIGURE 5:
CAPTURE MODE BLOCK
DIAGRAM
Set CCPxIF
PIR<b>
Prescaler
1, 4, 16
RCy/CCPx
CCPRxH
and
edge detect
Capture
Enable
TMR1H
Q’s
FIGURE 6:
CCPRxL
TMR1L
CCPxCON<3:0>
The changing of the Capture mode, via the
CCPxM3:CCPxM0 bits, may cause the CCPxIF bit to
be set. This “false” interrupt should be cleared (ignored)
after changing between capture modes. The CCP prescaler is only cleared by configuring the CCP module
into the OFF state (CCPxM3:CCPxM0 = 0h). Figure 5
shows the block diagram of the CCP module in Capture
mode. The use of the CCP module in Capture mode is
similar to the PIC17C42’s capture. Additional concepts
of capture operation can be found in Application Note
AN545.
Appendix C is a program which implements a 16-bit
capture from a free running timer (Timer1). The capture
event is configured as each rising edge. The 16-bit
capture value is the “new” 16-bit capture value minus
the “old” 16-bit capture value. If the time between
captures is greater than 216 Timer1 increments, an
invalid result will occur. This invalid result is not
indicated by the software. After the capture period
result is calculated, the “new” capture value is loaded
into the “old” register.
The waveform that is captured is generated from a
second CCP module in compare mode. The value that is
loaded in to the CCPR2H:CCPR2L is read from the
PORTB and PORTD registers. By setting the conditional
assemble flag PICMaster to TRUE, these values are
read from internal registers which are dummy registers
for the ports (DUMMY_Px). This allows the software to
be verified without the use of hardware and external
stimulus. Figure 6 shows an input into the CCPx pin, and
the capture measurement points.
EXAMPLE CAPTURE WAVEFORM
CCP1
Capture TMR1 Value
Capture TMR1 Value
Capture TMR1 Value
PIC16CXXX
DS00594B-page 4
 1997 Microchip Technology Inc.
AN594
INTERACTION OF CCP MODULES
Due to the modularity of the PIC16CXXX peripherals,
future devices with two or more CCP modules on a
device are possible. Each CCP module operates
independently from the others, though their interaction
with the timer resources must be taken into account.
When two or more CCP modules exist on a device,
there can be an interaction between the CCP modules.
This interaction is shown in Table 3. These interactions
do NOT include any interaction (S/W) caused by the
main program nor the interrupt service routines of the
CCP sources.
Interaction of Two Capture Modes
When two CCP modules are in a Capture mode,
Timer1 is the time-base for both captures. This means
that they will have the same capture resolution, as
determined by the Timer1 prescaler and frequency of
the timer/counter clock. This clock can come from an
external source (on the RC0/T1OSO/T1CKI pin), but
must be synchronized to the device.
TABLE 3:
Interaction of One Capture Mode and One
Compare Mode
When one CCP module is in a Capture mode and a
second CCP module is in Compare mode, Timer1 is
the time-base for both the captures and the compare.
This means that the capture and the compare will have
the same resolution, as determined by the Timer1
prescaler and frequency of the timer/counter clock.
This clock can come from an external source (on the
RC0/T1OSO/T1CKI pin), but must be synchronized to
the processor clock. Also, care must be taken in that
the compare can be configured to clear TMR1 register
(when in special Trigger mode). Care must be taken in
system design to ensure that this clearing of the TMR1
register does not have any negative impact on the
capture function.
INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Same Timer1 time-base.
Capture
Capture
The compare could be configured for trigger special event, which clears the TMR1
register.
Capture
Capture
The compare(s) could be configured for trigger special event, which clears the
TMR1 register.
PWM
PWM
The PWMs will have the same frequency, and update rate (Timer2 interrupt).
PWM
Capture
None
PWM
Capture
None
 1997 Microchip Technology Inc.
DS00594B-page 5
AN594
EXAMPLE 1:
ACTION
TIMER1 STATE
CCPR1H:CCPR1L = 0x0465
CCP1CON = 0x?B
:
:
:
CCPR2H:CCPR2L = 0x0165
CCP2CON = 0x?B
:
0x????
0x????
COMMENT
CCP1 in Compare - Special
Trigger Mode
0x0232
0x0333
0x0334
0x0465
0x0000
CCP2 in Compare - Special
Trigger Mode
CCP1 resets TMR1 and CCP1 Special Trigger function occurs
0x0165
0x0000
CCP2 resets TMR1 and CCP2 Special Trigger function occurs
0x0165
0x0000
CCP2 resets TMR1 and CCP2 Special Trigger function occurs
:
:
:
Interaction of Two Compare Modes
CONCLUSION
When two CCP modules are in a Compare mode,
Timer1 is the time-base for both compares. This means
that they will have the same compare resolution, as
determined by the Timer1 prescaler and frequency of
the timer/counter clock. This clock can come from an
external source (on the RC0/T1OSO/T1CKI pin), but
must be synchronized to the processor clock. Since the
compare modules can be configured to clear TMR1
register (when in special Trigger mode), care must be
taken in system design to ensure that this clearing of
the TMR1 register does not have any negative impact
on the compare function. If both compares are
configured with a special trigger, which clears the
TMR1 register, then the compare register that is closest
to (but greater than) the TMR1 register value is the
compare value that will reset the TMR1 register.
Example 1 shows a possible case.
The Capture/Compare/PWM modules offer enormous
flexibility in the use of the device timer resources. As
with all resources, care must be taken to ensure that no
adverse system complications can occur with the interaction between multiple CCP modules. The programs
for simple operation of the various CCP modes should
be a good foundation for modifications to suite your particular needs.
Interaction of Two PWM Modes
When two CCP modules are in a PWM mode, Timer2 is
the time-base for both PWM outputs. This means that
they will have the same PWM frequency and update
rates, as determined by the Timer2 prescaler and frequency of the device. The resolution of the two PWMs
may be different, since each CCP module has its own
CCPxX:CCPxY bits for high resolution mode. These
bits are found in the CCPxCON<5:4> register.
DS00594B-page 6
 1997 Microchip Technology Inc.
AN594
Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address:
www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not
required).
APPENDIX A: PWM_1.ASM
MPASM 01.40 Released
LOC OBJECT CODE
VALUE
00000000
00000001
00000001
00000001
00000001
0000
0000 1683
0001 188E
PWM_1.ASM
1-16-1997
17:35:52
PAGE
1
LINE SOURCE TEXT
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 1997 Microchip Technology Inc.
LIST
P = 16C74, n = 66
ERRORLEVEL -302
;
;*******************************************************************
;
; This program outputs a PWM signal on the CCP1 pin. The duty cycle and
; period of the PWM is read every time TMR1 overflows.
;
PERIOD
= PORTB
;
DUTY CYCLE = PORTD and PORTE<1:0>
;
; The prescaler of TMR2 is selected by the state of PORTA<1:0> after
; reset
RA1:RA0
Prescaler multiplies Tcyc by
;
0 0
1
;
0 1
4
;
1 x
16
;
;
;
Program = PWM_1.ASM
;
Revision Date:
7-13-94
;
1-16-97
Compatibility with MPASMWIN 1.40
;
;
;*********************************************************************
;
;
; HARDWARE SETUP
;
PORTA<1:0>
- Prescaler to TMR2, read only after reset
;
PORTB
- Period of PWM
;
PORTD
- Duty Cycle high of PWM (8-bits)
;
PORTE<1:0>
- Duty Cycle low of PWM (2-bits)
;
;
INCLUDE <p16c74.inc>
LIST
; P16C74.INC Standard Header File, Ver. 1.00 Microchip Technology, Inc.
LIST
FALSE
TRUE
EQU
EQU
0
1
INCLUDE <PWM.h>
list
;
PICMaster
EQU
TRUE
Debug
EQU
TRUE
Debug_PU
EQU
TRUE
;
;
; Reset address. Determine type
;
org
RESET_V
RESET
BSF
STATUS, RP0
BTFSC
PCON,NOT_POR
; A Debugging Flag
; A Debugging Flag
; A Debugging Flag
of RESET
; RESET vector location
; Bank 1
; Power-up reset?
DS00594B-page 7
AN594
0002 2832
0003 285C
0004
0004
0004
0005
0006
0007
0007
0008
0009
1283
180C
280D
1505
1105
2807
000A
000A 1585
000B 1185
000C 280A
000D
000D 100C
000E 0853
000F 00D5
0010 0854
0011 00D6
0012 0851
0013 1683
0014 00A0
0015 1283
0016
0016
0017
0018
0019
001A
001B
001C
001D
001E
001F
0020
0021
0022
0023
0811
0212
390F
1903
2816
0855
0095
300F
0597
18D6
1697
1856
1617
108C
0024
0024 1C8C
0025 2824
DS00594B-page 8
00050
00051
00052
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00054
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00111
00112
00113
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00115
GOTO
GOTO
START
OTHER_RESET
; YES
; NO, a WDT or MCLR reset
;
; This is the Periperal Interrupt routine. Need to determine the type
; of interrupt that occurred. The following interrupts are enabled:
;
1. CCP Capture Occured
;
page
org
ISR_V
; Interrupt vector location
PER_INT_V
BCF
STATUS, RP0 ; Bank 0
BTFSC
PIR1, TMR1IF ; TMR1 Overflow Interrupt occured?
GOTO
T1OVFL
; YES, Service the TMR1 Interrupt
ERROR1
; NO, Error Condition-Unknown Interrupt
BSF
PORTA, 2
; Toggle a PORT pin
BCF
PORTA, 2
GOTO
ERROR1
;
ERROR2
; NO, Error Condition-Unknown Interrupt
BSF
PORTA, 3
; Toggle a PORT pin
BCF
PORTA, 3
GOTO
ERROR2
;
T1OVFL
BCF
PIR1, TMR1IF ; Clear T1 Overflow Interrupt Flag
if (PICMaster )
MOVF
DUMMY_PD, W ;
else
MOVF
PORTD, W
;
endif
MOVWF
DC_HI
;
if (PICMaster )
MOVF
DUMMY_PE, W ;
else
MOVF
PORTE, W
;
endif
MOVWF
DC_LO
;
if (PICMaster )
MOVF
DUMMY_PB, W ;
else
MOVF
PORTB, W
;
endif
BSF
STATUS, RP0 ; Bank 1
MOVWF
T2_PERIOD
;
BCF
STATUS, RP0 ; Bank 0
;
WAIT_DC
MOVF
TMR2, W
; Read present TMR2 register value
SUBWF
PR2, W
; How close is the timer to rolling over
ANDLW
0x0F
; Does this make it zero?
BTFSC
STATUS, Z
; If Z is set, near rollover
GOTO
WAIT_DC
; loop until rolled over
MOVF
DC_HI, W
; else losd the duty cycle values
MOVWF
CCPR1L
; Load DC high
MOVLW
0x0F
;
ANDWF
CCP1CON, F
; Set the DC low bits
BTFSC
DC_LO, 1
;
BSF
CCP1CON, CCP1X;
BTFSC
DC_LO, 0
;
BSF
CCP1CON, CCP1Y;
BCF
PIR1, TMR2IF ; Clear the TRM2 = PR2 flag
;
WAIT_PR
BTFSS
PIR1, TMR2IF ; LOOP waiting for TRM2 = PR2
GOTO
WAIT_PR
; Need to wait until TMR2 = PR2 so that
; Duty Cycle is latched
 1997 Microchip Technology Inc.
AN594
0026
0027
0028
0029
002A
002B
002C
002D
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1683
300F
0092
30F0
0520
1903
2830
300F
0220
0792
0030
0030 1283
0031 0009
0032
0032 1283
0033 018F
0034 018E
0035
0035
0036
0037
0038
0039
003A
003B
003C
003D
0183
018B
018C
1683
3080
0081
018C
30FF
009F
003E
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0040
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1283
0185
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004C
004D
1683
30FF
0085
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140C
1283
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0050 018C
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0052 0192
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 1997 Microchip Technology Inc.
BSF
MOVLW
MOVWF
MOVLW
ANDWF
BTFSC
GOTO
STATUS, RP0
0x0F
PR2
0xF0
T2_PERIOD, W
STATUS, Z
NO_OFFSET
;
;
;
;
;
;
;
Bank 1
Load TMR2 period with minimum value Fh
MOVLW
SUBWF
ADDWF
0x0F
; Yes, calculate additional offset
T2_PERIOD, W ;
PR2, F
; ADD Period offset
BCF
RETFIE
STATUS, RP0
Determine if period needs to be greater
NO, Period is the minimum
PR_OFFSET
;
NO_OFFSET
; Bank 0
; Return / Enable Global Interrupts
;
page
;
;**********************************************************************
;*****
Start program here, Power-On Reset occurred.
;**********************************************************************
;
START
; POWER_ON Reset (Beginning of program)
BCF
STATUS, RP0
; Bank 0
CLRF
TMR1H
;
CLRF
TMR1L
;
;
MCLR_RESET
; A Master Clear Reset
CLRF
STATUS
; Do initialization (Bank 0)
CLRF
INTCON
CLRF
PIR1
BSF
STATUS, RP0
; Bank 1
MOVLW
0x80
;
MOVWF
OPTION_REG
;
CLRF
PIE1
; Disable all peripheral interrupts
MOVLW
0xFF
;
MOVWF
ADCON1
; Port A is Digital.
;
;
BCF
STATUS, RP0
; Bank 0
CLRF
PORTA
; ALL PORT output should output Low.
CLRF
PORTB
CLRF
PORTC
CLRF
PORTD
CLRF
PORTE
;
BSF
STATUS, RP0
; Select Bank 1
MOVLW
0xFF
;
MOVWF
TRISA
; RA5 - 0 inputs
MOVWF
TRISB
; RB7 - 0 inputs
CLRF
TRISC
; RC Port are outputs
MOVWF
TRISD
; RD Port are inputs
MOVWF
TRISE
; RE Port are inputs
MOVWF
PR2
; Default PWM period
BSF
PIE1, TMR1IE ; Enable TMR1 Interrupt
BCF
STATUS, RP0
; Select Bank 0
;
MOVLW
0X0C
; CCP module is in
MOVWF
CCP1CON
; PWM output mode
;
; Initialize the Special Function Registers (SFR) interrupts
;
CLRF
PIR1
;
CLRF
T1CON
;
CLRF
T2CON
;
if (PICMaster )
DS00594B-page 9
AN594
0053 1850
00182
00183
00184
00185
00186
00187
00188
00189
00190
00191
00192
00193
00194
00195
00196
00197
00198
00199
00200
00201
00202
00203
00204
00205
00206
00207
00208
00209
00210
00211
00212
00213
00214
00215
00216
00217
00218
00219
00220
0054 1412
0055 18D0
0056 1492
0057
0058
0059
005A
170B
178B
1410
1512
005B 285B
005C 1E03
005D 2807
005E 2832
005F 0000
07FF
07FF 2807
BTFSC
DUMMY_PA, 0
;
PORTA, 0
;
T2CON, 0
;
else
BTFSC
endif
BSF
;
if (PICMaster )
BTFSC
DUMMY_PA, 1
else
BTFSC
PORTA, 1
endif
BSF
T2CON, 1
;
;
;
;
BSF
BSF
BSF
BSF
INTCON, PEIE
INTCON, GIE
T1CON, TMR1ON
T2CON, TMR2ON
;
;
;
;
Enable Peripheral Interrupts
Enable all Interrupts
Turn Timer 1 ON
Turn Timer 2 ON
;
lzz
goto
lzz
; Loop waiting for TMR1 interrupt
;
; Here is where you do things depending on the type of RESET (Not a
; Power-On Reset).
OTHER_RESET BTFSS STATUS,NOT_TO ; WDT Time-out?
WDT_TIMEOUT GOTO
ERROR1
; YES, This is error condition
if ( Debug_PU )
goto
START
; MCLR reset, Goto START
else
GOTO
MCLR_RESET
; MCLR reset, Goto MCLR_RESET
endif
;
if (Debug )
END_START
NOP
; END label for debug
endif
;
;
org
PMEM_END
; End of Program Memory
GOTO
ERROR1
; If you get here your program was lost
end
_XT_OSC
__16C74
lzz
00003FBD
00000001
0000005B
MEMORY USAGE MAP (‘X’ = Used,
‘-’ = Unused)
0000 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
0040 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX ---------------- ---------------07C0 : ---------------- ---------------- ---------------- ---------------X
All other memory blocks unused.
Program Memory Words Used:
Program Memory Words Free:
Errors
:
Warnings :
Messages :
0
0 reported,
0 reported,
DS00594B-page 10
97
3999
0 suppressed
17 suppressed
 1997 Microchip Technology Inc.
AN594
Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address:
www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not
required).
APPENDIX B:
PWM.H
nolist
;******************************************************************************
;
; This is the custom Header File for the real time clock application note
;
PROGRAM:CLOCK.H
;
Revision:7-13-94
;
;******************************************************************************
; This is used for the ASSEMBLER to recalculate certain frequency
; dependant variables. The value of Dev_Freq must be changed to
; reflect the frequency that the device actually operates at.
;
Dev_Freq
EQU
D’10000000’; Device Frequency is 4 MHz
PULSE_TIME
EQU
(( Dev_Freq / D’4000’ ) * D’188’ / D’10000’ )
;
DB_HI_BYTE
LCD_INIT_DELAY
INNER_CNTR
OUTER_CNTR
;
T1OSO
;
RESET_V
ISR_V
PMEM_END
TABLE_ADDR
;
COUNTER
;
XMIT_DATA
DATA_CNT
ONES_CNT
CCP1_INT_CNT
CCPREG_HI
CCPREG_LO
DUMMY_PA
DUMMY_PB
DUMMY_PC
DUMMY_PD
DUMMY_PE
DC_HI
DC_LO
T2_PERIOD
;
list
EQU
EQU
EQU
EQU
(HIGH ((( Dev_Freq / 4 ) * 1 / D’1000’ ) / 3 ) ) + 1
(HIGH ((( Dev_Freq / 4 ) * D’46’ / D’10000’ ) / 3 ) ) + 1
40
; RAM Location
41
; RAM Location
EQU
0
; The RC0 / T1OSO / T1CKI
EQU
EQU
EQU
EQU
0x0000
0x0004
0x07FF
0x0400
;
;
;
;
EQU
0x021
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
0x30
0x31
0x32
0x33
0x40
0x41
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0xA0
 1997 Microchip Technology Inc.
Address of RESET Vector
Address of Interrupt Vector
Last address in Program Memory
Address where to start Tables
;
DS00594B-page 11
AN594
Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address:
www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not
required).
APPENDIX C:
COMP_1.LST
MPASM 01.40 Released
LOC OBJECT CODE
VALUE
00000000
00000001
00000001
00000001
00000001
0000
0000
0001
0002
0003
1683
188E
287C
28BA
DS00594B-page 12
COMP_1.ASM
1-16-1997
17:35:21
PAGE
1
LINE SOURCE TEXT
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00001
00002
00318
00032
00033
00034
00035
00036
00052
00053
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
LIST
P = 16C74, n = 66
ERRORLEVEL -302
;
;********************************************************************
;
; This program outputs a pulse train on the CCP1 pin, as specified by
; the values in the CCPR1H:CCPR1L.
;
;
____
____
__
; Pulse Train
___|
|________|
|____|
; Data Value
<---- 1 ----> <-- 0 -->
;
^
^
^
^
;
|
|
|
|
;
| T_ONE_BIT | T_ZERO_BIT
;
|
|
;
PULSE_TIME
PULSE_TIME
;
;
;
Program = COMP_1.ASM
;
Revision Date:
7-13-94
;
1-16-97
Compatibility with MPASMWIN 1.40
;
;
;*********************************************************************
;
;
; HARDWARE SETUP
;
PORTB
- Data to serial transmit on CCP pin
;
;
INCLUDE <p16c74.inc>
LIST
;P16C74.INC Standard Header File, Version 1.00 Microchip Technology
LIST
FALSE
TRUE
EQU
EQU
0
1
INCLUDE <COMP.h>
list
;
PICMaster
EQU
TRUE
; A Debugging Flag
Debug
EQU
TRUE
; A Debugging Flag
Debug_PU
EQU
TRUE
; A Debugging Flag
;
;
; Reset address. Determine type of RESET
;
org
RESET_V
; RESET vector location
RESET
BSF
STATUS, RP0
; Bank 1
BTFSC
PCON,NOT_POR
; Power-up reset?
GOTO
START
; YES
GOTO
OTHER_RESET
; NO, a WDT or MCLR reset
 1997 Microchip Technology Inc.
AN594
0004
0004
0004 1405
0005
0006
0007
0008
0008
0009
000A
1283
190C
280E
1505
1105
2808
000B
000B 1585
000C 1185
000D 280B
000E
000E
000F
0010
0011
0012
0012
0013
0014
0015
0016
0017
0018
0018
0019
001A
001B
001C
001D
001E
001F
001F
0020
0021
0022
0023
0024
110C
0AB3
1C33
2833
03B1
1903
2827
0DB0
1803
281F
302F
0795
1803
0A96
3000
0796
287A
305E
0795
1803
0A96
3000
0796
00050
00051
00052
00053
00054
00055
00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00108
00109
00110
00111
00112
00113
00114
00115
;
; This is the Periperal Interrupt routine. Need to determine the type
; of interrupt that occurred. The following interrupts are enabled:
;
1. CCP Capture Occured
;
page
org
ISR_V
; Interrupt vector location
PER_INT_V
if ( Debug )
bsf
PORTA, 0
; Turn on strobe
endif
;
BCF
STATUS, RP0 ; Bank 0
BTFSC
PIR1, CCP1IF ; Compare Interrupt occured?
GOTO
CCP1_INT
; YES, Service the TMR1 Interrupt
ERROR1
; NO, Error Condition-Unknown Interrupt
BSF
PORTA, 2
; Toggle a PORT pin
BCF
PORTA, 2
GOTO
ERROR1
;
ERROR2
; NO, Error Condition-Unknown Interrupt
BSF
PORTA, 3
; Toggle a PORT pin
BCF
PORTA, 3
GOTO
ERROR2
;
;
;*********************************************************************
; In the CCP interrupt.
; Since timer1 is not cleared on a CCP match, the value in the
; CCPR1H:CCPR1L register pair must be updated. This is done with
; a 16-bit add. Also after the 1st CCP1 match (CCP1 pin goes high) the
; next match will force it low. Depending on the value of the data bit
; determines the value add to the CCPR1H:CCPR1L register pair.
;
; After the data has been transmitted, the pin will have a sync pulse
; and then remain low for 300 us.
;**********************************************************************
;
CCP1_INT
BCF
INCF
BTFSS
GOTO
PIR1, CCP1IF
; Clear CCP1 Interrupt Flag
CCP1_INT_CNT, F ;
CCP1_INT_CNT, 0 ;
SYNC_PULSE
DECF
BTFSC
GOTO
RLF
BTFSC
GOTO
DATA_CNT, F
STATUS, Z
PERIOD_DELTA
XMIT_DATA, F
STATUS, C
ONE_DATA
MOVLW
ADDWF
BTFSC
INCF
MOVLW
ADDWF
GOTO
LOW ( T_ZERO_BIT ) ; NO, Stay low for 8.8 us
CCPR1L, F
; Update Compare register pair latch
STATUS, C
;
CCPR1H, F
;
HIGH (T_ZERO_BIT ) ;
CCPR1H, F
;
RET_FIE
MOVLW
ADDWF
BTFSC
INCF
MOVLW
ADDWF
LOW ( T_ONE_BIT )
CCPR1L, F
STATUS, C
CCPR1H, F
HIGH ( T_ONE_BIT )
CCPR1H, F
DATA_PULSE
;
;
;
;
;
;
Decrement the Count of data bits
Have we transmitted all the Data Bits?
YES, Delay to 300 us
NO, get next bit to transmit
Is the bit to transmit a ‘1’?
YES, Stay low for 17.6 us
ZERO_DATA
;
ONE_DATA
 1997 Microchip Technology Inc.
; Stay low for 17.6 us
; Update Compare register pair latch
;
;
;
;
DS00594B-page 13
AN594
0025 0AB2
0026 287A
0027
0027
0028
0029
002A
002B
002C
002D
002E
002F
0030
0031
0032
0033
0033
0034
0035
0036
0037
0038
0039
003A
003B
003B
003C
003D
003E
003F
0040
0041
0042
0042
0043
0044
0045
0046
0047
0048
0049
0049
004A
004B
004C
004D
004E
004F
0050
0050
0051
0052
0053
0054
0055
0056
0832
390F
0782
283B
2842
2849
2850
2857
285E
2865
286C
2873
302F
0795
1803
0A96
3000
0796
1417
0009
30EC
0795
1803
0A96
3002
0796
287A
30BD
0795
1803
0A96
3002
0796
287A
308E
0795
1803
0A96
3002
0796
287A
305F
0795
1803
0A96
3002
0796
287A
0057
0057 3030
0058 0795
00116
00117
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127
00128
00129
00130
00131
00132
00133
00134
00135
00136
00137
00138
00139
00140
00141
00142
00143
00144
00145
00146
00147
00148
00149
00150
00151
00152
00153
00154
00155
00156
00157
00158
00159
00160
00161
00162
00163
00164
00165
00166
00167
00168
00169
00170
00171
00172
00173
00174
00175
00176
00177
00178
00179
00180
00181
DS00594B-page 14
INCF
GOTO
ONES_CNT, F
RET_FIE
; Increment the number of 1’s in the byte
MOVF
ANDLW
ADDWF
GOTO
GOTO
GOTO
GOTO
GOTO
GOTO
GOTO
GOTO
GOTO
ONES_CNT, W
0x0F
PCL, F
ZERO_1
ONE_1
TWO_1
THREE_1
FOUR_1
FIVE_1
SIX_1
SEVEN_1
EIGHT_1
;
;
;
;
;
;
;
;
;
;
;
;
MOVLW
ADDWF
BTFSC
INCF
MOVLW
ADDWF
BSF
RETFIE
LOW ( PULSE_TIME ) ;Update Compare register pair latch
CCPR1L, F
;
STATUS, C
;
CCPR1H, F
;
HIGH ( PULSE_TIME );
CCPR1H, F
;
CCP1CON, 0
; On Compare match, CCP1 pin = L
MOVLW
ADDWF
BTFSC
INCF
MOVLW
ADDWF
GOTO
LOW ( ZERO_1S )
CCPR1L, F
STATUS, C
CCPR1H, F
HIGH ( ZERO_1S )
CCPR1H, F
RET_FIE
; Update Compare register pair latch
;
;
;
;
;
MOVLW
ADDWF
BTFSC
INCF
MOVLW
ADDWF
GOTO
LOW ( ONE_1S )
CCPR1L, F
STATUS, C
CCPR1H, F
HIGH ( ONE_1S )
CCPR1H, F
RET_FIE
; Update Compare register pair latch
;
;
;
;
;
MOVLW
ADDWF
BTFSC
INCF
MOVLW
ADDWF
GOTO
LOW ( TWO_1S )
CCPR1L, F
STATUS, C
CCPR1H, F
HIGH ( TWO_1S )
CCPR1H, F
RET_FIE
; Update Compare register pair latch
;
;
;
;
;
MOVLW
ADDWF
BTFSC
INCF
MOVLW
ADDWF
GOTO
LOW ( THREE_1S )
CCPR1L, F
STATUS, C
CCPR1H, F
HIGH ( THREE_1S )
CCPR1H, F
RET_FIE
; Update Compare register pair latch
;
;
;
;
;
MOVLW
ADDWF
LOW ( FOUR_1S )
CCPR1L, F
; Update Compare register pair latch
;
;
PERIOD_DELTA
Only want 9 states (0 1s to 8 1s)
There
There
There
There
There
There
There
There
There
was
was
was
was
was
was
was
was
was
0
1
2
3
4
5
6
7
8
ones in the data byte
one in the data byte
ones in the data byte
ones in the data byte
ones in the data byte
ones in the data byte
ones in the data byte
ones in the data byte
ones in the data byte
;
SYNC_PULSE
;
ZERO_1
;
ONE_1
;
TWO_1
;
THREE_1
;
FOUR_1
 1997 Microchip Technology Inc.
AN594
0059
005A
005B
005C
005D
005E
005E
005F
0060
0061
0062
0063
0064
0065
0065
0066
0067
0068
0069
006A
006B
006C
006C
006D
006E
006F
0070
0071
0072
0073
0073
0074
0075
0076
0077
0078
0079
1803
0A96
3002
0796
287A
3001
0795
1803
0A96
3002
0796
287A
30D2
0795
1803
0A96
3001
0796
287A
30A3
0795
1803
0A96
3001
0796
287A
3074
0795
1803
0A96
3001
0796
287A
007A
007A 1017
007B 0009
007C
007C 1283
007D 018F
007E 018E
007F
007F
0080
0081
0082
0083
0084
0085
0086
1283
0183
018B
018C
1683
3080
0081
018C
00182
00183
00184
00185
00186
00187
00188
00189
00190
00191
00192
00193
00194
00195
00196
00197
00198
00199
00200
00201
00202
00203
00204
00205
00206
00207
00208
00209
00210
00211
00212
00213
00214
00215
00216
00217
00218
00219
00220
00221
00222
00223
00224
00225
00226
00227
00228
00229
00230
00231
00232
00233
00234
00235
00236
00237
00238
00239
00240
00241
00242
00243
00244
00245
00246
00247
BTFSC
INCF
MOVLW
ADDWF
GOTO
STATUS, C
;
CCPR1H, F
;
HIGH ( FOUR_1S );
CCPR1H, F
;
RET_FIE
MOVLW
ADDWF
BTFSC
INCF
MOVLW
ADDWF
GOTO
LOW ( FIVE_1S )
CCPR1L, F
STATUS, C
CCPR1H, F
HIGH ( FIVE_1S
CCPR1H, F
RET_FIE
; Update Compare register pair latch
;
;
;
;
;
MOVLW
ADDWF
BTFSC
INCF
MOVLW
ADDWF
GOTO
LOW ( SIX_1S )
CCPR1L, F
STATUS, C
CCPR1H, F
HIGH ( SIX_1S )
CCPR1H, F
RET_FIE
; Update Compare register pair latch
;
;
;
;
;
MOVLW
ADDWF
BTFSC
INCF
MOVLW
ADDWF
GOTO
LOW ( SEVEN_1S )
CCPR1L, F
STATUS, C
CCPR1H, F
HIGH ( SEVEN_1S )
CCPR1H, F
RET_FIE
; Update Compare register pair latch
;
;
;
;
;
MOVLW
ADDWF
BTFSC
INCF
MOVLW
ADDWF
GOTO
LOW ( EIGHT_1S )
CCPR1L, F
STATUS, C
CCPR1H, F
HIGH ( EIGHT_1S )
CCPR1H, F
RET_FIE
; Update Compare register pair latch
;
;
;
;
;
BCF
RETFIE
CCP1CON, 0
; On Compare match, CCP1 pin = H
; Return / Enable Global Interrupts
;
FIVE_1
;
SIX_1
;
SEVEN_1
;
EIGHT_1
RET_FIE
;
page
;
;**********************************************************************
;*****
Start program here, Power-On Reset occurred.
;**********************************************************************
;
START
; POWER_ON Reset (Beginning of program)
BCF
STATUS, RP0
; Bank 0
CLRF
TMR1H
;
CLRF
TMR1L
;
;
MCLR_RESET
; A Master Clear Reset
BCF
STATUS, RP0
; Bank 0
CLRF
STATUS
; Do initialization (Bank 0)
CLRF
INTCON
CLRF
PIR1
BSF
STATUS, RP0
; Bank 1
MOVLW
0x80
; Disable PORTB weak pull-ups
MOVWF
OPTION_REG
;
CLRF
PIE1
; Disable all peripheral interrupts
 1997 Microchip Technology Inc.
DS00594B-page 15
AN594
0087 30FF
0088 009F
0089
008A
008B
008C
008D
008E
008F
0090
0091
0092
0093
0094
0095
0096
0097
0098
1283
0185
0186
0187
0188
0189
1010
1683
0185
30FF
0086
0187
0188
0189
150C
1283
0099
009A
009B
009C
018C
0190
170B
178B
009D
009E
009F
00A0
00A1
00A2
00A3
00A4
00A5
00A6
00A7
00A8
00A9
00AA
00AB
00AC
1010
3041
008F
3042
008E
038E
1803
038F
3008
0097
3009
00B1
01B2
30FF
00B3
1410
00AD
00AD
00AE
00AF
00B0
0831
1D03
28AD
0000
00B1 1005
DS00594B-page 16
00248
00249
00250
00251
00252
00253
00254
00255
00256
00257
00258
00259
00260
00261
00262
00263
00264
00265
00266
00267
00268
00269
00270
00271
00272
00273
00274
00275
00276
00277
00278
00279
00280
00281
00282
00283
00284
00285
00286
00287
00288
00289
00290
00291
00292
00293
00294
00295
00296
00297
00298
00299
00300
00301
00302
00303
00304
00305
00306
00307
00308
00309
00310
00311
00312
00313
MOVLW
MOVWF
0xFF
ADCON1
;
; Port A is Digital.
BCF
CLRF
CLRF
CLRF
CLRF
CLRF
BCF
STATUS, RP0
PORTA
PORTB
PORTC
PORTD
PORTE
T1CON, TMR1ON
; Bank 0
; ALL PORT output should output Low.
BSF
CLRF
MOVLW
MOVWF
CLRF
CLRF
CLRF
BSF
BCF
STATUS, RP0
TRISA
0xFF
TRISB
TRISC
TRISD
TRISE
PIE1, CCP1IE
STATUS, RP0
;
;
;
;
;
;
;
;
;
;
;
; Timer 1 is NOT incrementing
;
Select Bank 1
RA5 - 0 outputs
RB Port are
RC Port are
RD Port are
RE Port are
Enable CCP1
Select Bank
inputs
outputs
outputs
outputs
Interrupt
0
;
page
;
;
; Initialize the Special Function Registers (SFR) interrupts
;
CLRF
PIR1
;
CLRF
T1CON
; Timer mode
BSF
INTCON, PEIE
; Enable Peripheral Interrupts
BSF
INTCON, GIE
; Enable all Interrupts
;
; Set-up timer and compare latches and then turn timer1 on.
;
BCF
T1CON, TMR1ON ; Turn OFF timer1
MOVLW
CCPREG_HI
; TMR1 = CCPR1H:CCPR1L - 1
MOVWF
TMR1H
;
MOVLW
CCPREG_LO
;
MOVWF
TMR1L
;
DECF
TMR1L, F
;
BTFSC
STATUS, C
;
DECF
TMR1H, F
;
MOVLW
0x08
; On match CCP1 = H level
MOVWF
CCP1CON
;
MOVLW
0x09
;
MOVWF
DATA_CNT
; 8-bits to transfer
CLRF
ONES_CNT
; Result after xmit holds the number
MOVLW
0xFF
; of 1’s in a byte
MOVWF
CCP1_INT_CNT
; No CCP1 transmit interrups yet
BSF
T1CON, TMR1ON ; Turn ON timer1
;
;
; This code segment is an infinite loop that will always transmit the data
; contained in the XMIT_DATA register. After each byte is transmitted a
; new byte is read. If using PICMASTER (in stand alone mode), this is
; read from a register that is updated after a break (at NOP). If in a
; system, PORTB is read. All other variables are reinitalized after each
; byte.
NEXT_BYTE
;
WAIT
MOVF
DATA_CNT, w
;
BTFSS
STATUS, Z
; Is DATA_CNT = 0 ?
GOTO
WAIT
; NO, must wait until YES
NOP
;
if ( Debug )
bcf
PORTA, 0
; Turn off strobe
 1997 Microchip Technology Inc.
AN594
00B2
00B3
00B4
00B5
00B6
00B7
00B8
00B9
00BA
00BB
00BC
00BD
07FF
07FF
0000
0040
0080
07C0
00314
endif
;
00315
00316
if ( PICMaster )
0840
00317
MOVF
DUMMY_PB, W
;
00318
else
00319
MOVF
PORTB, W
;
00320
endif
00B0
00321
MOVWF
XMIT_DATA
; New data to transmit
30FF
00322
MOVLW
0xFF
;
00B3
00323
MOVWF
CCP1_INT_CNT
;
3009
00324
MOVLW
0x09
;
00B1
00325
MOVWF
DATA_CNT
;
01B2
00326
CLRF
ONES_CNT
;
28AD
00327
GOTO
NEXT_BYTE
;
00328 ;
00329 ;
00330 ; Here is where you do things depending on the type of RESET (Not a
00331 ; Power-On Reset).
1E03
00332 OTHER_RESET
BTFSS STATUS,NOT_TO ; WDT Time-out?
2808
00333 WDT_TIMEOUT
GOTO
ERROR1
; YES, This is error condition
00334
if ( Debug_PU )
287C
00335
goto
START
; MCLR reset, Goto START
00336
else
00337
GOTO
MCLR_RESET
; MCLR reset, Goto MCLR_RESET
00338
endif
00339 ;
00340
if (Debug )
0000
00341 END_START
NOP
; END label for debug
00342
endif
00343 ;
00344 ;
00345
org
PMEM_END
; End of Program Memory
2808
00346
GOTO
ERROR1
; If you get here your program was lost
00347
00348
end
: XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
: XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
: XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXX-: ---------------- ---------------- ---------------- ---------------X
All other memory blocks unused.
Program Memory
Program Memory
Errors
:
Warnings :
Messages :
Words Used:
Words Free:
0
0 reported,
0 reported,
 1997 Microchip Technology Inc.
191
3905
0 suppressed
10 suppressed
DS00594B-page 17
AN594
Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address:
www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not
required).
APPENDIX D:
nolist
;******************************************************************************
;
; This is the custom Header File for the real time clock application note
;
PROGRAM:CLOCK.H
;
Revision:7-13-94
;
;******************************************************************************
; This is used for the ASSEMBLER to recalculate certain frequency
; dependant variables. The value of Dev_Freq must be changed to
; reflect the frequency that the device actually operates at.
;
Dev_Freq
EQU D’10000000’; Device Frequency is 10 MHz
PULSE_TIME EQU (( Dev_Freq / D’4000’ ) * D’188’ / D’10000’ )
T_ZERO_BIT EQU (( Dev_Freq / D’4000’ ) * D’188’ / D’10000’ )
T_ONE_BIT
EQU (( Dev_Freq / D’4000’ ) * D’376’ / D’10000’ )
;
ZERO_1S
EQU ((( Dev_Freq / D’4000’ ) * (D’6000’ - (D’16’ * D’188’))) / D’10000’ )
ONE_1S
EQU ( ( Dev_Freq / D’4000’ ) * (D’6000’ - (3 * D’188’ + D’14’ * D’188’)) / D’10000’)
TWO_1S
EQU ( ( Dev_Freq / D’4000’ ) * (D’6000’ - (6 * D’188’ + D’12’ * D’188’)) / D’10000’)
THREE_1S
EQU ( ( Dev_Freq / D’4000’ ) * (D’6000’ - (D’9’ * D’188’ + D’10’ * D’188’)) / D’10000’)
FOUR_1S
EQU ( ( Dev_Freq / D’4000’ ) * (D’6000’ - (D’12’ * D’188’ + 8 * D’188’)) / D’10000’)
FIVE_1S
EQU ( ( Dev_Freq / D’4000’ ) * (D’6000’ - (D’15’ * D’188’ + 6 * D’188’)) / D’10000’)
SIX_1S
EQU ( ( Dev_Freq / D’4000’ ) * (D’6000’ - (D’18’ * D’188’ + 4 * D’188’)) / D’10000’)
SEVEN_1S
EQU ( ( Dev_Freq / D’4000’ ) * (D’6000’ - (D’21’ * D’188’ + 2 * D’188’)) / D’10000’)
EIGHT_1S
EQU ( ( Dev_Freq / D’4000’ ) * (D’6000’ - (D’24’ * D’188’) ) / D’10000’ )
DB_HI_BYTE EQU (HIGH ((( Dev_Freq / 4 ) * 1 / D’1000’ ) / 3 ) ) + 1
LCD_INIT_DELAY EQU (HIGH ((( Dev_Freq / 4 ) * D’46’ / D’10000’ ) / 3 ) ) + 1
INNER_CNTR EQU 40
; RAM Location
OUTER_CNTR EQU 41
; RAM Location
;
T1OSO
EQU 0
; The RC0 / T1OSO / T1CKI
;
RESET_V
EQU 0x0000
; Address of RESET Vector
ISR_V
EQU 0x0004
; Address of Interrupt Vector
PMEM_END
EQU 0x07FF
; Last address in Program Memory
TABLE_ADDR EQU 0x0400
; Address where to start Tables
;
COUNTER
EQU
0x021
;
;
XMIT_DATA
EQU
0x30
DATA_CNT
EQU
0x31
ONES_CNT
EQU
0x32
CCP1_INT_CNT
EQU
0x33
DUMMY_PB
EQU
0x40
CCPREG_HI
EQU
0x41
CCPREG_LO
EQU
0x42
;
list
DS00594B-page 18
 1997 Microchip Technology Inc.
AN594
Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address:
www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not
required).
APPENDIX E:
MPASM 01.40 Released
LOC OBJECT CODE
VALUE
CAPT_2.ASM
00000000
00000001
00000001
00000001
00000001
0000
0000
0001
0002
0003
1683
188E
282F
2861
1-16-1997
17:34:47
PAGE
1
LINE SOURCE TEXT
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00001
00002
00318
00025
00026
00027
00028
00029
00052
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
LIST
P = 16C74, n = 66
ERRORLEVEL -302
;
;********************************************************************
;
; This program implements a real time clock using the TMR1 module of the
; PIC16CXXX family.
;
;
Program = CAPT_2.ASM
;
Revision Date:
7-19-94
;
1-16-97
Compatibility with MPASMWIN 1.40
;
;
;*******************************************************************
;
;
; HARDWARE SETUP
;
;
CCP2 Compare Output
;
CCP1 Capture Input
;
CCP2 ---> CCP1
;
;
INCLUDE <p16c74.inc>
LIST
; P16C74.INC Standard Header File, Ver. 1.00 Microchip Technology, Inc.
LIST
FALSE
TRUE
EQU
EQU
0
1
INCLUDE <CAPT.h>
list
;
;
PICMaster
EQU
TRUE
; A Debugging Flag
Debug
EQU
TRUE
; A Debugging Flag
Debug_PU
EQU
TRUE
; A Debugging Flag
;
;
; Reset address. Determine type of RESET
;
org
RESET_V
; RESET vector location
RESET
BSF
STATUS, RP0
; Bank 1
BTFSC
PCON,NOT_POR
; Power-up reset?
GOTO
START
; YES
GOTO
OTHER_RESET
; NO, a WDT or MCLR reset
;
; This is the Periperal Interrupt routine. Need to determine the type
; of interrupt that occurred. The following interrupts are enabled:
;
1. CCP1 Capture Occurred
;
2. CCP2 Compare Occurred
;
page
 1997 Microchip Technology Inc.
DS00594B-page 19
AN594
0004
0004
0004
0005
0006
0007
0008
0009
000A
000B
000B
000C
000D
1283
190C
281D
180D
2811
180C
282D
1488
1088
280B
000E
000E 1508
000F 1108
0010 280E
0011
0011 100D
0012 0851
0013 079B
0014 1803
0015 0A9C
0016 0853
0017
0018
0019
001A
001B
001C
001C
079C
0AB3
141D
1C33
101D
0009
001D
001D
001E
001F
0020
0021
110C
0815
00C1
0816
00C0
0022
0023
0024
0025
0026
0027
0028
0843
02C1
1C03
03C0
0842
02C0
0815
DS00594B-page 20
00051
00052
00053
00054
00055
00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00108
00109
00110
00111
00112
00113
00114
00115
00116
org
PER_INT_V
ISR_V
BCF
BTFSC
GOTO
BTFSC
GOTO
BTFSC
GOTO
STATUS, RP0
PIR1, CCP1IF
CAPTURE
PIR2, CCP2IF
COMPARE
PIR1, TMR1IF
T1OVFL
BSF
BCF
GOTO
PORTD, 1
PORTD, 1
ERROR1
BSF
BCF
GOTO
PORTD, 2
PORTD, 2
ERROR2
ERROR1
;
ERROR2
; Interrupt vector location
;
;
;
;
;
;
;
;
;
Bank 0
CCP1 Interrupt occurred? (Capture)
YES, Service the CCP1 Interrupt
CCP2 Interrupt occurred? (Compare)
YES, Service the CCP2 Interrupt
NO, Timer 1 Overflow?
YES,
NO, Error Condition-Unknown Interrupt
Toggle a PORT pin
; NO, Error Condition-Unknown Interrupt
; Toggle a PORT pin
;
; The Compare generates a Square wave based on the value on PORTB (in
; DUMMY_PB) and on PORTD (in DUMMY_PD). PORTB is loaded into low compare
; latch and PORTD is loaded into the high compare latch. If the value of
; the ports is not changed, a capture overflow condition will occur when
; PORTD:PORTB > 7Fh. This overflow is only indicated by the time between
; captures being much less then expected.
COMPARE
BCF
PIR2, CCP2IF
; Clear CCP2 Interrupt Flag
if ( PICMaster )
MOVF
DUMMY_PB, W
;
else
MOVF
PORTB, W
;
endif
ADDWF
CCPR2L, F
; Update Compare register pair latch
BTFSC
STATUS, C
;
INCF
CCPR2H, F
;
if ( PICMaster )
MOVF
DUMMY_PD, W
;
else
MOVF
PORTD, W
;
endif
ADDWF
CCPR2H, F
;
INCF
CCP2_INT_CNT, F ;
BSF
CCP2CON, 0
; On Compare match, CCP2 pin = L
BTFSS
CCP2_INT_CNT, 0 ;
BCF
CCP2CON, 0
; On Compare match, CCP2 pin = H
END_COMPARE
RETFIE
; Return / Enable Global Interrupts
;
; The result of the new capture minus the old capture is stored in the
; new capture registers (CAPT_NEW_H:CAPT_NEW_L)
;
CAPTURE
BCF
PIR1, CCP1IF
; Clear CCP1 Interrupt Flag
MOVF
CCPR1L, W
; New capture value (low byte)
MOVWF
CAPT_NEW_L
;
MOVF
CCPR1H, W
; New capture value (high byte)
MOVWF
CAPT_NEW_H
;
;
MOVF
CAPT_OLD_L, W
;
SUBWF
CAPT_NEW_L, F
; Subtract the low bytes of the 2 captures
BTFSS
STATUS, C
; Did a borrow occur?
DECF
CAPT_NEW_H, F
; YES, Decrement old capture (high byte)
MOVF
CAPT_OLD_H, W
; New capture value (low byte)
SUBWF
CAPT_NEW_H, F
; Subtract the low bytes of the 2 captures
LOAD_OLD
MOVF
CCPR1L, W ; New capture value (low byte)
 1997 Microchip Technology Inc.
AN594
0029
002A
002B
002C
002C
00C3
0816
00C2
0009
002D
002D 100C
002E 0009
002F
002F 1283
0030 018F
0031 018E
0032
0032
0033
0034
0035
0036
0037
0038
0039
003A
003B
003C
1283
0183
018B
018C
1683
3000
0081
018C
018D
30FF
009F
003D
003E
003F
0040
0041
0042
0043
1283
0185
0186
0187
0188
0189
1010
0044
0045
0046
0047
0048
0049
004A
004B
004C
004D
004E
1683
0185
30FF
0086
0187
1507
0088
0189
150C
140D
1283
004F
0050
0051
0052
0053
018C
018D
0190
170B
178B
00117
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127
00128
00129
00130
00131
00132
00133
00134
00135
00136
00137
00138
00139
00140
00141
00142
00143
00144
00145
00146
00147
00148
00149
00150
00151
00152
00153
00154
00155
00156
00157
00158
00159
00160
00161
00162
00163
00164
00165
00166
00167
00168
00169
00170
00171
00172
00173
00174
00175
00176
00177
00178
00179
00180
00181
00182
MOVWF
CAPT_OLD_L
;
MOVF
CCPR1H, W
; New capture value (high byte)
MOVWF
CAPT_OLD_H
;
END_CAPTURE
RETFIE
;
;
T1OVFL
BCF
PIR1, TMR1IF
; Clear T1 Overflow Interrupt Flag
RETFIE
; Return / Enable Global Interrupts
;
;
;***********************************************************************
;*****
Start program here, Power-On Reset occurred.
;***********************************************************************
;
START
; POWER_ON Reset (Beginning of program)
BCF
STATUS, RP0
; Bank 0
CLRF
TMR1H
;
CLRF
TMR1L
;
;
MCLR_RESET
; A Master Clear Reset
BCF
STATUS, RP0
; Bank 0
CLRF
STATUS
; Do initialization (Bank 0)
CLRF
INTCON
CLRF
PIR1
BSF
STATUS, RP0
; Bank 1
MOVLW
0x00
; The LCD module does not like to work w/
MOVWF
OPTION_REG
;
weak pull-ups
CLRF
PIE1
; Disable all peripheral interrupts
CLRF
PIE2
; Disable all peripheral interrupts
MOVLW
0xFF
;
MOVWF
ADCON1
; Port A is Digital.
;
;
BCF
STATUS, RP0
; Bank 0
CLRF
PORTA
; ALL PORT output should output Low.
CLRF
PORTB
CLRF
PORTC
CLRF
PORTD
CLRF
PORTE
BCF
T1CON, TMR1ON
; Timer 1 is NOT incrementing
;
BSF
STATUS, RP0
; Select Bank 1
CLRF
TRISA
; RA5 - 0 outputs
MOVLW
0xFF
;
MOVWF
TRISB
; RB7 - 0 inputs
CLRF
TRISC
; RC Port are outputs
BSF
TRISC, 2
; CCP1 is an INPUT
MOVWF
TRISD
; RD Port are inputs
CLRF
TRISE
; RE Port are outputs
BSF
PIE1, CCP1IE
; Enable CCP1 Interrupt
BSF
PIE2, CCP2IE
; Enable CCP2 Interrupt
BCF
STATUS, RP0
; Select Bank 0
;
;
; Initialize the Special Function Registers (SFR) interrupts
;
CLRF
PIR1
;
CLRF
PIR2
;
CLRF
T1CON
; Timer mode
BSF
INTCON, PEIE
; Enable Peripheral Interrupts
BSF
INTCON, GIE
; Enable all Interrupts
;
; Set-up timer and compare latches and then turn timer1 on.
;
 1997 Microchip Technology Inc.
DS00594B-page 21
AN594
0054 1010
0055
0056
0057
0058
0059
005A
005B
005C
005D
005E
005F
0060
0061
0062
0063
0064
07FF
07FF
0000
0040
07C0
00183
BCF
T1CON, TMR1ON
; Turn OFF timer1
00184
if ( PICMaster )
0851
00185
MOVF
DUMMY_PB, W
;
00186
else
00187
MOVF
PORTB, W
;
00188
endif
079B
00189
ADDWF
CCPR2L, F
; Update Compare register pair latch
1803
00190
BTFSC
STATUS, C
;
0A9C
00191
INCF
CCPR2H, F
;
00192
if ( PICMaster )
08D3
00193
MOVF
DUMMY_PD, F
;
00194
else
00195
MOVF
PORTD, W
;
00196
endif
079C
00197
ADDWF
CCPR2H, F
;
3008
00198
MOVLW
0x08
; On match CCP2 = H level
009D
00199
MOVWF
CCP2CON
;
3005
00200
MOVLW
0x05
; Capture on every rising edge
0097
00201
MOVWF
CCP1CON
;
1410
00202
BSF
T1CON, TMR1ON
; Turn ON timer1
00203 ;
00204 ;
00205 ;
2860
00206 lzz goto
lzz
; Loop waiting for interrupts (for use
00207
;
with PICMASTER)
00208 ;
00209 ; Here is where you do things depending on the type of RESET (Not a
00210 ; Power-On Reset).
1E03
00211 OTHER_RESET
BTFSS STATUS,NOT_TO ; WDT Time-out?
280B
00212 WDT_TIMEOUT
GOTO
ERROR1
; YES, This is error condition
00213
if ( Debug_PU )
282F
00214
goto
START
; MCLR reset, Goto START
00215
else
00216
GOTO
MCLR_RESET
; MCLR reset, Goto MCLR_RESET
00217
endif
00218 ;
00219
if (Debug )
0000
00220 END_START
NOP
; END lable for debug
00221
endif
00222 ;
00223 ;
00224
org
PMEM_END
; End of Program Memory
280B
00225
GOTO
ERROR1
; If you get here your program was lost
00226
00227
end
: XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
: XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXX----------- ---------------: ---------------- ---------------- ---------------- ---------------X
All other memory blocks unused.
Program Memory
Program Memory
Errors
:
Warnings :
Messages :
Words Used:
Words Free:
0
0 reported,
0 reported,
DS00594B-page 22
102
3994
0 suppressed
13 suppressed
 1997 Microchip Technology Inc.
AN594
Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address:
www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not
required).
APPENDIX F:
nolist
;******************************************************************************
;
; This is the custom Header File for the real time clock application note
;
PROGRAM:CLOCK.H
;
Revision:7-19-94
;
;******************************************************************************
; This is used for the ASSEMBLER to recalculate certain frequency
; dependant variables. The value of Dev_Freq must be changed to
; reflect the frequency that the device actually operates at.
;
Dev_Freq
EQU
D’4000000’; Device Frequency is 4 MHz
DB_HI_BYTE
EQU
(HIGH ((( Dev_Freq / 4 ) * 1 / D’1000’ ) / 3 ) ) + 1
LCD_INIT_DELAY EQU
(HIGH ((( Dev_Freq / 4 ) * D’46’ / D’10000’ ) / 3 ) ) + 1
INNER_CNTR
EQU
40
; RAM Location
OUTER_CNTR
EQU
41
; RAM Location
;
T1OSO
EQU
0
; The RC0 / T1OSO / T1CKI
;
RESET_V
EQU
0x0000
; Address of RESET Vector
ISR_V
EQU
0x0004
; Address of Interrupt Vector
PMEM_END
EQU
0x07FF
; Last address in Program Memory
TABLE_ADDR
EQU
0x0400
; Address where to start Tables
;
COUNTER
EQU
0x021
;
CCP2_INT_CNT
EQU
0x33
;
;
; DUMMY_PD:DUMMY_PB contain the value to be loaded into the CCP2 compare registers
; (CCPR2H:CCPR2L)
;
DUMMY_PA
EQU
0x50
DUMMY_PB
EQU
0x51
DUMMY_PC
EQU
0x52
DUMMY_PD
EQU
0x53
DUMMY_PE
EQU
0x54
;
;
; CAPT_NEW_H:CAPT_NEW_L stores the NEW captured value and the result of the
; subtraction between this capture and the previous.
;
CAPT_NEW_H:CAPT_NEW_L = CAPT_NEW_H:CAPT_NEW_L - CAPT_OLD_H:CAPT_OLD_L
;
; After all computations the new capture value is moved to the CAPT_OLD_H:CAPT_OLD_L
; in preperation for the next capture value.
;
CAPT_NEW_H
EQU
0x040
;
CAPT_NEW_L
EQU
0x041
;
CAPT_OLD_H
EQU
0x042
;
CAPT_OLD_L
EQU
0x043
;
;
list
 1997 Microchip Technology Inc.
DS00594B-page 23
Note the following details of the code protection feature on PICmicro® MCUs.
•
•
•
•
•
•
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
 2002 Microchip Technology Inc.
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 2002 Microchip Technology Inc.
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