High Performance, 145 MHz FastFET Op Amps AD8065/AD8066 FEATURES APPLICATIONS Qualified for automotive applications FET input amplifier 1 pA input bias current Low cost High speed: 145 MHz, −3 dB bandwidth (G = +1) 180 V/μs slew rate (G = +2) Low noise 7 nV/√Hz (f = 10 kHz) 0.6 fA/√Hz (f = 10 kHz) Wide supply voltage range: 5 V to 24 V Single-supply and rail-to-rail output Low offset voltage 1.5 mV maximum High common-mode rejection ratio: −100 dB Excellent distortion specifications SFDR −88 dBc @ 1 MHz Low power: 6.4 mA/amplifier typical supply current No phase reversal Small packaging: SOIC-8, SOT-23-5, and MSOP-8 Automotive driver assistance systems Photodiode preamps Filters A/D drivers Level shifting Buffering CONNECTION DIAGRAMS VOUT 1 AD8065 5 +VS NC 1 –VS 2 +IN 3 4 TOP VIEW (Not to Scale) –IN AD8065 8 NC –IN 2 7 +VS +IN 3 6 VOUT –VS 4 5 NC TOP VIEW (Not to Scale) 8 +VS –IN1 2 7 VOUT2 +IN1 3 6 –IN2 –VS 4 5 +IN2 TOP VIEW (Not to Scale) 02916-E-001 AD8066 VOUT1 1 Figure 1. 1 The AD8065/AD8066 FastFET™ amplifiers are voltage feedback amplifiers with FET inputs offering high performance and ease of use. The AD8065 is a single amplifier, and the AD8066 is a dual amplifier. These amplifiers are developed in the Analog Devices, Inc. proprietary XFCB process and allow exceptionally low noise operation (7.0 nV/√Hz and 0.6 fA/√Hz) as well as very high input impedance. The AD8065/AD8066 are high performance, high speed, FET input amplifiers available in small packages: SOIC-8, MSOP-8, and SOT-23-5. They are rated to work over the industrial temperature range of −40°C to +85°C. The AD8065WARTZ-REEL7 is fully qualified for automotive applications. It is rated to operate over the extended temperature range (−40°C to +105°C), up to a maximum supply voltage range of +5V only. 24 With a wide supply voltage range from 5 V to 24 V, the ability to operate on single supplies, and a bandwidth of 145 MHz, the AD8065/AD8066 are designed to work in a variety of applications. For added versatility, the amplifiers also contain rail-to-rail outputs. G = +10 VO = 200mV p-p 18 15 GAIN (dB) Despite the low cost, the amplifiers provide excellent overall performance. The differential gain and phase errors of 0.02% and 0.02°, respectively, along with 0.1 dB flatness out to 7 MHz, make these amplifiers ideal for video applications. Additionally, they offer a high slew rate of 180 V/μs, excellent distortion (SFDR of −88 dBc @ 1 MHz), extremely high common-mode rejection of −100 dB, and a low input offset voltage of 1.5 mV maximum under warmed up conditions. The AD8065/AD8066 operate using only a 6.4 mA/amplifier typical supply current and are capable of delivering up to 30 mA of load current. 21 G = +5 12 9 G = +2 6 3 G = +1 0 –3 –6 0.1 1 10 100 FREQUENCY (MHz) 1000 02916-E-002 GENERAL DESCRIPTION Figure 2. Small Signal Frequency Response 1 Protected by U. S. Patent No. 6,262,633. Rev. J Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2010 Analog Devices, Inc. All rights reserved. AD8065/AD8066 TABLE OF CONTENTS Features .............................................................................................. 1 Wideband Operation ................................................................. 21 Applications ....................................................................................... 1 Input Protection ......................................................................... 21 Connection Diagrams ...................................................................... 1 Thermal Considerations............................................................ 22 General Description ......................................................................... 1 Input and Output Overload Behavior ..................................... 22 Revision History ............................................................................... 3 Layout, Grounding, and Bypassing Considerations .................. 23 Specifications ±5 V ........................................................................... 4 Power Supply Bypassing ............................................................ 23 Specifications ±12 V ......................................................................... 6 Grounding ................................................................................... 23 Specifications +5 V ........................................................................... 7 Leakage Currents ........................................................................ 23 Absolute Maximum Ratings............................................................ 9 Input Capacitance ...................................................................... 23 Maximum Power Dissipation ..................................................... 9 Output Capacitance ................................................................... 23 Output Short Circuit .................................................................... 9 Input-to-Output Coupling ........................................................ 24 ESD Caution .................................................................................. 9 Wideband Photodiode Preamp ................................................ 24 Typical Performance Characteristics ........................................... 10 High Speed JFET Input Instrumentation Amplifier.............. 25 Test Circuits ..................................................................................... 17 Video Buffer ................................................................................ 26 Theory of Operation ...................................................................... 20 Outline Dimensions ....................................................................... 27 Closed-Loop Frequency Response ........................................... 20 Ordering Guide .......................................................................... 28 Noninverting Closed-Loop Frequency Response .................. 20 Automotive Products ................................................................. 28 Inverting Closed-Loop Frequency Response ......................... 20 Rev. J | Page 2 of 28 AD8065/AD8066 REVISION HISTORY 8/10—Rev. I to Rev. J Changes to Features Section, Applications Section, and General Description Section ........................................................................... 1 Change to Table 1 .............................................................................. 4 Change to Table 3 .............................................................................. 7 Changes to Table 4 ............................................................................ 9 Changes to Figure 9.........................................................................10 Changes to Inverting Closed-Loop Frequency Response Section ..............................................................................................20 Moved Leakage Currents Section, Input Capacitance Section, and Output Capacitance Section ...................................................23 Moved Input-to-Input Coupling Section, Wideband Photodiode Preamp Section, and Figure 59 ................................24 Changes to Table 5 ..........................................................................25 Moved Figure 60 and High Speed JFET Input Instrumentation Amplifier Section ............................................................................25 Updated Outline Dimensions ........................................................27 Changes to Ordering Guide ...........................................................28 Added Automotive Products Section ...........................................28 3/09—Rev. H to Rev. I Changes to High Speed JFET Input Instrumentation Amplifier Section ..............................................................................................23 Updated Outline Dimensions ........................................................24 9/08—Rev. G to Rev. H Deleted Usable Range Parameter, Table 1 ...................................... 3 Deleted Usable Range Parameter, Table 2 ...................................... 4 Deleted Usable Range Parameter, Table 3 ...................................... 5 Changes to Layout ............................................................................. 6 Changes to Input and Output Overload Behavior Section........19 Changes to Table 5 Expressions Column .....................................22 1/06—Rev. F to Rev. G Changes to Ordering Guide ...........................................................26 12/05—Rev. E to Rev. F Updated Format ................................................................. Universal Changes to Features .......................................................................... 1 Changes to General Description ..................................................... 1 Changes to Figure 22 through Figure 27...................................... 11 Updated Outline Dimensions........................................................ 25 Changes to Ordering Guide ........................................................... 26 2/04—Rev. D to Rev. E. Updated Format ................................................................ Universal Updated Figure 56 ......................................................................... 21 Updated Outline Dimensions...................................................... 25 Updated Ordering Guide ............................................................. 26 11/03—Rev. C to Rev. D. Changes to Features .........................................................................1 Changes to Connection Diagrams .................................................1 Updated Ordering Guide ................................................................5 Updated Outline Dimensions...................................................... 22 4/03—Rev. B to Rev. C. Added SOIC-8 (R) for the AD8065 ...............................................4 2/03—Rev. A to Rev. B. Changes to Absolute Maximum Ratings.......................................4 Changes to Test Circuit 10 ........................................................... 14 Changes to Test Circuit 11 ........................................................... 15 Changes to Noninverting Closed-Loop Frequency Response 16 Changes to Inverting Closed-Loop Frequency Response ....... 16 Updated Figure 6 .......................................................................... 18 Changes to Figure 7 ...................................................................... 19 Changes to Figure 10 .................................................................... 21 Changes to Figure 11 .................................................................... 22 Changes to High Speed JFET Instrumentation Amplifier ...... 22 Changes to Video Buffer .............................................................. 22 8/02—Rev. 0 to Rev. A. Added AD8066 .................................................................. Universal Added SOIC-8 (R) and MSOP-8 (RM) .........................................1 Edits to General Description ..........................................................1 Edits to Specifications ......................................................................2 New Figure 2 .....................................................................................5 Changes to Ordering Guide ............................................................5 Edits to TPCs 18, 25, and 28 ...........................................................8 New TPC 36 ................................................................................... 11 Added Test Circuits 10 and 11 .................................................... 14 MSOP (RM-8) Added .................................................................. 23 Rev. J | Page 3 of 28 AD8065/AD8066 SPECIFICATIONS ±5 V @ TA = 25°C, VS = ±5 V, RL = 1 kΩ, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Input Overdrive Recovery Time Output Recovery Time Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE SFDR Third-Order Intercept Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Conditions Min Typ G = +1, VO = 0.2 V p-p (AD8065) AD8065WARTZ only: TMIN − TMAX G = +1, VO = 0.2 V p-p (AD8066) G = +2, VO = 0.2 V p-p G = +2, VO = 2 V p-p G = +2, VO = 0.2 V p-p G = +1, −5.5 V to +5.5 V G = −1, −5.5 V to +5.5 V G = +2, VO = 4 V step AD8065WARTZ only: TMIN − TMAX G = +2, VO = 2 V step G = +2, VO = 8 V step 100 88 100 145 55 205 fC = 1 MHz, G = +2, VO = 2 V p-p fC = 5 MHz, G = +2, VO = 2 V p-p fC = 1 MHz, G = +2, VO = 8 V p-p fC = 10 MHz, RL = 100 Ω f = 10 kHz f = 10 kHz NTSC, G = +2, RL = 150 Ω NTSC, G = +2, RL = 150 Ω −88 −67 −73 24 7 0.6 0.02 0.02 dBc dBc dBc dBm nV/√Hz fA/√Hz % Degrees VCM = 0 V, SOIC package AD8065WARTZ only: TMIN − TMAX 0.4 130 155 TMIN to TMAX VO = ±3 V, RL = 1 kΩ AD8065WARTZ only: TMIN − TMAX INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range FET Input Range Common-Mode Rejection Ratio 120 50 42 7 175 170 180 1 AD8065WARTZ only: TMIN − TMAX SOIC package TMIN to TMAX Input Offset Current Open-Loop Gain Unit MHz MHz MHz MHz MHz MHz ns ns V/μs V/μs ns ns Input Offset Voltage Drift Input Bias Current Max AD8065WARTZ only: TMIN − TMAX VCM = −1 V to +1 V VCM = −1 V to +1 V (SOT-23) AD8065WARTZ only: TMIN − TMAX Rev. J | Page 4 of 28 100 100 −5 to +1.7 −5 to +1.7 −85 −82 −82 2 25 1 1 113 1.5 2.6 17 17 6 125 10 125 mV mV μV/°C μV/°C pA pA pA pA dB dB 1000 || 2.1 1000 || 4.5 GΩ || pF GΩ || pF −5.0 to +2.4 V V dB dB dB −100 −91 AD8065/AD8066 Parameter OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Conditions Min Typ RL = 1 kΩ AD8065WARTZ only: TMIN − TMAX RL = 150 Ω VO = 9 V p-p, SFDR ≥ −60 dBc, f = 500 kHz −4.88 to +4.90 −4.88 to +4.90 −4.94 to +4.95 5 5 Quiescent Current per Amplifier Power Supply Rejection Ratio 6.4 AD8065WARTZ only: TMIN − TMAX ±PSRR AD8065WARTZ only: TMIN − TMAX Rev. J | Page 5 of 28 −85 −85 −100 Unit V V V mA mA pF −4.8 to +4.7 35 90 20 30% overshoot G = +1 AD8065WARTZ only: TMIN − TMAX Max 24 10 7.2 7.2 V V mA mA dB dB AD8065/AD8066 SPECIFICATIONS ±12 V @ TA = 25°C, VS = ±12 V, RL = 1 kΩ, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Input Overdrive Recovery Output Overdrive Recovery Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE SFDR Third-Order Intercept Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Conditions Min Typ G = +1, VO = 0.2 V p-p (AD8065) G = +1, VO = 0.2 V p-p (AD8066) G = +2, VO = 0.2 V p-p G = +2, VO = 2 V p-p G = +2, VO = 0.2 V p-p G = +1, −12.5 V to +12.5 V G = −1, −12.5 V to +12.5 V G = +2, VO = 4 V step G = +2, VO = 2 V step G = +2, VO = 10 V step 100 100 145 115 50 40 7 175 170 180 55 250 MHz MHz MHz MHz MHz ns ns V/μs ns ns fC = 1 MHz, G = +2, VO = 2 V p-p fC = 5 MHz, G = +2, VO = 2 V p-p fC = 1 MHz, G = +2, VO = 10 V p-p fC = 10 MHz, RL = 100 Ω f = 10 kHz f = 10 kHz NTSC, G = +2, RL = 150 Ω NTSC, G = +2, RL = 150 Ω −100 −67 −85 24 7 1 0.04 0.03 dBc dBc dBc dBm nV/√Hz fA/√Hz % Degrees VCM = 0 V, SOIC package 0.4 1 3 25 2 2 114 130 SOIC package TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range FET Input Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio TMIN to TMAX VO = ±10 V, RL = 1 kΩ VCM = −1 V to +1 V VCM = −1 V to +1 V (SOT-23) RL = 1 kΩ RL = 350 Ω VO = 22 V p-p, SFDR ≥ −60 dBc, f = 500 kHz 103 10 mV μV/°C pA pA pA pA dB GΩ || pF GΩ || pF −12 to +8.5 −85 −82 −12.0 to +9.5 −100 −91 V dB dB −11.8 to +11.8 −11.9 to +11.9 −11.25 to +11.5 30 120 25 V V mA mA pF 5 −84 Rev. J | Page 6 of 28 1.5 17 7 Unit 1000 || 2.1 1000 || 4.5 30% overshoot G = +1 ±PSRR Max 6.6 −93 24 7.4 V mA dB AD8065/AD8066 SPECIFICATIONS +5 V @ TA = 25°C, VS = 5 V, RL = 1 kΩ, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Input Overdrive Recovery Time Output Recovery Time Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE SFDR Third-Order Intercept Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Conditions Min Typ G = +1, VO = 0.2 V p-p (AD8065) AD8065WARTZ only: TMIN − TMAX G = +1, VO = 0.2 V p-p (AD8066) G = +2, VO = 0.2 V p-p G = +2, VO = 2 V p-p G = +2, VO = 0.2 V p-p G = +1, −0.5 V to +5.5 V G = −1, −0.5 V to +5.5 V G = +2, VO = 2 V step AD8065WARTZ only: TMIN − TMAX G = +2, VO = 2 V step 125 90 110 155 60 fC = 1 MHz, G = +2, VO = 2 V p-p fC = 5 MHz, G = +2, VO = 2 V p-p fC = 10 MHz, RL = 100 Ω f = 10 kHz f = 10 kHz NTSC, G = +2, RL = 150 Ω NTSC, G = +2, RL = 150 Ω −65 −50 22 7 0.6 0.13 0.16 dBc dBc dBm nV/√Hz fA/√Hz % Degrees VCM = 1.0 V, SOIC package AD8065WARTZ only: TMIN − TMAX 0.4 105 123 TMIN to TMAX VO = 1 V to 4 V (AD8065) AD8065WARTZ only: TMIN − TMAX VO = 1 V to 4 V (AD8066) INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range FET Input Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive 130 50 43 6 175 170 160 103 mV mV μV/ºC μV/ºC pA pA pA pA dB dB dB 1000 || 2.1 1000 || 4.5 GΩ || pF GΩ || pF 0 to 2.4 V V dB dB dB 1 AD8065WARTZ only: TMIN − TMAX SOIC package TMIN to TMAX Input Offset Current Open-Loop Gain Unit MHz MHz MHz MHz MHz MHz ns ns V/μs V/μs ns Input Offset Voltage Drift Input Bias Current Max AD8065WARTZ only: TMIN − TMAX VCM = 0.5 V to 1.5 V VCM = 1 V to 2 V (SOT-23) AD8065WARTZ only: TMIN-TMAX RL = 1 kΩ AD8065WARTZ only: TMIN − TMAX RL = 150 Ω VO = 4 V p-p, SFDR ≥ −60 dBc, f = 500 kHz 30% overshoot G = +1 Rev. J | Page 7 of 28 100 100 90 0 to 1.7 0 to 1.7 −74 −78 −76 0.1 to 4.85 0.1 to 4.85 1 25 1 1 113 −100 −91 0.03 to 4.95 0.07 to 4.83 35 75 5 1.5 2.6 17 17 5 125 5 125 V V V mA mA pF AD8065/AD8066 Parameter POWER SUPPLY Operating Range Conditions Min AD8065WARTZ only: TMIN − TMAX 5 5 5.8 Quiescent Current per Amplifier Power Supply Rejection Ratio AD8065WARTZ only: TMIN − TMAX ±PSRR AD8065WARTZ only: TMIN − TMAX Rev. J | Page 8 of 28 −78 −78 Typ 6.4 −100 Max Unit 24 10 7.0 7.0 V V mA mA dB dB AD8065/AD8066 ABSOLUTE MAXIMUM RATINGS RMS output voltages should be considered. If RL is referenced to VS−, as in single-supply operation, then the total drive power is VS × IOUT. Table 4. Rating 26.4 V See Figure 3 VEE − 0.5 V to VCC + 0.5 V 1.8 V −65°C to +125°C −40°C to +85°C −40°C to +105°C 300°C If the rms signal levels are indeterminate, then consider the worst case, when VOUT = VS/4 for RL to midsupply. PD = (VS × I S ) + (VS /4)2 RL In single-supply operation with RL referenced to VS−, worst case is VOUT = VS/2. 2.0 MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8065/AD8066 packages is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8065/AD8066. Exceeding a junction temperature of 175°C for an extended time can result in changes in the silicon devices, potentially causing failure. The still air thermal properties of the package and PCB (θJA), ambient temperature (TA), and total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature can be calculated by 1.5 MSOP-8 SOIC-8 1.0 SOT-23-5 0.5 0 –60 –40 –20 0 20 40 60 AMBIENT TEMPERATURE (°C) 80 100 02916-E-003 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAXIMUM POWER DISSIPATION (W) Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Differential Input Voltage Storage Temperature Range Operating Temperature Range AD8065WARTZ Only Lead Temperature (Soldering, 10 sec) Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board Airflow increases heat dissipation, effectively reducing θJA. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduce the θJA. Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps as discussed in the Layout, Grounding, and Bypassing Considerations section. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the SOIC (125°C/W), SOT-23 (180°C/W), and MSOP (150°C/W) packages on a JEDEC standard 4-layer board. θJA values are approximations. TJ = TA + (PD × θJA) The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, then the total drive power is VS /2 × IOUT, some of which is dissipated in the package and some in the load (VOUT × IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = Quiescent Power + (Total Drive Power − Load Power ) OUTPUT SHORT CIRCUIT Shorting the output to ground or drawing excessive current for the AD8065/AD8066 will likely cause catastrophic failure. ESD CAUTION ⎛V V ⎞ V OUT 2 PD = (VS × I S ) + ⎜ S × OUT ⎟ − RL ⎠ RL ⎝ 2 Rev. J | Page 9 of 28 AD8065/AD8066 TYPICAL PERFORMANCE CHARACTERISTICS Default Conditions: ±5 V, CL = 5 pF, RL = 1 kΩ, VOUT = 2 V p-p, Temperature = 25°C. 24 21 6.9 RL = 150Ω 6.8 G = +10 G = +2 VO = 200mV p-p 18 G = +5 VOUT = 0.7V p-p 6.6 12 9 G = +2 6 VOUT = 1.4V p-p 6.5 GAIN (dB) GAIN (dB) 15 VOUT = 0.2V p-p 6.7 6.4 6.3 3 6.2 0 6.1 –3 6.0 1 10 100 1000 FREQUENCY (MHz) 5.9 0.1 02916-E-004 –6 0.1 1 10 02916-E-007 G = +1 100 FREQUENCY (MHz) Figure 4. Small Signal Frequency Response for Various Gains Figure 7. 0.1 dB Flatness Frequency Response (See Figure 43) 6 9 VO = 200mV p-p VO = 200mV p-p G = +1 G = +2 4 8 VS = +5V VS = +5V 7 GAIN (dB) 0 VS = ±12V 6 VS = ±12V –2 5 –4 4 –6 0.1 1 10 100 1000 FREQUENCY (MHz) VS = ±5V 3 0.1 10 100 1000 FREQUENCY (MHz) Figure 5. Small Signal Frequency Response for Various Supplies (See Figure 42) Figure 8. Small Signal Frequency Response for Various Supplies (See Figure 43) 8 2 VO = 2V p-p 1 1 02916-E-008 VS = ±5V 02916-E-005 GAIN (dB) 2 G = +1 7 VO = 2V p-p G = +2 VS = +5V VS = ±5V 6 0 VS = ±12V GAIN (dB) –1 VS = ±12V –2 5 4 3 –3 2 –4 1 10 100 1000 FREQUENCY (MHz) 0 0.1 1 10 100 1000 FREQUENCY (MHz) Figure 9. Large Signal Frequency Response for Various Supplies (See Figure 43) Figure 6. Large Signal Frequency Response for Various Supplies (See Figure 42) Rev. J | Page 10 of 28 02916-009 –5 0.1 1 02916-E-006 GAIN (dB) VS = ±5V AD8065/AD8066 9 8 VO = 200mV p-p G = +1 6 CL = 25pF CL = 25pF RSNUB = 20Ω 6 CL = 55pF CL = 5pF 4 CL = 20pF CL = 25pF GAIN (dB) GAIN (dB) 3 0 CL = 5pF 2 0 –2 –3 –4 –6 1 10 100 1000 FREQUENCY (MHz) –8 0.1 02916-E-010 –9 0.1 Figure 10. Small Signal Frequency Response for Various CLOAD (See Figure 42) VO = 200mV p-p G = +2 1 10 100 1000 FREQUENCY (MHz) 02916-E-013 –6 Figure 13. Small Signal Frequency Response for Various CLOAD (See Figure 43) 8 8 VOUT = 0.2V p-p 6 6 2 5 VOUT = 4V p-p 0 4 –2 3 –4 2 –6 1 –8 0.1 0 0.1 1 10 100 1000 FREQUENCY (MHz) Figure 11. Frequency Response for Various Output Amplitudes (See Figure 43) RL = 1kΩ VO = 200mV p-p G = +2 1 10 100 1000 FREQUENCY (MHz) 02916-E-014 GAIN (dB) 4 02916-E-011 GAIN (dB) RL = 100Ω 7 VOUT = 2V p-p G = +2 Figure 14. Small Signal Frequency Response for Various RLOAD (See Figure 43) 120 80 14 VO = 200mV p-p G = +2 GAIN (dB) 8 RF = RG = 500Ω, RS = 250Ω 6 4 RF = RG = 1kΩ, RS = 500Ω, CF = 3.3pF 2 RF = RG = 500Ω, RS = 250Ω, CF = 2.2pF 0 60 60 40 0 GAIN 20 –60 0 –120 PHASE (DEGREES) PHASE RF = RG = 1kΩ, RS = 500Ω 10 OPEN-LOOP GAIN (dB) 12 1 10 FREQUENCY (MHz) 100 1000 Figure 12. Small Signal Frequency Response for Various RF/CF (See Figure 43) Rev. J | Page 11 of 28 –20 0.01 0.1 1 10 100 FREQUENCY (MHz) Figure 15. Open-Loop Response –180 1000 02916-E-015 –4 0.1 02916-E-012 –2 AD8065/AD8066 –40 –30 –40 G = +2 –50 –50 DISTORTION (dBc) –70 HD2 RL = 150Ω HD2 RL = 1kΩ –80 HD3 RL = 1kΩ –90 HD2 G = +2 HD2 G = +1 –80 –90 HD3 RL = 150Ω –100 HD3 G = +1 1 10 100 FREQUENCY (MHz) –110 0.1 02916-E-016 –120 0.1 1 10 100 FREQUENCY (MHz) 02916-E-019 –100 –110 Figure 19. Harmonic Distortion vs. Frequency for Various Gains (See Figure 42 and Figure 43) Figure 16. Harmonic Distortion vs. Frequency for Various Loads (See Figure 43) –20 –30 –40 –30 G = +2 VS = ±12V F = 1MHz –60 HD2 RL = 150Ω –70 HD3 RL = 150Ω –80 VS = ±12V G = +2 HD2 VO = 20V p-p –40 –90 HD2 RL = 300Ω –100 HD3 VO = 20V p-p –50 DISTORTION (dBc) –50 DISTORTION (dBc) HD3 G = +2 –70 –60 HD2 VO = 10V p-p –70 –80 HD3 VO = 10V p-p –90 HD2 VO = 2V p-p –100 HD3 RL = 300Ω –120 0 1 2 3 4 5 6 7 HD3 VO = 2V p-p –110 8 9 10 11 12 13 14 15 OUTPUT AMPLITUDE (V p-p) –120 0.1 02916-E-017 –110 1.0 10.0 FREQUENCY (MHz) Figure 17. Harmonic Distortion vs. Amplitude for Various Loads VS = ±12 V (See Figure 43) 02916-E-020 DISTORTION (dBc) –60 –60 Figure 20. Harmonic Distortion vs. Frequency for Various Amplitudes (See Figure 43) 50 100 RL = 100Ω VS = ±12V 40 NOISE (nV/ Hz) VS = ±5V 35 30 VS = +5V 10 25 15 1 10 FREQUENCY (MHz) 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 21. Voltage Noise Figure 18. Third-Order Intercept vs. Frequency and Supply Voltage Rev. J | Page 12 of 28 10M 100M 1G 02916-E-021 20 02916-E-018 INTERCEPT POINT (dBm) 45 AD8065/AD8066 G = +1 CL = 20pF G = +1 CL = 5pF 25ns/DIV 50mV/DIV 25ns/DIV Figure 22. Small Signal Transient Response 5 V Supply (See Figure 42) G = +1 VS = ±12V 02916-025 02916-022 50mV/DIV Figure 25. Small Signal Transient Response ±5 V (See Figure 42) VOUT = 10V p-p VOUT = 10V p-p G5µs = +2 VS = ±12V VOUT = 4V p-p VOUT = 2V p-p VOUT = 2V p-p 2V/DIV 50ns/DIV 50ns/DIV Figure 23. Large Signal Transient Response (See Figure 42) 02916-026 02916-023 2V/DIV Figure 26. Large Signal Transient Response (See Figure 43) G = –1 VS = ±5V 2.0V/DIV 100ns/DIV 100ns/DIV Figure 24. Output Overdrive Recovery (See Figure 44) 02916-027 02916-024 2.0V/DIV G = +1 VS = ±5V Figure 27. Input Overdrive Recovery (See Figure 42) Rev. J | Page 13 of 28 AD8065/AD8066 VIN = 140mV/DIV VIN = 500mV/DIV VOUT – 2VIN +0.1% –0.1% +0.1% t=0 –0.1% t=0 VOUT – 2VIN 2mV/DIV 02916-E-028 10ns/DIV 02916-E-031 64 μs/DIV 2mV/DIV Figure 31. 0.1% Short-Term Settling Time (See Figure 49) Ib (μA) 0 –Ib –10 –Ib –Ib 0 –20 –5 +Ib –10 –15 –30 25 35 45 55 65 75 85 TEMPERATURE (°C) 02916-E-029 –20 –25 –30 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 COMMON-MODE VOLTAGE (V) 02916-E-032 FET INPUT STAGE 5 +Ib –25 Figure 32. Input Bias Current vs. Common-Mode Voltage Range (See the Input and Output Overload Behavior Section) Figure 29. Input Bias Current vs. Temperature 0.3 40 N = 299 SD = 0.388 MEAN = –0.069 35 0.2 30 0.1 25 VS = +5V 0 VS = ±5V 20 –0.1 15 VS = ±12V 10 –0.2 –0.3 –14 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14 COMMON-MODE VOLTAGE (V) Figure 30. Input Offset Voltage vs. Common-Mode Voltage 0 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 INPUT OFFSET VOLTAGE (mV) Figure 33. Input Offset Voltage Rev. J | Page 14 of 28 1.5 2.0 02916-E-033 5 02916-E-030 OFFSET VOLTAGE (mV) +Ib 10 –15 Ib (pA) INPUT BIAS CURRENT (pA) –5 42 36 30 24 18 12 6 0 BJT INPUT STAGE Figure 28. Long-Term Settling Time (See Figure 49) AD8065/AD8066 100 –30 –40 OUTPUT IMPEDANCE (Ω) 10 CMRR (dB) –50 –60 –70 VS = ±12V –80 1 G = +1 G = +2 0.1 0.01 1 10 100 FREQUENCY (MHz) 0 100 02916-E-034 –100 0.1 100k 1M 10M 100M FREQUENCY (Hz) 80 0.25 VCC – VOH 0.20 0.15 0.10 VOL – VEE 0 0 10 20 30 40 ILOAD (mA) VCC – VOH 60 50 VOL – VEE 40 30 02916-E-035 0.05 70 25 35 45 55 65 75 85 TEMPERATURE (°C) 02916-E-038 OUTPUT SATURATION VOLTAGE (mV) 0.30 Figure 38. Output Saturation Voltage vs. Temperature Figure 35. Output Saturation Voltage vs. Output Load Current 0 0 –10 –10 –20 VIN = 2V p-p G = +1 –20 CROSSTALK (dB) –PSRR –30 +PSRR –40 –50 –60 –70 –30 –40 –50 B TO A –60 –70 –80 A TO B –80 –100 0.01 0.1 1 10 100 1000 FREQUENCY (MHz) 02916-E-036 –90 Figure 36. PSRR vs. Frequency (See Figure 48 and Figure 50) –90 0.1 1 10 100 FREQUENCY (MHz) Figure 39. Crosstalk vs. Frequency (See Figure 51) Rev. J | Page 15 of 28 02916-E-039 OUTPUT SATURATION VOLTAGE (V) 10k Figure 37. Output Impedance vs. Frequency (See Figure 45 and Figure 47) Figure 34. CMRR vs. Frequency (See Figure 46) PSRR (dB) 1k 02916-E-037 VS = ±5V –90 AD8065/AD8066 6.60 125 VS = ±12V 6.55 120 VS = ±5V OPEN-LOOP GAIN (dB) 6.45 VS = +5V 6.40 6.35 VS = ±12V 110 105 100 VS = +5V 95 VS = ±5V 90 6.30 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 40. Quiescent Supply Current vs. Temperature for Various Supply Voltages 80 0 10 20 ILOAD (mA) 30 40 02916-E-041 85 6.25 –40 02916-E-040 SUPPLY CURRENT (mA) 115 6.50 Figure 41. Open-Loop Gain vs. Load Current for Various Supply Voltages Rev. J | Page 16 of 28 AD8065/AD8066 TEST CIRCUITS SOIC-8 Pinout +VCC +VCC 4.7μF 4.7μF 0.1μF 0.1μF 2.2pF 24.9Ω 499Ω VIN 499Ω 49.9Ω RSNUB FET PROBE FET PROBE AD8065 AD8065 VIN 249Ω CLOAD 4.7μF 4.7μF 02916-E-042 0.1μF –VEE –VEE Figure 44. G = −1 Figure 42. G = +1 +VCC +VCC 4.7μF 4.7μF 0.1μF 0.1μF 2.2pF 499Ω 1kΩ 0.1μF 02916-E-044 1kΩ 49.9Ω 24.9Ω 499Ω FET PROBE RSNUB AD8065 VIN AD8065 NETWORK ANALYZER S22 0.1μF 49.9Ω 1kΩ CLOAD 0.1μF 4.7μF 02916-E-043 –VEE 4.7μF Figure 43. G = +2 –VEE Figure 45. Output Impedance G = +1 Rev. J | Page 17 of 28 02916-E-045 249Ω AD8065/AD8066 +VCC VIN 1V p-p 4.7μF +VCC 49.9Ω 0.1μF 24.9Ω 499Ω 499Ω VIN FET PROBE FET PROBE AD8065 AD8065 49.9Ω 499Ω 1kΩ 0.1μF 4.7μF 4.7μF –VEE –VEE Figure 46. CMRR Figure 48. Positive PSRR +VCC +VCC 4.7μF 4.7μF 0.1μF 0.1μF 2.2pF 499Ω 499Ω 499Ω AD8065 NETWORK ANALYZER S22 976Ω 249Ω TO SCOPE AD8065 VIN 0.1μF 0.1μF 49.9Ω 49.9Ω 4.7μF –VEE 02916-E-047 249Ω 4.7μF –VEE Figure 49. Settling Time Figure 47. Output Impedance G = +2 Rev. J | Page 18 of 28 02916-E-049 499Ω 1kΩ 02916-E-048 0.1μF 02916-E-046 499Ω AD8065/AD8066 2.2pF +VCC 4.7μF 499Ω 499Ω 0.1μF 5V 4.7μF 1.5V 24.9Ω 0.1μF FET PROBE 249Ω FET PROBE AD8065 VIN AD8065 1kΩ 49.9Ω 1.5V 1.5V 02916-E-050 VIN 1V p-p –VEE Figure 50. Negative PSRR Figure 52. Single Supply 24.9Ω FET PROBE 24.9Ω AD8066 +5V 1kΩ 4.7μF 0.1μF RECEIVE SIDE AD8066 VIN 0.1μF 1kΩ 49.9Ω –5V DRIVE SIDE 02916-E-051 4.7μF Figure 51. Crosstalk—AD8066 Rev. J | Page 19 of 28 02916-E-052 49.9Ω 1kΩ AD8065/AD8066 THEORY OF OPERATION The AD8065/AD8066 are voltage feedback operational amplifiers that combine a laser-trimmed JFET input stage with the Analog Devices eXtra Fast Complementary Bipolar (XFCB) process, resulting in an outstanding combination of precision and speed. The supply voltage range is from 5 V to 24 V. The amplifiers feature a patented rail-to-rail output stage capable of driving within 0.5 V of either power supply while sourcing or sinking up to 30 mA. Also featured is a single-supply input stage that handles commonmode signals from below the negative supply to within 3 V of the positive rail. Operation beyond the JFET input range is possible because of an auxiliary bipolar input stage that functions with input voltages up to the positive supply. The amplifiers operate as if they have a rail-to-rail input and exhibit no phase reversal behavior for common-mode voltages within the power supply. With voltage noise of 7 nV/√Hz and −88 dBc distortion for 1 MHz, 2 V p-p signals, the AD8065/AD8066 are a great choice for high resolution data acquisition systems. Their low noise, sub-pA input current, precision offset, and high speed make them superb preamps for fast photodiode applications. The speed and output drive capability of the AD8065/AD8066 also make them useful in video applications. CLOSED-LOOP FREQUENCY RESPONSE The AD8065/AD8066 are classic voltage feedback amplifiers with an open-loop frequency response that can be approximated as the integrator response shown in Figure 53. Basic closed-loop frequency response for inverting and noninverting configurations can be derived from the schematics shown. NONINVERTING CLOSED-LOOP FREQUENCY RESPONSE Solving for the transfer function 2π × f crossover (RG + RF ) VO = VI (RF + RG ) s + 2π × f crossover × RG where fcrossover is the frequency where the amplifier’s open-loop gain equals 0 db At dc VO RF + RG = VI RG Closed-loop −3 dB frequency INVERTING CLOSED-LOOP FREQUENCY RESPONSE −2π × f crossover × RF VO = VI s (RF + RG ) + 2π × f crossover × RG At dc VO R =− F VI RG Closed-loop −3 dB frequency f −3dB = f crossover × RF VI VE VO A RG VE A VO A = (2π × fcrossover)/s 80 60 40 fcrossover = 65MHz 20 0 0.01 0.1 1 FREQUENCY (MHz) 10 100 Figure 53. Open-Loop Gain vs. Frequency and Basic Connections Rev. J | Page 20 of 28 02916-E-053 OPEN-LOOP GAIN (A) (dB) RG R F + RG RF RG VI RG RF + RG f −3dB = f crossover × AD8065/AD8066 The closed-loop bandwidth is inversely proportional to the noise gain of the op amp circuit, (RF + RG )/RG. This simple model is accurate for noise gains above 2. The actual bandwidth of circuits with noise gains at or below 2 is higher than those predicted with this model due to the influence of other poles in the frequency response of the real op amp. RF VO Ib+ Figure 54. Voltage Feedback Amplifier DC Errors Figure 54 shows a voltage feedback amplifier’s dc errors. For both inverting and noninverting configurations ⎛ R + RF ⎞ VO (error ) = I b+ × RS ⎜ G ⎟ − I b− × RF + VOS ⎝ RG ⎠ ⎛ RG + RF ⎞ ⎜ ⎟ ⎝ RG ⎠ The voltage error due to Ib+ and Ib– is minimized if RS = RF || RG (though with the AD8065 input currents at typically less than 20 pA over temperature, this is likely not a concern). To include common-mode and power supply rejection effects, total VOS can be modeled VOS = VOSnom + The closed-loop gain of the application Whether it is inverting or noninverting Amplifier loading Signal frequency and amplitude Board layout Δ VS Δ VCM + PSR CMR VOSnom is the offset voltage specified at nominal conditions, ΔVS is the change in power supply from nominal conditions, PSR is the power supply rejection, ΔVCM is the change in commonmode voltage from nominal conditions, and CMR is the commonmode rejection. INPUT PROTECTION The inputs of the AD8065/AD8066 are protected with back-toback diodes between the input terminals as well as ESD diodes to either power supply. This results in an input stage with picoamps of input current that can withstand up to 1500 V ESD events (human body model) with no degradation. Excessive power dissipation through the protection devices destroys or degrades the performance of the amplifier. Differential voltages greater than 0.7 V result in an input current of approximately (|V+ − V−| 0.7 V)/RI, where RI is the resistance in series with the inputs. For input voltages beyond the positive supply, the input current is approximately (VI − VCC − 0.7)/RI. Beyond the negative supply, the input current is about (VI − VEE + 0.7)/RI. If the inputs of the amplifier are to be subjected to sustained differential voltages greater than 0.7 V, or to input voltages beyond the amplifier power supply, input current should be limited to 30 mA by an appropriately sized input resistor (RI), as shown in Figure 55. RI > (| V+– V– | – 0.7V) RI > FOR LARGE | V+ – V– | WIDEBAND OPERATION Figure 42 through Figure 44 show the circuits used for wideband characterization for gains of +1, +2, and −1. Source impedance at the summing junction (RF || RG) forms a pole in the amplifier’s loop response with the amplifier’s input capacitance of 6.6 pF. This can cause peaking and ringing if the time constant formed is too low. Feedback resistances of 300 Ω to 1 kΩ are recommended, because they do not unduly load down the amplifier, and the time constant formed will not be too low. Peaking in the frequency response can be compensated for with a small capacitor (CF) in parallel with the feedback resistor, as illustrated in Figure 12. This shows the effect of different feedback capacitances on the peaking and bandwidth for a noninverting G = +2 amplifier. For the best settling times and the best distortion, the impedances at the AD8065/AD8066 input terminals should be matched. This minimizes nonlinear common-mode capacitive effects that can degrade ac performance. Rev. J | Page 21 of 28 (VI – VEE – 0.7V) 30mA 30mA VI RI RI > AD8065 (VI – VEE + 0.7V) 30mA FOR VI BEYOND SUPPLY VOLTAGES VO 02916-E-055 A 02916-E-054 VI Ib – RS • • • • • Also see Figure 16 to Figure 20. The lowest distortion is obtained with the AD8065 used in low gain inverting applications, because this eliminates common-mode effects. Higher closedloop gains result in worse distortion performance. +VOS – RG Actual distortion performance depends on a number of variables: Figure 55. Current-Limiting Resistor AD8065/AD8066 THERMAL CONSIDERATIONS INPUT AND OUTPUT OVERLOAD BEHAVIOR With 24 V power supplies and 6.5 mA quiescent current, the AD8065 dissipates 156 mW with no load. The AD8066 dissipates 312 mW. This can lead to noticeable thermal effects, especially in the small SOT-23-5 (thermal resistance of 160°C/W). VOS temperature drift is trimmed to guarantee a maximum drift of 17 μV/°C, so it can change up to 0.425 mV due to warm-up effects for an AD8065/AD8066 in a SOT-23-5 package on 24 V. A simplified schematic of the AD8065/AD8066 input stage is shown in Figure 56. This shows the cascoded N-channel JFET input pair, the ESD and other protection diodes, and the auxiliary NPN input stage that eliminates any phase inversion behavior. When the common-mode input voltage to the amplifier is driven to within approximately 3 V of the positive power supply, the input JFET’s bias current turns off and the bias of the NPN pair turns on, taking over control of the amplifier. The NPN differential pair now sets the amplifier’s offset, and the input bias current is now in the range of several tens of microamps. This behavior is shown in Figure 32. Normal operation resumes when the common-mode voltage goes below the 3 V from the positive supply threshold. Ib increases by a factor of 1.7 for every 10°C rise in temperature. Ib is close to five times higher at 24 V supplies as opposed to a single 5 V supply. Heavy loads increase power dissipation and raise the chip junction temperature as described in the Maximum Power Dissipation section. Care should be taken not to exceed the rated power dissipation of the package. The output transistors of the rail-to-rail output stage have circuitry to limit the extent of their saturation when the output is overdriven. This helps output recovery time. Output recovery from a 0.5 V output overdrive on a ±5 V supply is shown in Figure 24. VCC R1 R5 TO REST OF AMP Q2 VTHRESHOLD Q5 VBIAS D1 R6 R3 Q3 S Q6 D2 D3 R4 VP D4 Q4 S R7 R2 R8 IT1 Q7 IT2 –VEE Figure 56. Simplified Input Stage Rev. J | Page 22 of 28 02916-E-056 Q1 VN AD8065/AD8066 LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS Power supply pins are actually inputs and care must be taken so that a noise-free stable dc voltage is applied. The purpose of bypass capacitors is to create low impedances from the supply to ground at all frequencies, thereby shunting or filtering most of the noise. Decoupling schemes are designed to minimize the bypassing impedance at all frequencies with a parallel combination of capacitors. 0.1 μF (X7R or NPO) chip capacitors are critical and should be as close as possible to the amplifier package. The 4.7 μF tantalum capacitor is less critical for high frequency bypassing, and, in most cases, only one is needed per board at the supply inputs. GROUNDING A ground plane layer is important in densely packed PC boards to spread the current minimizing parasitic inductances. However, an understanding of where the current flows in a circuit is critical to implementing effective high speed circuit design. The length of the current path is directly proportional to the magnitude of parasitic inductances and, therefore, the high frequency impedance of the path. High speed currents in an inductive ground return create unwanted voltage noise. The length of the high frequency bypass capacitor leads is most critical. A parasitic inductance in the bypass grounding works against the low impedance created by the bypass capacitor. Place the ground leads of the bypass capacitors at the same physical location. Because load currents flow from the supplies as well, the ground for the load impedance should be at the same physical location as the bypass capacitor grounds. For the larger value capacitors, which are effective at lower frequencies, the current return path distance is less critical. inputs and surrounding area to set up any leakage currents. For the guard ring to be completely effective, it must be driven by a relatively low impedance source and should completely surround the input leads on all sides, above and below, using a multilayer board. Another effect that can cause leakage currents is the charge absorption of the insulator material itself. Minimizing the amount of material between the input leads and the guard ring helps to reduce the absorption. Also, low absorption materials, such as Teflon® or ceramic, could be necessary in some instances. INPUT CAPACITANCE Along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. A few pF of capacitance reduces the input impedance at high frequencies, in turn increasing the amplifier’s gain, causing peaking of the frequency response or even oscillations, if severe enough. It is recommended that the external passive components connected to the input pins be placed as close as possible to the inputs to avoid parasitic capacitance. The ground and power planes must be kept at a small distance from the input pins on all layers of the board. OUTPUT CAPACITANCE To a lesser extent, parasitic capacitances on the output can cause peaking and ringing of the frequency response. There are two methods to effectively minimize their effect: • • LEAKAGE CURRENTS Poor PC board layout, contaminants, and the board insulator material can create leakage currents that are much larger than the input bias current of the AD8065/AD8066. Any voltage differential between the inputs and nearby runs sets up leakage currents through the PC board insulator, for example, 1 V/100 GΩ = 10 pA. Similarly, any contaminants on the board can create significant leakage (skin oils are a common problem). To reduce leakage significantly, put a guard ring (shield) around the inputs and input leads that are driven to the same voltage potential as the inputs. This way there is no voltage potential between the Rev. J | Page 23 of 28 As shown in Figure 57, put a small value resistor (RS) in series with the output to isolate the load capacitor from the amp’s output stage. A good value to choose is 20 Ω (see Figure 10). Increase the phase margin with higher noise gains or add a pole with a parallel resistor and capacitor from −IN to the output. AD8065 RS = 20Ω VO CL VI 02916-E-057 POWER SUPPLY BYPASSING Figure 57. Output Isolation Resistor AD8065/AD8066 CF RF RSH = 1011Ω IPHOTO CM CS CD CM VO CF + CS 02916-E-058 VB RF Figure 58. Wideband Photodiode Preamp To minimize capacitive coupling between the inputs and output, the output signal traces should not be parallel with the inputs. The frequency response in this case shows about 2 dB of peaking and 15% overshoot. Doubling CF and cutting the bandwidth in half results in a flat frequency response with about 5% transient overshoot. WIDEBAND PHOTODIODE PREAMP The preamp’s output noise over frequency is shown in Figure 59. Figure 58 shows an I/V converter with an electrical model of a photodiode. The basic transfer function is where IPHOTO is the output current of the photodiode, and the parallel combination of RF and CF sets the signal bandwidth. The stable bandwidth attainable with this preamp is a function of RF, the gain bandwidth product of the amplifier, and the total capacitance at the amplifier’s summing junction, including CS and the amplifier input capacitance. RF and the total capacitance produce a pole in the amplifier’s loop transmission that can result in peaking and instability. Adding CF creates a 0 in the loop transmission that compensates for the pole’s effect and reduces the signal bandwidth. It can be shown that the signal bandwidth resulting in a 45° phase margin (f(45)) is defined by f ( 45 ) = f CR 2 π × RF × C S where fCR is the amplifier crossover frequency, RF is the feedback resistor, and CS is the total capacitance at the amplifier summing junction (amplifier + photodiode + board parasitics). The value of CF that produces f(45) can be shown to be CF = CS 2π × RF × f CR f2 = VOLTAGE NOISE (nV/ Hz) VOUT f1 = I PHOTO × RF = 1 + sC F RF f3 = 1 2π RF (CF + CS + CM + 2CD) 1 2πRFCF fCR (CS + CM + 2CD + CF) /CF RF NOISE f2 VEN (CF + CS + CM + 2CD)/CF f3 f1 VEN NOISE DUE TO AMPLIFIER FREQUENCY (Hz) 02916-E-059 INPUT-TO-OUTPUT COUPLING Figure 59. Photodiode Voltage Noise Contributions The pole in the loop transmission translates to a 0 in the amplifier’s noise gain, leading to an amplification of the input voltage noise over frequency. The loop transmission 0 introduced by CF limits the amplification. The noise gain bandwidth extends past the preamp signal bandwidth and is eventually rolled off by the decreasing loop gain of the amplifier. Keeping the input terminal impedances matched is recommended to eliminate common-mode noise peaking effects, which adds to the output noise. Integrating the square of the output voltage noise spectral density over frequency and then taking the square root allows users to obtain the total rms output noise of the preamp. Table 5 summarizes approximations for the amplifier and feedback and source resistances. Noise components for an example preamp with RF = 50 kΩ, CS = 15 pF, and CF = 2 pF (bandwidth of about 1.6 MHz) are also listed. Rev. J | Page 24 of 28 AD8065/AD8066 Table 5. RMS Noise Contributions of Photodiode Preamp Contributor RF (×2) Expression Amp to f1 VEN × f1 VEN × C S + C M + C F + 2C D × CF VEN × C S + C M + 2C D + C F × f 3 × 1.57 CF Amp (f2 – f1) Amp to (past f2) RMS Noise with RF = 50 kΩ, CS = 15 pF, CF = 2 pF 64.5 μV 2 × 4 kT × RF × f 2 × 1.57 2.4 μV 31 μV f 2 − f1 260 μV 270 μV (Total) VCC 0.1μF 4.7μF RS1 1/2 VN 2.2pF AD8066 0.1μF 4.7μF R2 500Ω VCC VEE 0.1μF R1 4.7μF 500Ω RF = 500Ω VO AD8065 RG 0.1μ F 4.7μ F R3 RF = 500Ω VEE 500Ω VCC 0.1μ F 4.7μF R4 500Ω 1/2 VP 2.2pF AD8066 0.1μ F 4.7μF 02916-E-060 RS2 VEE Figure 60. High Speed Instrumentation Amplifier HIGH SPEED JFET INPUT INSTRUMENTATION AMPLIFIER Figure 60 shows an example of a high speed instrumentation amplifier with high input impedance using the AD8065/AD8066. The dc transfer function is ⎛ 1000 ⎞ ⎟ VOUT = (V N − V P ) ⎜⎜1 + R G ⎟⎠ ⎝ Common-mode rejection of the in-amp is primarily determined by the match of the resistor ratios R1:R2 to R3:R4. It can be estimated (δ1 − δ2 ) VO = VCM (1 + δ1) δ2 The summing junction impedance for the preamps is equal to RF || 0.5(RG). This is the value to be used for matching purposes. For G = +1, it is recommended that the feedback resistors for the two preamps be set to a low value (for instance 50 Ω for 50 Ω source impedance). The bandwidth for G = +1 is 50 MHz. For higher gains, the bandwidth is set by the preamp, equaling Inamp−3dB = ( f CR × RG )/ (2 × RF ) Rev. J | Page 25 of 28 AD8065/AD8066 +VS VIDEO BUFFER The G = +2 configuration compensates for the voltage division of the signal due to the signal termination. This buffer maintains 0.1 dB flatness for signals up to 7 MHz, from low amplitudes up to 2 V p-p (see Figure 7). Differential gain and phase have been measured to be 0.02% and 0.028°, respectively, at ±5 V supplies. 0.1μ F 249Ω + VI – 4.7μ F 75Ω AD8065 75Ω 0.1μ F 4.7μ F –VS 2.2pF 499Ω 499Ω Figure 61. Video Buffer Rev. J | Page 26 of 28 + VO – 02916-E-061 The output current capability and speed of the AD8065 make it useful as a video buffer, shown in Figure 61. AD8065/AD8066 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 4.00 (0.1574) 3.80 (0.1497) 5 1 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 1.75 (0.0688) 1.35 (0.0532) 0.25 (0.0098) 0.10 (0.0040) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 012407-A COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 62. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.00 2.90 2.80 5 1.70 1.60 1.50 1 4 2 3.00 2.80 2.60 3 0.95 BSC 1.90 BSC 1.30 1.15 0.90 0.20 MAX 0.08 MIN 0.15 MAX 0.05 MIN 10° 5° 0° SEATING PLANE 0.50 MAX 0.35 MIN 0.20 BSC 0.55 0.45 0.35 121608-A 1.45 MAX 0.95 MIN COMPLIANT TO JEDEC STANDARDS MO-178-AA Figure 63. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5.15 4.90 4.65 5 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.40 0.25 6° 0° 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 64. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. J | Page 27 of 28 0.80 0.55 0.40 100709-B 0.15 0.05 COPLANARITY 0.10 AD8065/AD8066 ORDERING GUIDE Model 1, 2 AD8065AR AD8065AR-REEL AD8065AR-REEL7 AD8065ARZ AD8065ARZ-REEL AD8065ARZ-REEL7 AD8065ART-R2 AD8065ART-REEL AD8065ART-REEL7 AD8065ARTZ-R2 AD8065ARTZ-REEL AD8065ARTZ-REEL7 AD8065WARTZ-REEL7 AD8065ART-EBZ AD8065AR-EBZ AD8066AR AD8066AR-REEL7 AD8066ARZ AD8066ARZ-RL AD8066ARZ-R7 AD8066ARM AD8066ARM-REEL AD8066ARM-REEL7 AD8066ARMZ AD8066ARMZ-REEL7 AD8066AR-EBZ AD8066ARM-EBZ 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +105°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 Evaluation Board (8-Lead SOIC_N) Evaluation Board (5-Lead SOT-23) 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP Evaluation Board (8-Lead SOIC_N) Evaluation Board (5-Lead SOT-23) Package Option R-8 R-8 R-8 R-8 R-8 R-8 RJ-5 RJ-5 RJ-5 RJ-5 RJ-5 RJ-5 RJ-5 Branding HRA HRA HRA HRA # HRA # HRA # H2F# R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 RM-8 H1B H1B H1B H7C H7C Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD8065W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ©2002–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02916-0-8/10(J) Rev. J | Page 28 of 28