Data Sheet

Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF52277
Rev. 8, 09/2009
MCF52277
LQFP–176
24 mm x 24 mm
MCF5227x ColdFire®
Microprocessor Data Sheet
Features
• Version 2 ColdFire® Core with EMAC
• Up to 159 Dhrystone 2.1 MIPS @ 166.67 MHz
• 8 Kbytes configurable cache (instruction only, data only, or
split instruction/data)
• 128 Kbytes internal SRAM
• Support for booting from SPI-compatible flash, EEPROM,
and FRAM devices
• Crossbar switch technology (XBS) for concurrent access to
peripherals or RAM from multiple bus masters
• 16 channel DMA controller
• 16- or 32-bit SDR/DDR controller
• USB 2.0 On-the-Go controller
• Liquid crystal display controller with support up to
800 × 600 pixels
• ADC and touchscreen controller
• FlexCAN module
• 4 32-bit timers with DMA support
• DMA supported serial peripheral interface (DSPI)
• 3 UARTs
• I2C bus interface
• Synchronous serial interface (SSI)
• Plus-width modulator (PWM)
• Real-time clock (RTC)
• Two programmable interrupt controllers (PIT)
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
MAPBGA–196
15mm x 15mm
Table of Contents
1
2
3
4
5
MCF5227x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . .4
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .5
3.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.2 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.3 ADC Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.4 Supply Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . .6
3.4.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . .6
3.4.2 Power Down Sequence . . . . . . . . . . . . . . . . . . . .6
3.5 Power Consumption Specifications. . . . . . . . . . . . . . . . .7
Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .9
4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.2 Pinout—176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.3 Pinout—196 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .15
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .17
5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .18
5.5
5.6
5.7
6
7
8
Oscillator and PLL Electrical Characteristics. . . . . . . .
ASP Electrical Characteristics . . . . . . . . . . . . . . . . . . .
External Interface Timing Specifications . . . . . . . . . . .
5.7.1 FlexBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.2 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . .
5.9 Reset and Configuration Override Timing . . . . . . . . . .
5.10 LCD Controller Timing Specifications . . . . . . . . . . . . .
5.11 USB On-The-Go Specifications. . . . . . . . . . . . . . . . . .
5.12 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . .
5.13 I2C Timing Specifications . . . . . . . . . . . . . . . . . . . . . .
5.14 DMA Timer Timing Specifications . . . . . . . . . . . . . . . .
5.15 DSPI Timing Specifications . . . . . . . . . . . . . . . . . . . . .
5.16 SBF Timing Specifications. . . . . . . . . . . . . . . . . . . . . .
5.17 JTAG and Boundary Scan Timing Specifications . . . .
5.18 Debug AC Timing Specifications . . . . . . . . . . . . . . . . .
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
20
21
21
23
29
29
30
33
34
36
38
38
39
40
42
43
43
44
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
2
Freescale Semiconductor
MCF52277
JTAG
Oscillator
Version 2 ColdFire Core
8K
Configurable
Cache
PLL
Serial Boot
Facility
BDM
Hardware
Divide
128K
SRAM
EMAC
USB OTG
LCD
Controller
eDMA
Crossbar Switch (XBS)
Peripheral Bridge
FlexBus
Touch
Screen
DSPI
RTC
SSI
FlexCAN
GPIO
EPORT
I2C
INTC
2 PITs
3 UARTs
4 DMA
Timers
SDRAM
Controller
PWM
LEGEND
BDM
DSPI
eDMA
EMAC
EPORT
GPIO
I2 C
INTC
JTAG
– Background debug module
– DMA serial peripheral interface
– Enhanced direct memory access
– Enchanced multiply-accumulate unit
– Edge port module
– General purpose input/output module
– Inter-intergrated circuit
– Interrupt controller
– Joint Test Action Group interface
LCD
PIT
PLL
PWM
RTC
SSI
UART
USB OTG
– Liquid-crystal display
– Programmable interrupt timer
– Phase-locked loop module
– Pulse-width modulator
– Real time clock
– Synchronous serial interface
– Universal asynchronous receiver/transmitter
– Universal Serial Bus On-the-Go controller
Figure 1. MCF52277 Block Diagram
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
3
MCF5227x Family Comparison
1
MCF5227x Family Comparison
The following table compares the various device derivatives available within the MCF5227x family.
Table 1. MCF5227x Family Configurations
Module
MCF52274
MCF52277
•
•
Core (System) Clock
up to 120 MHz
up to 166.67 MHz
Peripheral and External Bus Clock
(Core clock ÷ 2)
up to 60 MHz
up to 83.33 MHz
Performance (Dhrystone/2.1 MIPS)
up to 114
up to 159
ColdFire Version 2 Core with EMAC
(Enhanced Multiply-Accumulate Unit)
Static RAM (SRAM)
128 Kbytes
Configurable Cache
8 Kbytes
ASP Touchscreen Controller
•
•
12-bit color
18-bit color
USB 2.0 On-the-Go
•
•
FlexBus External Interface
•
•
SDR/DDR SDRAM Controller
•
•
FlexCAN 2.0B communication module
•
•
Real Time Clock
•
•
Watchdog Timer
•
•
16-channel Direct Memory Access (DMA)
•
•
Interrupt Controllers (INTC)
1
1
Synchronous Serial Interface (SSI)
•
•
•
•
DSPI
•
•
UARTs
3
3
32-bit DMA Timers
4
4
Periodic Interrupt Timers (PIT)
2
2
PWM Module
•
•
Edge Port Module (EPORT)
•
•
General Purpose I/O Module (GPIO)
•
•
•
•
176 LQFP
196 MAPBGA
LCD Controller
I
2C
®
JTAG - IEEE 1149.1 Test Access Port
Package
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
4
Freescale Semiconductor
Ordering Information
2
Ordering Information
Table 2. Orderable Part Numbers
Freescale Part
Number
Description
Package
Speed
Temperature
MCF52274CLU120
MCF52274 RISC Microprocessor
176 LQFP
120 MHz
–40° to +85° C
MCF52277CVM160
MCF52277 RISC Microprocessor
196 MAPBGA
166.67 MHz
–40° to +85° C
3
Hardware Design Considerations
3.1
PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in
Figure 2 should be connected between the board VDD and the PLLVDD pins. The resistor and capacitors should be placed as
close to the dedicated PLLVDD pin as possible.
10 Ω
Board IVDD
PLL VDD Pin
10 µF
0.1 µF
GND
Figure 2. System PLL VDD Power Filter
3.2
USB Power Filtering
To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 3 should be
connected between the board EVDD and the USBVDD pin. The resistor and capacitors should be placed as close to the dedicated
USBVDD pin as possible.
0Ω
Board EVDD
USB VDD Pin
10 µF
0.1 µF
GND
Figure 3. USB VDD Power Filter
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel
with those shown.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
5
Hardware Design Considerations
3.3
ADC Power Filtering
To minimize noise, an external filters is required for the ADCVDD power pin. The filter shown in Figure 4 should be connected
between the board EVDD and the ADCVDD pin. The resistor and capacitors should be placed as close to the dedicated ADCVDD
pin as possible.
0Ω
Board EVDD
ADC VDD Pin
10 µF
0.1 µF
GND
Figure 4. ADC VDD Power Filter
3.4
Supply Voltage Sequencing
The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. Both SDVDD (2.5V
or 3.3V) and EVDD are specified relative to IVDD.
3.4.1
Power Up Sequence
If EVDD/SDVDD are powered up with IVDD at 0 V, then the sense circuits in the I/O pads will cause all pad output drivers
connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up
before IVDD must powered up. IVDD should not lead the EVDD, SDVDD or PLLVDD by more than 0.4 V during power ramp-up,
or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than
500 us to avoid turning on the internal ESD protection clamp diodes.
3.4.2
Power Down Sequence
If IVDD/PLLVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high
impedance state. There is no limit on how long after IVDD and PLLVDD power down before EVDD or SDVDD must power
down. IVDD should not lag EVDD, SDVDD, or PLLVDD going low by more than 0.4 V during power down or there will be
undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1.
2.
Drop IVDD/PLLVDD to 0 V.
Drop EVDD/SDVDD supplies.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
6
Freescale Semiconductor
Hardware Design Considerations
3.5
Power Consumption Specifications
All application power consumption data is lab data measured on an M52277EVB running the Freescale Linux BSP.
Table 3. MCF52277 Application Power Consumption1
Core
Freq.
160 MHz
1
Idle (LCD
image)
Idle (audio
image)
Button
Demo
Slideshow
Demo
MP3
Playback
USB FS
File Copy
IVDD
61.4
59.2
84.7
96.5
89.2
89.5
EVDD
28.87
25.73
35.3
34.6
33.46
29.86
SDVDD
18.8
18.57
21.8
23.9
22.66
22.2
Total Power
221.211
207.135
282.78
301.95
285.006
272.748
Units
mA
mW
All voltage rails at nominal values: IVDD = 1.5 V, EVDD = 3.3 V, and SDVDD = 1.8 V.
350
Total Power (mW)
300
250
200
150
100
50
0
Idle (LCD
image)
Idle (Audio
Image)
Button
Demo
Slideshow
Demo
MP3
Playback
USB FS
File Copy
Figure 5. Power Consumption in Various Applications
All current consumption data is lab data measured on a single device using an evaluation board. Table 4 shows the typical power
consumption in low-power modes. These current measurements are taken after executing a STOP instruction.
Table 4. Current Consumption in Low-Power Modes1,2
System Frequency
Mode
RUN
WAIT
80MHz
64MHz
48MHz
32MHz
4MHz
(LIMP
mode)
IVDD (mA)
75.1
62.7
49.2
36.6
3.5
Power (mW)
112.65
94.05
73.80
54.90
5.25
IVDD (mA)
61.9
52.8
42.0
31.7
2.9
Power (mW)
92.85
79.20
63.00
47.55
4.35
Voltage Supply
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
7
Hardware Design Considerations
Table 4. Current Consumption in Low-Power Modes1,2 (continued)
System Frequency
Mode
80MHz
64MHz
48MHz
32MHz
4MHz
(LIMP
mode)
IVDD (mA)
57.0
48.8
38.9
29.7
2.7
Power (mW)
85.50
73.20
58.35
44.55
4.05
IVDD (mA)
16.1
15.1
13.4
12.5
1.3
Power (mW)
24.15
22.65
20.10
18.75
1.95
IVDD (mA)
15.9
14.9
13.2
12.4
1.3
Power (mW)
23.85
22.35
19.80
18.60
1.95
IVDD (mA)
1.8
1.8
1.8
1.8
1.3
Power (mW)
2.70
2.70
2.70
2.70
1.95
IVDD (mA)
0.5
0.5
0.5
0.5
0.5
Power (mW)
0.75
0.75
0.75
0.75
0.75
Voltage Supply
DOZE
STOP 0
STOP 1
STOP 2
STOP 3
1
All values are measured on an M52277EVB with nominal core voltage(IVDD = 1.5 V). Tests
performed at room temperature. All peripheral clocks on prior to entering low-power mode
2 Refer to the Power Management chapter in the MCF52277 Reference Manual for more information
on low-power modes.
IVDD Power Consumption (mW)
120
100
RUN
80
WAIT
DOZE
STOP 0
60
STOP 1
STOP 2
40
STOP 3
20
0
80
64
48
32
4 (LIMP)
System Frequency (MHz)
Figure 6. IVDD Power Consumption in Low-Power Modes
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
8
Freescale Semiconductor
Pin Assignments and Reset States
4
Pin Assignments and Reset States
4.1
Signal Multiplexing
The following table lists all the MCF5227x pins grouped by function. The direction column is the direction for the primary
function of the pin only. Refer to Section 4, “Pin Assignments and Reset States,” for package diagrams. For a more detailed
discussion of the MCF5227x signals, consult the MCF52277 Reference Manual (MCF52277RM).
NOTE
In this table and throughout this document a single signal within a group is designated
without square brackets (i.e., FB_A23), while designations for multiple signals within a
group use brackets (i.e., FB_A[23:21]) and is meant to include all signals within the two
bracketed numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality. Most pins that
are muxed with GPIO will default to their GPIO functionality. See Table 5 for a list of the
exceptions.
Table 5. Special-Case Default Signal Functionality
Pin
Default Signal
FB_BE/BWE[3:0]
FB_BE/BWE[3:0]
FB_CS[3:0]
FB_CS[3:0]
FB_OE
FB_OE
FB_TA
FB_TA
FB_R/W
FB_R/W
FB_TS
FB_TS
Pull-up (U)1
Pull-down (D)
Direction2
Voltage Domain
Table 6. MCF5227x Signal Information and Muxing
MCF52274
176 LQFP
RESET
—
—
—
U
I
EVDD
103
J11
RSTOUT
—
—
—
—
O
EVDD
102
K11
—
—
I
EVDD
106
F14
—
3
U
O
EVDD
105
G14
—
I
EVDD
110, 109
G10, H10
Signal Name
GPIO
Alternate 1
Alternate 2
MCF52277
196 MAPBGA
Reset
Clock
EXTAL
XTAL
—
—
—
—
Mode Selection
BOOTMOD[1:0]
—
—
—
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
9
Pin Assignments and Reset States
Pull-up (U)1
Pull-down (D)
Direction2
Voltage Domain
Table 6. MCF5227x Signal Information and Muxing (continued)
MCF52274
176 LQFP
FB_A[23:22]
—
FB_CS[5:4]
—
—
O
SDVDD
143, 142
FB_A[21:16]
—
—
—
—
O
SDVDD 141–139, 137–135
Signal Name
GPIO
Alternate 1
Alternate 2
MCF52277
196 MAPBGA
C11, D11
FlexBus
A12, B12, C12,
B13, A13, A14
FB_A[15:14]
—
SD_BA[1:0]
—
—
O
SDVDD
131, 130
B14, C13
FB_A[13:11]
—
SD_A[13:11]
—
—
O
SDVDD
129–127
C14, D12, D13
FB_A10
—
—
—
O
SDVDD
126
D14
FB_A[9:0]
—
SD_A[9:0]
—
O
SDVDD
125–116
E11–E14,
F11–F13, G11,
G12, H11
FB_D[31:16]
—
SD_D[31:16]
—
I/O
SDVDD
30–37, 49–56
J4, K1–K4, L1–L3,
M3, N3, P3,M4,
N4, P4, L5, M5
FB_D[15:0]
—
FB_D[31:16]
—
I/O
SDVDD
19–26, 60–67
G1–G4, H1–H4,
M6, N6, P6, L7,
M7, N7, P7, L8
FB_CLK
—
—
—
O
SDVDD
42
P1
FB_BE/BWE[3:0]
PBE[3:0]
SD_DQM[3:0]
—
—
O
SDVDD
29, 57, 27, 59
J3, N5, J1, L6
FB_CS[3:2]
PCS[3:2]
—
—
—
O
SDVDD
—
B11, A11
FB_CS1
PCS1
SD_CS1
—
—
O
SDVDD
144
D10
FB_CS0
PCS0
—
—
—
O
SDVDD
145
C10
FB_OE
PFBCTL3
—
—
—
O
SDVDD
69
N8
FB_TA
PFBCTL2
—
—
U
I
SDVDD
115
H12
FB_R/W
PFBCTL1
—
—
—
O
SDVDD
68
M8
FB_TS
PFBCTL0
DACK0
—
—
O
SDVDD
15
F4
SDRAM Controller
SD_A10
—
—
—
—
O
SDVDD
46
L4
SD_CAS
—
—
—
—
O
SDVDD
47
N2
SD_CKE
—
—
—
—
O
SDVDD
17
F2
SD_CLK
—
—
—
—
O
SDVDD
40
M1
SD_CLK
—
—
—
—
O
SDVDD
41
N1
SD_CS0
—
—
—
—
O
SDVDD
18
F1
SD_DQS[3:2]
—
—
—
—
I/O
SDVDD
28, 58
J2, P5
SD_RAS
—
—
—
—
O
SDVDD
48
P2
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
10
Freescale Semiconductor
Pin Assignments and Reset States
Alternate 1
Alternate 2
SD_SDR_DQS
—
—
—
—
SD_WE
—
—
—
—
Voltage Domain
GPIO
Direction2
Signal Name
Pull-up (U)1
Pull-down (D)
Table 6. MCF5227x Signal Information and Muxing (continued)
MCF52274
176 LQFP
MCF52277
196 MAPBGA
O
SDVDD
38
M2
O
SDVDD
16
F3
I
EVDD
162
D7
I
EVDD
161
C7
External Interrupts Port4
IRQ7
PIRQ7
—
—
—
IRQ4
PIRQ4
DREQ0
DSPI_PCS4
5
IRQ1
PIRQ1
USB_CLKIN
SSI_CLKIN
—
I
EVDD
160
B7
LCD Controller6
LCD_D[17:16]6
PLCDDH[1:0]
LCD_D[11:10]
—
—
O
EVDD
9, 8
E3, E4
LCD_D[15:14]6
PLCDDM[7:6]
LCD_D[9:8]
—
—
O
EVDD
7, 6
D1, D2
LCD_D13
PLCDDM5
CANTX
—
—
O
EVDD
—
C1
LCD_D12
PLCDDM4
CANRX
—
—
O
EVDD
—
C2
LCD_D[11:8]6
PLCDDM[3:0]
LCD_D[7:4]
—
—
O
EVDD
5–2
D3, C3, D4, B1
LCD_D7
PLCDDL7
PWM7
—
—
O
EVDD
—
B2
LCD_D6
PLCDDL6
PWM5
—
—
O
EVDD
—
A1
LCD_D[5:2]6
PLCDDL[5:2]
LCD_D[3:0]
—
—
O
EVDD
175–172
A2, A3, B3, A4
LCD_D1
PLCDDL1
PWM3
—
—
O
EVDD
—
B4
LCD_D0
PLCDDL0
PWM1
—
—
O
EVDD
—
C4
LCD_ACD/
LCD_OE
PLCDCTL3
LCD_SPL_SPR
—
—
O
EVDD
169
B5
LCD_FLM/
LCD_VSYNC
PLCDCTL2
—
—
—
O
EVDD
10
E2
LCD_LP/
LCD_HSYNC
PLCDCTL1
—
—
—
O
EVDD
11
E1
LCD_LSCLK
PLCDCTL0
—
—
—
O
EVDD
170
A5
—
O
USB
149
A9
150
A10
USB On-the-Go
USB_DM
—
—
—
VDD
USB_DP
—
—
—
—
O
USB
VDD
Real Time Clock
RTC_EXTAL
—
—
—
—
I
EVDD
100
J14
RTC_XTAL
—
—
—
—
O
EVDD
99
K14
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
11
Pin Assignments and Reset States
Alternate 1
Alternate 2
Voltage Domain
GPIO
Direction2
Signal Name
Pull-up (U)1
Pull-down (D)
Table 6. MCF5227x Signal Information and Muxing (continued)
MCF52274
176 LQFP
—
I
VDD_
82–85, 87–90
MCF52277
196 MAPBGA
Touchscreen Controller
ADC_IN[7:0]
—
—
—
ADC
P12, N12, P13,
N13, P14, N14,
M13, M14
ADC_REF
—
—
—
—
I
VDD_
86
M12
ADC
I2C
I2C_SCL
PI2C1
CANTX
U2TXD
U
I/O
EVDD
168
C5
I2C_SDA
PI2C0
CANRX
U2RXD
U
I/O
EVDD
167
D5
—
U
I/O
EVDD
152
B9
I
EVDD
155
D8
DSPI7
DSPI_PCS0/SS
PDSPI3
U2RTS
DSPI_SIN
PDSPI2
U2RXD
SBF_DI
8
DSPI_SOUT
PDSPI1
U2TXD
SBF_D0
—
O
EVDD
154
D9
DSPI_SCK
PDSPI0
U2CTS
SBF_CK
—
I/O
EVDD
153
C9
UARTs
U1CTS
PUART7
SSI_BCLK
LCD_CLS
—
I
EVDD
156
C8
U1RTS
PUART6
SSI_FS
LCD_PS
—
O
EVDD
157
B8
U1TXD
PUART5
SSI_TXD
—
—
O
EVDD
159
A7
U1RXD
PUART4
SSI_RXD
—
—
I
EVDD
158
A8
U0CTS
PUART3
DT1OUT
USB_VBUS_EN
—
I
EVDD
97
K12
U0RTS
PUART2
DT1IN
USB_VBUS_OC
—
O
EVDD
98
J12
U0TXD
PUART1
CANTX
—
—
O
EVDD
95
L12
U0RXD
PUART0
CANRX
—
—
I
EVDD
96
K13
DMA Timers
DT3IN
PTIMER3
DT3OUT
SSI_MCLK
—
I
EVDD
163
D6
DT2IN/SBF_CS7
PTIMER2
DT2OUT
DSPI_PCS2
—
I
EVDD
164
C6
DT1IN
PTIMER1
DT1OUT
LCD_CONTRAST
—
I
EVDD
165
B6
DT0IN
PTIMER0
DT0OUT
LCD_REV
—
I
EVDD
166
A6
BDM/JTAG9
PST[3:0]
—
—
—
—
O
EVDD
—
L9, M9, N9, P9
DDATA[3:0]
—
—
—
—
O
EVDD
—
L10, M10, N10,
P10
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
12
Freescale Semiconductor
Pin Assignments and Reset States
Voltage Domain
MCF52274
176 LQFP
MCF52277
196 MAPBGA
O
EVDD
76
—
I
EVDD
79
K10
U
O
EVDD
74
P8
—
U
I
EVDD
78
M11
TDO
—
—
O
EVDD
81
L11
—
TMS
—
U
I
EVDD
80
N11
—
TRST
—
U
I
EVDD
77
P11
—
D
I
EVDD
134
E10
—
—
—
39, 75, 114, 138,
K5, F10, E5, J10
Signal Name
GPIO
Alternate 1
Alternate 2
Pull-up (U)1
Pull-down (D)
Direction2
Table 6. MCF5227x Signal Information and Muxing (continued)
ALLPST
—
—
—
—
JTAG_EN
—
—
—
D
PSTCLK
—
TCLK
—
DSI
—
TDI
DSO
—
BKPT
DSCLK
Test
TEST
—
—
Power Supplies
IVDD
—
—
—
171
EVDD
—
—
—
—
—
—
12, 72, 73, 94, 111, E6, E7, F5, F6, G5,
148, 176
SD_VDD
1
2
3
4
5
6
7
8
—
—
—
—
—
—
H9, J9, K8, K9
14, 43, 44, 70, 113, E8, E9, F9, G9, H5,
132, 146
J5, J6, K6, K7
VDD_OSC
—
—
—
—
—
—
108
G13
VDD_PLL
—
—
—
—
—
—
104
H14
VDD_USB
—
—
—
—
—
—
151
B10
VDD_RTC
—
—
—
—
—
—
101
J13
VDD_ADC
—
—
—
—
—
—
91
L13
VSS
—
—
—
—
—
—
1, 13, 45, 71, 93,
F7, F8, G6–G8,
112, 133, 147
H6–H8, J7, J8
VSS_OSC
—
—
—
—
—
—
107
H13
VSS_ADC
—
—
—
—
—
—
92
L14
Pull-ups are generally only enabled on pins with their primary function, except as noted.
Refers to pin’s primary function.
Enabled only in oscillator bypass mode (internal crystal oscillator is disabled).
GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions.
Pull-up when DREQ controls the pin.
The 176 LQFP device only supports a 12-bit LCD data bus.
DSPI or SBF signal functionality is controlled by RESET. When asserted, these pins are configured for serial boot; when negated, the
pins are configured for DSPI.
Pull-up when the serial boot facility (SBF) controls the pin.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
13
Pin Assignments and Reset States
If JTAG_EN is asserted, these pins default to alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these
pins.
4.2
Pinout—176 LQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
•
SD_VDD
FB_A15
FB_A14
FB_A13
FB_A12
FB_A11
FB_A10
FB_A9
FB_A8
FB_A7
FB_A6
FB_A5
FB_A4
FB_A3
FB_A2
FB_A1
FB_A0
FB_TA
IVDD
SD_VDD
VSS
EVDD
BOOTMOD1
BOOTMOD0
VDD_OSC
VSS_OSC
EXTAL
XTAL
VDD_PLL
RESET
RSTOUT
VDD_RTC
RTC_EXTAL
RTC_XTAL
U0RTS
U0CTS
U0RXD
U0TXD
EVDD
VSS
VSS_ADC
VDD_ADC
ADC_IN0
ADC_IN1
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VSS
LCD_D8
LCD_D9
LCD_D10
LCD_D11
LCD_D14
LCD_D15
LCD_D16
LCD_D17
LCD_FLM/VSYNC
LCD_LP/HSYNC
EVDD
VSS
SD_VDD
FB_TS
SD_WE
SD_CKE
SD_CS0
FB_D15
FB_D14
FB_D13
FB_D12
FB_D11
FB_D10
FB_D9
FB_D8
FB_BE/BWE1
SD_DQS3
FB_BE/BWE3
FB_D31
FB_D30
FB_D29
FB_D28
FB_D27
FB_D26
FB_D25
FB_D24
SD_SDR_DQS
IVDD
SD_CLK
SD_CLK
FB_CLK
SD_VDD
SD_VDD
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
EVDD
LCD_D5
LCD_D4
LCD_D3
LCD_D2
IVDD
LCD_LSCLK
LCD_ACD/OE
I2C_SCL
I2C_SDA
T0IN
T1IN
T2IN
T3IN
IRQ7
IRQ4
IRQ1
U1TXD
U1RXD
U1RTS
U1CTS
DSPI_SIN
DSPI_SOUT
DSPI_SCK
DSPI_PCS0
VDD_USB
USB_DP
USB_DM
EVDD
VSS
SD_VDD
FB_CS0
FB_CS1
FB_A23
FB_A22
FB_A21
FB_A20
FB_A19
IVDD
FB_A18
FB_A17
FB_A16
TEST
VSS
The pinout for the MCF52274 package is shown below.
VSS
SD_A10
SD_CAS
SD_RAS
FB_D23
FB_D22
FB_D21
FB_D20
FB_D19
FB_D18
FB_D17
FB_D16
FB_BE/BWE2
SD_DQS2
FB_BE/BWE0
FB_D7
FB_D6
FB_D5
FB_D4
FB_D3
FB_D2
FB_D1
FB_D0
FB_R/W
FB_OE
SD_VDD
VSS
EVDD
EVDD
PSTCLK
IVDD
ALLPST
DSCLK
DSI
JTAG_EN
BKPT
DSO
ADC_IN7
ADC_IN6
ADC_IN5
ADC_IN4
ADC_REF
ADC_IN3
ADC_IN2
9
Figure 7. MCF52274 Pinout (176 LQFP)
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
14
Freescale Semiconductor
Electrical Characteristics
4.3
Pinout—196 MAPBGA
The pinout for the MCF52277 package is shown below.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
LCD_D6
LCD_D5
LCD_D4
LCD_D2
LCD_
LSCLK
T0IN
U1TXD
U1RXD
USB_DM
USB_DP
FB_CS2
FB_A21
FB_A17
FB_A16
A
B
LCD_D8
LCD_D7
LCD_D3
LCD_D1
LCD_
ACD/OE
T1IN
IRQ_1
U1RTS
DSPI_
PCS0
VDD_
USB
FB_CS3
FB_A20
FB_A18
FB_A15
B
C
LCD_D13 LCD_D12 LCD_D10
LCD_D0
I2C_SCL
T2IN
IRQ_4
U1CTS
DSPI_
SCK
FB_CS0
FB_A23
FB_A19
FB_A14
FB_A13
C
D
LCD_D15 LCD_D14 LCD_D11
LCD_D9
I2C_SDA
T3IN
IRQ_7
DSPI_SIN
DSPI_
SOUT
FB_CS1
FB_A22
FB_A12
FB_A11
FB_A10
D
E
LCD_LP/ LCD_FLM/
LCD_D17 LCD_D16
HSYNC
VSYNC
IVDD
EVDD
EVDD
SDVDD
SDVDD
TEST
FB_A9
FB_A8
FB_A7
FB_A6
E
F
SD_CS0
SD_CKE
SD_WE
FB_TS
EVDD
EVDD
VSS
VSS
SDVDD
IVDD
FB_A5
FB_A4
FB_A3
EXTAL
F
G
FB_D15
FB_D14
FB_D13
FB_D12
EVDD
VSS
VSS
VSS
SDVDD
BOOT
MOD1
FB_A2
FB_A1
VDD_
OSC
XTAL
G
H
FB_D11
FB_D10
FB_D9
FB_D8
SDVDD
VSS
VSS
VSS
EVDD
BOOT
MOD0
FB_A0
FB_TA
VSS_
OSC
VDD_
PLL
H
J
FB_BE/
BWE1
SD_DQS3
FB_BE/
BWE3
FB_D31
SDVDD
SDVDD
VSS
VSS
EVDD
IVDD
RESET
U0RTS
VDD_
RTC
RTC_
EXTAL
J
K
FB_D30
FB_D29
FB_D28
FB_D27
IVDD
SDVDD
SDVDD
EVDD
EVDD
U0CTS
U0RXD
RTC_
XTAL
K
L
FB_D26
FB_D25
FB_D24
SD_A10
FB_D17
FB_BE/
BWE0
FB_D4
FB_D0
PST3
DDATA3
TDO
U0TXD
VDD_
ADC
VSS_
ADC
L
M
SD_CLK
SD_
SDR_DQS
FB_D23
FB_D20
FB_D16
FB_D7
FB_D3
FB_R/W
PST2
DDATA2
TDI
ADC_
REF
N
SD_CLK
SD_CAS
FB_D22
FB_D19
FB_BE/
BWE2
FB_D6
FB_D2
FB_OE
PST1
DDATA1
P
FB_CLK
SD_RAS
FB_D21
FB_D18
SD_
DQS0
FB_D5
FB_D1
TCLK
PST0
1
2
3
4
5
6
7
8
9
JTAG_EN RSTOUT
ADC_IN1 ADC_IN0
M
TMS
ADC_IN6 ADC_IN4 ADC_IN2
N
DDATA0
TRST
ADC_IN7 ADC_IN5 ADC_IN3
P
10
11
12
13
14
Figure 8. MCF52277 Pinout (196 MAPBGA)
5
Electrical Characteristics
This document contains electrical specification tables and reference timing diagrams for the MCF5227x microprocessor. This
section contains detailed information on DC/AC electrical characteristics and AC timing specifications.
The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not
be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specifications will
be met. Finalized specifications will be published after complete characterization and device qualifications have been
completed.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
15
Electrical Characteristics
NOTE
The parameters specified in this MCU document supersede any values found in the module
specifications.
5.1
Maximum Ratings
Table 7. Absolute Maximum Ratings1, 2
Characteristic
Symbol
Value
Unit
Core Supply Voltage
IVDD
–0.5 to +2.0
V
CMOS Pad Supply Voltage
EVDD
–0.3 to +4.0
V
SDVDD
–0.3 to +4.0
V
Oscillator Supply Voltage
OSCVDD
–0.3 to +4.0
V
PLL Supply Voltage
PLLVDD
–0.3 to +2.0
V
RTC Supply Voltage
RTCVDD
–0.5 to +2.0
V
Digital Input Voltage 3
VIN
–0.3 to +3.6
V
Instantaneous Maximum Current
Single pin limit (applies to all pins) 3, 4, 5
ID
25
mA
TA
(TL – TH)
–40 to +85
°C
Tstg
–55 to +150
°C
DDR/Memory Pad Supply Voltage
Operating Temperature Range (Packaged)
Storage Temperature Range
1
2
3
4
5
Functional operating conditions are given in Section 5.4, “DC Electrical Specifications.” Absolute maximum ratings
are stress ratings only, and functional operation at the maxima is not guaranteed. Continued operation at these
levels may affect device reliability or cause permanent damage to the device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is
advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages
to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic
voltage level (e.g., either VSS or EVDD).
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
All functional non-supply pins are internally clamped to VSS and EVDD.
Power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum
current conditions. If positive injection current (Vin > EVDD) is greater than IDD, the injection current may flow out of
EVDD and could result in external power supply going out of regulation. Insure external EVDD load will shunt current
greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power (ex; no
clock). Power supply must maintain regulation within operating EVDD range during instantaneous and operating
maximum current conditions.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
16
Freescale Semiconductor
Electrical Characteristics
5.2
Thermal Characteristics
Table 8. Thermal Characteristics
Characteristic
Symbol
196
MAPBGA
176
LQFP
Unit
Junction to ambient, natural convection
Four layer board (2s2p)
θJA
381,2
481,2
°C/W
Junction to ambient (@200 ft/min)
Four layer board (2s2p)
θJMA
341,2
421,2
°C/W
37
3
°C/W
4
°C/W
°C/W
Junction to board
θJB
Junction to case
θJC
17
14
Junction to top of package
Ψjt
41,5
31,5
Maximum operating junction temperature
Tj
105
105
1
2
3
4
5
3
27
4
o
C
θJA, θJMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.
Freescale recommends the use of θJmA and power dissipation specifications in the system design to prevent device
junction temperatures from exceeding the rated specification. System designers should be aware that device
junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the
device junction temperature specification can be verified by physical measurement in the customer’s system using
the Ψjt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter
is written in conformance with Psi-JT.
The average chip-junction temperature (TJ) in °C can be obtained from:
T J = T A + ( P D × Θ JMA )
Eqn. 1
Where:
TA
QJMA
PD
PINT
PI/O
=
=
=
=
=
Ambient Temperature, °C
Package Thermal Resistance, Junction-to-Ambient, °C/W
PINT + PI/O
IDD × IVDD, Watts - Chip Internal Power
Power Dissipation on Input and Output Pins — User Determined
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is:
K
P D = --------------------------------( T J + 273 ° C )
Eqn. 2
Solving equations 1 and 2 for K gives:
2
K = P D × ( T A × 273°C ) + Q JMA × P D
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively
for any value of TA.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
17
Electrical Characteristics
5.3
ESD Protection
Table 9. ESD Protection Characteristics1,2
Characteristic
ESD Target for Human Body Model
Symbol
Value
Unit
HBM
2000
V
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits.
2
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing is performed per
applicable device specification at room temperature followed by hot temperature, unless specified
otherwise in the device specification.
5.4
DC Electrical Specifications
Table 10. DC Electrical Specifications
Characteristic
Symbol
Min
Max
Unit
Core Supply Voltage
IVDD
1.4
1.6
V
PLL Supply Voltage
PLLVDD
1.4
1.6
V
RTC Supply Voltage
RTCVDD
1.4
1.6
V
EVDD
3.0
3.6
V
1.7
2.25
3.0
1.95
2.75
3.6
CMOS Pad Supply Voltage
SDRAM and FlexBus Supply Voltage
Mobile DDR/Bus Pad Supply Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
V
SDVDD
USB Supply Voltage
USBVDD
3.0
3.6
V
Oscillator Supply Voltage
OSCVDD
3.0
3.6
V
CMOS Input High Voltage
EVIH
2
EVDD + 0.3
V
CMOS Input Low Voltage
EVIL
VSS – 0.3
0.8
V
CMOS Output High Voltage
IOH = –5.0 mA
EVOH
EVDD – 0.4
—
V
CMOS Output Low Voltage
IOL = 5.0 mA
EVOL
—
0.4
V
SDRAM and FlexBus Input High Voltage
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
SDVIH
1.35
1.7
2
SDVDD + 0.3
SDVDD + 0.3
SDVDD + 0.3
SDRAM and FlexBus Input Low Voltage
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
SDVIL
VSS – 0.3
VSS – 0.3
VSS – 0.3
0.45
0.8
0.8
V
V
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
18
Freescale Semiconductor
Electrical Characteristics
Table 10. DC Electrical Specifications (continued)
Characteristic
Symbol
Min
Max
1.4
2.1
2.4
—
—
—
—
—
—
0.3
0.3
0.5
Iin
–1.0
1.0
μA
Weak Internal Pull-Up Device Current, tested at VIL Max.1
IAPU
–10
–130
μA
Input Capacitance 2
All input-only pins
All input/output (three-state) pins
Cin
—
—
7
7
Symbol
Min
Max
Unit
fref_crystal
fref_ext
16
16
251
66.671
MHz
MHz
fsys
166.67
83.33
MHz
MHz
SDRAM and FlexBus Output High Voltage
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
IOH = –5.0 mA for all modes
SDVOH
SDRAM and FlexBus Output Low Voltage
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
IOL = 5.0 mA for all modes
SDVOL
Input Leakage Current
Vin = VDD or VSS, Input-only pins
1
Unit
V
V
pF
Refer to the signals section for pins having weak internal pull-up devices.
This parameter is characterized before qualification rather than 100% tested.
2
5.5
Oscillator and PLL Electrical Characteristics
Table 11. PLL Electrical Characteristics
Num
1
Characteristic
PLL Reference Frequency Range
Crystal reference
External reference
Core/system frequency
CLKOUT Frequency
fsys/2
512 Hz2
256 Hz2
3
Crystal Start-up Time3,4
tcst
—
10
ms
4
EXTAL Input High Voltage
Crystal Mode5
All other modes (External, Limp)
VIHEXT
VIHEXT
VXTAL + 0.4
EVDD/2 + 0.4
—
—
V
V
EXTAL Input Low Voltage
Crystal Mode5
All other modes (External, Limp)
VILEXT
VILEXT
—
—
VXTAL – 0.4
EVDD/2 – 0.4
V
V
tlpll
—
50000
CLKIN
tdc
40
60
%
IXTAL
1
3
mA
2
5
7
PLL Lock Time 3,6
3
8
Duty cycle of reference
9
XTAL Current
10
Total on-chip stray capacitance on XTAL
CS_XTAL
—
1.5
pF
11
Total on-chip stray capacitance on EXTAL
CS_EXTAL
—
1.5
pF
12
Crystal capacitive load
CL
See crystal spec
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
19
Electrical Characteristics
Table 11. PLL Electrical Characteristics (continued)
Num
Characteristic
Symbol
Min
Max
Unit
13
Discrete load capacitance for XTAL
Discrete load capacitance for EXTAL
CL_XTAL
CL_EXTAL
—
2 × (CL –
CS_XTAL –
CS_EXTAL –
CS_PCB)7
pF
14
Frequency un-LOCK Range
fUL
–4.0
4.0
% fsys
15
Frequency LOCK Range
fLCK
–2.0
2.0
% fsys
—
—
10
TBD
% fsys/2
% fsys/2
350
540
MHz
17
19
1
2
3
4
5
6
7
8
4, 5, 8
CLKOUT period jitter
measured at fsys max
Peak-to-peak jitter (Clock edge to clock edge)
Long-term jitter
Cjitter
VCO frequency (fvco = fref × PFDR)
fvco
Although these are the allowable frequency ranges, do not violate the VCO frequency range of the PLL. See the
MCF5227x Reference Manual for more details.
The minimum system frequency is the minimum input clock divided by the maximum low-power divider
(16 MHz ÷ 32,768). When the PLL is enabled, the minimum system frequency (fsys) is 37.5 MHz.
This parameter is guaranteed by characterization before qualification rather than 100% tested. Applies to external clock
reference only.
Proper PC board layout procedures must be followed to achieve specifications.
This parameter is guaranteed by design rather than 100% tested.
This specification is the PLL lock time only and does not include oscillator start-up time..
CS_PCB is the measured PCB stray capacitance on EXTAL and XTAL.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase
the Cjitter percentage for a given interval.
5.6
ASP Electrical Characteristics
Table 12 lists the electrical specifications for the ASP module.
Table 12. ASP Electrical Characteristics
Characteristic
Symbol
Min
Typical
Max
Unit
ASP Analog Supply Voltage
VDDA
3.0
—
3.6
V
Input Voltage Range
VADIN
0
—
VDDA
V
Operating Current Consumption
IDDA_ON
—
700
—
uA
Power-down Current Consumption
IDDA_OFF
—
1
—
uA
RES
—
—
12
bits
—
—
125
kS/s
Resolution
Sampling rate
Integral Non-linearity
INL
—
±8
±24
lsb1
Differential Non-linearity
DNL
—
±2
±24
lsb1
ADC Internal Clock Frequency
tAIC
2
—
8
MHz
Conversion Range
RAD
0
—
VDDA
V
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
20
Freescale Semiconductor
Electrical Characteristics
Table 12. ASP Electrical Characteristics (continued)
Characteristic
Symbol
Min
Typical
Max
Unit
Conversion Time
tADC
15
—
32
tAIC
cycles
Sample Time
tADS
3
—
20
tAIC
cycles
Multiplexer Settling Time
tAMS
—
—
3
tAIC
cycles
Zero-scale Error
ZE
—
±4
±12
lsb1
Full-scale Error
FE
—
±320
±370
lsb1
CAIN
—
—
34
pF
Input Capacitance
1
A least significant bit (lsb) is a unit of voltage equal to the smallest resolution of the ADC. This unit of measure approximately
relates the error voltage to the observed error in conversion (code error), and is useful for systemic errors such as differential
non-linearity. A 2.56-V input on an ADC with ± 3 lsb of error could read between 0x1FD and 0x203. This unit is by far the most
common terminology and will be the preferred unit used for error representation.
A bit is a unit equal to the log (base2) of the error voltage normalized to the resolution of the ADC. An error of N bits
corresponds to 2N lsb of error. This measure is easily confused with lsb and is hard to extrapolate between integer values.
5.7
5.7.1
External Interface Timing Specifications
FlexBus
A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up
to a maximum bus frequency of 66MHz. It can be directly connected to asynchronous or synchronous devices such as external
boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For
asynchronous devices a simple chip-select based interface can be used.
All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect to the rising edge of
a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider
of that frequency.
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the Flexbus output
clock, FB_CLK. All other timing relationships can be derived from these values.
Table 13. FlexBus AC Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit
Notes
—
83.33
MHz
fsys/2
tFBCK
12.0
—
ns
tcyc
Frequency of Operation
FB1
Clock Period (FB_CLK)
FB2
Address, Data, and Control Output Valid (FB_A[23:0], FB_D[31:0],
FB_CS[5:0], FB_R/W, FB_TS, FB_BE/BWE[3:0] and FB_OE)
tFBCHDCV
—
7.0
ns
1
FB3
Address, Data, and Control Output Hold (FB_A[23:0], FB_D[31:0],
FB_CS[5:0], FB_R/W, FB_TS, FB_BE/BWE[3:0], and FB_OE)
tFBCHDCI
1
—
ns
1, 2
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
21
Electrical Characteristics
Table 13. FlexBus AC Timing Specifications (continued)
Num
Characteristic
Symbol
Min
Max
Unit
FB4
Data Input Setup
tDVFBCH
3.5
—
ns
FB5
Data Input Hold
tDIFBCH
0
—
ns
FB6
Transfer Acknowledge (TA) Input Setup
tCVFBCH
4
—
ns
FB7
Transfer Acknowledge (TA) Input Hold
tCIFBCH
0
—
ns
Notes
1
Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2.2, “DDR SDRAM AC Timing
Specifications,” for SD_CS[3:0] timing.
2
The FlexBus supports programming an extension of the address hold. Please consult the device reference manual for more
information.
NOTE
The processor drives the data lines during the first clock cycle of the transfer with the full
32-bit address. This may be ignored by standard connected devices using non-multiplexed
address and data buses. However, some applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM controller. At
the end of the read and write bus cycles the address signals are indeterminate.
S0
S1
S2
S3
FB_CLK
FB1
FB3
ADDR[23:0]
FB_A[23:0]
FB_D[31:X]
FB2
FB5
ADDR[31:X]
DATA
FB4
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB6
FB7
FB_TA
Figure 9. FlexBus Read Timing
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
22
Freescale Semiconductor
Electrical Characteristics
S0
S1
S2
S3
FB_CLK
FB1
FB3
ADDR[23:0]
FB_A[23:0]
FB2
FB_D[31:X]
ADDR[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB6
FB7
FB_TA
Figure 10. Flexbus Write Timing
5.7.2
SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports either standard
SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.
5.7.2.1
SDR SDRAM AC Timing Specifications
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the memory bus
clock, when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device’s SDRAM controller
is a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must still be supplied to the
device for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during
read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SD_SDR_DQS signal and its usage.
Table 14. SDR Timing Specifications
Num
Characteristic
Symbol
Frequency of Operation
Min
Max
Unit
Notes
60
83.33
MHz
1
SD1 Clock Period
tSDCK
12.0
16.67
ns
2
SD2 Pulse Width High
tSDCKH
0.45
0.55
SD_CLK
3
SD3 Pulse Width Low
tSDCKH
0.45
0.55
SD_CLK
3
SD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Valid
tSDCHACV
—
0.5 × SD_CLK
+ 1.0
ns
SD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Hold
tSDCHACI
2.0
—
ns
tDQSOV
—
Self timed
ns
4
tDQVSDCH
0.25 ×
SD_CLK
0.40 × SD_CLK
ns
5
SD6 SD_SDR_DQS Output Valid
SD7 SD_DQS[3:2] input setup relative to SD_CLK
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
23
Electrical Characteristics
Table 14. SDR Timing Specifications (continued)
Num
Characteristic
Symbol
Min
Max
Unit
SD8 SD_DQS[3:2] input hold relative to SD_CLK
tDQISDCH
SD9 Data (D[31:0]) Input Setup relative to SD_CLK (reference
only)
tDVSDCH
0.25 ×
SD_CLK
—
ns
SD10 Data Input Hold relative to SD_CLK (reference only)
tDISDCH
1.0
—
ns
SD11 Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid
tSDCHDMV
—
0.5 × SD_CLK
+2
ns
SD12 Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold
tSDCHDMI
1.5
—
ns
1
2
3
4
5
6
7
Does not apply. 0.5×SD_CLK fixed
width.
Notes
6
7
The device supports same frequency of operation for both FlexBus and SDRAM clock operates as that of the internal bus clock.
Please see the PLL chapter of the device reference manual for more information on setting the SDRAM clock rate.
SD_CLK is one SDRAM clock in ns.
Pulse width high plus pulse width low cannot exceed min and max clock period.
SD_SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle
variation from this guideline is expected. SD_SDR_DQS will only pulse during a read cycle and one pulse will occur for each
data beat.
SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SD_DQS will only pulse during a read cycle and one pulse will occur for each data
beat.
The SD_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does
not affect the memory controller.
Since a read cycle in SDR mode still uses the DQS circuit within the device, it is critical that the data valid window be centered
1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup spec is
provided as guidance.
SD2
SD1
SD_CLK
SD3
SD5
SD_CSn
SD_RAS
SD_CAS
SD_WE
A[23:0]
SD_BA[1:0]
CMD
SD4
ROW
COL
SD11
SDDM
SD12
D[31:0]
WD1
WD2
WD3
WD4
Figure 11. SDR Write Timing
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
24
Freescale Semiconductor
Electrical Characteristics
SD2
SD1
SD_CLK
SD5
SD_CSn,
SD_RAS,
SD_CAS,
SD_WE
SD3
CMD
3/4 MCLK
Reference
SD4
A[23:0],
SD_BA[1:0]
ROW
COL
tDQS
SDDM
SD6
SD_SDR_DQS
(Measured at Output Pin)
Board Delay
SD_DQS[3:2]
SD8
(Measured at Input Pin)
SD7
Board Delay
Delayed
SD_CLK
SD9
D[31:0]
from
Memories
WD1
NOTE: Data driven from memories relative
to delayed memory clock.
WD2
WD3
WD4
SD10
Figure 12. SDR Read Timing
5.7.2.2
DDR SDRAM AC Timing Specifications
When using the SDRAM controller in DDR mode, the following timing numbers must be followed to properly latch or drive
data onto the memory bus. All timing numbers are relative to the two DQS byte lanes.
Table 15. DDR Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit
Notes
Frequency of Operation
tDDCK
60
83.33
MHz
1
DD1
Clock Period
tDDSK
12.0
16.67
ns
2
DD2
Pulse Width High
tDDCKH
0.45
0.55
SD_CLK
3
DD3
Pulse Width Low
tDDCKL
0.45
0.55
SD_CLK
3
DD4
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Valid
tSDCHACV
—
0.5 × SD_CLK
+ 1.0
ns
4
DD5
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Hold
tSDCHACI
2.0
—
ns
DD6
Write Command to first DQS Latching Transition
tCMDVDQ
—
1.25
SD_CLK
DD7
Data and Data Mask Output Setup (DQ→DQS)
Relative to DQS (DDR Write Mode)
tDQDMV
1.5
—
ns
5
6
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
25
Electrical Characteristics
Table 15. DDR Timing Specifications (continued)
Num
Characteristic
Symbol
Min
Max
Unit
Notes
DD8
Data and Data Mask Output Hold (DQS→DQ) Relative
to DQS (DDR Write Mode)
tDQDMI
1.0
—
ns
7
DD9
Input Data Skew Relative to DQS (Input Setup)
tDVDQ
—
1
ns
8
tDIDQ
0.25 × SD_CLK
+ 0.5ns
—
ns
9
0.5
—
ns
DD10 Input Data Hold Relative to DQS
DD11 DQS falling edge from SDCLK rising (output hold time) tDQLSDCH
1
2
3
4
5
6
7
8
9
The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the
same frequency as the internal bus clock.
SD_CLK is one SDRAM clock in ns.
Pulse-width high plus pulse-width low cannot exceed minimum or maximum clock period.
Command output valid should be one-half the memory bus clock (SD_CLK) plus some minor adjustments for process,
temperature, and voltage variations.
This specification relates to the required input setup time of today’s DDR memories. The device’s output setup should be larger
than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_DATA[7:0] is relative MEM_DQS[0].
The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats
will be valid for each subsequent DQS edge.
This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],
MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_DATA[7:0] is relative
MEM_DQS[0].
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system-level board skew (due to routing or other
factors).
Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes
invalid.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
26
Freescale Semiconductor
Electrical Characteristics
DD1
DD2
SD_CLK
DD3
SD_CLK
DD5
SD_CSn, SD_WE,
SD_RAS, SD_CAS
CMD
DD4
A[13:0]
ROW
COL
DD11
SD_DQS[3:2]
DD6
DD7
SD_DM[3:2]
D[31:16]
WD1
WD2
WD3
WD4
DD8
Figure 13. DDR Write Timing
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
27
Electrical Characteristics
DD1
DD2
SD_CLK
DD3
SD_CLK
CL=2
DD5
SD_CSn,SD_WE,
SD_RAS, SD_CAS
CMD
CL=2.5
DD4
A[13:0]
ROW
COL
DD9
DQS Read
Postamble
DQS Read
Preamble
CL = 2
SD_DQS3/SD_DQS2
DD10
D[31:24]/D[23:16]
WD1
DQS Read
Preamble
CL = 2.5
SD_DQS3/SD_DQS2
WD2
WD3
WD4
DQS Read
Postamble
D[31:24]/D[23:16]
WD1
WD2
WD3
WD4
Figure 14. DDR Read Timing
Table 16. DDR Clock Crossover Specifications
Symbol
1
Characteristic
Min
Max
Unit
VMP
Clock output mid-point voltage
1.05
1.45
V
VOUT
Clock output voltage level
–0.3
SD_VDD + 0.3
V
VID
Clock output differential voltage (peak to peak swing)
0.7
SD_VDD + 0.6
V
VIX
Clock crossing point voltage1
1.05
1.45
V
The clock crossover voltage is only guaranteed when using the highest drive strength option for the SDCLK[1:0] and
SDCLK[1:0] signals.
SD_CLK
VIX
VMP
VIX
VID
SD_CLK
Figure 15. SD_CLK and SD_CLK Crossover Timing
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
28
Freescale Semiconductor
Electrical Characteristics
5.8
General Purpose I/O Timing
Table 17. GPIO Timing1
Num
1
Characteristic
Symbol
Min
Max
Unit
G1
FB_CLK High to GPIO Output Valid
tCHPOV
—
10
ns
G2
FB_CLK High to GPIO Output Invalid
tCHPOI
1.5
—
ns
G3
GPIO Input Valid to FB_CLK High
tPVCH
9
—
ns
G4
FB_CLK High to GPIO Input Invalid
tCHPI
1.5
—
ns
These general purpose specifications apply to the following signals: IRQn, all UART signals, FlexCAN signals, PWM
signals, DACKn and DREQn, and all signals configured as GPIO.
FB_CLK
G1
G2
GPIO Outputs
G3
G4
GPIO Inputs
Figure 16. GPIO Timing
5.9
Reset and Configuration Override Timing
Table 18. Reset and Configuration Override Timing
Num
1
Characteristic
Symbol
Min
Max
Unit
R1
RESET Input valid to FB_CLK High
tRVCH
9
—
ns
R2
FB_CLK High to RESET Input invalid
tCHRI
1.5
—
ns
tRIVT
5
—
tCYC
1
R3
RESET Input valid Time
R4
FB_CLK High to RSTOUT Valid
tCHROV
—
10
ns
R5
RSTOUT valid to Config. Overrides valid
tROVCV
0
—
ns
R6
Configuration Override Setup Time to RSTOUT invalid
tCOS
20
—
tCYC
R7
Configuration Override Hold Time after RSTOUT invalid
tCOH
0
—
ns
R8
RSTOUT invalid to Configuration Override High Impedance
tROICZ
—
1
tCYC
During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to
the system. Thus, RESET must be held a minimum of 100 ns.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
29
Electrical Characteristics
FB_CLK
R1
R2
R3
RESET
R4
R4
RSTOUT
R8
R5
R6
R7
Configuration Overrides*:
(RCON, Override pins)
Figure 17. RESET and Configuration Override Timing
NOTE
Refer to the CCM chapter of the MCF52277 Reference Manual for more information.
5.10
LCD Controller Timing Specifications
This sections lists the timing specifications for the LCD Controller.
Table 19. LCD_LSCLK Timing
Num
Characteristic
Min
Max
Unit
T1
LCD_LSCLK Period
25
2000
ns
T2
Pixel data setup time
11
—
ns
T3
Pixel data up time
11
—
ns
Note: The pixel clock is equal to LCD_LSCLK / (PCD + 1). When it is in CSTN, TFT, or monochrome mode with
bus width = 1, LCD_LSCLK is equal to the pixel clock. When it is in monochrome with other bus width
settings, LCD_LSCLK is equal to the pixel clock divided by bus width. The polarity of LCD_LSCLK and
LCD_D signals can also be programmed.
T1
LCD_LSCLK
LCD_D[17:0]
T2
T3
Figure 18. LCD_LSCLK to LCD_D[17:0] timing diagram
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
30
Freescale Semiconductor
Electrical Characteristics
Non-display Region
LCD_VSYNC
Display Region
T3
T1
T4
T2
LCD_HSYNC
LCD_OE
LCD_D[17:0]
Line Y
Line 1
T5
T6
Line Y
XMAX
T7
LCD_HSYNC
LCD_LSCLK
LCD_OE
LCD_D[15:0]
(1,1)
(1,2)
(1,X)
Figure 19. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing
Table 20. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing
Num
Characteristic
Min
Value
Unit
T5 + T6 + T7 – 1
(VWAIT1 × T2) +
T5 + T6 + T7 – 1
Ts
T1
End of LCD_OE to beginning of LCD_VSYNC
T2
LCD_HSYNC period
—
XMAX+T5+T6+T7
Ts
T3
LCD_VSYNC pulse width
T2
VWIDTH × T2
Ts
T4
End of LCD_VSYNC to beginning of LCD_OE
1
(VWAIT2 × T2)+1
Ts
T5
LCD_HSYNC pulse width
1
HWIDTH + 1
Ts
T6
End of LCD_HSYNC to beginning to LCD_OE
3
HWAIT2 + 3
Ts
T7
End of LCD_OE to beginning of LCD_HSYNC
1
HWAIT1 + 1
Ts
Note: Ts is the LCD_LSCLK period. LCD_VSYNC, LCD_HSYNC, and LCD_OE can be programmed as active high or active
low. In Figure 19, all 3 signals are active low. LCD_LSCLK can be programmed to be deactivated during the
LCD_VSYNC pulse or the LCD_OE deasserted period. In Figure 19, LCD_LSCLK is always active.
Note: XMAX is defined in number of pixels in one line.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
31
Electrical Characteristics
XMAX
LCD_LSCLK
LCD_D
D1
D320
D2
D320
T1
LCD_SPL_SPR
T2
T3
T2
LCD_HSYNC
T4
T4
LCD_CLS
T5
LCD_PS
T6
T7
T7
LCD_REV
Figure 20. Sharp TFT Panel Timing
Table 21. Sharp TFT Panel Timing
Num
Characteristic
Min
Value
Unit
T1
LCD_SPL/LCD_SPR pulse width
—
1
Ts
T2
End of LCD_D of line to beginning of LCD_HSYNC
1
HWAIT1+1
Ts
T3
End of LCD_HSYNC to beginning of LCD_D of line
4
HWAIT2 + 4
Ts
T4
LCD_CLS rise delay from end of LCD_D of line
3
CLS_RISE_DELAY+1
Ts
T5
LCD_CLS pulse width
1
CLS_HI_WIDTH+1
Ts
T6
LCD_PS rise delay from LCD_CLS negation
0
PS_RISE_DELAY
Ts
T7
LCD_REV toggle delay from last LCD_D of line
1
REV_TOGGLE_DELAY+1
Ts
Note: Falling of LCD_SPL/LCD_SPR aligns with first LCD_D of line.
Note: Falling of LCD_PS aligns with rising edge of LCD_CLS.
Note: LCD_REV toggles in every LCD_HSYN period.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
32
Freescale Semiconductor
Electrical Characteristics
T1
T1
LCD_VSYNC
T3
T2
T4
XMAX
T2
LCD_HSYNC
LCD_LSCLK
Ts
LCD_D[15:0]
Figure 21. Non-TFT Mode Panel Timing
Table 22. Non-TFT Mode Panel Timing
Num
Characteristic
Min
Value
Unit
T1
LCD_HSYNC to LCD_VSYNC delay
2
HWAIT2 + 2
Tpix
T2
LCD_HSYNC pulse width
1
HWIDTH + 1
Tpix
T3
LCD_VSYNC to LCD_LSCLK
—
0 ≤ T3 ≤ Ts
—
T4
LCD_LSCLK to LCD_HSYNC
1
HWAIT1 + 1
Tpix
Note: Ts is the LCD_LSCLK period while Tpix is the pixel clock period. LCD_VSYNC, LCD_HSYNC, and
LCD_LSCLK can be programmed as active high or active low. In Figure 21, all these 3 signals are active
high. When it is in CSTN mode or monochrome mode with bus width = 1, T3 = Tpix = Ts. When it is in
monochrome mode with bus width = 2, 4 and 8, T3 = 1, 2 and 4 Tpix respectively.
5.11
USB On-The-Go Specifications
The MCF5227x device is compliant with industry standard USB 2.0 specification.
Table 23. USB On-Chip Transceiver DC Characteristics
Characteristic
Condition
Symbol
Min
Typ
Max
Unit
Driven
VIH
2.0
—
—
V
VIL
—
—
0.8
V
VID
200
—
00
mV
Differential Common Mode Range
VCM
0.8
—
2.5
V
Single Ended Receive Threshold
VSETHR
0.8
—
2.0
V
Single Ended Receive Hysteresis
VSEHYS
—
400
—
mV
Input High
Input Low
Input Differential
(DP – DM)
Output High
Driven
VOH
0.0
—
300
mV
Output Low
Driven
VOL
2.8
—
2.0
V
DP = DM
VCRS
1.3
—
2.0
V
Differential Output Crossover
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
33
Electrical Characteristics
Table 23. USB On-Chip Transceiver DC Characteristics (continued)
Characteristic
Condition
Symbol
Min
Typ
Max
Unit
P side Impedance
Driven
ZP
6.25
8.25
11.25
Ω
M side Impedance
Driven
ZM
6.25
8.25
11.25
Ω
ZMatching
—
0.17
0.23
Ω
RPD
30k
50k
70k
Ω
Impedance Matching P/M
Pulldown Resistance1
1
The pulldown resistors are included to provide a method to keep DP and DM signals in a known quiescent state
if desired when the USB port is not being used or when the USB cable is not connected. These on-chip
resistors should not be used to provide the 15-kΩ host-mode pulldowns called for in Chapter 7 of the USB
Specification, Rev. 1.1 or Rev. 2.0.
Table 24. USB On-Chip Transceiver Full Speed AC Characteristics
Characteristic
Condition
Symbol
Min
Typ
Max
Unit
Rise Time
10–90%
tLH
7
11
17.5
ns
Fall Time
90–10%
tHL
7
11
17.5
ns
Rise/Fall Matching
—
t LH
-------- Matching
t HL
20
40
60
ps
Rise/Fall Matching, DP and DM
—
t LH
-------- Pad-to-Pad
t HL
330
360
640
ps
TIme Skew Between DP and DM
—
tSKE
100
140
210
ps
Table 25. USB On-Chip Transceiver Low Speed AC Characteristics
Characteristic
Condition
Symbol
Min
Typ
Max
Unit
Rise Time
10–90%
tLH
75
—
300
ns
Fall Time
90–10%
tHL
75
—
300
ns
t LH
-------t HL
t LH
-------- Matching
t HL
80
—
125
%
Rise/Fall Matching
5.12
SSI Timing Specifications
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given
for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings
remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.
Table 26. SSI Timing—Master Modes1
Num
Characteristic
S1
SSI_MCLK cycle time
S2
SSI_MCLK pulse width high / low
S3
SSI_BCLK cycle time
S4
SSI_BCLK pulse width
Symbol
Min
Max
Unit
Notes
tMCLK
4 × 1/fSYS
—
ns
2
45%
55%
tMCLK
4 × 1/fSYS
—
ns
45%
55%
tBCLK
tBCLK
3
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
34
Freescale Semiconductor
Electrical Characteristics
Table 26. SSI Timing—Master Modes1 (continued)
Num
Characteristic
Symbol
Min
Max
Unit
S5
SSI_BCLK to SSI_FS output valid
—
10
ns
S6
SSI_BCLK to SSI_FS output invalid
0
—
ns
S7
SSI_BCLK to SSI_TXD valid
—
10
ns
S8
SSI_BCLK to SSI_TXD invalid / high impedence
0
—
ns
S9
SSI_RXD / SSI_FS input setup before SSI_BCLK
10
—
ns
S10
SSI_RXD / SSI_FS input hold after SSI_BCLK
0
—
ns
Notes
1
All timings specified with a capactive load of 25pF.
SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (SYSCLK).
3
SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the minimum
divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure that SSI_BCLK does not
exceed 4 x fSYS.
2
Table 27. SSI Timing—Slave Modes1
Num
1
Characteristic
Symbol
Min
Max
Unit
tBCLK
4 × 1/fSYS
—
ns
45%
55%
tBCLK
S11
SSI_BCLK cycle time
S12
SSI_BCLK pulse width high / low
S13
SSI_FS input setup before SSI_BCLK
10
—
ns
S14
SSI_FS input hold after SSI_BCLK
2
—
ns
S15
SSI_BCLK to SSI_TXD / SSI_FS output valid
—
10
ns
S16
SSI_BCLK to SSI_TXD / SSI_FS output invalid / high
impedence
0
—
ns
S17
SSI_RXD setup before SSI_BCLK
10
—
ns
S18
SSI_RXD hold after SSI_BCLK
2
—
ns
Notes
All timings specified with a capactive load of 25 pF.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
35
Electrical Characteristics
S1
S2
S2
SSI_MCLK
(Output)
S3
SSI_BCLK
(Output)
S4
S4
S5
S6
SSI_FS
(Output)
S9
S10
SSI_FS
(Input)
S7
S7
S8
S8
SSI_TXD
S9
S10
SSI_RXD
Figure 22. SSI Timing—Master Modes
S11
SSI_BCLK
(Input)
S12
S12
S15
S16
SSI_FS
(Output)
S13
S14
SSI_FS
(Input)
S15
S16
S16
S15
SSI_TXD
S17
S18
SSI_RXD
Figure 23. SSI Timing—Slave Modes
5.13
I2C Timing Specifications
Table 28 lists specifications for the I2C input timing parameters shown in Figure 24.
Table 28. I2C Input Timing Specifications between SCL and SDA
Num
Characteristic
Min
Max
Unit
I1
Start condition hold time
2
—
tcyc
I2
Clock low period
8
—
tcyc
I3
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
—
1
ms
I4
Data hold time
0
—
ns
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
36
Freescale Semiconductor
Electrical Characteristics
Table 28. I2C Input Timing Specifications between SCL and SDA (continued)
Num
Characteristic
Min
Max
Unit
I5
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
1
ms
I6
Clock high time
4
—
tcyc
I7
Data setup time
0
—
ns
I8
Start condition setup time (for repeated start condition only)
2
—
tcyc
I9
Stop condition setup time
2
—
tcyc
Min
Max
Unit
Table 29 lists specifications for the I2C output timing parameters shown in Figure 24.
Table 29. I2C Output Timing Specifications between SCL and SDA
Num
Characteristic
I11
Start condition hold time
6
—
tcyc
I21
Clock low period
10
—
tcyc
I32
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
—
—
µs
I41
Data hold time
7
—
tcyc
I53
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
3
ns
I61
Clock high time
10
—
tcyc
I71
Data setup time
2
—
tcyc
I81
Start condition setup time (for repeated start condition only)
20
—
tcyc
I91
Stop condition setup time
10
—
tcyc
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Table 29. The I2C interface is designed
to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is
affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 29
are minimum values.
2
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive
low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up
resistor values.
3
Specified at a nominal 50-pF load.
Figure 24 shows timing for the values in Table 29 and Table 28.
I5
I6
I2
I2C_SCL
I1
I4
I7
I8
I3
I9
I2C_SDA
Figure 24. I2C Input/Output Timings
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
37
Electrical Characteristics
5.14
DMA Timer Timing Specifications
Table 30 lists timer module AC timings.
Table 30. Timer Module AC Timing Specifications
Num
5.15
Characteristic
Min
Max
Unit
T1
DT0IN / DT1IN / DT2IN / DT3IN cycle time
3
—
tCYC
T2
DT0IN / DT1IN / DT2IN / DT3IN pulse width
1
—
tCYC
DSPI Timing Specifications
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with both master and slave operations. Many
of the transfer attributes are programmable. Table 31 provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the MCF52277 Reference Manual for information on the modified transfer formats used for
communicating with slower peripheral devices.
Table 31. DSPI Module AC Timing Specifications1
Num
Characteristic
Symbol
Min
Max
Unit
Notes
2
DS1
DSPI_SCK Cycle Time
tSCK
4 x 1/fSYS
—
ns
DS2
DSPI_SCK Duty Cycle
—
(tsck ÷ 2) – 2.0
(tsck ÷ 2) + 2.0
ns
Master Mode
DS3
DSPI_PCSn to DSPI_SCK delay
tCSC
(2 × 1/fSYS) – 2.0
—
ns
3
DS4
DSPI_SCK to DSPI_PCSn delay
tASC
(2 × 1/fSYS) – 3.0
—
ns
4
DS5
DSPI_SCK to DSPI_SOUT valid
—
—
5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
—
–5
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
—
9
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
—
0
—
ns
Slave Mode
DS9
DSPI_SCK to DSPI_SOUT valid
—
—
4
ns
DS10
DSPI_SCK to DSPI_SOUT invalid
—
0
—
ns
DS11
DSPI_SIN to DSPI_SCK input setup
—
2
—
ns
DS12
DSPI_SCK to DSPI_SIN input hold
—
7
—
ns
DS13
DSPI_SS active to DSPI_SOUT driven
—
—
20
ns
DS14
DSPI_SS inactive to DSPI_SOUT not driven
—
—
18
ns
1
Timings shown are for DMCR[MTFE] = 0 (classic SPI) and DCTARn[CPHA] = 0. Data is sampled on the DSPI_SIN pin on the
odd-numbered DSPI_SCK edges and driven on the DSPI_SOUT pin on even-numbered DSPI edges.
2 When in master mode, the baud rate is programmable in DCTARn[PBR] and DCTARn[BR].
3 The DSPI_PCSn to DSPI_SCK delay is programmable in DCTARn[PCSSCK] and DCTARn[CSSCK].
4 The DSPI_SCK to DSPI_PCSn delay is programmable in DCTARn[PASC] and DCTARn[ASC].
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
38
Freescale Semiconductor
Electrical Characteristics
DS3
DS4
DSPI_PCSn
DS1
DS2
DSPI_SCK
(DCTARn[CPOL] = 0)
DS2
DSPI_SCK
(DCTARn[CPOL] = 1)
DS7
DS8
DSPI_SIN
First Data
Data
DS6
DSPI_SOUT
Last Data
DS5
First Data
Data
Last Data
Figure 25. DSPI Classic SPI Timing—Master Mode
DSPI_SS
DS1
DSPI_SCK
(DCTARn[CPOL] = 0)
DS2
DS2
DSPI_SCK
(DCTARn[CPOL] = 1)
DS13
DSPI_SOUT
DS10
First Data
DS11
DSPI_SIN
DS9
Data
Last Data
Data
Last Data
DS14
DS12
First Data
Figure 26. DSPI Classic SPI Timing—Slave Mode
5.16
SBF Timing Specifications
The Serial Boot Facility (SBF) provides a means to read configuration information and system boot code from a broad array of
SPI-compatible EEPROMs, flashes, FRAMs, nVSRAMs, etc. Table 32 provides the AC timing specifications for the SBF.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
39
Electrical Characteristics
Table 32. SBF AC Timing Specifications
Num
1
Characteristic
Symbol
Min
Max
Unit
Notes
tSBFCK
30
—
ns
1
SB1
SBF_CK Cycle Time
SB2
SBF_CK High/Low Time
—
30%
—
tSBFCK
SB3
SBF_CS to SBF_CK delay
—
tSBFCK – 2.0
—
ns
SB4
SBF_CK to SBF_CS delay
—
tSBFCK – 2.0
—
ns
SB5
SBF_CK to SBF_DO valid
—
—
12
ns
SB6
SBF_CK to SBF_DO invalid
—
0
—
ns
SB7
SBF_DI to SBF_SCK input setup
—
6
—
ns
SB8
SBF_CK to SBF_DI input hold
—
0
—
ns
At reset, the SBF_CK cycle time is tREF × 67. The first byte of data read from the serial memory contains a divider
value that is used to set the SBF_CK cycle time for the duration of the serial boot process.
SB1
SB2
SB4
SB2
SBF_CK
SB3
SBF_CS
SB7
SBF_DI
SB8
First Data
Data
SB6
SBF_DO
First Data
Last Data
SB5
Data
Last Data
Figure 27. SBF Timing
5.17
JTAG and Boundary Scan Timing Specifications
Table 33. JTAG and Boundary Scan Timing
Characteristic1
Num
Symbol
Min
Max
Unit
J1
TCLK Frequency of Operation
fJCYC
DC
1/4
fsys/2
J2
TCLK Cycle Period
tJCYC
4
—
tCYC
J3
TCLK Clock Pulse Width
tJCW
26
—
ns
J4
TCLK Rise and Fall Times
tJCRF
0
3
ns
J5
Boundary Scan Input Data Setup Time to TCLK Rise
tBSDST
4
—
ns
J6
Boundary Scan Input Data Hold Time after TCLK Rise
tBSDHT
26
—
ns
J7
TCLK Low to Boundary Scan Output Data Valid
tBSDV
0
33
ns
J8
TCLK Low to Boundary Scan Output High Z
tBSDZ
0
33
ns
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
40
Freescale Semiconductor
Electrical Characteristics
Table 33. JTAG and Boundary Scan Timing (continued)
Characteristic1
Num
1
Symbol
Min
Max
Unit
J9
TMS, TDI Input Data Setup Time to TCLK Rise
tTAPBST
4
—
ns
J10
TMS, TDI Input Data Hold Time after TCLK Rise
tTAPBHT
10
—
ns
J11
TCLK Low to TDO Data Valid
tTDODV
0
26
ns
J12
TCLK Low to TDO High Z
tTDODZ
0
8
ns
J13
TRST Assert Time
tTRSTAT
100
—
ns
J14
TRST Setup Time (Negation) to TCLK High
tTRSTST
10
—
ns
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
J2
J3
VIH
TCLK
(input)
J3
VIL
J4
J4
Figure 28. Test Clock Input Timing
TCLK
VIL
VIH
J5
Data Inputs
J6
Input Data Valid
J7
Data Outputs
Output Data Valid
J8
Data Outputs
J7
Data Outputs
Output Data Valid
Figure 29. Boundary Scan (JTAG) Timing
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
41
Electrical Characteristics
TCLK
VIL
VIH
J9
TDI
TMS
J10
Input Data Valid
J11
TDO
Output Data Valid
J12
TDO
J11
TDO
Output Data Valid
Figure 30. Test Access Port Timing
TCLK
J14
TRST
J13
Figure 31. TRST Timing
5.18
Debug AC Timing Specifications
Table 34 lists specifications for the debug AC timing parameters shown in Figure 32.
Table 34. Debug AC Timing Specification
Num
1
Characteristic
Min
Max
Units
D0
PSTCLK cycle time
1
1
1/fSYS
D1
PSTCLK rising to PSTDDATA valid
—
3.0
ns
D2
PSTCLK rising to PSTDDATA invalid
1.5
—
ns
D3
DSI-to-DSCLK setup
1
—
PSTCLK
D41
DSCLK-to-DSO hold
4
—
PSTCLK
D5
DSCLK cycle time
5
—
PSTCLK
D6
BKPT assertion time
1
—
PSTCLK
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative
to the rising edge of PSTCLK.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
42
Freescale Semiconductor
Package Information
D0
PSTCLK
D2
D1
PSTDDATA[7:0]
Figure 32. Real-Time Trace AC Timing
D5
DSCLK
D3
DSI
Current
Next
D4
DSO
Past
Current
Figure 33. BDM Serial Port AC Timing
6
Package Information
The latest package outline drawings are available on the product summary pages on our web site:
http://www.freescale.com/coldfire. The following table lists the case outline numbers per device. Use these numbers in the web
page’s keyword search engine to find the latest package outline drawings.
Table 35. Package Information
7
Device
Package Type
Mask Set
Revision
Case Outline Numbers
MCF52274
176 LQFP
All
All
98ASS23479W
M26H
1.1
98ASH98061A
MCF52277
196 MAPBGA
2M26H, 3M26H
1.2–1.3
98ARH98390A
Product Documentation
Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution
Center, or through the Freescale world-wide web address at http://www.freescale.com/coldfire.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
43
Revision History
8
Revision History
Table 36 summarizes revisions to this document.
f
Table 36. MCF52277 Data Sheet Revision History
Rev. No.
Date of Release
Summary of Changes
3
02/2008
Initial public revision.
4
05/2008
Corrected MCF52274 order number from MCF52274CAB120 to
MCF52274CLU120 in Table 2
5
07/2008
Corrected MCF52277CVM166 part number to MCF52277CVM160 in Table 2.
Although, this device has a maximum rated frequency of 166.67 MHz.
6
07/2008
Added data to Section 3.5, “Power Consumption Specifications.”
7
02/2009
Changed document type from Data Sheet: Advance Information to Data Sheet:
Technical Data and corresponding footnote on first page
Replaced tSYS with 1/fSYS throughout
Changed the following specs in Table 14 and Table 15:
• Minimum frequency of operation from TBD to 60MHz
• Maximum clock period from TBD to 16.67 ns
Added RTC and Oscillator Supply Voltage specs to Table 7 and Table 10
In Table 8:
• Updated thermal characteristics for the 196 MAPBGA package
• Added thermal characteristics for the 176 LQFP package that were TBD
In Table 11:
• Corrected maximum crystal reference frequency range from 66.67 to 25 MHz
• Added footnotes to maximum crystal and external reference frequency ranges
• Changed minimum core/system and CLKOUT frequencies from TBD to 512 and
256 Hz, respectively.
In Table 12:
• Added Typical column
• Removed Internal Reference Voltage spec as it isn’t necessary
• Moved Current Consumption specs from maximum column to typical column
• Added INL and DNL specs that were TBD, and changed the unit footnote
• Replaced Gain and Offset Error specs with Full-Scale and Zero-Scale Error
• Removed Input Leakage Current and Input Current specs as they aren’t
necessary
Removed Gain Calculations section as it isn’t necessary
8
09/2009
Iin Table 35, added case outline number for MCF52277 masks 2M26H and 3M26H
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
44
Freescale Semiconductor
Revision History
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
45
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Document Number: MCF52277
Rev. 8
09/2009
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