28C16A DATA SHEET (07/21/2004) DOWNLOAD

Obsolete Device
28C16A
16K (2K x 8) CMOS EEPROM
 2004 Microchip Technology Inc.
30 NC
32 Vcc
31 WE
2 NC
1 NU
4 A7
3 NC
5
29 A8
6
28 A9
7
27 NC
8
9
10
26 NC
25 OE
24 A10
20
19
21 I/O6
18
22 I/O7
13
17
23 CE
12
16
11
15
Vcc
A8
A6
A9
A5
WE
A4
OE
A3
A10
A2
CE
A1
I/O7 A0
I/O6 NC
I/O5 I/O0
I/O4
I/O3
14
24
23
22
21
20
19
18
17
16
15
14
13
• Pin 1 indicator on PLCC on top of package
BLOCK DIAGRAM
I/O0
VSS
VCC
CE
WE
I/O7
Data Protection
Circuitry
Chip Enable/
Output Enable
Control Logic
OE
Auto Erase/Write
Timing
Data
Poll
Input/Output
Buffers
Program Voltage
Generation
A0
L
a
t
c
h
e
s
DESCRIPTION
The Microchip Technology Inc. 28C16A is a CMOS 16K
non-volatile electrically Erasable PROM. The 28C16A
is accessed like a static RAM for the read or write
cycles without the need of external components. During a “byte write”, the address and data are latched
internally, freeing the microprocessor address and data
bus for other operations. Following the initiation of
write cycle, the device will go to a busy state and automatically clear and write the latched data using an
internal control timer. To determine when a write cycle
is complete, the 28C16A uses Data polling. Data polling allows the user to read the location last written to
when the write operation is complete. CMOS design
and processing enables this part to be used in systems
where reduced power consumption and reliability are
required. A complete family of packages is offered to
provide the utmost flexibility in applications.
•1
2
3
4
5
6
7
8
9
10
11
12
PLCC
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
DIP
• Fast Read Access Time—150 ns
• CMOS Technology for Low Power Dissipation
- 30 mA Active
- 100 µA Standby
• Fast Byte Write Time—200 µs or 1 ms
• Data Retention >200 years
• High Endurance - Minimum 104 Erase/Write Cycles
• Automatic Write Operation
- Internal Control Timer
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
• Data polling
• Chip Clear Operation
• Enhanced Data Protection
- VCC Detector
- Pulse Filter
- Write Inhibit
• Electronic Signature for Device Identification
• 5-Volt-Only Operation
• Organized 2Kx8 JEDEC Standard Pinout
• 24-pin Dual-In-Line Package
• 32-pin PLCC Package
• Available for Extended Temperature Ranges:
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
PACKAGE TYPES
I/O1
I/O2
Vss
NU
I/O3
I/O4
I/O5
FEATURES
Y
Decoder
Y Gating
X
Decoder
16K bit
Cell Matrix
A10
DS11125J-page 1
28C16A
1.0
ELECTRICAL CHARACTERISTICS
1.1
MAXIMUM RATINGS*
TABLE 1-1:
Name
VCC and input voltages w.r.t. VSS ....... -0.6V to + 6.25V
Function
A0 - A10
Voltage on OE w.r.t. VSS...................... -0.6V to +13.5V
Voltage on A9 w.r.t. VSS ...................... -0.6V to +13.5V
Output Voltage w.r.t. VSS .................-0.6V to VCC+0.6V
Storage temperature ..........................-65°C to +125°C
Address Inputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Ambient temp. with power applied .......-50°C to +95°C
*Notice: Stresses above those listed under “Maximum Ratings”
may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any
other conditions above those indicated in the operation listings of
this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2:
PIN FUNCTION TABLE
Data Inputs/Outputs
VCC
+5V Power Supply
VSS
Ground
NC
No Connect; No Internal Connection
NU
Not Used; No External Connection is
Allowed
READ/WRITE OPERATION DC CHARACTERISTICS
VCC = +5V ±10%
Commercial (C): Tamb = 0°C
to
Industrial
(I): Tamb = -40°C to
Parameter
+70°C
+85°C
Status
Symbol
Min
Max
Units
Input Voltages
Logic ‘1’
Logic ‘0;
VIH
VIL
2.0
-0.1
VCC+1
0.8
V
V
Input Leakage
—
ILI
-10
10
µA
VIN = -0.1V to VCC+1
Input Capacitance
—
CIN
—
10
pF
VIN = 0V; Tamb = 25°C;
f = 1 MHz
Logic ‘1’
Logic ‘0’
VOH
VOL
2.4
0.45
V
V
IOH = -400µA
IOL = 2.1 mA
Output Leakage
—
ILO
-10
10
µA
VOUT = -0.1V to VCC+0.1V
Output Capacitance
—
COUT
—
12
pF
VIN = 0V; Tamb = 25°C;
f = 1 MHz
Power Supply Current,
Active
TTL input
ICC
—
30
mA
f = 5 MHz (Note 1)
VCC = 5.5V;
Power Supply Current,
Standby
TTL input
TTL input
CMOS input
ICC(S)TTL
ICC(S)TTL
ICC(S)CMOS
—
2
3
100
mA
mA
µA
CE = VIH (0°C to +70°C)
CE = VIH (-40°C to +85°C)
CE = VCC-0.3 to VCC+1
OE = VCC
Other inputs equal VCC or VSS
Output Voltages
Note 1:
Conditions
AC power supply current above 5 MHz; 1 mA/MHz.
DS11125J-page 2
 2004 Microchip Technology Inc.
28C16A
TABLE 1-3:
READ OPERATION AC CHARACTERISTICS
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:
Parameter
VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; Vol = 0.8V
1 TTL Load + 100pF
20 ns
Commercial (C): Tamb = 0°C to +70°0°C
Industrial (I):
Tamb = -40°C to +85°C
28C16A-15
28C16A-20
28C16A-25
Min
Max
Min
Max
Min
Max
Sym
Units
Conditions
Address to Output Delay
tACC
—
150
—
200
—
250
ns
OE = CE = VIL
CE to Output Delay
tCE
—
150
—
200
—
250
ns
OE = VIL
OE to Output Delay
tOE
—
70
—
80
—
100
ns
CE = VIL
CE or OE High to Output Float
tOFF
0
50
0
55
0
70
ns
Output Hold from CE or OE,
whichever occurs first
tOH
0
—
0
—
0
—
ns
Endurance
—
1M
—
1M
—
1M
—
cycles 25°C, Vcc =
5.0V, Block
Mode (Note)
Note: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-1:
READ WAVEFORMS
V IH
Address
Address Valid
V IL
V IH
CE
V IL
t CE(2)
V IH
OE
t OFF(1,3)
t OH
V IL
t OE(2)
V OH
Data
High Z
High Z
Valid Output
V OL
V IH
t ACC
WE
V IL
Notes: (1) t OFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to t CE - t OE after the falling edge of CE without impact on t
(3) This parameter is sampled and is not 100% tested
 2004 Microchip Technology Inc.
CE
DS11125J-page 3
28C16A
TABLE 1-4:
BYTE WRITE AC CHARACTERISTICS
AC Testing Waveform:
Output Load:
Input Rise/Fall Times:
Ambient Temperature:
Parameter
VIH = 2.4V and VIL = 0.45V; VOH = 2.0V; VOL = 0.8V
1 TTL Load + 100 pF
20 ns
Commercial (C):
Tamb = 0°C to +70°C
Industrial
(I):
Tamb = -40°C to +85°C
Symbol
Min
Max
Units
Remarks
Address Set-Up Time
tAS
10
—
ns
Address Hold Time
tAH
50
—
ns
Data Set-Up Time
tDS
50
—
ns
Data Hold Time
tDH
10
—
ns
Write Pulse Width
tWPL
100
—
ns
Write Pulse High Time
tWPH
50
—
ns
OE Hold Time
tOEH
10
—
ns
OE Set-Up Time
tOES
10
—
ns
Data Valid Time
tDV
—
1000
ns
Note 2
Write Cycle Time (28C16A)
tWC
—
1
ms
0.5 ms typical
Write Cycle Time (28C16AF)
tWC
—
200
µs
100 µs typical
Note 1
Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the positive edge of CE or WE, whichever occurs first.
2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until tDH
after the positive edge of WE or CE, whichever occurs first.
FIGURE 1-2:
PROGRAMMING WAVEFORMS
VIH
Address
VIL
VIH
t AS
t AH
t WPL
CE, WE
VIL
t DV
Data In
t DS
t DH
VIH
VIL
t OES
VIH
OE
VIL
t OEH
DS11125J-page 4
 2004 Microchip Technology Inc.
28C16A
FIGURE 1-3:
DATA POLLING WAVEFORMS
VIH
Last Written
Address Valid
Address Valid
Address
VIL
t ACC
VIH
CE
t CE
VIL
t WPH
VIH
t WPL
WE
VIL
t OE
VIH
OE
VIL
t DV
VIH
Data In
Valid
Data
VIL
I/O7 Out
True Data Out
t WC
FIGURE 1-4:
CHIP CLEAR WAVEFORMS
VIH
CE
VIL
VH
OE
VIH
tS
tH
tW
VIH
WE
tW = 10ms
tS = tH = 1µs
VH = 12.0V ±0.5V
VIL
TABLE 1-5:
SUPPLEMENTARY CONTROL
Mode
CE
OE
WE
A9
VCC
Chip Clear
VIL
VH
VIL
X
VCC
Extra Row Read
VIL
VIL
VIH
A9 = VH
VCC
Data Out
Extra Row Write
*
VIH
*
A9 = VH
VCC
Data In
Note 1: VH = 12.0V±0.5V
 2004 Microchip Technology Inc.
I/OI
* Pulsed per programming waveforms.
DS11125J-page 5
28C16A
2.0
DEVICE OPERATION
2.4
The Microchip Technology Inc. 28C16A has four basic
modes of operation—read, standby, write inhibit, and
byte write—as outlined in the following table.
Operation
Mode
CE
OE
WE
I/O
Read
L
L
H
DOUT
Standby
H
X
X
High Z
Write Inhibit
H
X
X
High Z
Write Inhibit
X
L
X
High Z
Write Inhibit
X
X
H
High Z
Byte Write
L
H
L
DIN
Byte Clear
Automatic Before Each “Write”
X = Any TTL level.
2.1
2.2
The 28C16A has a write cycle similar to that of a Static
RAM. The write cycle is completely self-timed and initiated by a low going pulse on the WE pin. On the falling edge of WE, the address information is latched. On
rising edge, the data and the control pins (CE and OE)
are latched.
2.5
Data Polling
The 28C16A features Data polling to signal the completion of a byte write cycle. During a write cycle, an
attempted read of the last byte written results in the
data complement of I/O7 (I/O0 to I/O6 are indeterminable). After completion of the write cycle, true data is
available. Data polling allows a simple read/compare
operation to determine the status of the chip eliminating
the need for external hardware.
2.6
Read Mode
The 28C16A has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and is used to gate data to the
output pins independent of device selection. Assuming
that addresses are stable, address access time (tACC)
is equal to the delay from CE to output (tCE). Data is
available at the output tOE after the falling edge of OE,
assuming that CE has been low and addresses have
been stable for at least tACC-tOE.
Write Mode
Electronic Signature for Device
Identification
An extra row of 32 bytes of EEPROM memory is available to the user for device identification. By raising A9
to 12V ±0.5V and using address locations 7EO to 7FF,
the additional bytes can be written to or read from in the
same manner as the regular memory array.
2.7
Chip Clear
All data may be cleared to 1's in a chip clear cycle by
raising OE to 12 volts and bringing the WE and CE
low. This procedure clears all data, except for the extra
row.
Standby Mode
The 28C16A is placed in the standby mode by applying
a high signal to the CE input. When in the standby
mode, the outputs are in a high impedance state, independent of the OE input.
2.3
Data Protection
In order to ensure data integrity, especially during critical power-up and power-down transitions, the following
enhanced data protection circuits are incorporated:
First, an internal VCC detect (3.3 volts typical) will inhibit
the initiation of non-volatile programming operation
when VCC is less than the VCC detect circuit trip.
Second, there is a WE filtering circuit that prevents WE
pulses of less than 10 ns duration from initiating a write
cycle.
Third, holding WE or CE high or OE low, inhibits a write
cycle during power-on and power-off (VCC).
DS11125J-page 6
 2004 Microchip Technology Inc.
28C16A
28C16A Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
28C16A
F
T
– 15 I
/P
Package:
Temperature
Range:
Access Time:
Blank = 0°C to +70°C
I = -40°C to +85°C
15
20
25
150 ns
200 ns
250 ns
Shipping:
Blank
T
Option:
Blank = twc = 1ms
F = twc = 200 µs
Device:
 2004 Microchip Technology Inc.
L = Plastic Leaded Chip Carrier (PLCC)
P = Plastic DIP (600 mil)
28C16A
Tube
Tape and Reel “L” only
2K x 8 CMOS EEPROM
DS11125J-page 7
28C16A
NOTES:
DS11125J-page 8
 2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
 2004 Microchip Technology Inc.
DS11125J-page 9
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07/12/04
 2004 Microchip Technology Inc.
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