DS9598 00

®
RT9598
MOSFET Integrated Smart Photoflash Capacitor Charger
with IGBT Driver
General Description
Features
The RT9598 is a complete photoflash module solution for
digital and film cameras. It is targeted for applications that
use 2 to 4 AA batteries or 1 to 2 Lithium-Ion batteries.
The RT9598 adopts Flyback topology which uses constant
primary peak current and zero secondary valley current
to charge photoflash capacitor quickly and efficiently. The
built-in 55V MOSFET allows flexibility in transformer design
and simplifies the PCB layout. The RT9598 also integrates
an IGBT driver for igniting photoflash tube. Only a few
external components are required, which greatly reduces
the PCB space and cost. The RT9598 is available in the
WDFN-8L 2x2 package.







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55V MOSFET Integrated
Charge any Size Photoflash Capacitor
Adjustable Input Current
Adjustable Output Voltage
Charge Complete Indicator
Built-In IGBT Driver for IGBT Application
Constant Peak Current Control
Over-Voltage Protection
Maximum On-Time Protection
8-Lead WDFN Package
RoHS Compliant and Halogen Free
Applications
Marking Information
1KW

1K : Product Code

W : Date Code

Digital Still Camera
Film Camera Flash Unit
Camera Phone Flash
Simplified Application Circuit
1:N
Battery
VOUT
R2
+
R1
COUT
R3
SW
FB
RT9598
VDD Power
VDD
DRVIN
CHARGE
DRVOUT
DRVIN
IGBT Gate
GND
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS9598-00
November 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT9598
Ordering Information
Pin Configurations
RT9598
Package Type
QW : WDFN-8L 2x2 (W-Type)
DRVOUT
DRVIN
CHARGE
STAT
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
1
2
3
4
GND
(TOP VIEW)
9
8
7
6
5
SW
VDD
CS
FB
WDFN-8L 2x2
Richtek products are :

RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering processes.
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
DRVOUT
IGBT Driver Output.
2
DRVIN
IGBT Driver Input.
3
CHARGE
Charge Enable Control Input. The charge function is executed when CHARGE
pin is set from Low to High. The chip is in Shutdown mode when CHARGE pin
is set to Low.
4
STAT
Charge Status Open-Drain Output. When target output voltage is reached, this
pin will be pulled low. This pin needs a pull-up resistor.
5
FB
Feedback Voltage Input.
6
CS
Input Current Setting.
7
VDD
Supply Voltage Input.
8
SW
N-MOSFET Switch Node.
GND
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
9 (Exposed Pad)
Function Block Diagram
DRVIN
VDD
Maximum
Off
DRVOUT
SW
Sense
DCM
S
CHARGE
FB
1V
+
-
Enable
SW
FB
R
Q
GND
0.8V
Maximum
On-Time
Protection
STAT
SW
+
-
IPEAK
SW
OVP
CS
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is a registered trademark of Richtek Technology Corporation.
DS9598-00
November 2013
RT9598
Operation
Basic Operation
Maximum Off-Time
The RT9598 is a photo flash charger comprised of several
building blocks. The following paragraphs are described
in detail.
During pre-charge, a 9μs maximum off-time is used to
reduce the charging time.
Maximum On-Time Protection
Enable
If the output voltage is below its target voltage, the
CHARGE pin pulling high enables charging cycle and
pulling low stops charging. When the output voltage
reaches the target voltage, the MOSFET will be turned off
and the STAT pin will be pulled low to indicate that charging
is completed.
If the on-time of the internal MOSFET is over 2ms, the
maximum on-time protection will be triggered to shut down
the charging system.
OVP Protection
The over-voltage protection supervises the abnormal
voltage via the FB and SW pins. If OVP occurs, the internal
MOSFET will turn off immediately.
Peak Current Control
The MOSFET peak current is set by an external resistor
on the CS pin.
DCM
The RT9598 uses DCM operation mechanism to decide
the timing to turn on MOSFET. This block senses
transformer's secondary current through the SW pin. When
the current drops to zero, the energy is delivered to output,
and the MOSFET will turn on for next cycle.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS9598-00
November 2013
IGBT Driver
The DRVOUT is used to trigger flash tube module when
HV capacitor is charged ready. It also equips with false
trigger protection when VDD is low or the STAT pin is not
at low status.
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RT9598
Absolute Maximum Ratings
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(Note 1)
Supply Voltage, VDD ----------------------------------------------------------------------------------------------------Built-in N-Channel Enhancement MOSFET
Drain-Source Voltage ----------------------------------------------------------------------------------------------------CS, CHARGE, DRVIN, DRVOUT, STAT, FB ------------------------------------------------------------------------SW Pulse Current (Pulse Width 1μs) -------------------------------------------------------------------------------SW Continuous Current ------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
WDFN-8L 2x2 -------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
WDFN-8L 2x2, θJA --------------------------------------------------------------------------------------------------------WDFN-8L 2x2, θJC -------------------------------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------------------MM (Machine Model) -----------------------------------------------------------------------------------------------------
Recommended Operating Conditions


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
−0.3V to 6V
−0.3V to 55V
−0.3V to 6V
4A
2A
2.19W
45.5°C/W
11.5°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
(Note 4)
Supply Voltage, VDD ----------------------------------------------------------------------------------------------------Battery Voltage -----------------------------------------------------------------------------------------------------------Drain Source Voltage ----------------------------------------------------------------------------------------------------Junction Temperature Range -------------------------------------------------------------------------------------------Ambient Temperature Range --------------------------------------------------------------------------------------------
2.9V to 5.5V
1.6V to 9V
50V
−40°C to 125°C
−40°C to 85°C
Electrical Characteristics
(VDD = 3.3V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Switch Off Current
IVDD_SW_OFF
VFB = 1.1V
--
1
10
A
Shutdown Current
IOFF
CHARGE pin = 0V
--
0.1
1
A
FB Voltage
VFB
0.985
1
1.015
V
Line Regulation
| VFB |
--
--
10
mV
--
11
19

2.9V < VDD < 5.5V
STAT Open Drain RDS(ON)
Charge Enable High
VCEH
1.3
--
--
V
Charge Enable Low
VCEL
--
--
0.4
V
--
0.3
0.4

Maximum Off-Time During
Pre-Charge
--
7
--
s
Minimum Off-Time
--
400
--
ns
VDD = 3.3V
1
1.5
2
VDD = 5V
1
1.5
2
Built-In N-Channel Enhancement MOSFET
Drain-Source On-Resistance
RDS(ON)
Maximum On-time Protection
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VDD = 3.3V, ID = 10mA
ms
is a registered trademark of Richtek Technology Corporation.
DS9598-00
November 2013
RT9598
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
0.8
1.05
1.4
V
IGBT Driver
DRVIN Trip Point
VDD = 3.3V to 5V
DRVOUT On-Resistance to VDD
VDD = 3.3V
5
10
15

DRVOUT On-Resistance to GND
VDD = 3.3V
10
16
22

VDD = 5V
--
11
20
VDD = 3.3V
--
13.5
20
VDD = 5V
50
110
200
VDD = 3.3V
40
70
120
Propagation Delay (Rising)
TPD_R
Propagation Delay (Falling)
TPD_F
ns
ns
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS9598-00
November 2013
is a registered trademark of Richtek Technology Corporation.
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RT9598
Typical Application Circuit
VOUT
GSD2004S
1:N
VBAT
R1
150k
+
C2
47µF
R2
150k
7
3.3V/5V
C1
1µF
R4
100k
8
5
SW
FB
VDD
R3
1k
DRVIN
2 Strobe
RT9598
4 STAT
3
DRVOUT
CHARGE
6 CS
R5
54k
COUT
100µF/
330V
GND
1
IGBT Gate
9 (Exposed Pad)
RCS
54k
GPIO
(Floating/GND)
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is a registered trademark of Richtek Technology Corporation.
DS9598-00
November 2013
RT9598
Typical Operating Characteristics
Switching
Switching
VSW
(20V/Div)
VSW
(20V/Div)
I PRI
(1A/Div)
I PRI
(1A/Div)
I SEC
(200mA/Div)
I SEC
(200mA/Div)
VDDM = 3.3V, VBAT = 3.7V, VOUT = 100V
VDDM = 3.3V, VBAT = 3.7V, VOUT = 300V
Time (2.5μs/Div)
Time (2.5μs/Div)
Charge Time vs. VBAT
Charging Time
15
CHARGE
(5V/Div)
Charge Time (s)
12
STAT
(5V/Div)
I IN
(500mA/Div)
9
IPK-PRI = 1.4A
6
IPK-PRI = 1.6A
3
VOUT
(200V/Div)
VDDM = 3.3V, VBAT = 3.7V, COUT = 140μF
VDDM = 3.3V, COUT = 140μF, VOUT = 0 to 300V
0
Time (1s/Div)
1.5
3
4.5
6
7.5
9
VBAT (V)
Output Voltage vs. VBAT
310
12
306
Output Voltage (V)
Charge Time (s)
Charge Time vs. VBAT
15
9
IPK-PRI = 1.4A
6
IPK-PRI = 1.6A
3
−40°C
302
25°C
298
80°C
294
VDDM = 5V, COUT = 140μF, VOUT = 0 to 300V
VDDM = 3.3V
0
290
1.5
3
4.5
6
7.5
VBAT (V)
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November 2013
9
1.5
3
4.5
6
7.5
9
VBAT (V)
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RT9598
Application Information
The RT9598 integrates a constant peak current controller
for charging photoflash capacitor and an IGBT driver for
igniting flash tube. The photoflash capacitor charger uses
constant primary peak current and SW falling control to
efficiently charge the photoflash capacitor.
Pulling the CHARGE pin high will initiate the charging
cycle. However, the CHARGE signal must go from low to
high after VDD > 2V for at least 1μs delay time.
VDD
2V
The RT9598 simply adjusts peak primary current by a
resistor RCS connecting to the CS pin as shown in the
Function Block Diagram. RCS determines the peak current
of the primary N-MOSFET according to the following
equation :
40000
IPK_PRI 
(A)
RCS
where IPK-PRI is the primary peak current. Users could
select appropriate RCS according to the battery capability
and required charging time. We recommend RCS should
be greater than 13kΩ.
Transformer
CHARGE
>1µs
Figure 1. Recommend Charge Timing Chart
During MOSFET on-period, the primary current ramps up
linearly according to VBAT and primary inductance. A resistor
connecting from the CS pin to GND determines the primary
peak current.
During the MOSFET off-period, the energy stored in the
Flyback transformer is boosted to the output capacitor.
The secondary current decreases linearly at a rate
determined by the secondary inductance and the output
voltage (neglecting the voltage drop of the diode).
The SW pin monitors the secondary current. When the
secondary current drops to 0A, SW voltage falls, and then
the MOSFET on-period starts again. The charging cycle
repeats itself and charges the output capacitor. The output
voltage is sensed by a voltage divider connecting to the
anode of the rectifying diode. When the output voltage
reaches the desired voltage set by the resistor divider,
the charging block will be disabled and charging will be
stopped.
Then STAT pin will be pulled low to indicate complete
charging.
The voltage sensing path will be cut off when charging is
completed to minimize the output voltage decay. Both
the CHARGE and STAT pins can be easily interfaced to a
microprocessor in a digital system.
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Charge Current Setting
The Flyback transformer should be appropriately designed
to ensure effective and efficient operation.
1. Turns Ratio
The turns ratio of transformer (N) should be high enough
so that the absolute maximum voltage rating for the
internal N-MOSFET Drain to Source voltage is not
exceeded. Choose the minimum turns ratio according to
the following formula :
VOUT
50  VBAT
NMIN 
Where :
VOUT : Target Output Voltage
VBAT : Battery Voltage
2. Primary Inductance
Each switching cycle, energy transferred to the output
capacitor is proportional to the primary inductance for a
constant primary current. The higher the primary
inductance, the higher the charging efficiency. Besides,
to ensure enough off-time for the output voltage sensing,
the primary inductance should be high enough according
to the following formula :
LPRI 
400  10-9  VOUT
N  IPK-PRI
VOUT : Target Output Voltage
N : Transformer turns ratio
IPK-PRI : Primary peak current
is a registered trademark of Richtek Technology Corporation.
DS9598-00
November 2013
RT9598
3. Leakage Inductance
If VOUT = 300V, according the following equation :
The leakage inductance of the transformer results in the
first spike voltage when N-MOSFET turns off. The spike
voltage is proportional to the leakage inductance and
inductor peak current. The spike voltage must not exceed
the dynamic rating of the N-MOSFET Drain to Source
voltage (50V).
R1+R2
R1+R2
) and
 299
R3
R3
It is recommended to set R3 = 1kΩ and R1 = R2 = 150kΩ
4. Transformer Secondary Capacitance
VOUT  VFB  (1 
for reducing parasitic capacitance coupling effect of the
FB pin. R1 and R2 MUST be larger than 0805 package
size for enduring secondary HV. Another sensing method
is to sense the output voltage directly as shown in Figure
3.
Any capacitance on the secondary can severely affect the
efficiency. A small secondary capacitance is multiplied
by N2 when reflected to the primary side, so the equiralent
capacitance will become large.
This capacitance forms a resonant circuit with the primary
leakage inductance of the transformer. Therefore, both the
primary leakage inductance and secondary side
capacitance should be minimized.
Rectifying Diode
VOUT
R1
150k
COUT
R2
150k
FB
R3
1k
Figure 2. Sensing Anode of Diode
The rectifying diode should be with short reverse recovery
time (small parasitic capacitance). Large parasitic
capacitance increases switching loss and lowers charging
VOUT
efficiency.
R1
10M
In addition, the peak reverse voltage and peak current of
the diode should be sufficient.
The peak reverse voltage of the diode can be calculated
as the following equation :
VPK-R  VOUT  (N  VBAT )
The peak current of the diode is equal to the primary peak
current divided by the transformer turn ratio as the following
equation :
I
IPK-SEC  PK-PRI
N
Where : N is the transformer turns ratio.
Output Voltage Setting
The RT9598 senses the output voltage by a voltage divider
connecting to the anode of the rectifying diode during offtime as shown in Figure 2. This eliminates power loss at
voltage sensing circuit when charging is completed. R1
to R2 ratio determines the output voltage as shown in the
typical application circuit. The feedback reference voltage
is 1V.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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November 2013
R2
10M
COUT
FB
C1
10nF
R3
66.5k
Figure 3. Sensing Output Voltage
Over-Voltage Protection (OVP)
The RT9598 provides an Over-Voltage Protection (OVP)
function. In the typical application circuit, if the FB resistor
R1, R2 or R3 is open, the FB voltage will be pulled low or
floating. In this condition, when the CHARGE pin goes
high, the RT9598 begins switching. When the SW voltage
reaches 14V, the OVP function will be triggered.
False Triggering Prevention
The RT9598 includes a mechanism to prevent false
triggering of the DRVOUT pin while the device is still in
charging mode.
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RT9598
With this mechanism, the DRVIN pin is only allowed to
trigger DRVOUT when the CHARGE pin is low.
Maximum Power Dissipation (W)1
2.5
BUF
DRVIN
DRVOUT
CHARGE
Figure 4. Trigger Logic
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
Four- Layer PCB
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 5. Derating Curve of Maximum Power Dissipation
Layout Considerations
PD(MAX) = (TJ(MAX) − TA) / θJA
Where T J(MAX) is the maximum operation junction
temperature, TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
For the best performance of the RT9598, the following
PCB layout guidelines must be strictly followed.

Both of primary and secondary power paths should be
as short as possible.

Place the current setting resistor RCS to the CS pin as
close as possible. The GND side of RCS should be
directly connected to ground plane to avoid noise
coupling.

Keep the switching node area as small as possible to
reduce parasitic capacitance coupling effect.
PD(MAX) = (125°C − 25°C) / (45.5°C/W) = 2.19W for
WDFN-8L 2x2 package

Place the feedback resistors as close as possible to
the FB pin.
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 5 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.

The GND should be connected to a strong ground plane
to reduce switching noise.
For recommended operating conditions specification, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance θJA is layout dependent. For
WDFN-8L 2x2 package, the thermal resistance θJA is
45.5°C/W on the standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by following formula :
Connect the Exposed
Pad to a ground plane.
1
8
7
3
GND
DRVOUT
DRVIN
CHARGE
STAT
VOUT
GND
4
9
5
2
6
SW
VDD
CS
FB
GND
GND
VBAT
GND
Keep away from SW trace
Figure 6. PCB Layout Guide
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is a registered trademark of Richtek Technology Corporation.
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November 2013
RT9598
Outline Dimension
D2
D
L
E
E2
1
e
SEE DETAIL A
b
2
1
2
1
A
A1
A3
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.200
0.300
0.008
0.012
D
1.950
2.050
0.077
0.081
D2
1.000
1.250
0.039
0.049
E
1.950
2.050
0.077
0.081
E2
0.400
0.650
0.016
0.026
e
L
0.500
0.300
0.020
0.400
0.012
0.016
W-Type 8L DFN 2x2 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS9598-00
November 2013
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