24LC41A DATA SHEET (10/23/2003) DOWNLOAD

24LC41A
1K/4K 2.5V Dual Mode, Dual Port I2C™ Serial EEPROM
Package Type
PDIP
VCLK
2
VSS
3
MSDA
4
8
DSDA
7
Vcc
6
MWP
5
MSCL
VCLK
DSCL
DDC Monitor Port
DSDA
EDID Table
1K-Bit
The Microchip Technology Inc. 24LC41A is a dual port
128 x 8 and 512 x 8-bit Electrically Erasable PROM
(EEPROM). This device is designed for use in applications requiring storage and serial transmission of
configuration and control information. Three modes of
operation have been implemented:
Upon power-up, the DDC Monitor Port will be in the
Transmit-only mode, repeatedly sending a serial bit
stream of the entire memory array contents, clocked by
the VCLK pin. A valid high-to-low transition on the
DSCL pin will cause the device to enter the transition
mode, an look for a valid control byte on the I2C bus. If
it detects a valid control byte from the master, it will
switch to Bidirectional mode, with byte selectable read/
write capability of the memory array using DSCL. If no
control byte is received, the device will revert to the
Transmit-only mode after it received 128 consecutive
VCLK Package Type pulses while the DSCL pin is idle.
1
Block Diagram
Description
• Transmit-only mode for the DDC Monitor Port
• Bidirectional mode for the DDC Monitor Port
• Bidirectional, industry-standard 2-wire bus for the
4K Microcontroller Access Port
DSCL
24LC41A
• Single supply with operation down to 2.5V
• Completely implements DDC1/DDC2 interface
for monitor identification, including recovery to
DDC1
• Improved noise immunity
• Separate high speed 2-wire bus for
microcontroller access to 4K-bit Serial EEPROM
• Low-power CMOS technology
• 2 mA active current typical
• 20 µA standby current typical at 5.5V
• Dual 2-wire serial interface bus, I2C™ compatible
• Hardware write-protect for Microcontroller Access
Port
• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 8 bytes (DDC port) or
16 bytes (4K Port)
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• 1,000,000 erase/write cycles
• Data retention > 40 years
• 8-pin PDIP package
• Available for extended temperature ranges
- Commercial (C):
0°C to
+70°C
- Industrial (I):
-40°C to
+85°C
The 4K-bit microcontroller port is completely independent of the DDC port, therefore, it can be accessed
continuously by a microcontroller without interrupting
DDC transmission activity. The 24LC41A is available in
a standard 8-pin PDIP package in both commercial and
industrial temperature ranges.
Microcontroller Access Port
Features
MSDA
4K-Bit
Serial
EEPROM
MSCL
Pin Function Table
Name
DSCL
I2
Function
Serial Clock for DDC Bidirectional mode
(DDC2)
DSDA
Serial Address and Data I/O(DDC Bus)
VCLK
Serial Clock for DDC Transmit-only mode
(DDC1)
MSCL
Serial clock for 4K-bit MCU port
MSDA
Serial Address and Data I/O for 4K-bit MCU port
MWP
Hardware write-protect for Microcontroller
Access Port
VSS
Ground
VCC
+2.5V to +5.5V power supply
C is a trademark of Philips Corporation.
DDC is a trademark of Video Electronics Standards Association.
 2003 Microchip Technology Inc.
DS21176D-page 1
24LC41A
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-65°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
DC CHARACTERISTICS
VCC = +2.5V to 5.5V
Commercial (C): TA = 0°C to +70°C
Industrial (I):
TA =-40°C to +85°C
Parameter
Symbol
Min
Max
Units
DSCL, DSDA, MSCL & MSDA pins:
High-level input voltage
Low-level input voltage
VIH
VIL
.7 VCC
—
—
.3 VCC
V
V
Input levels on VCLK pin:
High-level input voltage
Low-level input voltage
VIH
VIL
2.0
—
.8
.2 VCC
V
V
VCC ≥ 2.7V (Note)
VCC < 2.7V (Note)
Hysteresis of Schmitt Trigger inputs
VHYS
.05 VCC
—
V
(Note)
Low-level output voltage
VOL1
—
.4
V
IOL = 3 mA, VCC = 2.5V (Note)
Low-level output voltage
VOL2
—
.6
V
IOL = 6 mA, VCC = 2.5V
Input leakage current
ILI
—
±1
µA
VIN =.1V to VCC
Output leakage current
ILO
—
±1
µA
VOUT =.1V to VCC
Pin capacitance (all inputs/outputs)
CIN, COUT
—
10
pF
VCC = 5.0V (Note),
TA = 25°C, FCLK = 1 MHz
Operating current
ICC Write
ICC Read
—
—
3
1
mA
mA
VCC = 5.5V, DSCL or MSCL = 400 kHz
ICCS
—
—
60
200
µA
µA
VCC = 3.0V, DSDA or MSDA = DSCL
or MSCL = VCC
VCC = 5.5V, DSDA or MSDA = DSCL
or MSCL = VCCVCLK = VSS
Standby current
Note:
Conditions
This parameter is periodically sampled and not 100% tested.
DS21176D-page 2
 2003 Microchip Technology Inc.
24LC41A
TABLE 1-2: AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER ACCESS PORTS)
DDC Monitor Port (Bidirectional mode) and Microcontroller Access Port
Standard Mode
Parameter
Symbol
Clock frequency (DSCL and
FCLK
MSCL)
Clock high time (DSCL and
THIGH
MSCL)
Clock low time (DSCL and
TLOW
MSCL)
DSCL, DSDA, MSCL &
TR
MSDA rise time
DSCL, DSDA, MSCL &
TF
MSDA fall time
Start condition hold time
THD:STA
Vcc = 4.5 - 5.5V
Fast Mode
Units
Remarks
Min
Max
Min
Max
—
100
—
400
kHz
4000
—
600
—
ns
4700
—
1300
—
ns
—
1000
—
300
ns
(Note 1)
—
300
—
300
ns
(Note 1)
4000
—
600
—
ns
After this period the first clock
pulse is generated
Only relevant for repeated
Start condition
(Note 2)
Start condition setup time
TSU:STA
4700
—
600
—
ns
Data input hold time
Data input setup time
Stop condition setup time
Output valid from clock
Bus free time
THD:DAT
TSU:DAT
TSU:STO
TAA
TBUF
0
250
4000
—
4700
—
—
—
3500
—
0
100
600
—
1300
—
—
—
900
—
ns
ns
ns
ns
ns
TOF
—
250
250
ns
TSP
—
50
20 + .1
CB
—
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1), CB ≤ 100 pF
50
ns
(Note 3)
TWR
—
—
1M
10
—
—
1M
10
—
Output fall time from VIH
min to VIL max
Input filter spike suppression (DSCL, DSDA, MSCL
& MSDA pins)
Write cycle time
Endurance
ms
Byte or Page mode
cycles 25°C, Vcc = 5.0V, Block mode
(Note 4)
DDC Monitor Port Transmit-only mode Parameters
Output valid from VCLK
TVAA
—
2000
—
1000
ns
4000
—
600
—
ns
VCLK high time
TVHIGH
VCLK low time
TVLOW
4700
—
1300
—
ns
VCLK setup time
TVHST
0
—
0
—
ns
4000
—
600
—
ns
VCLK hold time
TSPVL
Mode transition time
TVHZ
—
500
—
500
ns
Transmit-only power-up
TVPU
0
—
0
—
ns
time
—
100
—
100
ns
Input filter spike
TSPV
suppression (VCLK pin)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of DSCL or MSCL to avoid unintended generation of Start or Stop
conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained at www.microchip.com.
 2003 Microchip Technology Inc.
DS21176D-page 3
24LC41A
2.0
FUNCTIONAL DESCRIPTION
2.1
DDC Monitor Port
This device requires that it be initialized prior to valid
data being sent in the Transmit-only mode (see
Section 2.1.2 “Initialization Procedure”). In this
mode, data is transmitted on the DSDA pin in 8-bit
bytes, each followed by a ninth, null bit (see Figure 21). The clock source for the Transmit-only mode is
provided on the VCLK pin, and a data bit is output on
the rising edge on this pin. The eight bits in each byte
are transmitted by Most Significant bit first. Each byte
within the memory array will be output in sequence.
When the last byte in the memory array is transmitted, the output will wrap around to the first location
and continue. The Bidirectional mode Clock (DSCL)
pin must be held high for the device to remain in the
Transmit-only mode.
The DDC Monitor Port operates in two modes, the
Transmit-only mode and the Bidirectional mode. There
is a separate 2-wire protocol to support each mode,
each having a separate clock input and sharing a
common data line (DSDA). The device enters the
Transmit-only mode upon power-up. In this mode, the
device transmits data bits on the DSDA pin in response
to a clock signal on the VCLK pin. The device will
remain in this mode until a valid high-to-low transition is
placed on the DSCL input. When a valid transition on
DSCL is recognized, the device will switch into the
Bidirectional mode and look for its control byte to be
sent by the master. If it detects its control byte, it will
stay in the Bidirectional mode. Otherwise, it will revert
to the Transmit-only mode after it sees 128 VCLK
pulses.
2.1.1
2.1.2
TRANSMIT-ONLY MODE
The device will power-up in the Transmit-only mode
at address 00H. This mode supports a unidirectional
2-wire protocol for transmission of the contents of the
memory array.
FIGURE 2-1:
INITIALIZATION PROCEDURE
After VCC has stabilized, the device will be in the
Transmit-only mode. Nine clock cycles on the VCLK pin
must be given to the device for it to perform internal
sychronization. During this period, the DSDA pin will be
in a high-impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the Most Significant bit of a byte.
The device will power-up at an indeterminate byte
address (Figure 2-2).
TRANSMIT-ONLY MODE
SCL
TVAA
TVAA
SDA
Null Bit
Bit 1 (LSB)
Bit 1 (MSB)
Bit 7
VCLK
TVHIGH
FIGURE 2-2:
TVLOW
DEVICE INITIALIZATION
VCC
SCL
SDA
TVAA
High-impedance for 9 clock cycles
TVAA
Bit 8
Bit 7
TVPU
VCLK
DS21176D-page 4
1
2
8
9
10
11
 2003 Microchip Technology Inc.
24LC41A
2.1.3
BIDIRECTIONAL MODE
device that sends data on the bus is defined to be the
transmitter, and a device that receives data from the
bus is defined to be the receiver. The bus must be
controlled by a master device that generates the
Bidirectional mode Clock (DSCL), controls access to
the bus and generates the Start and Stop conditions,
while the monitor port acts as the slave. Both master
and slave can operate as transmitter or receiver, but
the master device determines which mode is activated.
In the Bidirectional mode, the monitor port only
responds to commands for device 1010 000X.
Before the 24LC41A can be switched into the Bidirectional mode (Figure 2-4), it must enter the transition
mode, which is done by applying a valid high-to-low
transition on the Bidirectional mode Clock (DSCL). As
soon it enters the transition mode, it looks for a control
byte 1010 000X on the I2C™ bus, and starts to count
pulses on VCLK. Any high-to-low transition on the
DSCL line will reset the count. If it sees a pulse count
of 128 on VCLK while the DSCL line is idle, it will revert
back to the Transmit-only mode, and transmit its
contents starting with the Most Significant bit in
address 00h. However, if it detects the control byte on
the I2C bus, (Figure 2-3) it will switch to the in the
Bidirectional mode. Once the device has made the
transition to the Bidirectional mode, the only way to
switch the device back to the Transmit-only mode is to
remove power from the device. The mode transition
process is shown in detail in Figure 2-4.
2.2
The Microcontroller Access Port supports a bidirectional 2-wire bus and data transmission protocol. A
device that sends data onto the bus is defined as
transmitter, and a device receiving data as receiver.
The bus has to be controlled by a master device which
generates the serial clock (MSCL), controls the bus
access, and generates the Start and Stop conditions,
while the Microcontroller Access Port works as slave.
Both master and slave can operate as transmitter or
receiver, but the master device determines which mode
is activated.
Once the device has switched into the Bidirectional
mode, the VCLK input is disregarded, with the exception that a logic high level is required to enable write
capability. This mode supports a two-wire bidirectional
data transmission protocol (I2C). In this protocol, a
FIGURE 2-3:
Microcontroller Access Port
SUCCESSFUL MODE TRANSITION TO BIDIRECTIONAL MODE
Transmit-only
mode
Transition mode with possibility to return to Transmit-only mode
Bidirectional
permanently
MODE
SCL
SDA
S
VCLK count =
VCLK
1
2
n
1
0
1
0
0
0
0
0
ACK
0
n < 128
FIGURE 2-4:
MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE
MODE Transmit-only
Recovery to Transmit-only mode
Bidirectional
TVHZ
SCL
(MSB of data in 00h)
Bit8
SDA
VCLK count =
VCLK
 2003 Microchip Technology Inc.
1
2
3
4
127 128
DS21176D-page 5
24LC41A
FIGURE 2-5:
DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA
The 24LC41A was designed to comply to the
portion of flowchart inside dash box.
Display Power-on
or
DDC Circuit Powered
from +5 volts
Communication
is idle
Is Vsync
present?
No
Yes
High-to-low
transition on
SCL?
Send EDID continuously
using Vsync as clock
No
Yes
High-to-low
transition on
SCL?
No
Yes
Stop sending EDID.
Switch to DDC2 mode.
Display has
optional
transition state
?
DDC2 communication
idle. Display waiting for
address byte.
No
DDC2B
address
received?
Yes
Set Vsync counter = 0
or start timer
Yes
Receive DDC2B
command
No
Reset counter or timer
Respond to DDC2B
command
Change on
SCL, SDA or
VCLK lines?
No
Yes
No
Is display
Access.busTM
capable?
High - low
transition on SCL
?
Yes
Yes
Reset Vsync counter = 0
Valid
DDC2 address
received?
No
Valid Access.bus
address?
No
Yes
Yes
No
No
VCLK
cycle?
See Access.bus
specification to determine
correct procedure.
Yes
Increment VCLK counter
(if appropriate)
No
Counter=128 or
timer expired?
Yes
Switch back to DDC1
mode.
Note 1: The base flowchart is copyright  1993, 1994, 1995 Video Electronic Standard Association (VESA) from
VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.
2: The dash box and text “The 24LC41A and ... inside dash box.” are added by Microchip Technology Inc.
3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LC41A.
DS21176D-page 6
 2003 Microchip Technology Inc.
24LC41A
3.0
BIDIRECTIONAL BUS
CHARACTERISTICS
Characteristics for the Bidirectional bus are identical for
both the DDC Monitor Port (in Bidirectional mode) and
the Microcontroller Access Port The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain high.
3.2
Start Data Transfer (B)
A high-to-low transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Start condition. All commands must be preceded by a
Start condition.
3.3
Stop Data Transfer (C)
A low-to-high transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Stop condition. All operations must be ended with a
Stop condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last eight will
be stored when doing a write operation. When an overwrite does occur, it will replace data in a first in first out
fashion.
 2003 Microchip Technology Inc.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Note:
The microcontroller access port and the
DDC Monitor Port (in Bidirectional mode)
will not generate any Acknowledge bits if
an internal programming cycle is in
progress.
The device that acknowledges has to pull down the
DSDA or MSDA line during the Acknowledge clock
pulse in such a way that the DSDA or MSDA line is
stable low during the high period of the acknowledge
related clock pulse. Of course, setup and hold times
must be taken into account. A master must signal an
end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of
the slave. In this case, the slave must leave the data
line high to enable the master to generate the Stop
condition.
3.6
Device Addressing
A control byte is the first byte received following the
Start condition from the master device. The first part of
the control byte consists of a 4-bit control code. This
control code is set as 1010 for both read and write
operations and is the same for both the DDC Monitor
Port and Microcontroller Access Port. The next three
bits of the control byte are block select bits (B1, B2, and
B0). All three of these bits are zero for the DDC Monitor
Port. The B2 and B1 bits are don’t care bits for the
Microcontroller Access Port, and the B0 bit is used by
the Microcontroller Access Port to select which of the
two 256 word blocks of memory are to be accessed
(see Figure 3-4). The B0 bit is effectively the Most
Significant bit of the word address. The last bit of the
control byte defines the operation to be performed.
When set to one, a read operation is selected; when set
to zero, a write operation is selected. Following the Start
condition, the device monitors the DSDA or MSDA bus
checking the device type identifier being transmitted,
upon a 1010 code the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of
the R/W bit, the device will select a read or a write
operation. The DDC Monitor Port and Microcontroller
Access Port can be accessed simultaneously because
they are completely independent of one another.
Operation
Control Code
Block Select
R/W
Read
1010
B2B1B0
1
Write
1010
B2B1B0
0
DS21176D-page 7
24LC41A
FIGURE 3-1:
DSCL
or
MSCL
(A)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
(D)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
(C)
(A)
DSDA
or
MSDA
FIGURE 3-2:
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
BUS TIMING START/STOP
VHYS
MSCL
or
MSCL
IN
THD:STA
TSU:STA
TSU:STO
DSDA
or
MSDA
IN
START
FIGURE 3-3:
STOP
BUS TIMING DATA
TR
TF
THIGH
TLOW
DSCL
or
MSCL TSU:STA
IN
THD:DAT
DSDA
OR
MSDA
IN
TSU:DAT
TSU:STO
THD:STA
TSP
TAA
THD:STA
TAA
TBUF
DSDA
OR
MSDA
OUT
FIGURE 3-4:
CONTROL BYTE ALLOCATION
READ/WRITE
START
R/W
SLAVE ADDRESS
1
0
1
0
B2
B1
A
B0
B0, B1, and B2 are zeros for DDC Monitor Port. B1 and B2 are don’t care bits for the Microcontroller Access Port,
and B0 is used to select which of the two 256 word blocks of memory are to be accessed.
DS21176D-page 8
 2003 Microchip Technology Inc.
24LC41A
4.0
WRITE OPERATION
Write operations are identical for the DDC Monitor Port
(when in Bidirectional mode) and the Microcontroller
Access Port, with the exception of the VCLK and MWP
pins noted in the next sections. Data can be written
using either a Byte Write or Page Write command. Write
commands for the DDC Monitor Port and the
Microcontroller
Access
Port
are
completely
independent of one another.
4.1
Byte Write
Following the Start signal from the master, the slave
address (4-bits), the chip select bits (3-bits) and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be
written into the address pointer of the port. After
receiving another Acknowledge signal from the port,
the master device will transmit the data word to be
written into the addressed memory location. The port
acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle, and
during this time, the port will not generate Acknowledge
signals (see Figure 4-1).
For the DDC Monitor Port it is required that VCLK be
held at a logic high level in order to program the device.
This applies to byte write and page write operation.
Note that VCLK can go low while the device is in its
self-timed program operation and not affect programming. The MWP pin must be held high for the duration
of the write protection.
 2003 Microchip Technology Inc.
4.2
Page Write
The write control byte, word address, and the first data
byte are transmitted to the port in the same way as in a
byte write. But, instead of generating a Stop condition,
the master transmits up to eight data bytes to the DDC
Monitor Port or 16 bytes to the Microcontroller Access
Port, which are temporarily stored in the on-chip page
buffer and will be written into the memory after the
master has transmitted a Stop condition. After the
receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order 5-bits of the word address remains
constant. If the master should transmit more than eight
words to the DDC Monitor Port or 16 words to the
Microcontroller Access Port prior to generating the Stop
condition, the address counter will roll over and the
previously received data will be overwritten. As with the
byte write operation, once the Stop condition is received
an internal write cycle will begin (see Figure 4-2).
For the DDC Monitor Port, it is required that VCLK be
held at a logic high level in order to program the device.
This applies to byte write and page write operation.
Note that VCLK can go low while the device is in its
self-timed program operation and not affect programming. For the DDC Monitor Port, the MWP pin must be
held high for the duration of the write cycle.
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
Start at addresses that are integer
multiples of the page buffer size (or ‘page
size’) and end at addresses that are
integer multiples of [page size - 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
DS21176D-page 9
24LC41A
FIGURE 4-1:
BUS ACTIVITY
MASTER
SDA or
MSDA LINE
BYTE WRITE
S
T
A
R
T
CONTROL
BYTE
WORD
ADDRESS
S
T
O
P
DATA
S
P
A
C
K
BUS ACTIVITY
A
C
K
A
C
K
VCLK
FIGURE 4-2:
PAGE WRITE
BUS ACTIVITY S
T
MASTER
A
R
T
DSDA or
MSDA LINE
BUS ACTIVITY
CONTROL
BYTE
WORD
ADDRESS
DATA n
S
T
O
P
DATAn + 7
DATAn + 1
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
VCLK
FIGURE 4-3:
VCLK WRITE ENABLE TIMING
SCL
THD:STA
TSU:STO
SDA
IN
VCLK
TVHST
DS21176D-page 10
TSPVL
 2003 Microchip Technology Inc.
24LC41A
5.0
ACKNOWLEDGE POLLING
Acknowledge polling can be done for both the DDC
Monitor Port (when in Bidirectional mode) and the
Microcontroller Access Port.
Since the port will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize but
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W=0). If the device is still busy
with the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next Read or
Write command. See Figure 5-1 for the flow diagram.
FIGURE 5-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
NO
YES
Next
Operation
 2003 Microchip Technology Inc.
DS21176D-page 11
24LC41A
6.0
WRITE PROTECTION
6.1
DDC Monitor Port
When using the DDC Monitor Port in the Bidirectional
mode, the VCLK pin operates as the write-protect
control pin. Setting VCLK high allows normal write
operations, while setting VCLK low prevents writing to
any location in the array. Connecting the VCLK pin to
VSS would allow the monitor port to operate as a serial
ROM, although this configuration would prevent using
the device in the Transmit-only mode.
7.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read. These operations are identical for
both the DDC Monitor Port (in Bidirectional mode) and
the Microcontroller Access Port and are completely
independent of one another.
7.1
Current Address Read
The port contains an address counter that maintains
the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the slave address
with R/W bit set to one, the port issues an acknowledge
and transmits the 8-bit data word. The master will not
acknowledge the transfer but does generate a Stop
condition and the port discontinues transmission
(Figure 7-1).
7.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
port as part of a write operation. After the word address
is sent, the master generates a Start condition following
the acknowledge. This terminates the write operation,
but not before the internal address pointer is set. The
master then issues the control byte again, but with
the R/W bit set to a one. The port then issues an
acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer but does
generate a Stop condition and the port discontinues
transmission (see Figure 7-2).
7.3
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the port transmits the
first data byte, and the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the port to transmit the next sequentially
addressed 8-bit word (see Figure 7-3).
To provide sequential reads, the port contains an
internal address pointer, which is incremented by one
at the completion of each operation. This address
pointer allows the entire memory contents to be serially
read during one operation.
DS21176D-page 12
 2003 Microchip Technology Inc.
24LC41A
7.4
Noise Protection
Both the DDC Monitor Port and Microcontroller Access
Port employ a VCC threshold detector circuit which
disables the internal erase/write logic, if the VCC is
below 1.5 volts at nominal conditions.
FIGURE 7-1:
The VCLK, DSCL, MSCL, DSDA, and MSDA inputs
have Schmitt Trigger and filter circuits which suppress
noise spikes to assure proper device operation even on
a noisy bus.
CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
S
T
A
R
T
DSDA or
MSDA LINE
S
CONTROL
BYTE
S
T
O
P
DATA n
P
A
C
K
BUS ACTIVITY
N
O
A
C
K
FIGURE 7-2:
RANDOM READ
S
T
CONTROL
BYTE
BUS ACTIVITY A
MASTER
R
S
T
A
R
T
WORD
ADDRESS
T
MSDA LINE
S
CONTROL
BYTE
S
T
O
P
DATA n
P
S
A
C
K
BUS ACTIVITY
A
C
K
A
C
K
N
O
A
C
K
FIGURE 7-3:
BUS ACTIVITY
MASTER
SEQUENTIAL READ
CONTROL
BYTE
DATA n + 1
DATA n
S
T
O
P
DATA n + 2
DSDA or
MSDA LINE
BUS ACTIVITY
P
A
C
K
A
C
K
A
C
K
A
C
K
DATA n + X
N
O
A
C
K
 2003 Microchip Technology Inc.
DS21176D-page 13
24LC41A
8.0
PIN DESCRIPTIONS
8.4
8.1
DSDA
This pin is used to write-protect the 4K memory array
for the Microcontroller Access Port.
This pin is used to transfer addresses and data into and
out of the DDC Monitor Port, when the device is in the
Bidirectional mode. In the Transmit-only mode, which
only allows data to be read from the device, data is also
transferred on the DSDA pin. This pin is an open drain
terminal, therefore the DSDA bus requires a pull-up
resistor to VCC (typical 10KΩ for 100 kHz, 2KΩ for 400
kHz).
For normal data transfer in the Bidirectional mode,
DSDA is allowed to change only during DSCL or MSDA
low. Changes during DSCL high are reserved for
indicating the Start and Stop conditions.
8.2
DSCL
This pin is the clock input for the DDC Monitor Port
while in the Bidirectional mode, and is used to synchronize data transfer to and from the device. It is also used
as the signaling input to switch the device from the
Transmit-only mode to the Bidirectional mode. It must
remain high for the chip to continue operation in the
Transmit-only mode.
8.3
VCLK
MWP
This pin must be connected to either VSS or VCC.
If tied to Vss, normal memory operation is enabled
(read/write the entire memory).
If tied to VCC, write operations are inhibited. The entire
memory will be write-protected. Read operations are
not affected.
8.5
MSCL
This pin is the clock input for the Microcontroller Access
Port, and is used to synchronize data transfer to and
from the device.
8.6
MSDA
This pin is used to transfer addresses and data into and
out of the Microcontroller Access Port. This pin is an
open drain terminal, therefore the MSDA bus requires
a pull-up resistor to VCC (typical 10KΩ for 100 kHz,
2KΩ for 400 kHz).
MSDA is allowed to change only during MSCL low.
Changes during MSCL high are reserved for indicating
the Start and Stop conditions.
This pin is the clock input for the DDC Monitor Port
while in the Transmit-only mode. In the Transmit-only
mode, each bit is clocked out on the rising edge of this
signal. In the Bidirectional mode, a high logic level is
required on this pin to enable write capability.
DS21176D-page 14
 2003 Microchip Technology Inc.
24LC41A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
XXX
Device
Temperature
Range
Package
Pattern
Device
24LC41A Dual Mode, Dual Port CMOS Serial EEPROM
Temperature Range
Blank
I
=
0°C to
= -40°C to
Package
P
=
+70°C
+85°C
Plastic DIP (300 mil), 8-lead
 2003 Microchip Technology Inc.
DS21176D-page 15
24LC41A
NOTES:
DS21176D-page 16
 2003 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
 2003 Microchip Technology Inc.
DS21176D-page 17
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
Korea
Corporate Office
Australia
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
Atlanta
Unit 915
Bei Hai Wan Tai Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100
Fax: 86-10-85282104
3780 Mansell Road, Suite 130
Alpharetta, GA 30022
Tel: 770-640-0034
Fax: 770-640-0307
Boston
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848
Fax: 978-692-3821
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
2767 S. Albright Road
Kokomo, IN 46902
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
China - Beijing
China - Chengdu
Rm. 2401-2402, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: 86-28-86766200
Fax: 86-28-86766599
China - Fuzhou
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
Tel: 86-591-7503506
Fax: 86-591-7503521
China - Hong Kong SAR
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Shanghai
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700
Fax: 86-21-6275-5060
China - Shenzhen
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888
Fax: 949-263-1338
Rm. 1812, 18/F, Building A, United Plaza
No. 5022 Binhe Road, Futian District
Shenzhen 518033, China
Tel: 86-755-82901380
Fax: 86-755-8295-1393
Phoenix
China - Shunde
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966
Fax: 480-792-4338
Room 401, Hongjian Building
No. 2 Fengxiangnan Road, Ronggui Town
Shunde City, Guangdong 528303, China
Tel: 86-765-8395507 Fax: 86-765-8395571
San Jose
China - Qingdao
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950
Fax: 408-436-7955
Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
Qingdao 266071, China
Tel: 86-532-5027355 Fax: 86-532-5027205
Toronto
India
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699
Fax: 905-673-6509
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
DS21176D-page 18
Singapore
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Kaohsiung Branch
30F - 1 No. 8
Min Chuan 2nd Road
Kaohsiung 806, Taiwan
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan
Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Austria
Durisolstrasse 2
A-4600 Wels
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45-4420-9895 Fax: 45-4420-9910
France
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany
Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy
Via Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
P. A. De Biesbosch 14
NL-5152 SC Drunen, Netherlands
Tel: 31-416-690399
Fax: 31-416-690340
United Kingdom
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44-118-921-5869
Fax: 44-118-921-5820
07/28/03
 2003 Microchip Technology Inc.
Similar pages