93AA46A DATA SHEET (06/20/2013) DOWNLOAD

93AA46A/B/C, 93LC46A/B/C,
93C46A/B/C
1K Microwire Compatible Serial EEPROM
Device Selection Table
VCC Range
ORG Pin
Word Size
Temp Ranges
93AA46A
1.8-5.5
No
8-bit
I
P, SN, ST, MS, OT, MC, MN
93AA46B
1.8-5-5
No
16-bit
I
P, SN, ST, MS, OT, MC, MN
93LC46A
2.5-5.5
No
8-bit
I, E
P, SN, ST, MS, OT, MC, MN
93LC46B
2.5-5.5
No
16-bit
I, E
P, SN, ST, MS, OT, MC, MN
93C46A
4.5-5.5
No
8-bit
I, E
P, SN, ST, MS, OT, MC, MN
P, SN, ST, MS, OT, MC, MN
Part Number
Packages
93C46B
4.5-5.5
No
16-bit
I, E
93AA46C
1.8-5.5
Yes
8- or 16-bit
I
P, SN, ST, MS, MC, MN
93LC46C
2.5-5.5
Yes
8- or 16-bit
I, E
P, SN, ST, MS, MC, MN
93C46C
4.5-5.5
Yes
8- or 16-bit
I, E
P, SN, ST, MS, MC, MN
Pin Function Table
Features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low-Power CMOS Technology
ORG Pin to Select Word Size for ‘46C’ Version
128 x 8-bit Organization ‘A’ Devices (no ORG)
64 x 16-bit Organization ‘B’ Devices (no ORG)
Self-Timed Erase/Write Cycles (including
Auto-Erase)
Automatic Erase All (ERAL) Before Write All
(WRAL)
Power-On/Off Data Protection Circuitry
Industry Standard 3-Wire Serial I/O
Device Status Signal (Ready/Busy)
Sequential Read Function
1,000,000 Erase/Write Cycles
Data Retention > 200 Years
RoHS Compliant
Temperature Ranges Supported:
- Industrial (I)
-40°C to +85°C
- Automotive (E) -40°C to +125°C
 2002-2013 Microchip Technology Inc.
Name
Function
CS
Chip Select
CLK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
VSS
Ground
NC
No internal connection
ORG
Memory Configuration
VCC
Power Supply
Description:
The Microchip Technology Inc. 93XX46A/B/C devices
are 1Kbit low-voltage serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93AA46C, 93LC46C or 93C46C are dependent
upon external logic levels driving the ORG pin to set
word size. For dedicated 8-bit communication, the
93AA46A, 93LC46A or 93C46A devices are available,
while the 93AA46B, 93LC46B and 93C46B devices
provide dedicated 16-bit communication. Advanced
CMOS technology makes these devices ideal for lowpower, nonvolatile memory applications. The entire
93XX Series is available in standard packages including 8-lead PDIP and SOIC, and advanced packaging
including 8-lead MSOP, 6-lead SOT-23, 8-lead
2x3 DFN/TDFN and 8-lead TSSOP. All packages are
Pb-free (Matte Tin) finish.
DS20001749K-page 1
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
Package Types (not to scale)
ROTATED SOIC
(ex: 93LC46BX)
NC
VCC
CS
CLK
1
2
3
4
8 ORG*
7 VSS
6 DO
5 DI
PDIP/SOIC
(P, SN)
CS
CLK
DI
DO
TSSOP/MSOP
(ST, MS)
CS
CLK
DI
DO
1
2
3
4
1
2
3
4
8
7
6
5
VCC
NC
ORG*
VSS
SOT-23
(OT)
8
7
6
5
VCC
NC
ORG*
VSS
DO
1
6
VCC
VSS
2
5
CS
DI
3
4
CLK
DFN/TDFN
(MC, MN)
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG*
VSS
*ORG pin is NC on A/B devices
DS20001749K-page 2
 2002-2013 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins  4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
Param.
No.
Symbol
Parameter
Industrial (I):
TA = -40°C to +85°C, VCC = +1.8V TO +5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V TO +5.5V
Min.
Typ
Max.
Units
Conditions
D1
VIH1
VIH2
High-level input voltage
2.0
0.7 VCC
—
—
VCC +1
VCC +1
V
V
VCC 2.7V
VCC 2.7V
D2
VIL1
VIL2
Low-level input voltage
-0.3
-0.3
—
—
0.8
0.2 VCC
V
V
VCC 2.7V
VCC 2.7V
D3
VOL1
VOL2
Low-level output voltage
—
—
—
—
0.4
0.2
V
V
IOL = 2.1 mA, VCC = 4.5V
IOL = 100 A, VCC = 2.5V
D4
VOH1
VOH2
High-level output voltage
2.4
VCC - 0.2
—
—
—
—
V
V
IOH = -400 A, VCC = 4.5V
IOH = -100 A, VCC = 2.5V
D5
ILI
Input leakage current
—
—
±1
A
VIN = VSS or VCC
D6
ILO
Output leakage current
—
—
±1
A
VOUT = VSS or VCC
D7
CIN,
COUT
Pin capacitance
(all inputs/outputs)
—
—
7
pF
VIN/VOUT = 0V (Note 1)
TA = 25°C, FCLK = 1 MHz
D8
ICC
write
Write current
—
—
—
500
2
—
mA
A
FCLK = 3 MHz, VCC = 5.5V
FCLK = 2 MHz, VCC = 2.5V
D9
ICC read Read current
—
—
—
—
—
100
1
500
—
mA
A
A
FCLK = 3 MHz, VCC = 5.5V
FCLK = 2 MHz, VCC = 3.0V
FCLK = 2 MHz, VCC = 2.5V
D10
ICCS
Standby current
—
—
—
—
1
5
A
A
I-Temp
E-Temp
CLK = CS = 0V
ORG = DI = VSS or VCC
(Note 2) (Note 3)
D11
VPOR
VCC voltage detect
—
—
1.5
3.8
—
—
V
V
(Note 1)
93AA46A/B/C, 93LC46A/B/C
93C46A/B/C
Note 1: This parameter is periodically sampled and not 100% tested.
2: ORG pin not available on ‘A’ or ‘B’ versions.
3: Ready/Busy status must be cleared from DO; see Section 3.4 “Data Out (DO)”.
 2002-2013 Microchip Technology Inc.
DS20001749K-page 3
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
TABLE 1-2:
AC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
Param.
No.
Symbol
Parameter
Industrial (I):
TA = -40°C to +85°C, VCC = +1.8V TO +5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V TO +5.5V
Min.
Max.
Units
Conditions
A1
FCLK
Clock frequency
—
3
2
1
MHz
MHz
MHz
4.5VVCC  5.5V, 93XX46C only
2.5V VCC  5.5V
1.8V VCC 2.5V
A2
TCKH
Clock high time
200
250
450
—
ns
ns
ns
4.5VVCC  5.5V, 93XX46C only
2.5V VCC  5.5V
1.8V VCC 2.5V
A3
TCKL
Clock low time
100
200
450
—
ns
ns
ns
4.5VVCC  5.5V, 93XX46C only
2.5V VCC  5.5V
1.8V VCC 2.5V
A4
TCSS
Chip Select setup time
50
100
250
—
ns
ns
ns
4.5VVCC  5.5V
2.5V VCC  4.5V
1.8V VCC 2.5V
A5
TCSH
Chip Select hold time
0
—
ns
1.8V VCC 5.5V
A6
TCSL
Chip Select low time
250
—
ns
1.8V VCC 5.5V
A7
TDIS
Data input setup time
50
100
250
—
ns
4.5VVCC  5.5V, 93XX46C only
2.5V VCC  5.5V
1.8V VCC 2.5V
A8
TDIH
Data input hold time
50
100
250
—
ns
4.5VVCC  5.5V, 93XX46C only
2.5V VCC  5.5V
1.8V VCC 2.5V
A9
TPD
Data output delay time
—
—
—
200
250
400
ns
4.5VVCC  5.5V, CL = 100 pF
2.5V VCC  4.5V, CL = 100 pF
1.8V VCC 2.5V, CL = 100 pF
A10
TCZ
Data output disable time
—
—
100
200
ns
4.5VVCC 5.5V, (Note 1)
1.8VVCC  4.5V, (Note 1)
A11
TSV
Status valid time
—
200
300
500
ns
4.5VVCC  5.5V, CL = 100 pF
2.5V VCC  4.5V, CL = 100 pF
1.8V VCC 2.5V, CL = 100 pF
A12
TWC
Program cycle time
—
6
ms
Erase/Write mode (AA and LC
versions)
A13
TWC
—
2
ms
Erase/Write mode (93C versions)
A14
TEC
—
6
ms
ERAL mode, 4.5V  VCC  5.5V
A15
TWL
—
15
ms
WRAL mode, 4.5V  VCC  5.5V
A16
—
1M
—
Endurance
cycles 25°C, VCC = 5.0V, (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This application is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which may be obtained from Microchip’s web
site at www.microchip.com.
DS20001749K-page 4
 2002-2013 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
FIGURE 1-1:
CS
SYNCHRONOUS DATA TIMING
VIH
TCSS
VIL
TCKH
TCKL
TCSH
VIH
CLK
VIL
TDIS
TDIH
VIH
DI
VIL
DO
(Read)
DO
(Program)
Note:
TPD
TPD
VOH
TCZ
TCZ
VOL
TSV
VOH
Status Valid
VOL
TSV is relative to CS.
TABLE 1-3: INSTRUCTION SET FOR X16 ORGANIZATION (93XX46B OR 93XX46C WITH ORG = 1)
Instruction
SB
Opcode
1
11
A5
A4
A3
A2
A1
ERAL
1
00
1
0
X
X
EWDS
1
00
0
0
X
X
EWEN
1
00
1
1
X
X
READ
1
10
A5
A4
A3
A2
WRITE
1
01
A5
A4
A3
A2
WRAL
1
00
0
1
X
X
ERASE
Address
Data In
Data Out
Req. CLK Cycles
A0
—
(RDY/BSY)
9
X
X
—
(RDY/BSY)
9
X
X
—
High-Z
9
X
X
—
High-Z
9
A1
A0
—
D15 - D0
25
A1
A0
D15 - D0
(RDY/BSY)
25
X
X
D15 - D0
(RDY/BSY)
25
TABLE 1-4: INSTRUCTION SET FOR X8 ORGANIZATION (93XX46A OR 93XX46C WITH ORG = 0)
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
1
11
A6 A5 A4 A3 A2 A1 A0
—
(RDY/BSY)
10
ERAL
1
00
1
0
X
X
X
X
X
—
(RDY/BSY)
10
EWDS
1
00
0
0
X
X
X
X
X
—
High-Z
10
EWEN
1
00
1
1
X
X
X
X
X
—
High-Z
10
READ
1
10
A6 A5 A4 A3 A2 A1 A0
—
D7 - D0
18
WRITE
1
01
A6 A5 A4 A3 A2 A1 A0
D7 - D0
(RDY/BSY)
18
WRAL
1
00
D7 - D0
(RDY/BSY)
18
ERASE
 2002-2013 Microchip Technology Inc.
0
1
X
X
X
X
X
DS20001749K-page 5
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.0
FUNCTIONAL DESCRIPTION
When the ORG pin (93XX46C) is connected to VCC,
the (x16) organization is selected. When it is connected
to ground, the (x8) organization is selected. Instructions, addresses and write data are clocked into the DI
pin on the rising edge of the clock (CLK). The DO pin is
normally held in a High-Z state except when reading
data from the device, or when checking the Ready/
Busy status during a programming operation. The
Ready/Busy status can be verified during an erase/
write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the High-Z
state on the falling edge of CS.
2.1
Start Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
2.3
All modes of operation are inhibited when VCC is below
a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices
or 3.8V for ‘93C’ devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
Note:
Block Diagram
VCC
2.2
Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. In order to
limit this current, a resistor should be connected
between DI and DO.
DS20001749K-page 6
VSS
Memory
Array
Address
Decoder
Address
Counter
An instruction following a Start condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
When preparing to transmit an instruction,
either the CLK or DI signal levels must be
at a logic low as CS is toggled active-high.
For added protection, an EWDS command
should be performed after every write
operation and an external 10 k pulldown protection resistor should be added
to the CS pin.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruction can be executed.
Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (Read, Write, Erase, EWEN, EWDS, ERAL
or WRAL). As soon as CS is high, the device is no
longer in Standby mode.
Note:
Data Protection
Data Register
Output
Buffer
DO
DI
ORG*
CS
CLK
Mode
Decode
Logic
Clock
Register
*ORG input is not available on A/B devices
 2002-2013 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.4
Erase
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
The ERASE instruction forces all data bits of the
specified address to the logical ‘1’ state. CS is brought
low following the loading of the last address bit. This
falling edge of the CS pin initiates the self-timed
programming cycle, except on ‘93C’ devices where the
rising edge of CLK before the last address bit initiates
the write cycle.
FIGURE 2-1:
Note:
After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
the Ready/Busy status from DO.
ERASE TIMING FOR 93AA AND 93LC DEVICES
TCSL
CS
Check Status
CLK
1
DI
1
1
AN
AN-1 AN-2
•••
A0
TCZ
TSV
DO
High-Z
Busy
Ready
High-Z
TWC
FIGURE 2-2:
ERASE TIMING FOR 93C DEVICES
TCSL
CS
Check Status
CLK
1
DI
1
1
AN
AN-1 AN-2
•••
A0
TCZ
TSV
DO
High-Z
Busy
Ready
High-Z
TWC
 2002-2013 Microchip Technology Inc.
DS20001749K-page 7
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.5
Erase All (ERAL)
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
FIGURE 2-3:
Note:
After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
VCC must be 4.5V for proper operation of ERAL.
ERAL TIMING FOR 93AA AND 93LC DEVICES
TCSL
CS
Check Status
CLK
1
DI
0
0
1
0
x
•••
x
TCZ
TSV
DO
High-Z
Busy
Ready
High-Z
TEC
VCC must be 4.5V for proper operation of ERAL.
FIGURE 2-4:
ERAL TIMING FOR 93C DEVICES
TCSL
CS
Check Status
CLK
1
DI
0
0
1
0
x
•••
x
TCZ
TSV
DO
High-Z
Busy
Ready
High-Z
TEC
DS20001749K-page 8
 2002-2013 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.6
Erase/Write Disable and Enable
(EWDS/EWEN)
enabled until an EWDS instruction is executed or Vcc is
removed from the device.
To protect against accidental data disturbance, the EWDS
instruction can be used to disable all erase/write functions
and should follow all programming operations. Execution
of a READ instruction is independent of both the EWEN
and EWDS instructions.
The 93XX46A/B/C powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be preceded
by an Erase/Write Enable (EWEN) instruction. Once the
EWEN instruction is executed, programming remains
FIGURE 2-5:
EWDS TIMING
TCSL
CS
CLK
1
DI
FIGURE 2-6:
0
0
0
0
•••
x
x
EWEN TIMING
TCSL
CS
CLK
2.7
0
1
DI
0
1
1
•••
x
Read
The output data bits will toggle on the rising edge of the
CLK and are stable after the specified time delay (TPD).
Sequential read is possible when CS is held high. The
memory data will automatically cycle to the next register
and output sequentially.
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (if ORG pin is low or A-version
devices) or 16-bit (if ORG pin is high or B-version
devices) output string.
FIGURE 2-7:
x
READ TIMING
CS
CLK
DI
DO
1
1
0
High-Z
 2002-2013 Microchip Technology Inc.
AN
•••
A0
0
Dx
•••
D0
Dx
•••
D0
Dx
•••
D0
DS20001749K-page 9
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.8
Write
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
The WRITE instruction is followed by 8 bits (if ORG is
low or A-version devices) or 16 bits (if ORG pin is high
or B-version devices) of data, which are written into the
specified address. For 93AA46A/B/C and 93LC46A/B/C
devices, after the last data bit is clocked into DI, the
falling edge of CS initiates the self-timed auto-erase and
programming cycle. For 93C46A/B/C devices, the selftimed auto-erase and programming cycle is initiated by
the rising edge of CLK on the last data bit.
FIGURE 2-8:
Note:
After the Write cycle is complete, issuing a
Start bit and then taking CS low will clear
the Ready/Busy status from DO.
WRITE TIMING FOR 93AA AND 93LC DEVICES
TCSL
CS
CLK
DI
0
1
1
AN
•••
A0
Dx
•••
D0
TSV
High-Z
DO
Busy
TCZ
Ready
High-Z
TWC
FIGURE 2-9:
WRITE TIMING FOR 93C DEVICES
TCSL
CS
CLK
DI
0
1
1
AN
•••
A0
Dx
•••
D0
TSV
DO
High-Z
Busy
TCZ
Ready
High-Z
TWC
DS20001749K-page 10
 2002-2013 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.9
Write All (WRAL)
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AA46A/B/C and 93LC46A/B/C devices, after the
last data bit is clocked into DI, the falling edge of CS
initiates the self-timed auto-erase and programming
cycle. For 93C46A/B/C devices, the self-timed autoerase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction, but the chip must be in the EWEN status.
FIGURE 2-10:
Note:
After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
VCC must be 4.5V for proper operation of WRAL.
WRAL TIMING FOR 93AA AND 93LC DEVICES
TCSL
CS
CLK
DI
1
0
0
0
1
x
•••
x
Dx
•••
D0
TSV
High-Z
DO
Busy
TCZ
Ready
HIGH-Z
TWL
VCC must be 4.5V for proper operation of WRAL.
FIGURE 2-11:
WRAL TIMING FOR 93C DEVICES
TCSL
CS
CLK
DI
1
0
0
0
1
x
•••
x
Dx
•••
D0
TSV
DO
High-Z
Busy
TCZ
Ready
HIGH-Z
TWL
 2002-2013 Microchip Technology Inc.
DS20001749K-page 11
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
3.0
PIN DESCRIPTIONS
TABLE 3-1:
Name
PIN DESCRIPTIONS
PDIP
SOIC TSSOP MSOP DFN(1) TDFN(1)
SOT-23
Rotated
SOIC
Function
CS
1
1
1
1
1
1
5
3
Chip Select
CLK
2
2
2
2
2
2
4
4
Serial Clock
DI
3
3
3
3
3
3
3
5
Data In
DO
4
4
4
4
4
4
1
6
Data Out
Vss
5
5
5
5
5
5
2
7
Ground
ORG/NC
6
6
6
6
6
6
—
8
Organization/93XX46C
No Internal Connection/
93XX46A/B
NC
7
7
7
7
7
7
—
1
No Internal Connection
VCC
8
8
8
8
8
8
6
2
Power Supply
Note 1:
3.1
The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating.
Chip Select (CS)
A high level selects the device; a low level deselects
the device and forces it into Standby mode. However, a
programming cycle that is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
programming cycle is completed.
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
3.2
Serial Clock (CLK)
The Serial Clock is used to synchronize the communication between a master device and the 93XX series
device. Opcodes, address and data bits are clocked in
on the positive edge of CLK. Data bits are also clocked
out on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing opcode, address and data.
CLK is a “don't care” if CS is low (device deselected). If
CS is high, but the Start condition has not been
detected (DI = 0), any number of clock cycles can be
received by the device without changing its status (i.e.,
waiting for a Start condition).
CLK cycles are not required during the self-timed write
(i.e., auto erase/write) cycle.
After detection of a Start condition the specified number
of clock cycles (respectively low-to-high transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
DS20001749K-page 12
data bits before an instruction is executed. CLK and DI
then become “don't care” inputs waiting for a new Start
condition to be detected.
3.3
Data In (DI)
Data In (DI) is used to clock in a Start bit, opcode,
address and data synchronously with the CLK input.
3.4
Data Out (DO)
Data Out (DO) is used in the Read mode to output data
synchronously with the CLK input (TPD after the
positive edge of CLK).
This pin also provides Ready/Busy status information
during erase and write cycles. Ready/Busy status information is available on the DO pin if CS is brought high
after being low for minimum Chip Select low time (TCSL)
and an erase or write operation has been initiated.
The Status signal is not available on DO if CS is held
low during the entire erase or write cycle. In this case,
DO is in the High-Z mode. If status is checked after the
erase/write cycle, the data line will be high to indicate
the device is ready.
Note:
3.5
After a programming cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
Organization (ORG)
When the ORG pin is connected to VCC or Logic HI, the
(x16) memory organization is selected. When the ORG
pin is tied to VSS or Logic LO, the (x8) memory
organization is selected. For proper operation, ORG
must be tied to a valid logic level.
93XX46A devices are always (x8) organization and
93XX46B devices are always (x16) organization.
 2002-2013 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
8-Lead MSOP (150 mil)
XXXXXXT
YWWNNN
Example:
3L46BI
5281L7
6-Lead SOT-23
Example:
XXNN
1EL7
8-Lead PDIP
Example:
XXXXXXXX
T/XXXNNN
YYWW
93LC46B
I/P e3 1L7
0528
8-Lead SOIC
Example:
XXXXXXXT
XXXXYYWW
NNN
8-Lead Rotated SOIC
XXXXXXXT
XXXXYYWW
NNN
8-Lead TSSOP
XXXX
TYWW
NNN
 2002-2013 Microchip Technology Inc.
93LC46BI
SN e3 0528
1L7
Example:
93L46BXI
SN e3 0528
1L7
Example:
L46B
I528
1L7
DS20001749K-page 13
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
Example:
8-Lead 2x3 DFN
314
528
L7
XXX
YWW
NN
Example:
8-Lead 2x3 TDFN
E14
528
L7
XXX
YWW
NN
1st Line Marking Codes
Part Number
TSSOP
MSOP
SOT-23
I Temp.
DFN
E Temp.
I Temp.
TDFN
E Temp.
I Temp.
E Temp.
93AA46A
A46A
3A46AT
1BNN
—
301
—
E01
—
93AA46B
A46B
3A46BT
1LNN
—
311
—
E11
—
93AA46C
A46C
3A46CT
—
—
321
—
E21
—
93LC46A
L46A
3L46AT
1ENN
1FNN
304
—
E04
E05
93LC46B
L46B
3L46BT
1PNN
1RNN
314
—
E14
E15
93LC46C
L46C
3L46CT
—
—
324
—
E24
E25
93C46A
C46A
3C46AT
1HNN
1JNN
307
—
E07
E08
93C46B
C46B
3C46BT
1TNN
1UNN
317
—
E17
E18
C46C
3C46CT
—
—
327
—
E27
E28
93C46C
Note:
T = Temperature grade (I, E)
NN = Alphanumeric traceability code
Legend: XX...X
T
Y
YY
WW
NNN
e3
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note:
For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS20001749K-page 14
 2002-2013 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2002-2013 Microchip Technology Inc.
DS20001749K-page 15
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001749K-page 16
 2002-2013 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2002-2013 Microchip Technology Inc.
DS20001749K-page 17
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
.
#
#$#/!- 0 #
1/%#
#!#
##+22---
2/
b
4
N
E
E1
PIN 1 ID BY
LASER MARK
1
2
3
e
e1
D
A
A2
c
φ
L
A1
L1
3#
4#
5$8
%1
44""
5
5
56
7
9
1#
()*
6$# !4!1#
)*
6,:#
;
!!1//
<
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(
#!
%%
;
(
6,=!#
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!!1/=!#
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6,4#
;
.
#4#
4
;
9
.
##
4
(
;
<
.
#
>
;
>
4!/
<
;
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4!=!#
8
;
(
!"!
#$!
!% #$ !% #$ #&! !
!#
"'(
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$##
- *<)
DS20001749K-page 18
 2002-2013 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2002-2013 Microchip Technology Inc.
DS20001749K-page 19
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
!"##
$% !
.
#
#$#/!- 0 #
1/%#
#!#
##+22---
2/
N
NOTE 1
E1
1
3
2
D
E
A2
A
L
A1
c
e
eB
b1
b
3#
4#
5$8
%1
5*:"
5
5
56
7
<
1#
#
#1
;
;
!!1//
(
(
) #
#1
(
;
;
$!#
$!=!#
"
(
!!1/=!#
"
(
<
6,4#
<
9(
#
#1
4
(
(
4!/
<
(
8
9
8
<
)
;
;
34!=!#
4
-4!=!#
6,
-?
)*
1, $!&%#$,08$#$ #8
#!-###!
?%#*# #
!"!
#$!
!% #$ !% #$ #&!@ !
!#
"'(
)*+) #&#,$ --#
$##
- *<)
DS20001749K-page 20
 2002-2013 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2002-2013 Microchip Technology Inc.
DS20001749K-page 21
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001749K-page 22
 2002-2013 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
"&'()#$%!*
.
#
#$#/!- 0 #
1/%#
#!#
##+22---
2/
 2002-2013 Microchip Technology Inc.
DS20001749K-page 23
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
++,
"-(-$%
.
#
#$#/!- 0 #
1/%#
#!#
##+22---
2/
D
N
E
E1
NOTE 1
1
2
b
e
c
A
φ
A2
A1
L
L1
3#
4#
5$8
%1
44""
5
5
56
7
<
1#
6,:#
;
9()*
;
!!1//
<
(
#!
%%
(
;
(
6,=!#
"
!!1/=!#
"
9)*
!!1/4#
.
#4#
4
(
9
(
.
##
4
(
".
.
#
>
;
<>
4!/
;
4!=!#
8
;
1, $!&%#$,08$#$ #8
#!-###!
!"!
#$!
!% #$ !% #$ #&!( !
!#
"'(
)*+ ) #&#,$ --#
$##
".+ % 0$ $-#
$##
0%
%
#
$
- *<9)
DS20001749K-page 24
 2002-2013 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2002-2013 Microchip Technology Inc.
DS20001749K-page 25
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
.
',/0*"11#()$% .
.
#
#$#/!- 0 #
1/%#
#!#
##+22---
2/
e
D
b
N
N
L
K
E2
E
EXPOSED PAD
NOTE 1
NOTE 1
2
1
2
1
D2
BOTTOM VIEW
TOP VIEW
A
A3
A1
NOTE 2
3#
4#
5$8
%1
44""
5
5
56
7
<
1#
6,:#
<
#!
%%
(
*
##/
".
6,4#
)*
6,=!#
"
"&
!1!4#
;
"&
!1!=!#
"
(
;
(
8
(
*
##4#
4
(
*
###
"&
!1!
U
;
;
*
##=!#
()*
)*
((
1, $!&%#$,08$#$ #8
#!-###!
1/,
&
!#8 #! 1/ - $#!
!#
"'(
)*+ ) #&#,$ --#
$##
".+ % 0$ $-#
$##
0%
%
#
$
- **
DS20001749K-page 26
 2002-2013 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2002-2013 Microchip Technology Inc.
DS20001749K-page 27
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001749K-page 28
 2002-2013 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2002-2013 Microchip Technology Inc.
DS20001749K-page 29
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
.
',/0"11#(23$% .
.
#
#$#/!- 0 #
1/%#
#!#
##+22---
2/
DS20001749K-page 30
 2002-2013 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
APPENDIX A:
REVISION HISTORY
Revision D (12/2003)
Corrections to Section 1.0, Electrical Characteristics.
Section 4.1, 6-Lead SOT-23 package to OT.
Revision E (3/2005)
Added DFN package.
Revision F (4/2005)
Added notes throughout.
Revision G (5/2008)
Revised Figures 2-1 through 2-4 and Figures 2-8
through 2-11; Revised Package Marking Information;
Replaced Package Drawings; Revised Product ID
section.
Revision H (08/2010)
Added 8-Lead Rotated SOIC marking information;
Revised Package Drawings; Revised Product ID
System.
Revision J (12/2011)
Added TDFN Package.
Revision K (06/2013)
Added E Temp to 93LC46C and 93C46C.
 2002-2013 Microchip Technology Inc.
DS20001749K-page 31
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
NOTES:
DS20001749K-page 32
 2002-2013 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
 2002-2013 Microchip Technology Inc.
DS20001749K-page 33
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device: 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
Literature Number: DS20001749K
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS20001749K-page 34
 2002-2013 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
X
Pinout Tape & Reel Temperature
Range
Device:
/XX
X
Package
X
Lead Finish
93AA46A: 1K 1.8V Microwire Serial EEPROM
93AA46B: 1K 1.8V Microwire Serial EEPROM
93AA46C: 1K 1.8V Microwire Serial EEPROM w/ORG
93LC46A: 1K 2.5V Microwire Serial EEPROM
93LC46B: 1K 2.5V Microwire Serial EEPROM
93LC46C: 1K 2.5V Microwire Serial EEPROM w/ORG
93C46A:
93C46B:
93C46C:
1K 5.0V Microwire Serial EEPROM
1K 5.0V Microwire Serial EEPROM
1K 5.0V Microwire Serial EEPROM w/ORG
Examples:
a)
b)
c)
93AA46C-I/P: 1K, 128x8 or 64x16 Serial
EEPROM, PDIP package, 1.8V
93AA46B-I/MS: 1K, 64x16 Serial EEPROM,
MSOP package, 1.8V
93AA46AT-I/OT: 1K, 128x8 Serial EEPROM,
SOT-23 package, tape and reel, 1.8V
d)
93AA46CT-I/SN: 1K, 128x8 or 16x16 Serial
EEPROM, SOIC package, tape and reel, 1.8V
a)
93LC46A-I/MS: 1K, 128x8 Serial EEPROM,
MSOP package, 2.5V
93LC46BT-I/OT: 1K, 64x16 Serial EEPROM,
SOT-23 package, tape and reel, 2.5V
93LC46B-I/ST: 1K, 64x16 Serial EEPROM,
TSSOP package, 2.5V
b)
c)
Pinout:
Blank =
X
=
Standard pinout
Rotated pinout (SOIC only)
d)
93LC46CT-I/MNY: 1K, 128x8 or 64x16 Serial
EEPROM, TDFN package, tape and reel, 2.5V
Tape & Reel:
Blank =
T
=
Standard packaging
Tape & Reel
a)
Temperature Range:
I
E
-40°C to +85°C
-40°C to +125°C
Package:
MS
=
OT
=
P
=
SN
=
ST
=
MC
=
MNY(1) =
93C46B-I/MS: 1K, 64x16 Serial EEPROM,
MSOP package, 5.0V
93C46C-I/MS: 1K, 128x8 or 64x16 Serial
EEPROM, MSOP package, 5.0V
93C46AT-I/OT: 1K, 128x8 Serial EEPROM,
SOT-23 package, tape and reel, 5.0V
93C46BX-I/SN: 1K, 64x16 Serial EEPROM,
Rotated SOIC Package, 5.0V
b)
=
=
c)
d)
Note
1:
Plastic MSOP (Micro Small outline), 8-lead
Plastic SOT-23, 6-lead (Tape & Reel only)
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (3.9 mm body), 8-lead
Plastic TSSOP (4.4 mm body), 8-lead
Plastic DFN (2x3x0.90 mm body), 8-lead
Plastic TDFN (2x3x0.75 mm body), 8-lead
(Tape & Reel only)
“Y” indicates a Nickel Palladium Gold (NiPdAu) finish.
 2002-2013 Microchip Technology Inc.
DS20001749K-page 35
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
NOTES:
DS20001749K-page 36
 2002-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2002-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620772799
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2002-2013 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS20001749K-page 37
Worldwide Sales and Service
AMERICAS
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Technical Support:
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Tel: 91-11-4160-8631
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Tel: 43-7242-2244-39
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DS20001749K-page 38
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11/29/12
 2002-2013 Microchip Technology Inc.
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