PIN CONFIGURATIONS Low offset voltage: 1 μV Input offset drift: 0.005 μV/°C Rail-to-rail input and output swing 5 V/2.7 V single-supply operation High gain: 145 dB typical CMRR: 140 dB typical PSRR: 130 dB typical Ultralow input bias current: 10 pA typical Low supply current: 750 μA per op amp Overload recovery time: 50 μs No external capacitors required NC 1 –IN A 2 +IN A 3 TOP VIEW 6 (Not to Scale) V– 4 5 NC 7 V+ OUT A NC Figure 1. 8-Lead MSOP (RM Suffix) NC 1 –IN A 2 AD8571 8 NC 7 V+ 6 OUT A TOP VIEW V– 4 (Not to Scale) 5 NC NC = NO CONNECT 01104-004 +IN A 3 OUT A 1 8 V+ –IN A 2 AD8572 7 OUT B +IN A 3 TOP VIEW (Not to Scale) 6 –IN B V– 4 5 +IN B 01104-002 Figure 2. 8-Lead SOIC (R Suffix) Temperature sensors Pressure sensors Precision current sensing Strain gage amplifiers Medical instrumentation Thermocouple amplifiers OUT A 1 2 +IN A 3 This family of amplifiers has ultralow offset, drift, and bias current. The AD8571/AD8572/AD85741 are single, dual, and quad amplifiers, respectively, featuring rail-to-rail input and output swings. All are guaranteed to operate from 2.7 V to 5 V single supply. The AD8571/AD8572/AD8574 provide benefits previously found only in expensive auto-zeroing or chopper-stabilized amplifiers. Using Analog Devices, Inc., topology, these zerodrift amplifiers combine low cost with high accuracy. (No external capacitors are required.) Using a spread-spectrum, auto-zero technique, the AD8571/AD8572/AD8574 eliminate the intermodulation effects from interaction of the chopping function with the signal frequency in ac applications. With an offset voltage of only 1 μV and drift of 0.005 μV/°C, the AD8571/AD8572/AD8574 are perfectly suited for applications where error sources cannot be tolerated. Position and pressure sensors, medical equipment, and strain gage amplifiers benefit greatly from nearly zero drift over their operating temperature range. Many more systems require the rail-to-rail input and output swings provided by the AD8571/AD8572/AD8574. Protected by U.S. Patent 6,130,578. V+ 7 OUT B TOP VIEW (Not to Scale) 6 –IN B 5 +IN B 4 Figure 4. 8-Lead SOIC (R Suffix) OUT A 1 14 OUT D –IN A 2 13 –IN D 12 +IN D +IN A 3 V+ 4 +IN B 5 AD8574 11 V– TOP VIEW (Not to Scale) 10 +IN C –IN B 6 9 –IN C OUT B 7 8 OUT C 01104-003 GENERAL DESCRIPTION V– 8 AD8572 01104-005 Figure 3. 8-Lead TSSOP (RU Suffix) –IN A Rev. F 8 NC = NO CONNECT APPLICATIONS 1 AD8571 01104-001 FEATURES Figure 5. 14-Lead TSSOP (RU Suffix) OUT A 1 14 OUT D 13 –IN D –IN A 2 +IN A 3 V+ 4 +IN B 5 AD8574 12 +IN D 11 V– TOP VIEW (Not to Scale) 10 +IN C –IN B 6 9 –IN C OUT B 7 8 OUT C 01104-006 Data Sheet Zero-Drift, Single-Supply, Rail-to-Rail Input/Output Operational Amplifiers AD8571/AD8572/AD8574 Figure 6. 14-Lead SOIC (R Suffix) The AD8571/AD8572/AD8574 are specified for the extended industrial/ automotive temperature range (−40°C to +125°C). The AD8571 single amplifier is available in 8-lead MSOP and narrow SOIC packages. The AD8572 dual amplifier is available in 8-lead narrow SOIC and surface-mount TSSOP packages. The AD8574 quad amplifier is available in 14-lead narrow SOIC and TSSOP packages. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©1999–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8571/AD8572/AD8574 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Maximizing Performance Through Proper Layout ............... 17 Applications ....................................................................................... 1 1/f Noise Characteristics ........................................................... 18 General Description ......................................................................... 1 Random Auto-Zero Correction Eliminates Intermodulation Distortion .................................................................................... 18 Pin Configurations ........................................................................... 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 5 V Electrical Characteristics ...................................................... 4 2.7 V Electrical Characteristics................................................... 5 Absolute Maximum Ratings ............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution .................................................................................. 6 Typical Performance Characteristics ............................................. 7 Functional Description .................................................................. 15 Amplifier Architecture .............................................................. 15 Basic Auto-Zero Amplifier Theory .......................................... 15 Auto-Zero Phase ......................................................................... 16 Amplification Phase ................................................................... 16 High Gain, CMRR, and PSRR .................................................. 17 Broadband and External Resistor Noise Considerations .......... 19 Output Overdrive Recovery ...................................................... 19 Input Overvoltage Protection ................................................... 19 Output Phase Reversal ............................................................... 19 Capacitive Load Drive ............................................................... 20 Power-Up Behavior .................................................................... 20 Applications Information .............................................................. 21 5 V Precision Strain Gage Circuit ............................................ 21 3 V Instrumentation Amplifier ................................................ 21 High Accuracy Thermocouple Amplifier ............................... 22 Precision Current Meter ............................................................ 22 Precision Voltage Comparator.................................................. 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 25 Rev. F | Page 2 of 28 Data Sheet AD8571/AD8572/AD8574 REVISION HISTORY 6/15—Rev. E to Rev. F Added Patent Note, Note 1............................................................... 1 Change to Input Voltage Parameter, Table 3.................................. 6 Changes to Ordering Guide ...........................................................25 2/11—Rev. D to Rev. E Changes to Figure 66 ......................................................................21 Updated Outline Dimensions ........................................................22 Changes to Ordering Guide ...........................................................23 6/08—Rev. C to Rev. D Changes to Figure 19 and Figure 20 ............................................... 8 Changes to Figure 44 ......................................................................12 Changes to Figure 38 ......................................................................13 Moved Figure 50 and Figure 51 .....................................................14 Changes to Figure 66, Precision Current Meter Section, Layout, Figure 67, Equation 24, and Figure 68 ..........................................21 5/07—Rev. B to Rev. C Changes to Features .......................................................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Changes to Basic Auto-Zero Amplifier Theory Section ............14 Changes to Figure 50 ......................................................................15 Changes to Figure 55 ......................................................................16 Changes to Figure 66 ......................................................................21 Updated Outline Dimensions ........................................................22 9/06—Rev. A to Rev. B Updated Format ................................................................. Universal Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Changes to Figure 50 ...................................................................... 14 Changes to Figure 51 ...................................................................... 15 Changes to Figure 66 ...................................................................... 21 Deleted Figure 69 and SPICE Macro-Model Section ................. 17 Deleted SPICE Macro-Model for the AD857x Section .............. 18 Updated Outline Dimensions........................................................ 22 Changes to Ordering Guide ........................................................... 23 7/03—Rev. 0 to Rev. A Renumbered Figures .......................................................... Universal Changes to Ordering Guide ............................................................. 4 Change to Figure 15. ....................................................................... 16 Updated Outline Dimensions........................................................ 19 10/99—Revision 0: Initial Version Rev. F | Page 3 of 28 AD8571/AD8572/AD8574 Data Sheet SPECIFICATIONS 5 V ELECTRICAL CHARACTERISTICS VS = 5 V, VCM = 2.5 V, VO = 2.5 V, TA = 25°C, unless otherwise noted. Table 1. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Conditions Min VOS Typ Max Unit 1 5 10 50 1.5 300 4 70 200 150 400 5 0.04 μV μV pA nA pA nA pA pA pA pA V dB dB dB dB μV/°C 10 10 V V V V mV mV −40°C ≤ TA ≤ +125°C Input Bias Current AD8571/AD8574 AD8572 IB Input Offset Current AD8571/AD8574 AD8572 IOS −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C Input Voltage Range Common-Mode Rejection Ratio CMRR Large Signal Voltage Gain1 AVO Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low 10 1.0 160 2.5 20 150 30 150 −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C ∆VOS/∆T VOH VOL VCM = 0 V to 5 V −40°C ≤ TA ≤ +125°C RL = 10 kΩ, VO = 0.3 V to 4.7 V −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +125°C RL = 100 kΩ to GND RL = 100 kΩ to GND @ −40°C to +125°C RL = 10 kΩ to GND RL = 10 kΩ to GND @ −40°C to +125°C RL = 100 kΩ to V+ RL = 100 kΩ to V+ @ −40°C to +125°C 0 120 115 125 120 4.99 4.99 4.95 4.95 RL = 10 kΩ to V+ RL = 10 kΩ to V+ @ −40°C to +125°C Short-Circuit Limit ISC ±25 −40°C to +125°C Output Current IO −40°C to +125°C POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier DYNAMIC PERFORMANCE Slew Rate Overload Recovery Time Gain Bandwidth Product NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density 1 PSRR ISY SR VS = 2.7 V to 5.5 V −40°C ≤ TA ≤ +125°C VO = 0 V −40°C ≤ TA ≤ +125°C RL = 10 kΩ GBP en p-p en in 0 Hz to 10 Hz 0 Hz to 1 Hz f = 1 kHz f = 10 Hz Gain testing is dependent upon test bandwidth. Rev. F | Page 4 of 28 120 115 140 130 145 135 0.005 4.998 4.997 4.98 4.975 1 2 10 15 ±50 ±40 ±30 ±15 130 130 850 1000 0.4 0.05 1.5 1.3 0.41 51 2 30 30 975 1075 0.3 mV mV mA mA mA mA dB dB μA μA V/μs ms MHz μV p-p μV p-p nV/√Hz fA/√Hz Data Sheet AD8571/AD8572/AD8574 2.7 V ELECTRICAL CHARACTERISTICS VS = 2.7 V, VCM = 1.35 V, VO = 1.35 V, TA = 25°C, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Conditions Min VOS Typ Max Unit 1 5 10 50 1.5 300 4 50 200 150 400 2.7 μV μV pA nA pA nA pA pA pA pA V dB dB dB dB µV/°C −40°C ≤ TA ≤ +125°C Input Bias Current AD8571/AD8574 AD8572 IB Input Offset Current AD8571/AD8574 AD8572 IOS −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C Input Voltage Range Common-Mode Rejection Ratio CMRR Large Signal Voltage Gain1 AVO Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High 10 1.0 160 2.5 10 150 30 150 −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C ∆VOS/∆T VOH Output Voltage Low VOL Short-Circuit Limit ISC VCM = 0 V to 2.7 V −40°C ≤ TA ≤ +125°C RL = 10 kΩ, VO = 0.3 V to 2.4 V −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +125°C RL = 100 kΩ to GND RL = 100 kΩ to GND @ −40°C to +125°C RL = 10 kΩ to GND RL = 10 kΩ to GND @ −40°C to +125°C RL = 100 kΩ to V+ RL = 100 kΩ to V+ @ −40°C to +125°C RL = 10 kΩ to V+ RL = 10 kΩ to V+ @ −40°C to +125°C 0 115 110 110 105 2.685 2.685 2.67 2.67 ±10 −40°C to +125°C Output Current IO −40°C to +125°C POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier DYNAMIC PERFORMANCE Slew Rate Overload Recovery Time Gain Bandwidth Product NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density 1 PSRR ISY SR VS = 2.7 V to 5.5 V −40°C ≤ TA ≤ +125°C VO = 0 V −40°C ≤ TA ≤ +125°C 2.697 2.696 2.68 2.675 1 2 10 15 ±15 ±10 ±10 ±5 130 130 750 950 0.04 10 10 20 20 900 1000 V V V V mV mV mV mV mA mA mA mA dB dB μA μA RL = 10 kΩ 0.5 0.05 1 V/μs ms MHz 0 Hz to 10 Hz f = 1 kHz f = 10 Hz 2.0 94 2 μV p-p nV/√Hz fA/√Hz GBP en p-p en in 120 115 130 130 140 130 0.005 Gain testing is dependent upon test bandwidth. Rev. F | Page 5 of 28 AD8571/AD8572/AD8574 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage Input Voltage Differential Input Voltage1 ESD (Human Body Model) Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) 1 Rating 6V GND − 0.3 V to VS + 0.3 V ±5.0 V 2000 V Indefinite −65°C to +150°C −40°C to +125°C −65°C to +150°C 300°C Differential input voltage is limited to ±5.0 V or the supply voltage, whichever is less. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL CHARACTERISTICS θJA is specified for the worst-case conditions, that is, θJA is specified for a device soldered in a circuit board for SOIC and TSSOP packages. Table 4. Thermal Resistance Package Type 8-Lead SOIC (R) 8-Lead MSOP (RM) 8-Lead TSSOP (RU) 14-Lead SOIC (R) 14-Lead TSSOP (RU) ESD CAUTION Rev. F | Page 6 of 28 θJA 158 190 240 120 180 θJC 43 44 43 36 36 Unit °C/W °C/W °C/W °C/W °C/W Data Sheet AD8571/AD8572/AD8574 TYPICAL PERFORMANCE CHARACTERISTICS 180 VS = 2.7V VCM = 1.35V TA = 25°C NUMBER OF AMPLIFIERS 140 120 100 80 60 140 120 100 80 60 40 40 20 20 0 –2.5 –1.5 –0.5 2.5 1.5 0.5 VS = 5V VCM = 2.5V TA = 25°C 160 0 –2.5 01104-007 OFFSET VOLTAGE (µV) –1.5 –0.5 0.5 Figure 7. Input Offset Voltage Distribution Figure 10. Input Offset Voltage Distribution 50 12 VS = 5V TA = –40°C, +25°C, +85°C 40 VS = 5V VCM = 2.5V TA = –40°C TO +125°C 30 NUMBER OF AMPLIFIERS INPUT BIAS CURRENT (pA) 10 +85°C 20 10 +25°C 0 –10 –40°C 3 1 2 4 INPUT COMMON-MODE VOLTAGE (V) 5 01104-008 0 8 6 4 2 –20 –30 2.5 1.5 OFFSET VOLTAGE (µV) 0 0 1 2 3 4 5 6 INPUT OFFSET DRIFT (nV/°C) 01104-011 NUMBER OF AMPLIFIERS 160 01104-010 180 Figure 11. Input Offset Voltage Drift Distribution Figure 8. Input Bias Current vs. Input Common-Mode Voltage 10k 1500 VS = 5V TA = 125°C VS = 5V TA = 25°C 1000 OUTPUT VOLTAGE (mV) 500 0 –500 –1000 100 SOURCE 10 SINK 1 –2000 0 1 2 3 4 COMMON-MODE VOLTAGE (V) 5 0.1 0.0001 0.001 0.01 0.1 1 10 LOAD CURRENT (mA) Figure 12. Output Voltage to Supply Rail vs. Load Current Figure 9. Input Bias Current vs. Common-Mode Voltage Rev. F | Page 7 of 28 100 01104-012 –1500 01104-009 INPUT BIAS CURRENT (pA) 1k AD8571/AD8572/AD8574 Data Sheet 10k 800 VS = 2.7V TA = 25°C SUPPLY CURRENT PER AMPLIFIER (µA) TA = 25°C SINK SOURCE 10 1 0.001 0.01 0.1 1 10 100 LOAD CURRENT (mA) 400 300 200 100 0 01104-013 0.1 0.0001 500 1 2 3 4 6 5 SUPPLY VOLTAGE (V) Figure 16. Supply Current per Amplifier vs. Supply Voltage Figure 13. Output Voltage to Supply Rail vs. Load Current 60 1000 VCM = 2.5V VS = 5V VS = 2.7V CL = 0pF RL = ∞ 50 750 OPEN-LOOP GAIN (dB) INPUT BIAS CURRENT (pA) 0 01104-016 100 600 500 250 40 0 30 45 20 90 10 135 0 180 –10 225 –20 270 PHASE SHIFT (Degrees) OUTPUT VOLTAGE (mV) 1k 700 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) –40 10k 01104-014 1M 10M 100M FREQUENCY (Hz) Figure 17. Open-Loop Gain and Phase Shift vs. Frequency Figure 14. Input Bias Current vs. Temperature 60 1.0 VS = 5V CL = 0pF RL = ∞ 50 5V OPEN-LOOP GAIN (dB) 0.8 2.7V 0.6 0.4 0.2 40 0 30 45 20 90 10 135 0 180 –10 225 –20 270 –50 –25 0 25 50 75 100 TEMPERATURE (°C) 125 150 –40 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 15. Supply Current vs. Temperature Figure 18. Open-Loop Gain and Phase Shift vs. Frequency Rev. F | Page 8 of 28 01104-018 –30 0 –75 01104-015 SUPPLY CURRENT (mA) 100k PHASE SHIFT (Degrees) 0 –75 01104-017 –30 Data Sheet AD8571/AD8572/AD8574 60 300 VS = 2.7V CL = 20pF RL = 2kΩ 50 270 240 OUTPUT IMPEDANCE (Ω) AV = 100 30 20 AV = 10 10 0 AV = 1 –10 210 180 150 AV = 100 120 90 –20 60 –30 30 AV = 10 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 19. Closed-Loop Gain vs. Frequency 0 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 22. Output Impedance vs. Frequency 60 VS = 5V CL = 20pF RL = 2kΩ 50 CLOSED-LOOP GAIN (dB) 40 30 VS = 2.7V CL = 300pF RL = 2kΩ AV = 1 AV = 100 20 AV = 10 10 0 AV = 1 –10 –30 2µs 1k 10k 1M 100k 10M FREQUENCY (Hz) 500mV 01104-020 –40 100 01104-023 –20 Figure 23. Large Signal Transient Response Figure 20. Closed-Loop Gain vs. Frequency 300 270 VS = 5V CL = 300pF RL = 2kΩ AV = 1 VS = 2.7V 210 180 AV = 100 150 120 AV = 10 90 30 0 100 AV = 1 1k 10k 100k 1M FREQUENCY (Hz) 5µs 10M 1V Figure 24. Large Signal Transient Response Figure 21. Output Impedance vs. Frequency Rev. F | Page 9 of 28 01104-024 60 01104-021 OUTPUT IMPEDANCE (Ω) 240 01104-022 AV = 1 –40 100 01104-019 CLOSED-LOOP GAIN (dB) 40 VS = 5V AD8571/AD8572/AD8574 Data Sheet 45 VS = ±1.35V CL = 50pF RL = ∞ AV = 1 SMALL SIGNAL OVERSHOOT (%) 40 35 +OS 30 25 20 –OS 15 10 0 10 100 1k 10k CAPACITANCE (pF) Figure 28. Small Signal Overshoot vs. Load Capacitance Figure 25. Small Signal Transient Response VS = ±2.5V CL = 50pF RL = ∞ AV = 1 0V VS = ±2.5V VIN = –200mV p-p (RET TO GND) CL = 0pF RL = 10kΩ AV = –100 VIN VOUT 0V 50mV 20µs 1V 01104-029 01104-026 5µs BOTTOM SCALE: 1V/DIV TOP SCALE: 200mV/DIV Figure 26. Small Signal Transient Response Figure 29. Positive Overvoltage Recovery 50 VS = ±1.35V RL = 2kΩ TA = 25°C VIN 40 0V 35 30 +OS 25 –OS 20 0V VS = ±2.5V VIN = 200mV p-p (RET TO GND) CL = 0pF RL = 10kΩ AV = –100 15 10 VOUT 5 100 1k 10k CAPACITANCE (pF) Figure 27. Small Signal Overshoot vs. Load Capacitance 1V BOTTOM SCALE: 1V/DIV TOP SCALE: 200mV/DIV Figure 30. Negative Overvoltage Recovery Rev. F | Page 10 of 28 01104-030 20µs 0 10 01104-027 SMALL SIGNAL OVERSHOOT (%) 45 01104-028 5 01104-025 50mV 5µs VS = ±2.5V RL = 2kΩ TA = 25°C Data Sheet AD8571/AD8572/AD8574 140 VS = ±1.35V VS = ±2.5V RL = 2kΩ AV = –100 VIN = 60mV p-p 120 PSRR (dB) 100 80 60 40 –PSRR +PSRR 1V 0 100 1k 10k 100k 1M 10M 1M 10M FREQUENCY (Hz) Figure 31. No Phase Reversal Figure 34. PSRR vs. Frequency 140 140 VS = ±2.5V 120 100 100 80 60 80 60 40 40 20 20 1k 10k 100k 1M 10M FREQUENCY (Hz) +PSRR 0 100 –PSRR 1k 100k 10k FREQUENCY (Hz) Figure 32. CMRR vs. Frequency 01104-035 PSRR (dB) 120 01104-032 CMRR (dB) VS = 2.7V 0 100 01104-034 01104-031 20 200µs Figure 35. PSRR vs. Frequency 140 3.0 VS = 5V 120 2.5 OUTPUT SWING (V p-p) 80 60 40 1.5 1.0 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 33. CMRR vs. Frequency 0 100 1k 10k 100k FREQUENCY (Hz) Figure 36. Maximum Output Swing vs. Frequency Rev. F | Page 11 of 28 1M 01104-036 0 100 2.0 VS = ±1.35V RL = 2kΩ AV = 1 THD + N < 1% TA = 25°C 0.5 20 01104-033 CMRR (dB) 100 AD8571/AD8572/AD8574 Data Sheet 5.5 VS = ±2.5V RL = 2kΩ AV = 1 THD + N < 1% TA = 25°C 5.0 VS = 2.7V RS = 0Ω 364 312 4.0 en (nV/ Hz) 3.5 3.0 2.5 2.0 1.5 260 208 156 104 1.0 1k 10k 100k 1M FREQUENCY (Hz) 01104-037 0 100 0 0.5 1.0 1.5 2.0 2.5 FREQUENCY (kHz) 01104-040 52 0.5 Figure 40. Voltage Noise Density from 0 Hz to 2.5 kHz Figure 37. Maximum Output Swing vs. Frequency VS = ±1.35V AV = 120,000 VS = 2.7V RS = 0Ω 112 en (nV/ Hz) 96 0V 80 64 48 32 50mV 0 5 10 15 20 25 FREQUENCY (kHz) Figure 38. 0.1 Hz to 10 Hz Noise 01104-041 16 01104-038 1sec Figure 41. Voltage Noise Density from 0 Hz to 25 kHz VS = ±2.5V AV = 120,000 VS = 5V RS = 0Ω 182 en (nV/ Hz) 156 130 104 78 52 50mV 26 0 0.5 1.0 1.5 2.0 FREQUENCY (kHz) Figure 39. 0.1 Hz to 10 Hz Noise Figure 42. Voltage Noise Density from 0 Hz to 2.5 kHz Rev. F | Page 12 of 28 2.5 01104-042 1sec 01104-039 OUTPUT SWING (V p-p) 4.5 Data Sheet AD8571/AD8572/AD8574 150 VS = 2.7V TO 5.5V POWER SUPPLY REJECTION (dB) VS = 5V RS = 0Ω 112 en (nV/ Hz) 96 80 64 48 32 145 140 135 130 5 15 10 20 25 FREQUENCY (kHz) 125 –75 01104-043 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) Figure 43. Voltage Noise Density from 0 Hz to 25 kHz 01104-045 16 Figure 45. Power Supply Rejection vs. Temperature VS = 5V RS = 0Ω 210 150 120 90 60 30 0 5 FREQUENCY (Hz) 10 01104-044 en (nV/ Hz) 180 40 VS = 2.7V 30 ISC– 20 10 0 –10 ISC+ –20 –30 –40 –50 –75 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) Figure 46. Output Short-Circuit Current vs. Temperature Figure 44. Voltage Noise Density from 0 Hz to 10 Hz Rev. F | Page 13 of 28 150 01104-046 OUTPUT SHORT-CIRCUIT CURRENT (mA) 50 AD8571/AD8572/AD8574 Data Sheet 225 200 60 OUTPUT VOLTAGE (mV) ISC– 40 20 0 –20 –40 ISC+ 125 100 75 50 25 –50 –25 0 25 50 75 100 125 150 250 VS = 2.7V 200 175 150 RL = 1kΩ 125 100 75 50 RL = 10kΩ RL = 100kΩ –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) 150 01104-048 25 0 –75 0 –75 RL = 10kΩ –50 –25 0 25 RL = 100kΩ 50 75 100 125 TEMPERATURE (°C) Figure 49. Output Voltage to Supply Rail vs. Temperature Figure 47. Output Short-Circuit Current vs. Temperature 225 RL = 1kΩ 150 –80 TEMPERATURE (°C) OUTPUT VOLTAGE (mV) 175 –60 –100 –75 VS = 5V Figure 48. Output Voltage to Supply Rail vs. Temperature Rev. F | Page 14 of 28 150 01104-049 80 250 VS = 5V 01104-047 OUTPUT SHORT-CIRCUIT CURRENT (mA) 100 Data Sheet AD8571/AD8572/AD8574 FUNCTIONAL DESCRIPTION AMPLIFIER ARCHITECTURE Each AD8571/AD8572/AD8574 op amp consists of two amplifiers: a main amplifier and a secondary amplifier that is used to correct the offset voltage of the main amplifier. Both consist of a rail-to-rail input stage, allowing the input common-mode voltage range to reach both supply rails. The input stage consists of an NMOS differential pair operating concurrently with a parallel PMOS differential pair. The outputs from the differential input stages are combined in another gain stage whose output is used to drive a rail-to-rail output stage. The wide voltage swing of the amplifier is achieved by using two output transistors in a common-source configuration. The output voltage range is limited by the drain-to-source resistance of these transistors. As the amplifier is required to source or sink more output current, the voltage drop across these transistors increases due to their on resistance (RDS). Simply put, the output voltage does not swing as close to the rail under heavy output current conditions as it does with light output current. This is a characteristic of all rail-to-rail output amplifiers. Figure 12 and Figure 13 show how close the output voltage can get to the rails with a given output current. The output of the AD8571/ AD8572/AD8574 is short-circuit protected to approximately 50 mA of current. The AD8571/AD8572/AD8574 amplifiers have exceptional gain, yielding greater than 120 dB of open-loop gain with a load of 2 kΩ. Because the output transistors are configured in a common-source configuration, the gain of the output stage, and thus the open-loop gain of the amplifier, is dependent on the load resistance. Open-loop gain decreases with smaller load resistances, which is another characteristic of rail-to-rail output amplifiers. Autocorrection amplifiers are not a new technology. Various IC implementations have been available for more than 15 years, and some improvements have been made over time. The AD8571/AD8572/AD8574 design offers a number of significant performance improvements over older versions while attaining a very substantial reduction in device cost. This section offers a simplified explanation of how the AD8571/AD8572/AD8574 are able to offer extremely low offset voltages and high openloop gains. As noted in the Amplifier Architecture section, each AD8571/AD8572/AD8574 op amp contains two internal amplifiers. One is used as the primary amplifier, and the other as an autocorrection, or nulling, amplifier. Each amplifier has an associated input offset voltage that can be modeled as a dc voltage source in series with the noninverting input. In Figure 50 and Figure 51, these are labeled as VOSA and VOSB, where A denotes the nulling amplifier and B denotes the primary amplifier. The open-loop gain for the +IN and −IN inputs of each amplifier is given as AX. Both amplifiers also have a third voltage input with an associated open-loop gain of BX. VOSB + VIN+ AB VIN– BB ΦB VOA VOSA + ΦA1 VOUT ΦB AA CM2 VNB –BA ΦA2 CM1 01104-050 The AD8571/AD8572/AD8574 can run from a single-supply voltage as low as 2.7 V. The extremely low offset voltage of 1 µV and no IMD products allow the amplifier to be easily configured for high gains without risk of excessive output voltage errors, which makes the AD8571/AD8572/AD8574 an ideal amplifier for applications requiring both dc precision and low distortion for ac signals. The extremely small temperature drift of 5 nV/°C ensures a minimum of offset voltage error over its −40°C to +125°C temperature range. These combined features make the AD8571/AD8572/AD8574 an excellent choice for a variety of sensitive measurement and automotive applications. BASIC AUTO-ZERO AMPLIFIER THEORY VNA Figure 50. Auto-Zero Phase of the Amplifier VOSB + VIN+ VOUT AB VIN– BB ΦB ΦA VOA VOSA + ΦB AA CM2 VNB –BA ΦA VNA CM1 01104-051 The AD8571/AD8572/AD8574 are CMOS amplifiers that achieve their high degree of precision through random frequency auto-zero stabilization. The autocorrection topology allows the AD8571/AD8572/AD8574 to maintain its low offset voltage over a wide temperature range, and the randomized auto-zero clock eliminates any inter-modulation distortion (IMD) errors at the amplifier output. Figure 51. Output Phase of the Amplifier There are two modes of operation determined by the action of two sets of switches in the amplifier: an auto-zero phase and an amplification phase. Rev. F | Page 15 of 28 AD8571/AD8572/AD8574 Data Sheet AUTO-ZERO PHASE In this phase, all ΦAX switches are closed, and all ΦB switches are open. Here, the nulling amplifier is taken out of the gain loop by shorting its two inputs together. Of course, there is a degree of offset voltage, shown as VOSA, inherent in the nulling amplifier, that maintains a potential difference between the +IN and −IN inputs. The nulling amplifier feedback loop is closed through ΦA2, and VOSA appears at the output of the nulling amplifier and on CM1, an internal capacitor in the AD8571/ AD8572/AD8574. Mathematically, this can be expressed in the time domain as VOA[t] = AAVOSA[t] − BAVOA[t] (1) For the sake of simplification, it can be assumed that the autocorrection frequency is much faster than any potential change in VOSA or VOSB. This is a good assumption because changes in offset voltage are a function of temperature variation or longterm wear time, both of which are much slower than the auto-zero clock frequency of the AD8571/AD8572/AD8574, which effectively makes the VOS time invariant, and Equation 5 can be rewritten as VOA [t ] = AAVIN [t ] + VOA [t ] = 1 + BA VOSA VOA [t ] = A A V IN [t ] + 1 + B A (2) The previous equations show that the offset voltage of the nulling amplifier times a gain factor appears at the output of the nulling amplifier and thus on the CM1 capacitor. AMPLIFICATION PHASE When the ΦB switches close and the ΦAX switches open for the amplification phase, the offset voltage remains on CM1 and essentially corrects any error from the nulling amplifier. The voltage across CM1 is designated as VNA. The potential difference between the two inputs to the primary amplifier is designated as VIN, or VIN = (VIN+ − VIN−). The output of the nulling amplifier can then be expressed as VOA[t] = AA(VIN[t] − VOSA[t]) − BAVNA[t] (3) Because ΦAX is now open and there is no place for CM1 to discharge, the voltage (VNA) at the present time (t) is equal to the voltage at the output of the nulling amp (VOA) at the time when ΦAX is closed. If the period of the autocorrection switching frequency is designated as TS, the amplifier switches between phases every 0.5 × TS. Therefore, in the amplification phase 1 VNA [t ] = VNA t − TS 2 (4) and substituting Equation 4 and Equation 2 into Equation 3 yields 1 A A B AVOSA t − TS 2 (5) VOA [t ] = A AVIN [t ] + A AVOSA [t ] − 1 + BA 1 + BA (6) or This can also be expressed as A AVOSA [t ] AA (1 + BA )VOSA − AA BAVOSA (7) Here, the auto-zeroing becomes apparent. Note that the VOS term is reduced by a factor of 1 + BA, which shows how the nulling amplifier has greatly reduced its own offset voltage error even before correcting the primary amplifier. Therefore, the primary amplifier output voltage is the voltage at the output of the AD8571/AD8572/AD8574 amplifier. It is equal to VOUT[t] = AB(VIN[t] + VOSB) + BBVNB (8) In the amplification phase, VOA = VNB, so this can be rewritten as VOUT [t ] = V ABVIN [t ] + ABVOSB + BB AA VIN [t ] + OSA 1 + BA (9) Combining terms yield VOUT [t ] = VIN [t ](AB + AA BB ) + AA B BVOSA + ABVOSB 1 + BA (10) The AD8571/AD8572/AD8574 architecture is optimized in such a way that AA = AB, BA = BB, and BA >> 1. In addition, the gain product to AABB is much greater than AB. Therefore, Equation 10 can be simplified to VOUT[t] = VIN[t]AABA + AA(VOSA+ VOSB) (11) Most obvious is the gain product of both the primary and nulling amplifiers. This AABA term is what gives the AD8571/AD8572/ AD8574 extremely high open-loop gain. To understand how VOSA and VOSB relate to the overall effective input offset voltage of the complete amplifier, set up the generic amplifier equation of VOUT = k × (VIN + VOS, EFF) (12) where: k is the open-loop gain of an amplifier. VOS, EFF is its effective offset voltage. Putting Equation 12 into the form of Equation 11 gives VOUT[t] = VIN[t]AABA + VOS, EFFAABA Rev. F | Page 16 of 28 (13) Data Sheet AD8571/AD8572/AD8574 Therefore, V+ R1 (14) BA AD8572 R2 R1 VIN1 VIN2 GUARD RING Thus, the offset voltages of both the primary and nulling amplifiers are reduced by the gain factor BA, which takes a typical input offset voltage from several millivolts down to an effective input offset voltage of submicrovolts. This autocorrection scheme makes the AD8571/AD8572/AD8574 amplifiers extremely precise. GUARD RING VREF 01104-053 VOSA + VOSB VREF V– Figure 53. Top View of AD8572 SOIC Layout with Guard Rings Other potential sources of offset error are thermoelectric voltages on the circuit board. This voltage, also called Seebeck voltage, occurs at the junction of two dissimilar metals and is proportional to the junction temperature. The most common metallic junctions on a circuit board are solder-to-board trace and solder-to-component lead. Figure 54 shows a cross-section view of the thermal voltage error sources. When the temperature of the PCB at one end of the component (TA1) differs from the temperature at the other end (TA2), the Seebeck voltages are not equal, resulting in a thermal voltage error. HIGH GAIN, CMRR, AND PSRR Common-mode and power supply rejection are indications of the amount of offset voltage an amplifier has as a result of a change in its input common-mode or power supply voltages. As shown in the Amplification Phase section, the autocorrection architecture of the AD8571/AD8572/AD8574 allows it to effectively minimize offset voltages. The technique also corrects for offset errors caused by common-mode voltage swings and power supply variations, which results in superb CMRR and PSRR figures in excess of 130 dB. Because the autocorrection occurs continuously, these figures can be maintained across the temperature range of the device (−40°C to +125°C). This thermocouple error can be reduced by using dummy components to match the thermoelectric error source. Placing the dummy component as close as possible to its partner ensures that both Seebeck voltages are equal, thus canceling the thermocouple error. Maintaining a constant ambient temperature on the circuit board further reduces this error. The use of a ground plane helps distribute heat throughout the board and also reduces EMI noise pickup. MAXIMIZING PERFORMANCE THROUGH PROPER LAYOUT To achieve the maximum performance of the extremely high input impedance and low offset voltage of the AD8571/AD8572/ AD8574, care should be taken in the circuit board layout. The PCB surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board reduces surface moisture and provides a humidity barrier, reducing parasitic resistance on the board. The use of guard rings around the amplifier inputs further reduces leakage currents. Figure 52 shows how the guard ring should be configured, and Figure 53 shows the top view of how a surface-mount layout can be arranged. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. By setting the guard ring voltage equal to the voltage at the non-inverting input, parasitic capacitance is minimized as well. For further reduction of leakage currents, components can be mounted to the PCB using Teflon® standoff insulators. COMPONENT LEAD VSC1 VTS1 – – + + SURFACE MOUNT COMPONENT SOLDER VSC2 – + + VTS2 – PC BOARD TA2 TA1 COPPER TRACE IF TA1 ≠ TA2, THEN VTS1 + VSC1 ≠ VTS2 + VSC2 01104-054 VOS , EFF ≈ R2 Figure 54. Mismatch in Seebeck Voltages Causes a Thermoelectric Voltage Error RF R1 VIN RS = R1 AD8572 AD8571/AD8572/ AD8574 AV = 1 + (RF /R1) RS SHOULD BE PLACED IN CLOSE PROXIMITY AND ALIGNMENT TO R1 TO BALANCE SEEBECK VOLTAGES VIN Figure 55. Using Dummy Components to Cancel Thermoelectric Voltage Errors VOUT AD8572 01104-055 AD8572 VOUT VIN VOUT VOUT 01104-052 VIN Figure 52. Guard Ring Layout and Connections to Reduce PCB Leakage Currents Rev. F | Page 17 of 28 AD8571/AD8572/AD8574 Data Sheet 1/f NOISE CHARACTERISTICS 0 6 7 8 9 OUTPUT SIGNAL 01104-057 6 7 8 9 10 VS = 5V AV = 60dB OUTPUT SIGNAL –40 –60 –80 –120 0 1 2 3 4 5 6 7 8 9 10 FREQUENCY (kHz) Figure 58. Spectral Analysis of AD8572 in High Gain with an Input Signal 01104-056 5 5 –100 –120 4 4 –20 –100 3 3 0 –80 2 2 Figure 58 shows the spectral output of an AD8572 configured in a high gain (60 dB) with a 1 mV input signal applied. Note the absence of any IMD products in the spectrum. The signal-tonoise ratio (SNR) of the output signal is better than 60 dB, or 0.1%. –60 1 1 Figure 57. Spectral Analysis of AD8571/AD8572/AD8574 Output with 60 dB Gain –40 –160 0 FREQUENCY (kHz) VS = 5V AV = 0dB –140 –80 –120 0 –20 –60 –100 RANDOM AUTO-ZERO CORRECTION ELIMINATES INTERMODULATION DISTORTION The AD8571/AD8572/AD8574 can be used as conventional op amps for gains up to 1 MHz. The auto-zero correction frequency of the device continuously varies, based on a pseudorandom generator with a uniform distribution from 2 kHz to 4 kHz. The randomization of the autocorrection clock creates a continuous randomization of IMD products that show up as simple broadband noise at the output of the amplifier. This broadband noise naturally combines with the amplifier voltage noise in a root-squared-sum fashion, resulting in an output free IMD. Figure 56 shows the spectral output of an AD8572 with the amplifier configured for unity gain and the input grounded. Figure 57 shows the spectral output with the amplifier configured for a gain of 60 dB. –40 01104-058 Because the AD8571/AD8572/AD8574 amplifiers are selfcorrecting op amps, they do not have increasing flicker noise at lower frequencies. In essence, low frequency noise is treated as a slowly varying offset error and is greatly reduced with autocorrection. The correction becomes more effective as the noise frequency approaches dc, offsetting the tendency of the noise to increase exponentially as frequency decreases, which allows the AD8571/AD8572/AD8574 to have lower noise near dc than standard low noise amplifiers that are susceptible to 1/f noise. VS = 5V AV = 60dB –20 OUTPUT SIGNAL Another advantage of auto-zero amplifiers is their ability to cancel flicker noise. Flicker noise, also known as 1/f noise, is noise inherent in the physics of semiconductor devices and increases 3 dB for every octave decrease in frequency. The 1/f corner frequency of an amplifier is the frequency at which the flicker noise is equal to the broadband noise of the amplifier. At lower frequencies, flicker noise dominates, causing higher degrees of error for sub-Hertz frequencies or dc precision applications. 10 FREQUENCY (kHz) Figure 56. Spectral Analysis of AD8572 Output in Unity Gain Configuration Rev. F | Page 18 of 28 Data Sheet AD8571/AD8572/AD8574 BROADBAND AND EXTERNAL RESISTOR NOISE CONSIDERATIONS The total broadband noise output from any amplifier is primarily a function of three types of noise: input voltage noise from the amplifier, input current noise from the amplifier, and Johnson noise from the external resistors used around the amplifier. Input voltage noise, or en, is strictly a function of the amplifier used. The Johnson noise from a resistor is a function of the resistance and the temperature. Input current noise, or in, creates an equivalent voltage noise proportional to the resistors used around the amplifier. These noise sources are not correlated with each other and their combined noise sums in a rootsquared-sum fashion. The full equation is given as en, TOTAL = [en2 + 4kTrs + (inrs)2]1/2 (15) INPUT OVERVOLTAGE PROTECTION where: en is the input voltage noise of the amplifier. in is the input current noise of the amplifier. rs is the source resistance connected to the noninverting terminal. k is Boltzmann’s constant (1.38 × 10−23 J/K). T is the ambient temperature in Kelvin (K = 273.15 + °C). The input voltage noise density, en, of the AD8571/AD8572/ AD8574 is 51 nV/√Hz, and the input noise, in, is 2 fA/√Hz. The en, TOTAL is dominated by the input voltage noise provided that the source resistance is less than 172 kΩ. With source resistance greater than 172 kΩ, the overall noise of the system is dominated by the Johnson noise of the resistor itself. Because the input current noise of the AD8571/AD8572/ AD8574 is very small, in does not become a dominant term unless rs > 4 GΩ, which is an impractical value of source resistance. The total noise, en, TOTAL, is expressed in volts-per-square-root Hertz, and the equivalent rms noise over a certain bandwidth can be found as en = en, TOTAL × BW The output overdrive recovery for an autocorrection amplifier is defined as the time it takes for the output to correct to its final voltage from an overload state. It is measured by placing the amplifier in a high gain configuration with an input signal that forces the output voltage to the supply rail. The input voltage is then stepped down to the linear region of the amplifier, usually to halfway between the supplies. The time from the input signal step-down to the output settling to within 100 μV of its final value is the overdrive recovery time. Many autocorrection amplifiers require a number of auto-zero clock cycles to recover from output overdrive, and some can take several milliseconds for the output to settle properly. (16) Although the AD8571/AD8572/AD8574 are rail-to-rail input amplifiers, care should be taken to ensure that the potential difference between the inputs does not exceed 5 V. Under normal operating conditions, the amplifier corrects its output to ensure that the two inputs are at the same voltage. However, if the device is configured as a comparator, or is under some unusual operating condition, the input voltages may be forced to different potentials, which could cause excessive current to flow through the internal diodes in the AD8571/AD8572/AD8574 used to protect the input stage against overvoltage. If either input exceeds either supply rail by more than 0.3 V, large amounts of current begin to flow through the ESD protection diodes in the amplifier. These diodes are connected between the inputs and each supply rail to protect the input transistors against an electrostatic discharge event and are normally reverse-biased. However, if the input voltage exceeds the supply voltage, these ESD diodes become forward-biased. Without current-limiting, excessive amounts of current can flow through these diodes, causing permanent damage to the device. If inputs are subject to overvoltage, appropriate series resistors should be inserted to limit the diode current to less than 2 mA. where BW is the bandwidth of interest in Hertz. OUTPUT PHASE REVERSAL OUTPUT OVERDRIVE RECOVERY Output phase reversal occurs in some amplifiers when the input common-mode voltage range is exceeded. As common-mode voltage moves outside the common-mode range, the outputs of these amplifiers suddenly jump in the opposite direction to the supply rail. This is the result of the differential input pair shutting down, causing a radical shifting of internal voltages that results in the erratic output behavior. The AD8571/AD8572/AD8574 amplifiers have an excellent overdrive recovery of only 200 μs from either supply rail. This characteristic is particularly difficult for autocorrection amplifiers because the nulling amplifier requires a substantial amount of time to error correct the main amplifier back to a valid output. Figure 29 and Figure 30 show the positive and negative overdrive recovery times for the AD8571/AD8572/ AD8574. The AD8571/AD8572/AD8574 amplifiers have been carefully designed to prevent any output phase reversal, provided that both inputs are maintained within the supply voltages. If one or both inputs exceed either supply voltage, a resistor should be placed in series with the input to limit the current to less than 2 mA to ensure that the output does not reverse its phase. Rev. F | Page 19 of 28 AD8571/AD8572/AD8574 Data Sheet CAPACITIVE LOAD DRIVE The AD8571/AD8572/AD8574 have excellent capacitive load driving capabilities and can safely drive up to 10 nF from a single 5 V supply. Although the device is stable, capacitive loading limits the bandwidth of the amplifier. Capacitive loads also increase the amount of overshoot and ringing at the output. The RC snubber network shown in Figure 59 can be used to reduce the capacitive load ringing and overshoot. 5V – AD8571/ AD8572/ AD8574 The optimum value for the resistor and capacitor is a function of the load capacitance and is best determined empirically because actual CL includes stray capacitances and can differ substantially from the nominal capacitive load. Table 5 shows some snubber network values that can be used as starting points. Table 5. Snubber Network Values for Driving Capacitive Loads CL (nF) 1 4.7 10 Rx (Ω) 200 60 20 Cx 1 nF 0.47 µF 10 µF VOUT Rx 60Ω + 200mV p-p Cx 0.47µF CL 4.7nF POWER-UP BEHAVIOR 01104-059 VIN Figure 59. Snubber Network Configuration for Driving Capacitive Loads Although the snubber network does not recover the loss of amplifier bandwidth from the load capacitance, it does allow the amplifier to drive larger values of capacitance while maintaining a minimum of overshoot and ringing. Figure 60 shows the output of an AD8571/AD8572/AD8574 driving a 1 nF capacitor with and without a snubber network. At power-up, the AD8571/AD8572/AD8574 settle to a valid output within 5 μs. Figure 61 shows an oscilloscope photo of the output of the amplifier along with the power supply voltage. Figure 62 shows the test circuit. With the amplifier configured for unity gain, the device takes approximately 5 µs to settle to its final output voltage, hundreds of microseconds faster than many other autocorrection amplifiers. VOUT 10μs WITH SNUBBER 0V V+ 0V WITHOUT SNUBBER 100mV 1V 01104-061 VS = 5V CL = 4.7nF 01104-060 5µs BOTTOM TRACE = 2V/DIV TOP TRACE = 1V/DIV Figure 61. AD8571/AD8572/AD8574 Output Behavior at Power-Up Figure 60. Overshoot and Ringing Are Substantially Reduced Using a Snubber Network 100kΩ VSY = 0V TO 5V AD8571/ AD8572/ AD8574 01104-062 VOUT 100kΩ Figure 62. AD8571/AD8572/AD8574 Test Circuit for Power-Up Time Rev. F | Page 20 of 28 Data Sheet AD8571/AD8572/AD8574 APPLICATIONS INFORMATION R2 5 V PRECISION STRAIN GAGE CIRCUIT R1 The extremely low offset voltage of the AD8572 makes it an ideal amplifier for any application requiring accuracy with high gains, such as a weigh scale or strain gage. Figure 63 shows a configuration for a single-supply, precision strain gage measurement system. 2 × (R1 + R 2 ) 2 6 1kΩ REF192 3 A2 In an ideal difference amplifier, the ratio of the resistors is set equal to AV = 40mV FULL-SCALE R2 R1 CMRR = 20kΩ R2 100Ω A1 AD8572-A R3 17.4kΩ NOTE: USE 0.1% TOLERANCE RESISTORS. = (19) R3 CMRRMIN = The high common-mode rejection, high open-loop gain, and operation down to 3 V of the supply voltage make the AD8571/AD8572/AD8574 an excellent op amp choice for discrete single-supply instrumentation amplifiers. The common-mode rejection ratio of the AD8571/AD8572/ AD8574 is greater than 120 dB, but the CMRR of the system is also a function of the external resistor tolerances. The gain of the difference amplifier shown in Figure 64 is given as 1 (22) 2δ AD8574-A V2 3 V INSTRUMENTATION AMPLIFIER R2 R4 R1 = V 1 − V 2 1 + R2 R1 R3 + R 4 (21) 2R1R4 − 2R2R3 In the 3-op amp instrumentation amplifier configuration shown in Figure 65, the output difference amplifier is set to unity gain with all four resistors equal in value. If the tolerance of the resistors used in the circuit is given as δ, the worst-case CMRR of the instrumentation amplifier is VOUT 0V TO 4V R4 100Ω (20) R1R4 + 2R2R4 + R2R3 Figure 63. 5 V Precision Strain Gage Amplifier VOUT R4 Due to finite component tolerance, the ratio between the four resistors is not exactly equal, and any mismatch results in a reduction of common-mode rejection from the system. Referring to Figure 64, the exact common-mode rejection ratio can be expressed as 4 AD8572-B R1 17.4kΩ 350Ω LOAD CELL Figure 64. Using the AD8571/AD8572/AD8574 as a Difference Amplifier 01104-063 4.0V (V1 – V2) RG R R R R R VOUT R V1 AD8574-B VOUT = 1 + AD8574-C RTRIM 2R (V1 – V2) RG 01104-065 5V 12kΩ R2 R2 R4 , THEN VOUT = = R3 R1 R1 VOUT = AV (V1 − V2) Using the values given in Figure 63, the output voltage linearly varies from 0 V with no strain to 4 V under full strain. Q1 2N2222 OR EQUIVALENT IF Set the output voltage of the system to where RB is the resistance of the load cell. 2.5V AD8571/ AD8572/ AD8574 R4 (17) RB VOUT R3 V1 01104-064 The REF192 provides a 2.5 V precision reference voltage for A2. The A2 amplifier boosts this voltage to provide a 4.0 V reference for the top of the strain gage resistor bridge. Q1 provides the current drive for the 350 Ω bridge network. A1 is used to amplify the output of the bridge with the full-scale output voltage equal to V2 Figure 65. Discrete Instrumentation Amplifier Configuration (18) Therefore, using 1% tolerance resistors results in a worst-case system CMRR of 0.02, or 34 dB. To achieve high commonmode rejection, either high precision resistors or an additional trimming resistor, as shown in Figure 65, should be used. The value of this trimming resistor should be equal to the value of R multiplied by its tolerance. For example, using 10 kΩ resistors with 1% tolerance would require a series trimming resistor equal to 100 Ω. Rev. F | Page 21 of 28 AD8571/AD8572/AD8574 Data Sheet HIGH ACCURACY THERMOCOUPLE AMPLIFIER through R2. The monitor output is given by Figure 66 shows a K-type thermocouple amplifier configuration with cold-junction compensation. Even from a 5 V supply, the AD8571 can provide enough accuracy to achieve a resolution of better than 0.02°C from 0°C to 500°C. D1 is used as a temperature measuring device to correct the cold-junction error from the thermocouple and should be placed as close as possible to the two terminating junctions. With the thermocouple measuring tip immersed in a 0°C ice bath, R6 should be adjusted until the output is at 0 V. Monitor Output = R2 × (RSENSE/R1) × IL Using the components shown in Figure 67, the monitor output transfer function is 2.49 V/A. REF02EZ 2 6 0.1µF 0.1µF S M1 Si9433 R5 40.2kΩ + 1/2 AD8572 – LOAD 1 4 G D MONITOR OUTPUT 01104-067 R2 2.49kΩ Figure 68 shows the low-side monitor equivalent. In this circuit, the input common-mode voltage to the AD8572 is at or near ground. Again, a 0.1 Ω resistor provides a voltage drop proportional to the return current. The output voltage is given as R9 124kΩ 5V + 10µF D1 + 8 + Figure 67. High-Side Load Current Monitor 1N4148 – 3 2 4 – IL V+ R1 100Ω 5V R1 10.7kΩ R2 2.74kΩ R8 453Ω R2 × R SENSE × I L Monitor Output = V+ − R1 0.1µF 2 7 (24) 6 R4 5.62kΩ R3 53.6Ω 3 4 AD8571 0V TO 5V (0°C TO 500°C) For the component values shown in Figure 68, the monitor output transfer function is V+ − 2.49 V/A. V+ Figure 66. Precision K-Type Thermocouple Amplifier with Cold-Junction Compensation R2 2.49kΩ MONITOR OUTPUT PRECISION CURRENT METER V+ Q1 V+ Because of its low input bias current and superb offset voltage at single-supply voltages, the AD8571/AD8572/AD8574 are excellent amplifiers for precision current monitoring. Its rail-torail input allows the amplifier to be used as either a high-side or a low-side current monitor. Using both amplifiers in the AD8572 provides a simple method to monitor both current supply and return paths for load or fault detection. Figure 67 shows a high-side current monitor configuration. Here, the input common-mode voltage of the amplifier is at or near the positive supply voltage. The rail-to-rail input of the amplifier provides a precise measurement, even with the input common-mode voltage at the supply voltage. The CMOS input structure does not draw any input bias current, ensuring a minimum of measurement error. The 0.1 Ω resistor creates a voltage drop to the noninverting input of the AD8571/AD8572/AD8574. The output of the amplifier is corrected until this voltage appears at the inverting input, which creates a current through R1 that in turn flows 2 R1 100Ω LOAD 3 1/2 AD8572 RSENSE 0.1Ω IL 01104-068 R6 200Ω 01104-066 K-TYPE THERMOCOUPLE 40.7µV/°C RSENSE 0.1Ω V+ Using the values shown in Figure 66, the output voltage tracks temperature at 10 mV/°C. For a wider range of temperature measurement, R9 can be decreased to 62 kΩ. This creates a 5 mV/°C change at the output, allowing measurements of up to 1000°C. 12V (23) Figure 68. Low-Side Load Current Monitor PRECISION VOLTAGE COMPARATOR The AD8571/AD8572/AD8574 can be operated open loop and used as a precision comparator. The AD8571/AD8572/AD8574 have less than 50 µV of offset voltage when they run in this configuration. The slight increase of offset voltage stems from the fact that the autocorrection architecture operates with the lowest offset in a closed-loop configuration, that is, one with negative feedback. With 50 mV of overdrive, the device has a propagation delay of 15 µs on the rising edge and 8 µs on the falling edge. Care should be taken to ensure that the maximum differential voltage of the device is not exceeded. For more information, see the Input Overvoltage Protection section. Rev. F | Page 22 of 28 AD8571/AD8572/AD8574 Data Sheet OUTLINE DIMENSIONS 3.20 3.00 2.80 8 3.20 3.00 2.80 5.15 4.90 4.65 5 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.80 0.55 0.40 0.23 0.09 6° 0° 0.40 0.25 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 69. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 1 5 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 70. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. F | Page 23 of 28 012407-A 8 4.00 (0.1574) 3.80 (0.1497) AD8571/AD8572/AD8574 Data Sheet 3.10 3.00 2.90 8 5 4.50 4.40 4.30 1 6.40 BSC 4 PIN 1 0.65 BSC 0.15 0.05 1.20 MAX COPLANARITY 0.10 0.30 0.19 SEATING 0.20 PLANE 0.09 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AA Figure 71. 8-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8) Dimensions shown in millimeters 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 SEATING PLANE 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 72. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Rev. F | Page 24 of 28 0.75 0.60 0.45 061908-A 1.05 1.00 0.80 Data Sheet AD8571/AD8572/AD8574 8.75 (0.3445) 8.55 (0.3366) 8 14 1 7 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 6.20 (0.2441) 5.80 (0.2283) 0.50 (0.0197) 0.25 (0.0098) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 060606-A 4.00 (0.1575) 3.80 (0.1496) Figure 73. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model1 AD8571ARZ AD8571ARZ-REEL AD8571ARZ-REEL7 AD8571ARMZ AD8571ARMZ-REEL AD8572AR AD8572AR-REEL AD8572AR-REEL7 AD8572ARZ AD8572ARZ-REEL AD8572ARZ-REEL7 AD8572ARUZ AD8572ARUZ-REEL AD8574ARZ AD8574ARZ-REEL AD8574ARZ-REEL7 AD8574ARU AD8574ARU-REEL AD8574ARUZ AD8574ARUZ-REEL 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead TSSOP 8-Lead TSSOP 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked. Rev. F | Page 25 of 28 Package Option R-8 R-8 R-8 RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 RU-8 RU-8 R-14 R-14 R-14 RU-14 RU-14 RU-14 RU-14 Branding AJA# AJA# AD8571/AD8572/AD8574 Data Sheet NOTES Rev. F | Page 26 of 28 Data Sheet AD8571/AD8572/AD8574 NOTES Rev. F | Page 27 of 28 AD8571/AD8572/AD8574 Data Sheet NOTES ©1999–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01104-0-6/15(F) Rev. F | Page 28 of 28