NUP1301ML3T1G, SZNUP1301ML3T1G Low Capacitance Diode Array for ESD Protection in a Single Data Line NUP1301ML3T1G is a MicroIntegration device designed to provide protection for sensitive components from possible harmful electrical transients; for example, ESD (electrostatic discharge). http://onsemi.com Features Low Capacitance (0.9 pF Maximum) Single Package Integration Design Provides ESD Protection for JEDEC Standards JESD22 SOT−23 CASE 318 STYLE 11 Machine Model = Class C Human Body Model = Class 3B Protection for IEC61000−4−2 (Level 4) 8.0 kV (Contact) 15 kV (Air) Ensures Data Line Speed and Integrity Fewer Components and Less Board Space Direct the Transient to Either Positive Side or to the Ground SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable Pb−Free Package is Available* Applications T1/E1 Secondary IC Protection T3/E3 Secondary IC Protection HDSL, IDSL Secondary IC Protection Video Line Protection Microcontroller Input Protection Base Stations I2C Bus Protection ANODE 1 CATHODE 2 3 CATHODE/ANODE MARKING DIAGRAM 53 MG G 1 53 = Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Package Shipping† NUP1301ML3T1G SOT−23 (Pb−Free) 3,000 / Tape & Reel SZNUP1301ML3T1G SOT−23 (Pb−Free) 3,000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2012 February, 2012 − Rev. 6 1 Publication Order Number: NUP1301ML3T1/D NUP1301ML3T1G, SZNUP1301ML3T1G MAXIMUM RATINGS (Each Diode) (TJ = 25C unless otherwise noted) Rating Symbol Value Unit Reverse Voltage VR 70 Vdc Forward Current IF 215 mAdc IFM(surge) 500 mAdc Repetitive Peak Reverse Voltage VRRM 70 V Average Rectified Forward Current (Note 1) (averaged over any 20 ms period) IF(AV) Repetitive Peak Forward Current IFRM Non−Repetitive Peak Forward Current t = 1.0 ms t = 1.0 ms t = 1.0 S IFSM Peak Forward Surge Current mA 715 450 mA A 2.0 1.0 0.5 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. FR−5 = 1.0 0.75 0.062 in. THERMAL CHARACTERISTICS Characteristic Thermal Resistance Junction−to−Ambient Symbol Max Unit RqJA 625 C/W Lead Solder Temperature Maximum 10 Seconds Duration TL Junction Temperature TJ −65 to 150 C Storage Temperature Tstg −65 to +150 C C 260 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Each Diode) Characteristic Symbol Min Typ Max 70 − − − − − − − − 2.5 30 50 − − 0.9 − − − − − − − − 715 855 1000 1250 Unit OFF CHARACTERISTICS V(BR) Reverse Breakdown Voltage (I(BR) = 100 mA) Reverse Voltage Leakage Current (VR = 70 Vdc) (VR = 25 Vdc, TJ = 150C) (VR = 70 Vdc, TJ = 150C) IR Diode Capacitance (between I/O and ground) (VR = 0, f = 1.0 MHz) CD Forward Voltage (IF = 1.0 mAdc) (IF = 10 mAdc) (IF = 50 mAdc) (IF = 150 mAdc) VF 2. FR−5 = 1.0 0.75 0.062 in. 3. Alumina = 0.4 0.3 0.024 in, 99.5% alumina. 4. Include SZ-prefix devices where applicable. http://onsemi.com 2 Vdc mAdc pF mVdc NUP1301ML3T1G, SZNUP1301ML3T1G ESD Input Signal Figure 1. ESD Test Circuit APPLICATION NOTE Electrostatic Discharge surge to the supply rail or ground. This method has several advantages including low loading capacitance, fast response time, and inherent bidirectionality (within the reference voltages). See Figure 1 for the test circuit used to verify the ESD rating for this device. A common means of protecting high−speed data lines is to employ low−capacitance diode arrays in a rail−to−rail configuration. Two devices per line are connected between two fixed voltage references such as VCC and ground. When the transient voltage exceeds the forward voltage (VF) drop of the diode plus the reference voltage, the diodes direct the http://onsemi.com 3 NUP1301ML3T1G, SZNUP1301ML3T1G PACKAGE DIMENSIONS SOT−23 (TO−236) CASE 318−08 ISSUE AP NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. D SEE VIEW C 3 HE E DIM A A1 b c D E e L L1 HE q c 1 2 e b 0.25 q A L A1 MIN 0.89 0.01 0.37 0.09 2.80 1.20 1.78 0.10 0.35 2.10 0 MILLIMETERS NOM MAX 1.00 1.11 0.06 0.10 0.44 0.50 0.13 0.18 2.90 3.04 1.30 1.40 1.90 2.04 0.20 0.30 0.54 0.69 2.40 2.64 −−− 10 MIN 0.035 0.001 0.015 0.003 0.110 0.047 0.070 0.004 0.014 0.083 0 INCHES NOM 0.040 0.002 0.018 0.005 0.114 0.051 0.075 0.008 0.021 0.094 −−− MAX 0.044 0.004 0.020 0.007 0.120 0.055 0.081 0.012 0.029 0.104 10 STYLE 11: PIN 1. ANODE 2. CATHODE 3. CATHODE−ANODE L1 VIEW C SOLDERING FOOTPRINT 0.95 0.037 0.95 0.037 2.0 0.079 0.9 0.035 SCALE 10:1 0.8 0.031 mm Ǔ ǒinches ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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