Recommended SX1279 Settings for EU868 LoRaWAN Network Operation

AN1200.24
SX1276 Settings for LoRaWAN
WIRELESS & SENSING PRODUCTS
APPLICATION NOTE
AN1200.24
RecommendedSX1276Settingsfor
EU868LoRaWANNetworkOperation
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AN1200.24
SX1276 Settings for LoRaWAN
WIRELESS & SENSING PRODUCTS
APPLICATION NOTE
TableofContent
1
Introduction.....................................................................................................................................................3
2
UplinkTransmissions.................................................................................................................................3
3
2.1
LoRa Mode .............................................................................................................. 3
2.2
GFSK Mode .............................................................................................................. 4
DownlinkReceptionSlotsFollowinganUplink.............................................................................5
3.1
3.1.1
Register Settings............................................................................................... 6
3.1.2
RX Window Precise Timing ............................................................................... 7
3.2
4
LORA Mode ............................................................................................................. 6
GFSK Mode .............................................................................................................12
3.2.1
Register Settings..............................................................................................12
3.2.2
RX Window Precise Timing in GFSK Mode .......................................................14
RandomNumberGenerationforCryptography.........................................................................15
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AN1200.24
SX1276 Settings for LoRaWAN
WIRELESS & SENSING PRODUCTS
APPLICATION NOTE
1 Introduction
This application note presents the recommended setup of the SX1276 radio transceiver operating in
a LoRaWAN network.
2 Uplink Transmissions
2.1 LoRa Mode
Uplink transmissions can use the following LoRa settings:
1. LoRa modulation with 125 kHz bandwidth, SF7 to SF12.
2. LoRa modulation with 250 kHz bandwidth, SF7 only. Corresponding to the high speed
channel
The following radio settings should be used:
SX1276 Register (address)
Register bit field (bit #)
Values
Note
RegOpMode (0x01)
RegPaRamp (0x0A)
RegModemConfig1 (0x1D)
LongRangeMode[7]
Mode[2:0]
PaRamp[3:0]
Bw[7:4]
‘1’
‘011’
‘1000’
‘0111’ or ‘1000’
RegModemConfig2 (0x1E)
CodingRate[3:1]
ImplicitHeaderModeOn[0]
SpreadingFactor[7:4]
‘001’
‘0’
‘0111’ to ‘1100’
‘1’
RegModemConfig3 (0x26)
RxPayloadCrcOn[2]
LowDataRateOptimize[0]
LoRa mode enabled
Tx mode
50 us PA Ramp-up time
‘0111’ for 125kHz modulation Bandwidth
‘1000’ for 250kHz modulation Bandwidth
4/5 error coding rate
Packets have up-front header
with 125kHz bandwidth :
‘0111’ (SF7) = 6kbit/s
‘1100’ (SF12) = 300 bit/s
(only SF7 is supported with 250kHz BW)
CRC enable
Test39 (0x39)
LoRa sync word
0x34
‘0’ or ‘1’
‘0’ when Spreading Factor is <= 10
‘1’ when Spreading Factor is >= 11
Set sync word for LoRaWAN networks
(default is 0x12 for other networks)
All registers not explicitly mentioned can stay with their default value.
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SX1276 Settings for LoRaWAN
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2.2 GFSK Mode
The LoRaWAN specification defines a high speed uplink channel using 50kbit/s GFSK modulation. The
following radio settings should be used (all settings omitted should be left to their default value)
General and Transmitter settings
• Modulation = FSK
• Fdev = +/-25kHz (modulation index = 1)
• Bit rate setting = 50kbit/s
• Gaussian filter ON
• Filter setting : BT=0.5
• Output Power setting: hardware dependent
• PA selection: hardware dependent
SX1276 Register (address)
Register bit field (bit #)
Values
Note
RegOpMode (0x01)
LongRangeMode[7]
ModulationType[6:5]
Mode[2:0]
ModulationShaping[6:5]
BitRate[15:8]
BitRate[7:0]
Fdev[13:8]
Fdev[7:0]
‘0’
‘00’
‘011’
‘10’
0x02
0x80
0x01
0x99
FSK/OOK mode enable
FSK Modulation scheme
Tx mode
Gaussian filter BT = 0.5
BitRate set to 50kbps
RegPaRamp (0x0A)
RegBitrateMsb (0x02)
RegBitrateLsb (0x03)
RegFdevMsb (0x04)
RegFdevLsb (0x05)
Frequency deviation set to +/-25kHz
Frame and Packet Handler settings
Figure 1: Packet Handler Format
•
•
•
•
•
•
Packet Mode : this mode inserts a PHY header to support variable payload length
Preamble Length = 5 bytes
Sync Word= 3 bytes : 0xC194C1
Variable Length frame format
DC-free data encoding = Whitening
CrcOn=1, CrcAutoclearOn=1
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SX1276 Settings for LoRaWAN
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SX1276 Register (address)
Register bit field (bit #)
Values
Note
RegPreambleMsb (0x25)
RegPreambleLsb (0x26)
RegSyncConfig (0x27)
0x00
0x05
‘00’
‘0’
‘1’
‘002’
‘1’
‘10’
‘1’
‘0’
‘00’
‘0’
‘1’
5 Bytes of preamble for each packet
RegPacketConfig2 (0x31)
PreambleSize[15:8]
PreambleSize[7:0]
AutoRestartRxMode[7:6]
PreamblePolarity[5]
SyncOn[4]
SyncSize[2:0]
PacketFormat[7]
DcFree[6:5]
CrcOn[4]
CrcAutoClearOff[3]
AddressFiltering[2:1]
CrcWhiteningType[0]
DataMode[6]
RegSyncValue1 (0x28)
RegSyncValue2 (0x29)
RegSyncValue2 (0x2A)
SyncValue[63:56]
SyncValue[55:48]
SyncValue[47:40]
0xC1
0x94
0xC1
Sync Address is 0xC194C1
RegPacketConfig1 (0x30)
AutoRestart OFF
Preamble 0xAA
Sync Address enable
3 Bytes of Sync Word
Variable length packets
Whitening encoding enable
Enable CRC calculation
Clear FIFO when CRC check fails
No address filtering
CCITT CRC and Whitening implementation
Packet Mode
3 Downlink Reception Slots Following an Uplink
A LoRaWAN node opens two reception slots for potential downlink communications after each uplink
transmissions. The delay between the end of a transmission (signaled by the TxDone IRQ) and the
beginning of the reception slot is constant and defined extremely precisely to minimize the reception
current overhead on the end-point side. Most of the time this reception slot will not be used by the
gateways, id no frame will be received. Therefore, to minimize the current consumption the radio is
programmed to listen to the channel for the minimum time required to detect with certainty the
presence or absence of a preamble. In the absence of a preamble, the radio goes back to stand-by
mode.
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SX1276 Settings for LoRaWAN
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APPLICATION NOTE
3.1 LORA Mode
3.1.1
Register Settings
In LoRa mode this is achieved simply by using the Receive Single mode.
SX1276 Register (address)
Register bit field (bit #)
Values
Note
RegOpMode (0x01)
LongRangeMode[7]
Mode[2:0]
LnaGain[7:5]
LnaBoostHf[1:0]
Bw[7:4]
‘1’
‘110’
‘001’
‘11’
‘0111’ or ‘1000’
CodingRate[3:1]
ImplicitHeaderModeOn[0]
‘001’
‘0’
LoRa mode enable
Receive Single mode
LNA gain set to the maximum value
LNA Boost enable
‘0111’ for 125kHz modulation Bandwidth
‘1000’ for 250kHz modulation Bandwidth
4/5 error coding rate
Packets have up-front header
RegModemConfig2 (0x1E)
SpreadingFactor[7:4]
‘0111’ to ‘1100’
‘1’
‘00’
RegSymbTimeoutLsb (0x1F)
RxPayloadCrcOn[2]
SymbTimeout[1:0]
SymbTimeout[7:0]
RegModemConfig3 (0x26)
LowDataRateOptimize[3]
‘0’ or ‘1’
RegMaxPayloadLength (0x23)
AgcAutoOn[2]
PayloadMaxLength[7:0]
‘1’
0x40
RegInvertIQ (0x33)
InvertIQ[6]
‘1’
Test39 (0x39)
LoRa sync word
0x34
RegLna (0x0C)
RegModemConfig1 (0x1D)
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0x05 or 0x08
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with 125kHz bandwidth :
‘0111’ (SF7) = 6kbit/s
‘1100’ (SF12) = 300 bit/s
(only SF7 is supported with 250kHz BW)
CRC enable
0x05 when Spreading Factor is >= 10
0x08 when Spreading Factor is <= 9
Length of the receiver window in
symbols. If no preamble is detected
during this time , the receiver goes back
to stand-by
‘0’ when Spreading Factor is <= 10
‘1’ when Spreading Factor is >= 11
LNA gain set by internal AGC loop
Sets the maximum possible downlink
payload size to 64 bytes. Packets with
payload greater than this threshold will
not be demodulated, receiver will
immediately go back to “stand-by” low
power mode
I and Q signals are inverted
Set sync word for LoRaWAN networks
(default is 0x12 for other networks)
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SX1276 Settings for LoRaWAN
WIRELESS & SENSING PRODUCTS
APPLICATION NOTE
3.1.2 RX Window Precise Timing
This paragraph explains the optimal RX start-up time and RX slot duration for the given timing
precision reachable by the end-device.
The downlink preamble transmitted by the gateways contains 8 symbols. The receiver requires 5
symbols to detect the preamble and synchronize. Therefore there must be a 5 symbols overlap
between the receive window and the transmitted preamble.
The gateway always initiates the transmission of the preamble 1 sec +/- 20uSec after the end of the
uplink. Therefore the beginning of the downlink preamble can be considered as a perfectly precise
reference for the rest of this calculation.
Notation:
BW
SF
Tsymb
RXwindow
RXoffset
RXerror
T_RX_early
T_RX_late
Signal modulation bandwidth in Hz
LORA spreading factor : 7 to 12
Duration of a LORA symbol =
sec
Length of the receive window
Offset in sec between the optimal receiver turn-on time and the
actual start of the gateway transmission
Maximum timing error of the receiver. The receiver will turn-on in a
[-RXerror : +Rxerror] sec interval around RXoffset
Earliest time at which the receiver can start and synchronize on the
downlink preamble
Latest time at which the receiver can start and synchronize on the
downlink preamble
Those variables are illustrated in the following diagram:
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SX1276 Settings for LoRaWAN
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APPLICATION NOTE
Downlink start: T = end_uplink + 1
second (+/- 20uSec)
Desired RX start
(without timing
error)
Actual RX start
RXwindow
actual RX window
RXerror (positive)
RXoffset
(negative)
Tsymb
Downlink preamble
8 symbols
Time
Figure 2: Typical Rx Window Timing
The following diagram illustrates the positioning of the earliest and latest possible receive windows
to achieve 5 overlapping symbols with the downlink preamble:
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SX1276 Settings for LoRaWAN
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Downlink start: T = Rx + 1 second
(+/- 20uSec)
T_RX_late
T_RX_early
Latest possible RX
window start
Earliest possible RX
window start
Latest RX window
Earliest RX window
Downlink preamble
8 symbols
Figure 3: Worst Case Rx Window Timings
From this diagram the following equation can be deduced:
• T_RX_late = 3 x Tsymb
• T_RX_early = 5 x Tsymb – RXwindow
Additionnaly the difference between T_RX_late and T_RX_early corresponds to the maximum timing
error range of the receiver therefore:
• T_RX_late – T_RX_early = 2 x RXerror
To allow this maximum timing error range the receiver should be programmed to ideally turn-on at
the mid-point between T_RX_late and T_RX_early , therefore:
• RXoffset = (T_RX_late + T_RX_early)/2
So assuming the RXerror parameter is set (RXerror is a direct consequence of a given design, it
depends on the oscillator precision, temperature drift, …)
We can deduce:
• RXwindow = 2 x Tsymb + 2 x RXerror
• RXoffset = 4 x Tsymb – Rxwindow/2
Because the minimum RXwindow must be at least 5 symbols long, the system always tolerates at
least an RXerror of at least 1.5 x Tsymb
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SX1276 Settings for LoRaWAN
WIRELESS & SENSING PRODUCTS
APPLICATION NOTE
Numerical application:
The sensor can achieve a +/- 1.5mSec timing drift after a 1sec sleep period and is using SF7/125kHz
At SF7/125kHz Tsymb = 1mSec
So we set RXerror = 1.5mSec
We deduce RXwindow = 2 x Tsymb + 2 x RXerror
= 2 x 128 / 125e3 + 3e-3 = 5mSec
The RXwindow is expressed in symbol unit in the SX1276 transceiver, at SF7 a symbol is 1mSec long
therefore the RWwindow corresponds to 5 symbols.
The sensor will programmed to start with RXoffset
= 4 x Tsymb – RXwindow/2
= 4e-3 – 2.5e-3 = 1.5e3.
Without timing error, the receiver should turn on exactly 1.5mSec after the beginning of the
downlink preamble.
The sensor can achieve a +/- 20mSec timing drift after a 1sec sleep period and is using SF7/125kHz
RXwindow = 2 x Tsymb + 2x RXerror = 42mSec , this is larger than 5 symbols , therefore we set
RXwindow to the immediatemy greater or equal length which is an integer multiple of Tsymb
• RXwindow = 42 x Tsymb = 42mSec
Then:
• RXoffset = 4 x Tsymb – RXwindow/2 = -17mSec
The receiver should be programmed to start 17mSec before the start of the downlink preamble
The same sensor but now using SF10/125kHz instead of SF7
At SF10/125kHz Tsymb = 8.2mSec
RXwindow = 2 x Tsymb + 2x RXerror = 56.4mSec , this is larger than 5 symbols , therefore we set
RXwindow to the immediately greater or equal length which is an integer multiple of Tsymb
• RXwindow = 7 x Tsymb = 57.4mSec
Then:
• RXoffset = 4 x Tsymb – RXwindow/2 = 4.1mSec
The receiver should be programmed to start 4.1mSec after the start of the downlink preamble
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SX1276 Settings for LoRaWAN
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APPLICATION NOTE
The following tables give a few numerical examples for various SF / BW/ timing error sets:
Rxerror +/- 1.5 mSec
BW 125 kHz
SF
7
8
9
10
11
12
Tsymb
RXoffset
(mSec)
1.0
2.0
4.1
8.2
16.4
32.8
(mSec)
1.5
3.1
6.1
12.3
24.6
49.2
RX window
Symb
5.0
5.0
5.0
5.0
5.0
5.0
mSec
5.1
10.2
20.5
41.0
81.9
163.8
Rxerror +/- 20 mSec
BW 250 kHz
SF
7
8
9
10
11
12
Tsymb
RXoffset
(mSec)
0.5
1.0
2.0
4.1
8.2
16.4
(mSec)
-18.7
-17.4
-14.3
-8.2
4.1
24.6
RX window
Symb
81.0
42.0
22.0
12.0
7.0
5.0
mSec
41.5
43.0
45.1
49.2
57.3
81.9
Rxerror +/- 20 mSec
BW 250 kHz
SF
7
8
9
10
11
12
Tsymb
RXoffset
(mSec)
0.5
1.0
2.0
4.1
8.2
16.4
(mSec)
-18.7
-17.4
-14.3
-8.2
4.1
24.6
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RX window
Symb
81.0
42.0
22.0
12.0
7.0
5.0
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mSec
41.5
43.0
45.1
49.2
57.3
81.9
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SX1276 Settings for LoRaWAN
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3.2 GFSK Mode
3.2.1 Register Settings
Receiver-specific settings
• RxBw=50kHz // single side Carson BW=50kHz
• AfcBw=83.3kHz // assuming +/-30ppm of LO misalignment at 869.525 MHz
• AgcAuto=On
• Preamble Detection On, over 2 Bytes, Number of samples in error = 10
• AfcAutoOn
• AfcAutoClearOn
• RxTrigger=Preamble
• LnaBoost=On
SX1276 Register (address)
Register bit field (bit #)
Values
Note
RegLna (0x0C)
LnaGain[7:5]
LnaBoostHf[1:0]
RestartRxOnCollision[7]
RestartRxWithoutPllLock[6]
RestartRxWithPllLock[5]
AfcAutoOn[4]
AgcAutoOn[3]
RxTrigger[2:0]
RxBwMant[4:3]
RxBwExp[2:0]
RxBwMantAfc[4:3]
RxBwExpAfc[2:0]
‘001’
‘11’
’0’
‘0’
‘0’
‘1’
‘1’
‘110’
‘01’
‘011’
‘10’
‘010’
LNA gain set to the highest gain
LNA Boost enable
No restart on collision
PreambleDetectorOn[7]
PreambleDetectorSize[6:5]
PreambleDetectorTol[4:0]
AutoRestartRxMode[7:6]
PreamblePolarity[5]
SyncOn[4]
FifoFillCondition[3]
SyncSize[2:0]
‘1’
‘01’
‘01010’
‘00’
‘0’
‘1’
‘0’
‘002’
Preamble detector enable
Preamble detection over 2 bytes
10 chip errors tolerated over detection
AutoRestart OFF
Preamble 0xAA
Sync Address enable
Fill FIFO when Sync Address is detected
3 Bytes of Sync Word
PacketFormat[7]
DcFree[6:5]
CrcOn[4]
CrcAutoClearOff[3]
‘1’
‘10’
‘1’
‘1’
RegPacketConfig2 (0x31)
RegSyncValue1 (0x28)
RegSyncValue2 (0x29)
AddressFiltering[2:1]
CrcWhiteningType[0]
DataMode[6]
SyncValue[63:56]
SyncValue[55:48]
‘00’
‘0’
‘1’
0xC1
0x94
Variable length packets
Whitening encoding enable
Enable CRC calculation
PayloadReady IRQ will always be
generated at the end of the frame, CRC
must be checked through dedicated flag
No address filtering
CCITT CRC and Whitening implementation
Packet Mode
Sync Address is 0xC194C1
RegSyncValue2 (0x2A)
SyncValue[47:40]
0xC1
RegRxConfig (0x0D)
RegRxBw (0x12)
RegAfcBw (0x13)
RegPreambleDetect (0x1F)
RegSyncConfig (0x27)
RegPacketConfig1 (0x30)
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Corrects frequency offset
Automatic gain control
Trigs on preamble only
Receiver Bandwidth =50kHz SSB
Receiver Bandwidth =83.3kHz SSB for AFC
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SX1276 Settings for LoRaWAN
WIRELESS & SENSING PRODUCTS
APPLICATION NOTE
Expected performance: @ BER=0.1% = -109dBm (confirmed with PER on a short packet)
Operation Flowchart for Receiver
The following flowchart shows how the receiver should be operated for each reception slot in GFSK
mode.
Figure 4: FSK Rx Operation Flowchart
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SX1276 Settings for LoRaWAN
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DownlinkPresent timeout : timer started when the device is set to Rx mode. Sized to only leave the
receiver open for a short amount of time when the downlink command is expected. It is meant to
capture 5 bytes of Preamble + 3 Bytes of Sync Word + margin, so should be set to 1.3ms.
The “SyncAddress” interupt can be mapped to the DIO2 line of the SX1276 or can alternatively be
polled through the SPI interface.
The “PayloadReady” interrupt can be mapped to the DIO0 line of the SX1276, or polled through the
SPI interface.
3.2.2
RX Window Precise Timing in GFSK Mode
We note FSKbitrate the bit rate of the GFSK modulation in bit per sec
The GFSK frame preamble is 8 bytes long (5 bytes preamble + 3 bytes sync word), therefore the RX
window and the beginning of the TX preamble must overlap on 8*8/FSKbitrate sec
The LoRaWAN v3 only supports a single GFSK bit rate = 50kbits/sec
Therefore the overlap must be equal or greater than 1.3mSec
So using the same notation than in the LORA section we have:
• T_RX_late = 0
• T_RX_early = 1.3mSec – RXwindow
Similarly we can deduce that for 50kbit/sec GFSK the minimal RXwindow is:
• RXwindow = 1.3mSec + 2 x RXerror
and
• RXoffset = – Rxwindow/2
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SX1276 Settings for LoRaWAN
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4 Random Number Generation for Cryptography
The LoRaWAN MAC software layer requires the generation of truly random numbers for
cryptography purposes. This can be achieved using the naturally random noise of the radio channel.
The recommended way to generate a random binary number is the following:
Radio receiver settings:
SX1276 Register (address)
Register bit field (bit #)
Values
Note
RegOpMode (0x01)
RegModemConfig1 (0x1D)
LongRangeMode[7]
Mode[2:0]
Bw[7:4]
‘1’
‘101’
‘0111’
LoRa mode enable
Receive Continuous mode
‘0111’ for 125kHz modulation Bandwidth
RegModemConfig2 (0x1E)
CodingRate[3:1]
ImplicitHeaderModeOn[0]
SpreadingFactor[7:4]
‘001’
‘0’
‘0111’
4/5 error coding rate
Packets have up-front header
‘0111’ (SF7) = 6kbit/s
To generate an N bit random number, perform N read operation of the register RegRssiWideband
(address 0x2c) and use the LSB of the fetched value. The value from RegRssiWideband is derived
from a wideband (4MHz) signal strength at the receiver input and the LSB of this value constantly and
randomly changes.
The RegRssiValue register (at address 0x1b) should not be used for random number generation. It
has been experimentally measured that if a constant CW input power is applied at the receiver input
inside the current receiver channel the LSB of the RegRssiValue register may be constant or strongly
biased.
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SX1276 Settings for LoRaWAN
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Contact Information
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200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
E-mail: [email protected]
Internet: http://www.semtech.com
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