E12724B5Z

DVB-S2/S Front End
CXD2850AER
Description
The CXD2850AER is a single-chip device integrating demodulator and tuner for reception of satellite signals, conforming to
the DVB-S2 and DVB-S satellite digital broadcast standards.
The CXD2850AER is a total DVB-S2/S Front End solution from RF signal to MPEG transport stream output.
Featuring DiSEqC 2.x control and energy-saving performance the device is suitable for a wide range of applications.
(Applications: Digital TV, STB for digital satellite broadcasting, Digital video recorders)
Features
◆ Single-chip receiver
◆ High input sensitivity
◆ Low bill-of-materials for onboard and module design
◆ Excellent multipath equalization performance
◆ Built-in phase noise rejection circuit
◆ C/N, BER, Phase Noise monitoring
◆ Conforms to DiSEqC 2.x
◆ Sleep mode
◆ Low power consumption
◆ DVB-S2
◆ DVB-S
mode: 550 mW (typ.)
mode: 410 mW (typ.)
◆ Small package: VQFN56 (0.5 mm pitch)
1
CXD2850AER
Features DVB-S2
◆ Support DVB-S2 (Conforms to ETSI EN 302-307 Broadcast services)
◆ Modulation: 8PSK/QPSK
◆ Symbol rate
◆ 8PSK:
1 to 45 Msps (TS output: Parallel mode)
◆ 8PSK:
1 to 31 Msps (TS output: Serial mode)
◆ QPSK:
1 to 45 Msps
◆ Code rate
◆ 8PSK:
3/5, 2/3, 3/4, 5/6, 8/9, 9/10
◆ QPSK:
1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10
◆ Carrier frequency capture range: ±5 MHz
◆ High speed synchronization
Features DVB-S
◆ Support DVB-S (Conforms to ETSI EN 300-421 Broadcast services)
◆ Modulation: QPSK
◆ Symbol rate: 1 to 45 Msps
◆ Code rate: 1/2, 2/3, 3/4, 5/6, 7/8
◆ Carrier frequency capture range: ±5 MHz
◆ High speed synchronization
2
CXD2850AER
Contents
Description -------------------------------------------------------------------------------------------------------------------------------------------- 1
Features ----------------------------------------------------------------------------------------------------------------------------------------------- 1
Features DVB-S2------------------------------------------------------------------------------------------------------------------------------------ 2
Features DVB-S ------------------------------------------------------------------------------------------------------------------------------------- 2
1. Block Diagram ------------------------------------------------------------------------------------------------------------------------------------ 5
2. Functional Description--------------------------------------------------------------------------------------------------------------------------- 6
2-1. Tuner Part ------------------------------------------------------------------------------------------------------------------------------------ 6
2-2. Demodulator --------------------------------------------------------------------------------------------------------------------------------- 6
2
2-3. I C Interface---------------------------------------------------------------------------------------------------------------------------------- 7
2-4. DiSEqC Interface --------------------------------------------------------------------------------------------------------------------------- 7
3. Pin Configuration --------------------------------------------------------------------------------------------------------------------------------- 8
4. Pin Description ------------------------------------------------------------------------------------------------------------------------------------ 9
5. Absolute Maximum Ratings -------------------------------------------------------------------------------------------------------------------16
6. Recommended Operating Conditions-------------------------------------------------------------------------------------------------------17
7. DC Electrical Characteristics------------------------------------------------------------------------------------------------------------------18
8. AC Electrical Characteristics ------------------------------------------------------------------------------------------------------------------21
8-1. I2C Interface---------------------------------------------------------------------------------------------------------------------------------21
8-2. RF Input Interface--------------------------------------------------------------------------------------------------------------------------22
8-3. Clock Input Interface ----------------------------------------------------------------------------------------------------------------------22
8-4. General Perpose I/O ----------------------------------------------------------------------------------------------------------------------22
8-5. DiSEqC Interface --------------------------------------------------------------------------------------------------------------------------23
8-6. Reset Interface -----------------------------------------------------------------------------------------------------------------------------23
8-7. AGC Interface ------------------------------------------------------------------------------------------------------------------------------23
8-8. Regulator Node ----------------------------------------------------------------------------------------------------------------------------24
8-9. TS Output Interface -----------------------------------------------------------------------------------------------------------------------25
8-10. Other Input Interfaces -------------------------------------------------------------------------------------------------------------------25
9. Receiver Characteristics -----------------------------------------------------------------------------------------------------------------------26
10. Power Supply Sequence ---------------------------------------------------------------------------------------------------------------------27
11. I/O Interface -------------------------------------------------------------------------------------------------------------------------------------28
11-1. Clock Input Interface ---------------------------------------------------------------------------------------------------------------------28
XTALI, XTALO ---------------------------------------------------------------------------------------------------------------------------------28
OSCEN_X --------------------------------------------------------------------------------------------------------------------------------------28
XTALSEL0--------------------------------------------------------------------------------------------------------------------------------------28
11-2. Hardware Reset --------------------------------------------------------------------------------------------------------------------------29
RST_X ------------------------------------------------------------------------------------------------------------------------------------------29
When Power On ------------------------------------------------------------------------------------------------------------------------------29
When Start up Crystal Oscillation (When changing OSCEN_X from High to Low) ---------------------------------------------30
11-3. RF Input Interface ------------------------------------------------------------------------------------------------------------------------31
3
CXD2850AER
RFINP, RFINN ---------------------------------------------------------------------------------------------------------------------------------31
11-4. AGC Interface -----------------------------------------------------------------------------------------------------------------------------31
SAGC -------------------------------------------------------------------------------------------------------------------------------------------31
AGCIN ------------------------------------------------------------------------------------------------------------------------------------------31
11-5. Charge Pump Node ----------------------------------------------------------------------------------------------------------------------31
CP------------------------------------------------------------------------------------------------------------------------------------------------31
11-6. Regulator Node ---------------------------------------------------------------------------------------------------------------------------31
RXREG, VREF10, PLLREG, VCOREG --------------------------------------------------------------------------------------------------31
2
11-7. I C Interface -------------------------------------------------------------------------------------------------------------------------------32
2
I C bus specification compatibility ---------------------------------------------------------------------------------------------------------32
2
I C slave address -----------------------------------------------------------------------------------------------------------------------------32
SCL, SDA --------------------------------------------------------------------------------------------------------------------------------------32
SLVADR0 ---------------------------------------------------------------------------------------------------------------------------------------32
11-8. TS Output Interface ----------------------------------------------------------------------------------------------------------------------33
TSCLK, TSVALID, TSSYNC, TSDATA[7:0]----------------------------------------------------------------------------------------------33
11-9. DiSEqC Interface -------------------------------------------------------------------------------------------------------------------------33
DSQIN ------------------------------------------------------------------------------------------------------------------------------------------33
DSQOUT ---------------------------------------------------------------------------------------------------------------------------------------33
11-10. General Purpose I/O -------------------------------------------------------------------------------------------------------------------34
GPIO0 -------------------------------------------------------------------------------------------------------------------------------------------34
GPIO1, GPIO2 --------------------------------------------------------------------------------------------------------------------------------34
11-11. Test Pins ----------------------------------------------------------------------------------------------------------------------------------35
TESTMODE------------------------------------------------------------------------------------------------------------------------------------35
ATIN, ITN, ITP, QTN, QTP ------------------------------------------------------------------------------------------------------------------35
12. Measurement Circuit --------------------------------------------------------------------------------------------------------------------------36
13. Package Outline -------------------------------------------------------------------------------------------------------------------------------37
14. Marking ------------------------------------------------------------------------------------------------------------------------------------------38
4
CXD2850AER
1. Block Diagram
AGC LPF
AGC Ctl
GPIO
I2C
LDPC
Decoder
RF
Tuner
ADC
8PSK/QPSK
Demod
TS Output
Control
Viterbi
Decoder
OSC
BCH
Decoder
PLL
Status
Monitor
DiSEqC
Fig.1. Block Diagram of CXD2850AER
5
RS
Decoder
TS
CXD2850AER
2. Functional Description
This device supports DVB-S2 (ETSI EN 302-307) and DVB-S (ETSI EN 300-421) digital satellite broadcast standards.
Basic functions of this device are amplification and direct conversion of 1st IF signals (950 MHz-2150 MHz), demodulation,
forward error correction and output of TS signals.
This device realizes excellent multipath equalization performance and low power consumption. High-speed synchronization
algorithm allows fast signal acquisition even at low symbol rate.
Functions of this device also include DiSEqC 2.x control, performance monitoring and phase noise rejecter.
2-1. Tuner Part
Tuner supports the frequency range of 950 MHz-2150 MHz.
Tuner part of this device incorporates all the functions (RF gain controlled amplifier, oscillator circuit, other RF circuits, a
baseband LPF, baseband gain controlled amplifier and tuning PLL) required for a satellite broadcast tuner.
2-2. Demodulator
Demodulator part of this device consists of analog to digital converter (ADC), 8PSK/QPSK demodulator and forward error
correction decoder.
Supported modulation is;
◆ DVB-S2:
8PSK and QPSK
◆ DVB-S:
QPSK
Supported symbol rate is;
◆ 8PSK(DVB-S2
only):
1 to 45 Msps (TS output: Parallel mode)
◆ 8PSK(DVB-S2
only):
1 to 31 Msps (TS output: Serial mode)
◆ QPSK(DVB-S2
and DVB-S): 1 to 45 Msps
Forward error correction decoder performs LDPC/BCH decoding in DVB-S2 mode and Viterbi/Reed-Solomon decoding in
DVB-S mode.
Viterbi decoder supports the following code rate;
◆ 1/2,
2/3, 3/4, 5/6, 7/8
LDPC decoder supports following code rate;
◆ (8PSK):
3/5, 2/3, 3/4, 5/6, 8/9, 9/10
◆ (QPSK):
1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10
Demodulator also incorporates monitoring functions of lock status, phase noise, CNR (carrier to noise ratio), BER (bit error
rate) and PER (packet error rate).
6
CXD2850AER
2-3. I2C Interface
The internal registers of this device are set via the 2-wire serial bus (I2C).
Continuous write and read is available to registers with continuous sub addresses. There is no limit to the number of words
that can be continuously written or read.
Writing to read-only registers is ignored.
Please make sure that the first I2C access to RF portion via gateway after turning CXD2850AER on is ignored. The
work-around for this issue is to read some register as the first access in the initializing sequence. Please check our
reference code to find how to implement this.
2-4. DiSEqC Interface
This device supports controlling and monitoring of external devices which conforms to DiSEqC 2.x such as LNB, IF Switch,
etc.
This device can output DiSEqC Command, Tone Burst and Continuous Tone signal by register setting. The output signal can
be selected from envelope signal and tone signal.
Received reply signals are monitored by reading the internal registers.
7
CXD2850AER
SCL
SDA
RST_X
GPIO1
CVDD
DVDD
GPIO0
DSQOUT
DSQIN
SAGC
CVDD
PVDD
PAVDD
SAVDD
3. Pin Configuration
42 41 40 39 38 37 36 35 34 33 32 31 30 29
CXD2850AER
(Top View)
ITN 43
ITP 44
28 GPIO2
27 XTALSEL0
QTP 45
26 TSDATA7
QTN 46
25 TSDATA6
AGCIN 47
24 TSDATA5
RXREG 48
23 TSDATA4
RXVDD
49
22 TSDATA3
57
DIEGND
ATIN 50
21 CVDD
RXGND 51
20 DVDD
RFINP 52
19 TSDATA2
9 10 11 12 13 14
TSVALID
8
SLVADR0
7
OSCEN_X
6
CVDD
5
DVDD
4
XTALI
3
TESTMODE
2
XTALO
1
LOGND
15 TSSYNC
PLLREG
16 TSCLK
RXGND 56
LOVDD
VREF10 55
VCOGND
17 TSDATA0
CP
18 TSDATA1
VCOREG
RFINN 53
RXGND 54
Notes 1) DIEGND is located at the center bottom of the package.
2) DIEGND is for thermal enhancement and for electrical ground.
Fig. 2. Pin Configuration
8
CXD2850AER
4. Pin Description
Table 1. Pin List
No.
Symbol
I/O
Function
Equivalent Circuit
4
1
VCOREG
—
Regulator node (1.2 V)
1
2
CP
—
Charge pump node
LOVDD
Couple to analog ground
with capacitor
1
57
DIEGND
VCOREG
Connect to external loop
filter
2
57
DIEGND
3
VCOGND
—
Analog ground
n/a
4
LOVDD
—
2.5 V analog power supply
n/a
4
5
PLLREG
—
Regulator node (1.2 V)
LOGND
—
XTALO
O
Couple to analog ground
with capacitor
DIEGND
Analog ground
n/a
4
7
Crystal oscillator output
Supplies RF power
LOVDD
5
57
6
Description
5
LOVDD
PLLREG
Couple to analog ground
with capacitor when
external clock input to
XTALI
8
7
8
XTALI
I
Crystal oscillator input
External clock input pin
57
9
DIEGND
CXD2850AER
No.
Symbol
I/O
Function
Equivalent Circuit
DVDD
10
9
TESTMODE
I
Test mode setting
Description
5 V tolerant
1: Test mode
0: Normal mode
9
57
DIEGND
10
DVDD
—
3.3 V digital power supply
n/a
11
CVDD
—
1.2 V digital power supply
n/a
DVDD
20
12
SLVADR0
I
2
I C slave address selection
5 V tolerant
12
57
DIEGND
DVDD
20
13
OSCEN_X
I
5 V tolerant
1: Stop
0: Run
13
Oscillator enable
57
DIEGND
20
14
TSVALID
O
TS valid flag
20
TSSYNC
O
PE
Controllable pull-up
Selectable output current
PE
Controllable pull-up
Selectable output current
14
57
15
DVDD
TS sync flag
DIEGND
DVDD
15
57
10
DIEGND
CXD2850AER
No.
Symbol
I/O
Function
Equivalent Circuit
20
16
TSCLK
O
TS clock output
20
17
TSDATA0
O
DVDD
PE
Controllable pull-up
Selectable output current
PE
Controllable pull-up
Selectable output current
16
57
TS data output
DIEGND
DVDD
17
57
20
DIEGND
DVDD
PE
18
TSDATA1
O
TS data output
Description
18
Controllable pull-up
Selectable output current
57
DIEGND
20
DVDD
PE
19
TSDATA2
O
TS data output
19
57
DIEGND
20
DVDD
—
3.3 V digital power supply
n/a
21
CVDD
—
1.2 V digital power supply
n/a
20
DVDD
PE
22
TSDATA3
O
22
TS data output
57
11
Controllable pull-up
Selectable output current
DIEGND
Controllable pull-up
Selectable output current
CXD2850AER
No.
Symbol
I/O
Function
Equivalent Circuit
20
23
TSDATA4
O
TS data output
20
24
TSDATA5
O
DVDD
PE
Controllable pull-up
Selectable output current
PE
Controllable pull-up
Selectable output current
23
57
TS data output
DIEGND
DVDD
24
57
20
DIEGND
DVDD
PE
25
TSDATA6
O
TS data output
25
57
20
TSDATA7
O
TS data output
DVDD
26
57
20
27
XTALSEL0
I
Input clock frequency
select
20
28
GPIO2
I/O
DVDD
5 V tolerant
1: 27 MHz
DIEGND
DVDD
PE
General purpose I/O
TS error flag
28
57
DIEGND
12
Controllable pull-up
Selectable output current
DIEGND
27
57
Controllable pull-up
Selectable output current
DIEGND
PE
26
Description
5 V tolerant
Controllable pull-up
CXD2850AER
No.
Symbol
I/O
Function
Equivalent Circuit
20
29
SCL
I
2
DVDD
29
I C clock
Description
5 V tolerant
57
DIEGND
20
30
SDA
I/O
2
I C data
20
RST_X
I
Hardware reset
20
GPIO1
I/O
DIEGND
DVDD
5 V tolerant
31
57
32
5 V tolerant
30
57
31
DVDD
DIEGND
DVDD
PE
General purpose I/O
TS lock flag
32
57
DIEGND
33
CVDD
—
1.2 V digital power supply
n/a
34
DVDD
—
3.3 V digital power supply
n/a
34
35
GPIO0
I/O
DVDD
PE
General purpose I/O
Reference clock output
35
57
13
5 V tolerant
Controllable pull-up
DIEGND
5 V tolerant
Controllable pull-up
CXD2850AER
No.
Symbol
I/O
Function
Equivalent Circuit
34
36
DSQOUT
O
DiSEqC output
34
DSQIN
I
DVDD
36
57
37
Description
DIEGND
DVDD
37
DiSEqC input
57
DIEGND
34
38
SAGC
O
DVDD
38
AGC output
57
PWM output
DIEGND
39
CVDD
—
1.2 V digital power supply
n/a
40
PVDD
—
1.2 V analog power supply
n/a
Supplies PLL power
41
PAVDD
—
2.5 V analog power supply
n/a
Supplies PLL power
42
SAVDD
—
2.5 V analog power supply
n/a
Supplies ADC power
43
ITN
I/O
Test I (–) I/O
n/a
Leave open
44
ITP
I/O
Test I (+) I/O
n/a
Leave open
45
QTP
I/O
Test Q (+) I/O
n/a
Leave open
46
QTN
I/O
Test Q (–) I/O
n/a
Leave open
48
47
AGCIN
I
AGC input
RXREG
47
57
14
DIEGND
CXD2850AER
No.
Symbol
I/O
Function
RXVDD
49
48
RXREG
—
Regulator node (2.0 V)
Couple to analog ground
with capacitor
48
57
49
RXVDD
50
ATIN
51
RXGND
—
I
—
RFINP
I
n/a
Supplies RF power
Test analog input
n/a
Leave open
Analog ground
n/a
RXVDD
RF input (+)
52
57
49
53
RFINN
I
RF input (–)
DIEGND
RXVDD
RXGND
—
Analog ground
VREF10
—
DIEGND
n/a
49
55
Connected to GND
53
57
54
DIEGND
2.5 V analog power supply
49
52
Description
Equivalent Circuit
Regulator node (1.0 V)
RXVDD
Couple to analog ground
with capacitor
55
57
DIEGND
56
RXGND
—
Analog ground
n/a
57
DIEGND
—
Analog/Digital ground
n/a
DIEGND is an exposed pad
located under package.
Input voltage up to 3.6 V is acceptable on 5 V tolerant inputs even when the CXD2850AER power is off.
Do not apply voltage on non 5 V tolerant inputs when the CXD2850AER power is off.
*1 The ground corresponding to LOVDD, CVDD, DVDD, PVDD, PAVDD, SAVDD and RXVDD are DIEGND.
RXGND and VCOGND are shorted to DIEGND in package.
15
CXD2850AER
5. Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings
(Ta = 25 °C, DIEGND = RXGND = VCOGND = LOGND = 0 V)
Item
Power supplies
Symbol
Rating (*1)
Unit
CVDD
–0.3 to +1.68
V
DVDD
–0.3 to +4.62
V
PVDD
–0.3 to +1.68
V
PAVDD
–0.3 to +3.50
V
SAVDD
–0.3 to +3.50
V
RXVDD
–0.3 to +3.50
V
LOVDD
–0.3 to+ 3.50
V
VIN (*2)
–0.3 to DVDD + 0.3
(4.62 max.)
V
VIN5 (*3)
–0.3 to DVDD + 3.6
(6.00 max.) (*6)
V
VINI2C (*4)
–0.5 to DVDD+3.6
(6.00 max.) (*6)
V
VIN25 (*5)
–0.3 to VDD25 (*7) + 0.3
(3.5 max.)
V
VOUT (*2)
–0.3 to DVDD + 0.3
(4.62 max.)
V
VOUT5 (*3)
–0.3 to DVDD + 3.6
(6.00 max.) (*6)
V
VOUTI2C (*4)
–0.5 to DVDD + 3.6
(6.00 max.) (*6)
V
VOUT25 (*5)
–0.3 to VDD25 (*7) + 0.3
(3.5 max.)
V
–65 to +150
°C
Input voltage
Output voltage
Storage temperature
Tstg
*1 Absolute maximum rating values must not be exceeded, even momentarily, for any item. In addition, even when the
absolute maximum ratings and operating range are not exceeded, use of this product under operating conditions
(operating temperature, current, voltage, etc.) that apply a continuously high load (high temperature with high current
and high voltage applied, large temperature changes, etc.) may significantly degrade reliability.
*2 VIN/VOUT are the normal I/O rating. The applicable pins are TSCLK, TSSYNC, TSVALID, TSDATA[7:0], DSQIN, DSQOUT
and SAGC.
*3 VIN5/VOUT5 are the 5 V tolerant I/O rating. The applicable pins are RST_X, GPIO[2:0], OSCEN_X, XTALSEL0, SLVADR0
and TESTMODE.
*4 VINI2C/VOUTI2C are the I/O rating for SCL pin and SDA pin.
*5 VIN25/VOUT25 are the analog I/O rating. The applicable pins are XTALI and XTALO.
*6 5 V tolerant inputs are only 5 V tolerant while the CXD2850AER power is applied. If no power is applied to CXD2850AER
there in no protection to 5 V levels and the CXD2850AER may be permanently damaged. It is important to observe the
conditions for 5 V protection when sequencing power supplies in the application.
*7 VDD25 represents RXVDD and LOVDD.
16
CXD2850AER
6. Recommended Operating Conditions
Table 3. Recommended Operating Conditions
(DIEGND = RXGND = VCOGND = LOGND = 0 V)
Item
Power supplies
Input voltage
Output voltage
Symbol
Min.
Typ.
Max.
Unit
CVDD
1.08
1.2
1.32
V
DVDD
3.0
3.3
3.6
V
PVDD
1.08
1.2
1.32
V
PAVDD
2.35
2.5
2.7
V
SAVDD
2.35
2.5
2.7
V
RXVDD
2.35
2.5
2.7
V
LOVDD
2.35
2.5
2.7
V
VIN (*1)
—
—
DVDD + 0.3
(3.6 max.)
V
VIN5 (*2)
—
—
DVDD + 2.5
(5.5 max.)
V
VINI2C (*3)
—
—
DVDD + 2.5
(5.5 max.)
V
VOUT (*1)
0
—
3.6
V
VOUT5 (*2)
0
—
3.6
V
VOUTI2C (*3)
0
—
3.6
V
Junction temperature
Tj
–20
—
+105
°C
Ambient temperature (*4)
Ta
–20
—
+75
°C
*1 VIN/VOUT are the normal I/O rating. The applicable pins are TSCLK, TSSYNC, TSVALID, TSDATA[7:0], DSQIN, DSQOUT
and SAGC.
*2 VIN5/VOUT5 are the 5 V tolerant I/O rating. The applicable pins are RST_X, GPIO[2:0], OSCEN_X, XTALSEL0, SLVADR0
and TESTMODE.
*3 VINI2C/VOUTI2C are the 5 V tolerant I/O rating for pins SCL and SDA.
*4 Ambient Temperature is for such test board condition given in JESD51-7 “High Effective Thermal Conductivity Test
Board for Leaded Surface Mount Package” without thermal via and at still air. DIEGND is thoroughly attached to the test
board.
17
CXD2850AER
7. DC Electrical Characteristics
Table 4. DC Electrical Characteristics
(DIEGND = RXGND = VCOGND = LOGND = 0 V, Supply voltage and temperature within the recommended operating conditions)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Pins
VIH
—
2.0
—
DVDD + 0.3
(3.6 max.)
V
DSQIN
VIH5
—
2.0
—
DVDD + 2.5
(5.5 max.)
V
(b), (c),
(d), (e)
VIL
—
–0.3
—
0.8
V
DSQIN
VIL5
—
–0.3
—
0.8
V
(b), (c),
(d), (e)
2
VBUSI2C
—
2.97
3.3
5.0
V
—
2
VIHI2C
—
VBUSI2C * 0.7
VBUSI2C
VBUSI2C + 0.5
V
(a)
2
VILI2C
—
–0.5
0.0
VBUSI2C * 0.3
V
(a)
Input High voltage
Input Low voltage
I C bus voltage
I C input High voltage
I C input Low voltage
Output High voltage
(*1)
Output Low voltage
(*1)
VOH2
IO = 2 mA
DVDD – 0.4
3.3
—
V
SAGC,
DSQOUT
VOH8
IO = 8 mA
DVDD – 0.4
3.3
—
V
(d), (f)
VOH10
IO = 10 mA
DVDD – 0.4
3.3
—
V
(f)
VOL2
IO = 2 mA
—
0.0
0.4
V
SAGC,
DSQOUT
VOL8
IO = 8 mA
—
0.0
0.4
V
(d), (f)
VOL10
IO = 10 mA
—
0.0
0.4
V
(f)
VOLSDA
IO = 3 mA
—
0.0
0.4
V
SDA
IIH
VI = DVDD
—
—
±10
µA
DSQIN
IIH5
VI = 5.5 V
—
—
±10
µA
(b), (c),
(d), (e)
IIHI2C
VI = 5.5 V
—
—
±10
µA
(a)
IIHAGC
VI = DVDD
—
—
±40
µA
AGCIN
IIL
VI = 0 V
—
—
±10
µA
DSQIN
IIL5
VI = 0 V
—
—
±10
µA
(b), (c),
(d), (e)
IILI2C
VI = 0 V
—
—
±10
µA
(a)
IILAGC
VI = 0 V
—
—
±10
µA
AGCIN
IOZ
VO = DVDD or 0 V
—
—
±10
µA
(f),
DSQOUT,
SAGC
IOZSDA
VO = 5.5 V or 0 V
—
—
±10
µA
SDA
Input High current
Input Low current
Output leakage current
Input pull-up resistor
(*2)
RPU
—
26
38
60
kΩ
(c), (d), (f)
Input pull-down
resistor
RPD
—
33
47
81
kΩ
(b)
Power-off leakage
current
IOFF
DVDD = 0 V
VI = 3.6 V or 0 V
—
—
±10
µA
(a), (b),
(c), (d), (e)
18
CXD2850AER
XTALI input dynamic
range
VIXI
XTALO
transconductance
gm
XTALI DC bias voltage
VBIASXI
AC coupled sine wave,
XTALO is open
0.35
—
0.66
Vp-p
XTALI
XOSC_SEL = 5’b11111 *4
9
—
18
ms
XTALO
XOSC_SEL = 5’b01000 *4
3
—
7
ms
XTALO
0.33
0.43
0.53
V
XTALI
—
420
500
mA
CVDD
—
5
10.7
mA
DVDD
—
1.9
2.1
mA
PVDD
—
0.5
0.6
mA
PAVDD
—
24
27
mA
SAVDD
IRXVDD
—
75
87
mA
RXVDD
ILOVDD
—
49
55
mA
LOVDD
ICVDD
—
105
140
mA
CVDD
IDVDD (*3)
—
5
10.7
mA
DVDD
—
1.9
2.1
mA
PVDD
—
0.5
0.6
mA
PAVDD
—
24
27
mA
SAVDD
IRXVDD
—
75
87
mA
RXVDD
ILOVDD
—
49
55
mA
LOVDD
ICVDD
—
6.0
40
mA
CVDD
IDVDD
—
10
11
mA
DVDD
—
1.9
2.1
mA
PVDD
—
0.5
0.6
mA
PAVDD
ISAVDD
—
100
110
µA
SAVDD
IRXVDD
—
75
87
mA
RXVDD
ILOVDD
—
49
55
mA
LOVDD
ICVDD
—
10
45
mA
CVDD
IDVDD
—
0.6
1
mA
DVDD
—
1.9
2.1
mA
PVDD
—
0.5
0.6
mA
PAVDD
ISAVDD
—
100
110
µA
SAVDD
IRXVDD
—
4
5
mA
RXVDD
ILOVDD
—
1.6
3.5
mA
LOVDD
ICVDD
—
1
35
mA
CVDD
IDVDD
—
120
150
µA
DVDD
IPVDD
—
1
60
µA
PVDD
—
2
100
nA
PAVDD
ISAVDD
—
100
110
µA
SAVDD
IRXVDD
—
27
35
mA
RXVDD
ILOVDD
—
0.8
2.5
mA
LOVDD
ICVDD
IDVDD (*3)
IPVDD
Operating current
DVB-S2 operation
IPAVDD
ISAVDD
IPVDD
Operating current
DVB-S operation
IPAVDD
ISAVDD
Measurement condition: 45 Msps,
8PSK, R3/5, Pilot-ON,
CN = 5.7 dB, HSmode,
FOSC = 27 MHz,
RF: 950 MHz, –38 dBm
Measurement condition: 45 Msps,
QPSK, R7/8, HSmode,
FOSC = 27 MHz
RF: 950 MHz, –38 dBm
IPVDD
Operating current
Shutdown-SW mode
IPAVDD
State after hardware reset
FOSC = 27 MHz
IPVDD
Operating current
Sleep mode
Standby current
Shutdown-HW mode
IPAVDD
IPAVDD
Sleep mode
FOSC = 27 MHz
OSCEN_X = 1
19
CXD2850AER
(a): SCL, SDA
(b): TESTMODE, SLVADR0
(c): OSCEN_X, XTALSEL0
(d): GPIO[2:0]
(e): RST_X
(f): TSCLK, TSSYNC, TSVALID, TSDATA[7:0]
*1 Output current of (f) group can be changed by the register settings.
*2 Pull-up resistance of (d) and (f) group can be enabled or disabled by the register settings.
*3 DVDD current consumption is calculated based on the following assumptions:
Typical current:
TS loading 15 pF, SAGC loading 1 pF held at center voltage, only OSCEN_X internal pull-up
resistor driven by the opposite polarity.
Maximum current:
TS loading 15 pF, SAGC loading 15 pF held at center voltage, all internal pull-up/down resistor
driven by the opposite polarity.
*4 XOSC_SEL is the 5 bit register to change the oscillator bias current. It is default 5’b11111 at power-up, and user set this
register to 5’b10000 when the crystal oscillator is stabilized to minimize the crystal oscillator power.
20
CXD2850AER
8. AC Electrical Characteristics
(DIEGND = RXGND = VCOGND = LOGND = 0 V, supply voltage and temperature within the recommended operating conditions)
8-1. I2C Interface
Corresponding I/O name: SCL, SDA
2
Table 5. AC Electrical Characteristics of I C Interface
Item
Symbol
Condition
Min.
Typ.
Fast Mode
Standard Mode
Max.
400
100
Unit
SCL clock frequency
fSCL
kHz
Hold time START condition
tHD;STA
0.6
—
—
µs
Low period of the SCL clock
tLOW
1.3
—
—
µs
High period of the SCL clock
tHIGH
0.6
—
—
µs
Setup time for a repeated START condition
tSU;STA
0.6
—
—
µs
Data hold time
tHD;DAT
0.0
—
0.9
µs
Data setup time
tSU;DAT
100
—
—
ns
Setup time for STOP condition
tSU;STO
0.6
—
—
µs
Bus free time between STOP and START condition
tBUF
1.3
—
—
µs
Output fall time
tof
*1
21
—
250
ns
Output rise time
tor
*2
21
—
300
ns
Pulse width of spikes allowed
tSP
—
—
50
ns
Input capacitance
CIN
—
—
10
pF
Output load capacitance
CLD
—
—
400
pF
*1 Output fall time from VIHmin to VILmax with a bus capacitance from 10 pF to 400 pF.
*2 Output rise time from VILmax to VIHmin with a bus capacitance from 10 pF to 400 pF.
tor
tof
SDA
tSU;DAT
tLOW
tHD;STA
tBUF
tSP
SCL
tHD;STA
S
tHD;DAT
tHIGH
tSU;STO
tSU;STA
Sr
P
2
Fig. 3. Waveform of I C Interface
21
S
CXD2850AER
8-2. RF Input Interface
Corresponding I/O names are: RFINP, RFINN
Table 6. AC Electrical Characteristics of RF Interface
Item
Input frequency
Symbol
Condition
FIN
Min.
Typ.
Max.
Unit
950
—
2150
MHz
Min.
Typ.
Max.
Unit
—
27
—
MHz
8-3. Clock Input Interface
Corresponding I/O name: XTALI, XTALO
Table 7. AC Electrical Characteristics of Clock Input Interface
Item
Symbol
Condition
Input clock frequency
FOSC
Frequency tolerance
FTOL
FOSC = 27 MHz *1
—
—
±200
ppm
Input impedance
ZIN
Applies to XTALI
FOSC = 27 MHz
850
—
—
Ω
Input capacitance
CIN
Applies to XTALI
2.5
—
3.5
pF
Output capacitance
COUT
Applies to XTALO
1.5
—
2.0
pF
Min.
Typ.
Max.
Unit
—
27
—
MHz
45 %
50 %
55 %
—
*1 Total of frequency tolerance, aging and temperature stability.
8-4. General Perpose I/O
Corresponding I/O name: GPIO0, GPIO1 and GPIO2
Table 8. AC Electrical Characteristics of GPIO Interface
Item
Symbol
Condition
Reference clock output
frequency (*1)
FREFOUT
Reference clock duty (*1)
DutyREFOUT
Input capacitance
CIN
—
—
5
pF
Output load capacitance
CLD
—
—
20
pF
XTALI clock duty is 50 %
*1 Clock output is supported on GPIO0 only.
22
CXD2850AER
8-5. DiSEqC Interface
Corresponding I/O name: DSQIN and DSQOUT
Table 9. AC Electrical Characteristics of DSQIN Pin
Item
Input capacitance
Symbol
Condition
CIN
Min.
Typ.
Max.
Unit
—
—
5
pF
Min.
Typ.
Max.
Unit
—
—
15
pF
Min.
Typ.
Max.
Unit
—
—
5
pF
Min.
Typ.
Max.
Unit
—
—
15
pF
Table 10. AC Electrical Characteristics of DSQOUT Pin
Item
Output load capacitance
Symbol
Condition
CLD
8-6. Reset Interface
Corresponding I/O name: RST_X
Table 11. AC Electrical Characteristics of Reset Interface
Item
Input capacitance
Symbol
Condition
CIN
8-7. AGC Interface
Corresponding I/O name: SAGC and AGCIN
Table 12. AC Electrical Characteristics of SAGC Pin
Item
Output load capacitance *1
Symbol
Condition
CLPWM
*1 Output load capacitance value is the allowable capacitance value until the RC filter.
23
CXD2850AER
8-8. Regulator Node
Corresponding I/O name: RXREG, VCOREG, PLLREG and VREF10
Table 13. AC Electrical Characteristics of Regulator Node
Item
Symbol
Regulator startup time
tREG
Condition
Min.
Typ.
Max.
Unit
1 µF capacitor is
connected to each node.
—
—
3.3
ms
RXVDD, LOVDD
Voltage [V]
Vddmin
Regulator
startup time
0V
Internal regulator output
90 %
0V
Time [s]
Fig. 4. Regulator Startup Waveform
24
CXD2850AER
8-9. TS Output Interface
Corresponding I/O name: TSCLK, TSVALID, TSSYNC, TSDATA[7:0]
TSVALID, TSSYNC and TSDATA[7:0] are triggered by TSCLK negative edge in default. TSCLK may be inverted by register.
Table 14. AC Electrical Characteristics of TS Output Interface
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
tCYC;S
TS Serial
10.2
—
—
ns
tCYC;P
TS Parallel
61.3
—
—
ns
tLOW;S
TS Serial
4.4
—
—
ns
tLOW;P
TS Parallel
26.9
—
—
ns
tHIGH;S
TS Serial
4.4
—
—
ns
tHIGH;P
TS Parallel
26.9
—
—
ns
tPD;S
TS Serial
–2.2
—
1.0
ns
tPD;P
TS Parallel
–4.0
—
2.0
ns
—
—
15
pF
Min.
Typ.
Max.
Unit
—
—
5
pF
Clock frequency
Clock Low period
Clock High period
Propagation delay
Output load capacitance
CL
TSCLK
(default polarity)
tLOW
tHIGH
tCYC
TSDATA[7:0]
TSVALID
TSSYNC
TSERR
tPD
Fig. 5. Waveform of TS Output Interface
8-10. Other Input Interfaces
Corresponding I/O name: TESTMODE, SLVADR0, OSCEN_X and XTALSEL0
Table 15. AC Electrical Characteristics of Other Interfaces
Item
Input capacitance
Symbol
Condition
CIN
25
CXD2850AER
9. Receiver Characteristics
Table 16. Receiver Characteristics
Item
Mode
Min.
Typ.
Max.
Unit
DVB-S
–20
–5
—
dBm
QPSK 7/8, Noise Free, SR 27.5 Msps,
–4
QEF (Pre-RS BER = 2 * 10 )
DVB-S2
–20
–5
—
dBm
8PSK 9/10, Noise Free, SR 27.5 Msps,
QEF (PER = 1 * 10–7)
DVB-S
—
–86
–81
dBm
QPSK 7/8, Noise Free, SR 27.5 Msps,
QEF (Pre-RS BER = 2 * 10–4)
DVB-S2
—
–80
–75
dBm
8PSK 9/10, Noise Free, SR 27.5 Msps,
–7
QEF (PER = 1 * 10 )
950-2150 MHz
–65
–90
dBm
2150-5000 MHz
–55
–70
dBm
Maximum
input level
Condition
Sensitivity
VCO
leakage at
RF input
fd = ±1
–30
–20
dB
fd = ±2
–35
–25
dB
fd = ±1 ch, 2 ch
(29.5 + 59.0 MHz)
–20
–15
dB
fd = ±2 ch, 4 ch
(59.0 + 118.0 MHz)
–20
–15
dB
Digital ACI
IM3
D/U Ratio for QEF (PER = 1 * 10–7)
Desire fd:DVB-S2 8PSK
SR 22 Mbps 9/10 Roll off 0.2 Pilot On CN off
Un desire fu:DVB-S QPSK
SR 19 Mbps 3/4 Roll off 0.35 fu = –25 dBm
D/U Ratio for QEF (PER = 1 * 10–7)
Desire fd:DVB-S2 8PSK
SR 27.5 Mbps 9/10 Roll off 0.2 Pilot On CN 19 dB
Un desire fu1, fu2:
fu1, fu2 = Fu = –25 dBm CW
* These values are measured using evaluation circuit described in chapter 12.
26
CXD2850AER
10. Power Supply Sequence
For all power supplies (i.e. CVDD, DVDD, PVDD, PAVDD, SAVDD, RXVDD, and LOVDD), there is no restriction on the order of
applying or removing the power supplies.
Do not keep applying only a part of power supplies.
27
CXD2850AER
11. I/O Interface
11-1. Clock Input Interface
Corresponding I/O name: XTALI, XTALO, OSCEN_X and XTALSEL0
The CXD2850AER operates with the clock reference from a crystal or external clock source input. XTALI and XTALO are the
crystal oscillator interface of the internal oscillator. OSCEN_X and XTALSEL0 are the control signals of the oscillator. With
these pins, users can control the reference clock of the device.
XTALI, XTALO
Internal voltage bias: Exists on XTALI and XTALO
There are two ways to input clock, one is to connect crystal, and the other is to input external clock source to XTALI.
No register setting is required for clock source selection.
OSCEN_X
I/O type: 5 V tolerant, pull-up
This enables or disables the crystal oscillator. Set OSCEN_X to 0 to enable the oscillator. The pin is internally pulled up.
Therefore, when the pin is open, OSCEN_X is set to 1 and the oscillator is disabled.
The oscillator uses the internal bias voltage to pull XTALI to the threshold level of the internal circuit. When there is no
clock applied to XTALI, the level of XTALI is close to the threshold level of the parasitic noise and there is a risk of
hazardous clock propagation to the internal logic. To avoid this hazardous situation, it is recommended that OSCEN_X is
set to 1 when there is no clock supplied to XTALI.
Table 17. OSCEN_X Truth Table
OSCEN_X
Description
0
Enable oscillator
The oscillator generates clock when crystal is connected to XTALI and XTALO.
The oscillator propagates clock when external clock is supplied to XTALI.
1
Disable oscillator
Set OSCEN_X to 1 when no external clock is supplied.
XTALSEL0
I/O type: 5 V tolerant, pull-up
The clock reference frequency is 27 MHz. This pin is internally pulled up.
Table 18. XTALSEL0 Truth Table
XTALSEL0
Description
0
(Prohibited)
1
Set XTALSEL to 1 when 27 MHz clock source is used.
28
CXD2850AER
11-2. Hardware Reset
Corresponding I/O name: RST_X
RST_X
I/O type: 5 V tolerant, Schmitt
This is the Hardware Reset pin to reset the entire CXD2850AER.
The RST_X should be held low until the oscillator is stabilized.
A Hardware Reset is also required, before normal operation can be resumed, after the crystal oscillator has been
disabled and re-enabled.
Table 19. RST_X Truth Table
RST_X
Description
0
Assert Hardware Reset
1
Negate Hardware Reset
The following pins; OSCEN_X, XTALSEL0, SLVADR0 and TESTMODE must be asserted or negated while RST_X is 0.
The only exception is OSCEN_X, the oscillator can be disabled by setting OSCEN_X to 1 while RST_X is 1.
When Power On
Keep RST_X low until 1 ms after crystal oscillation is stabilized.
I2C communication is not valid
I2C communication is valid
PAVDD (Pin 41) 2.5 V
SAVDD (Pin 42)
RXVDD (Pin 49)
0V
1.2 V
CVDD (Pin 11, 21, 33, 39)
PVDD (Pin 40)
0V
LOVDD (Pin 4) 2.35 V
0V
XTALO (Pin 7)
OSCEN_X (Pin 13)
0V
RST_X (Pin 31)
2.0 V
0V
*1
Wait for X'tal oscillation
to be stabilized
1 ms
1 ms
*1 Waiting time for X'tal oscillation stabilization varies depending on external crystal and components.
Fig. 6. Power on Sequence
29
CXD2850AER
When Start up Crystal Oscillation (When changing OSCEN_X from High to Low)
Apply low to RST_X before applying low to OSCEN_X.
I2C communication is valid
I2C communication is not valid
PAVDD (Pin 41)
SAVDD (Pin 42)
RXVDD (Pin 49)
CVDD (Pin 11, 21, 33, 39)
PVDD (Pin 40)
LOVDD (Pin 4)
2.5 V
1.2 V
2.5 V
XTALO (Pin 7)
OSCEN_X (Pin 13)
RST_X (Pin 31)
2.0 V
0.8 V
2.0 V
Don't care
0V
*1
Wait for X'tal oscillation
to be stabilized
1 ms
1 ms
*1 Waiting time for X'tal oscillation stabilization varies depending on external crystal and components.
Fig. 7. Resume Sequence
30
CXD2850AER
11-3. RF Input Interface
Corresponding I/O name: RFINP, RFINN
These are analog RF signal input pins.
Connect the external LNA output to RFINP pin and connect RFINN pin to the ground.
RFINP, RFINN
I/O type: Analog input
11-4. AGC Interface
Corresponding I/O name: AGCIN, SAGC
The Demodulator part of CXD2850AER outputs PWM signal that controls the tuner part of this device. The PWM signal is
output from SAGC pin and input to AGCIN pin through external LPF which flatten the PWM signal into DC signal. Put the
external LPF as near by SAGC pin of CXD2850AER as possible.
SAGC
I/O type: CMOS output
Initial condition: Hi-Z
AGCIN
I/O type: Analog input
11-5. Charge Pump Node
Corresponding I/O name: CP
This is a charge pump pin of an internal PLL.
Connect to external loop filter. Put the external filter as near by CP pin of CXD2850AER as possible.
CP
I/O type: Analog signal node
11-6. Regulator Node
Corresponding I/O name: RXREG, VREF10, PLLREG and VCOREG
These pins are regulator nodes. Couple to analog ground with capacitor to eliminate noise.
RXREG, VREF10, PLLREG, VCOREG
I/O type: Analog power node
31
CXD2850AER
11-7. I2C Interface
Corresponding I/O name: SCL, SDA and SLVADR0
2
I C bus is used to control the device.
CXD2850AER supports both standard mode and fast mode.
2
Table 20. I C Modes
2
I C mode
Description
Standard mode
SCL operates at 100 kHz.
Fast mode
SCL operates at 400 kHz.
I2C bus specification compatibility
2
The host I C interfaces (i.e. SCL and SDA) supports the mandatory protocol features for a Slave configuration as listed in
2
the NXP specification reference document: UM10204 “I C bus specification and user manual Rev. 03-19 June 2007”.
Refer to Table 2 on page 8 of the reference document.
I2C slave address
Table 21. I2C Slave Address Including Read/Write Bit (Left Aligned)
SLVADR0 = 0
System
DVB-S2/S
SLVADR0 = 1
Write
Read
Write
Read
0xD0
0xD1
0xD2
0xD3
SCL, SDA
I/O type: 5 V tolerant, Schmitt, open-drain
Initial condition: Hi-Z
These are I2C slave interface to control the CXD2850AER.
SLVADR0
I/O type: 5 V tolerant, pull-down
This is one bit of I2C slave address. This pin is internally pulled down. Therefore, when this pin is open, SLVADR0
becomes 0.
Fix SLVADR0 before hardware reset is negated.
Table 22. SLVADR0 Truth Table
SLVADR0
Description
0
Set bit [1] of the I2C slave address to 0.
1
Set bit [1] of the I C slave address to 1.
2
32
CXD2850AER
11-8. TS Output Interface
Corresponding I/O name: TSCLK, TSVALID, TSSYNC and TSDATA[7:0]
These are the transport stream output pins.
The TS output can be selected to be either parallel output or serial output. The CXD2850AER has internal pull-ups that can
be enabled by the register setting. The internal pull-up is disabled in default.
TSCLK, TSVALID, TSSYNC, TSDATA[7:0]
I/O type: Selectable Pull-up (*1), Selectable Output current (*2)
Initial condition: Hi-Z
(*1) Pull-up disabled by default. The register enables the pull-up.
(*2) IOLH = 8 mA by default. The register can set it to 10 mA.
11-9. DiSEqC Interface
Corresponding I/O name: DSQIN and DSQOUT
These are DiSEqC interface pins.
Through this interface, DiSEqC command, Tone Burst and Continuous Tone can be output.
Up to 16 words (max.) of the reply signal output by a slave device can be received.
Control signal which selects transmission/reception status of LNB controller can be output using GPIO0, GPIO1 and GPIO2
pin by register setting. In addition, voltage control signal which indicates transmitting Single Cable commands can be output
using GPIO0, GPIO1, GPIO2 pin.
DSQIN
I/O type: Pull-up
DSQOUT
I/O type: CMOS output
33
CXD2850AER
11-10. General Purpose I/O
Corresponding I/O name: GPIO0, GPIO1 and GPIO2
These are general purpose I/Os and the pins are directly connected to the internal I 2C registers. These pins are multiplexed
with the other functions listed below. GPIO pin initially outputs multiplexed signal.
2
By setting I C register users can output arbitrary data and other multiplexed signals and other multiplexed signals from
GPIO pins.
Table 23. Table 23 GPIO multiplexed signal table
Pin
name
Initial Multiplexed
Signals
Option 1
(Control signals
for DiSEqC 2.x)
Option 2
(Control signals for
SingleCable)
GPIO0
REFOUT (*1)
Tx/Rx control
Voltage Control
GPIO1
TSLOCK (*2)
Tx/Rx control
Voltage Control
GPIO2
TSERR (default)(*3)
Tx/Rx control
Voltage Control
Option 3
PWM (*4)
(*1) REFOUT is a repeater of a clock signal input to XTALI pin.
(*2) A high value of TSLOCK indicates CXD2850AER is locking transport stream.
(*3) A high value of TSERR indicates outputting transport stream includes uncorrected error.
(*4) This device can also output PWM digital signal which can be converted into analog voltage with external filter.
GPIO0
I/O type: Selectable Pull-up (*1), 5 V tolerant
Initial condition: Pull-up (*1)
(*1) Pull-up enabled at default. The register disables the pull-up.
GPIO0 is multiplexed with reference clock output. Initially reference clock is output from GPIO0 pin.
By I2C register setting, arbitrary data can be output from GPIO0.
GPIO1, GPIO2
I/O type: Selectable Pull-up (*1), 5 V tolerant
Initial condition: Hi-Z, pull-up (*1)
(*1) Pull-up enabled at default. The register disables the pull-up.
34
CXD2850AER
11-11. Test Pins
Corresponding I/O name: TESTMODE, ATIN, ITN, ITP, QTN and QTP
TESTMODE
I/O type: Selectable pull-down, 5 V tolerant
This pin is set CXD2850AER to testing mode. For normal operation, connect TESTMODE directly to GND.
Table 24. TESTMODE Truth Table
TESTMODE
Description
0
Set TESTMODE = 0 when in normal operation.
1
TESTMODE = 1 is only for LSI testing purpose.
ATIN, ITN, ITP, QTN, QTP
I/O type: Analog
These pins are analog test pins. Leave them open for normal operation.
35
CXD2850AER
DSQFLAG
DSQIN
1.2 V
2.5 V
1.2 V
0.1 µF
DSQOUT
12. Measurement Circuit
3.3 V
10 kΩ
2.2 kΩ
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
2.2 nF
2.2 kΩ
3.3 V 1.2 V
2.5 V
SDA
SCL
SCL
SDA
RST_X
CVDD
GPIO1
DVDD
GPIO0
DSQOUT
DSQIN
TSDATA6 25
47 AGCIN
TSDATA5 24
48 RXREG
TSDATA4 23
49 RXVDD
TSDATA3 22
DVDD 20
51 RXGND
55 VREF10
TSCLK 16
1
2
3
4
5
6
7
8
9
10 11 12
13 14
3300 pF
1 µF
15 pF
100 pF
47 Ω
47 Ω
0.1 µF
1.2 V
47 Ω
3.3 V
0.1 µF
47 Ω
47 Ω
47 Ω
47 Ω
TSCLK
TSSYNC
47 Ω
X'tal
27 MHz
15 pF
100 pF
47 Ω
TSVALID
150 pF
100 pF
47 Ω
TSSYNC 15
1 µF
4.7 kΩ
TSDATA
TSVALID
4.7 nH
57 DG
SLVADR0
56 RXGND
CVDD
100 pF
OSCEN_X
TSDATA0 17
DVDD
54 RXGND
TESTMODE
TSDATA1 18
XTALI
53 RFINN
XTALO
TSDATA2 19
LOGND
52 RFINP
LNB Power Supply
47 Ω
CVDD 21
50 ATIN
PLLREG
1 µF
46 QTN
LOVDD
2SC5509
TSDATA7 26
VCOGND
1.2 pF
3 pF
1.5 kΩ
2 pF
3.9 nH
2 pF
4 pF
45 QTP
CP
33 Ω
2.2 kΩ
GPIO2 28
XTALSEL0 27
VCOREG
6.2 nH
1 µF
1 µF
1st-IF Input
CVDD
44 ITP
56 Ω
1 nF
SAGC
43 ITN
5V
PVDD
SAVDD
2.5 V
PAVDD
42 41 40 39 38 37 36 35 34 33 32 31 30 29
1.2 V
0.1 µF
3.3 V
0.1 µF
2.5 V
1 µF
Fig. 8. Measurement Circuit
Note) Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of
third party patent and other right due to same.
36
CXD2850AER
13. Package Outline
(Unit: mm)
The new package code is “VQFN-56P-L481”.
Fig. 9. Package Outline
37
CXD2850AER
14. Marking
38
CXD2850AER
Note
Sony reserves the right to change products and specifications without prior notice.
This information does not convey any license by any implication or otherwise under any patents or other right.
Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume
responsibility for any problems arising out of the use of these circuits.
39
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