Combined DVB-T2/DVB-T/DVB-C2/DVB-C/DVB-S2/DVB-S/ISDB-T/SBTVD-T/ISDB-S Demodulator CXD2854ER Description The CXD2854ER is a combined demodulator that conforms to the following standards. DVB-T2 : ETSI EN 302-755 v1.3.1 DVB-T : ETSI EN 300-744 V1.6.1 DVB-C2 : ETSI EN 302-769 v1.2.1 DVB-C : ETSI EN 300-429 v1.2.1 DVB-S2 : ETSI EN 302-307 v1.2.1 DVB-S : ETSI EN 300-421 v1.1.2 ISDB-T/SBTVD-T : ARIB STD-B31 ISDB-S : ARIB STD-B20 The CXD2854ER demodulator offers class-leading performance, optimized BOM requiring no external memory and low processor overhead. Features ◆ Features DVB-T2 ◆ Complies with DTG D-BOOK 7.0 V2.0, NorDig-Unified Test Specification ver2.2.1 and targeting upcoming Digital Europe Ebook requirements ◆ Supports 5 MHz, 6 MHz, 7 MHz, 8 MHz and 1.7 MHz BW ◆ Supports all DVB-T2 modes, including ◆ Single and multiple-PLPs T2-Lite profile SISO and MISO transmission Simple API Fully-automatic acquisition Fully-automatic L1-signalling decoding Automatic guard-interval detection Automatically-calculated constant-rate TS output (using L1 signalling and ISSY) ◆ Frequency offset detection range up to +/-600 kHz allows acquisition and performance optimization via tuner frequency offset compensation ◆ Stream processor for automatic common-PLP and data-PLP combination ◆ Null-packet insertion ◆ Improved performance for multipath channel (outside the guard interval) Note） Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 1 CXD2854ER ◆ Features DVB-T ◆ Complies with all European standards for static and portable equipment including NorDig-Unified Test Specification ver2.2.1 DTG D-BOOK 7.0 V2.0, IEC 62216 and targeting upcoming Digital Europe Ebook requirements ◆ Smart Auto Acquisition controller with fast 2k/8k acquisition, low processor overhead and re-acquisition mode ◆ Frequency offset detection range up to +/-600 kHz allows acquisition and performance optimization via tuner frequency offset compensation ◆ Advanced channel corrector for low multipath loss and enhanced Doppler performance ◆ Improved CNR performance ◆ Features DVB-C2 ◆ Demodulation: 16, 64, 256, 1024, 4096 QAM 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 Code Rates 1/64 and 1/128 Guard Intervals ◆ 8 MHz and 6 MHz channel bandwidths ◆ Data Slices Types 1 & 2 supported Data Slice width up to 7.61 MHz ◆ Stream processor for automatic common-PLP and data-PLP combination ◆ FEC Header Type ◆ ◆ ◆ Robust mode High Efficiency mode Simple API Fully-automatic acquisition Fully-automatic L1-signalling decoding Automatic spectrum inversion Automatic guard-interval detection Automatically-calculated constant-rate TS output Notch Support Narrowband and broadband notches Reception of narrow channels down to 2 MHz between broadband notches Time interleaving modes 4, 8 symbols and 'best fit' ◆ Features DVB-C ◆ Complies with NorDig-Unified Test specification Ver2.2.1 ◆ Wide symbol range, 1.8 to 7.2 Msym/s ◆ Integrated matched filter 0.15 roll-off factor ◆ Frequency offset detection range up to ±500 kHz allows acquisition and performance optimization via tuner frequency offset compensation ◆ Excellent equalization for cancellation of reflections at larger delays ◆ Improved performance against large continuous wave interference 2 CXD2854ER ◆ Features DVB-S2 ◆ Complies with NorDig-Unified Test Specification ver2.2.1 ◆ Modulation: 8PSK/QPSK ◆ Symbol rate ◆ 8PSK: 333 Ksym/s to 45 Msym/s QPSK: 333 Ksym/s to 45 Msym/s Code rate 8PSK: 3/5, 2/3, 3/4, 5/6, 8/9, 9/10 QPSK: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 ◆ High speed synchronization ◆ Fast and accurate channel scan ◆ Features DVB-S ◆ Complies with NorDig-Unified Test Specification ver2.2.1 ◆ Modulation: QPSK ◆ Symbol rate: 333 Ksym/s to 45 Msym/s ◆ Code rate: 1/2, 2/3, 3/4, 5/6, 7/8 ◆ High speed synchronization ◆ Fast and accurate channel scan ◆ Features ISDB-T/SBTVD-T ◆ Conforms to ARIB STD-B31 ◆ 6 MHz,7 MHz and 8 MHz BW support ◆ Excellent phase noise resistance ◆ Excellent multipath equalization performance ◆ Automatic detection of mode/guard interval lengths ◆ EWS (Emergency Warning System) flag output ◆ Read function of AC Carrier information corresponding to the earthquake broadcasting (ARIB STD-B31 v1.8) ◆ Enhanced in the following areas Improved CNR performance Improved performance for time varying channel ◆ Features ISDB-S ◆ Conforms to ARIB STD-B20 ◆ Supports Zero-IF tuner ◆ Tolerates large phase noise ◆ Excellent multipath equalization performance ◆ Tolerates large IQ amplitude and phase distortion 3 CXD2854ER ◆ General Features ◆ Single, 24MHz crystal with tolerance up to ±100 ppm. (Targeting support for crystal sharing with Sony SiTuner or other Sony Analogue/Digital demodulator) ◆ High performance ADC ◆ RF power level monitor ADC ◆ Low IF and Standard-IF (36, 44, 57MHz) mode input ◆ Fast 400 kHz I2C compatible bus interface ◆ Quiet I C interface for dedicated tuner control ◆ Programmable I2C addresses allowing up to four devices to be connected in a single system ◆ Automatic IF AGC and optional programmable RF AGC/GPIO functions ◆ Configurable parallel and serial MPEG-2 TS outputs with smoothing buffer ◆ Simple API ◆ Conforms to DiSEqC 1.x, DiSEqC 2.x and Single Cable Distribution (CENELEC/BS EN 50494) standards with external components. ◆ 3.3 V, 1.1 V supplies ◆ Temperature range -20 °C to +85 °C ◆ 48 pin VQFN 7 mm x 7 mm package ◆ Supplied with full reference design, including software driver, printed circuit board schematic/layouts and documentation 2 4 CXD2854ER Applications ◆ Set Top Boxes ◆ IDTV with Digital only or Hybrid Tuner Support ◆ PC TV TM ◆ PVRs and recordable Blu-ray /DVD players ◆ Professional equipment 5 CXD2854ER Contents 1. Block Diagram ----------------------------------------------------------------------------------------------------------------------------------- 7 2. Pin Layout ---------------------------------------------------------------------------------------------------------------------------------------- 8 3. Pin Description ---------------------------------------------------------------------------------------------------------------------------------- 9 4. Absolute Maximum Ratings ------------------------------------------------------------------------------------------------------------------15 5. Recommended Operating Conditions -----------------------------------------------------------------------------------------------------16 6. DC Electrical Characteristics ----------------------------------------------------------------------------------------------------------------17 7. AC Electrical Characteristics ----------------------------------------------------------------------------------------------------------------22 8. Power Supply Sequence ---------------------------------------------------------------------------------------------------------------------27 9. I/O Interfaces -----------------------------------------------------------------------------------------------------------------------------------28 9-1. Clock Interface-------------------------------------------------------------------------------------------------------------------------28 9-2. IF Input Interface for Terrestrial and Cable --------------------------------------------------------------------------------------28 9-3. IQ Input Interface for Satellite ------------------------------------------------------------------------------------------------------29 9-4. RF Level Monitor Interface ----------------------------------------------------------------------------------------------------------29 9-5. Hardware Reset -----------------------------------------------------------------------------------------------------------------------29 9-6. I2C Interfaces --------------------------------------------------------------------------------------------------------------------------30 9-7. AGC Output Interface ----------------------------------------------------------------------------------------------------------------32 9-8. TS Output Interface -------------------------------------------------------------------------------------------------------------------33 9-9. DiSEqC Interface----------------------------------------------------------------------------------------------------------------------34 9-10. General Purpose I/Os ----------------------------------------------------------------------------------------------------------------34 9-11. Test Pins --------------------------------------------------------------------------------------------------------------------------------35 10. Package Outline--------------------------------------------------------------------------------------------------------------------------------37 11. Marking-------------------------------------------------------------------------------------------------------------------------------------------38 6 CXD2854ER 1. Block Diagram Fig.1. Block Diagram 7 CXD2854ER 2. Pin Layout Fig.2. Pin Layout NOTE1) Exposed-Pad must be connected to the quiet ground level. 8 CXD2854ER 3. Pin Description Table.1. Pin Description Name No. I/O Function Equivalent Circuit Note 5 V tolerant / DVDD IE GPIO0 1 IO 1 General purpose I/O Input Enable (default: disable) VSS 5 V tolerant / DVDD GPIO2 IE General purpose I/O 2 2 IO (TSERR) Input Enable (default: disable) TS error flag Selectable output current for VSS TSERR 5 V tolerant / DVDD Selectable output current TSSYNC 3 O 3 TS sync flag VSS 5 V tolerant / DVDD Selectable output current TSVALID 4 O 4 TS valid flag VSS 5 V tolerant / DVDD Selectable output current TSCLK 5 O 5 TS clock output VSS VSS 6 n/a DVDD 7 n/a Digital ground n/a 3.3 V digital power n/a supply 5 V tolerant / DVDD Selectable output current TS parallel data 0 / TSDATA0 8 8 O It can be used as serial data TS serial data or parallel data 0. VSS 9 CXD2854ER Name No. I/O Function Equivalent Circuit Note 5 V tolerant / DVDD Selectable output current TSDATA1 9 O 9 TS parallel data 1 VSS 1.1 V digital power CVDD 10 n/a n/a supply VSS 11 n/a Digital ground n/a 5 V tolerant / DVDD Selectable output current TSDATA2 12 O 12 TS parallel data 2 VSS 5 V tolerant / DVDD Selectable output current TSDATA3 13 O 13 TS parallel data 3 VSS 5 V tolerant / DVDD Selectable output current TSDATA4 14 O 14 TS parallel data 4 VSS 5 V tolerant / DVDD Selectable output current TSDATA5 15 O 15 TS parallel data 5 VSS 5 V tolerant / DVDD Selectable output current TSDATA6 16 O 16 TS parallel data 6 VSS 10 CXD2854ER Name No. I/O Function Equivalent Circuit Note 5 V tolerant / DVDD Selectable output current TS parallel data 7 / TSDATA7 17 17 O It can be used as serial data TS serial data or parallel data 7. VSS VSS 18 n/a DVDD 19 n/a Digital ground n/a 3.3 V digital power n/a supply 5 V tolerant / DVDD Schmitt trigger input SCL 20 I 2 20 I C clock VSS 5 V tolerant / DVDD Schmitt trigger input / SDA 21 IO 2 21 I C data Open-drain output VSS 1.1 V digital power CVDD 22 n/a n/a supply 5 V tolerant DVDD DSQOUT 23 O 23 DiSEqC output VSS 5 V tolerant / DVDD IE DSQIN 24 I 24 DiSEqC input Input Enable (default: disable) VSS DVDD Internal pull-down I2C slave address , SLVADR0 25 5 V tolerant / 25 I selection VSS 11 CXD2854ER Name No. I/O Function Equivalent Circuit Note 5 V tolerant / DVDD AGC output SAGC 26 O PWM output 26 for satellite tuner VSS VSS 27 n/a CVDD 28 n/a Digital ground n/a 1.1 V digital power n/a supply 5 V tolerant / DVDD Schmitt trigger input RST_X 29 I 29 Hardware reset VSS 5 V tolerant / DVDD Internal pull-up 2 I C slave address SLVADR3 30 30 I selection VSS AVDD Internal regulated voltage 31 I-ch analog input for SIAIN 31 VINCMEN AI satellite tuner AVSS AVDD Internal regulated voltage 32 Q-ch analog input for SQAIN 32 VINCMEN AI satellite tuner AVSS 3.3 V analog power XVDD 33 n/a n/a supply XVDD XTALO 34 AO Crystal oscillator output Leave open when external Internal regulated voltage clock input to XTALI 34 XTALI 35 AI External clock input pin 35 Crystal oscillator input XVSS XVSS 36 n/a Analog ground n/a 12 CXD2854ER Name No. I/O Function Equivalent Circuit AVDD Note Differential input Internal regulated voltage 37 IF(+) analog input for TAINP 37 VINCMEN AI terrestrial tuner 38 AVSS IF(-) analog input for TAINM 38 AI terrestrial tuner AVSS 39 n/a Analog ground n/a 5 V tolerant / DVDD Test mode setting TESTMODE 40 I 0 Normal mode 1 Test mode Internal pull-down 40 This pin must be connected to ground. VSS AVDD RFAIN 41 AI RF level monitor input 41 AVSS 3.3 V analog power AVDD 42 n/a n/a supply VSS 43 n/a CVDD 44 n/a Digital ground n/a 1.1 V digital power n/a supply DVDD 5 V tolerant / Schmitt trigger input / TTUSDA 45 IO Tuner I2C data 45 Open-drain output VSS DVDD 5 V tolerant / Open-drain output TTUSCL 46 O 2 46 Tuner I C clock VSS 13 CXD2854ER Name No. I/O Function Equivalent Circuit Note 5 V tolerant / DVDD IE GPIO1 47 IO 47 General purpose I/O Input Enable (default: disable) VSS DVDD AGC output TIFAGC 48 5 V tolerant / 48 O for terrestrial tuner PWM output VSS AVSS 49 n/a Analog ground n/a NOTE1) Input voltage up to 3.6 V is acceptable on 5 V tolerant inputs even when the CXD2854ER power is off. Table.2. I/O type I/O Description I Digital Input O Digital Output IO Digital Input / Output AI Analog Input AO Analog Output 14 CXD2854ER 4. Absolute Maximum Ratings Table.3. Absolute Maximum Ratings (Ta = 25 °C, VSS = AVSS = XVSS = 0 V) Parameter Symbol Rating (*1) Unit VCVDD -0.5 to 1.54 V VDVDD -0.5 to 4.6 V VAVDD -0.5 to 4.6 V VXVDD -0.5 to 4.6 V VI5 (*2) -0.5 to VDVDD + 3.6 (6.0 V max.) (*3) V VIA (*4) -0.5 to VAVDD + 0.5 (4.6 V max.) V VIX (*5) -0.5 to VXVDD + 0.5 (4.6 V max.) V Supply Voltage Input Voltage -0.5 to VDVDD + 0.5 (4.6 V max.) in high or low state VO5 (*2) Storage Temperature V -0.5 to VDVDD + 3.6 (6.0 V max.) in 3-state (*3) Output Voltage VOX (*6) -0.5 to VXVDD + 0.5 (4.6 V max.) V Tstg -65 to 150 °C NOTE1) Absolute maximum rating values must not be exceeded, even momentarily, for any item. In addition, even when the absolute maximum ratings and operating range are not exceeded, use of this product under operating conditions (operating temperature, current, voltage, etc.) that apply a continuously high load (high temperature with high current and high voltage applied, large temperature changes, etc.) may significantly degrade reliability. NOTE2) VI5 and VO5 are the 5 V tolerant I/O ratings. NOTE3) 5 V tolerant inputs are only 5 V tolerant while the CXD2854ER power is applied. If no power is applied to CXD2854ER there is no protection to 5 V levels and the CXD2854ER may be permanently damaged. It is important to observe the conditions for 5 V protection when sequencing power supplies in the application. NOTE4) VIA is the analog input rating. The applicable pins are TAINP, TAINM, SIAIN, SQAIN and RFAIN. NOTE5) VIX is the analog input rating. The applicable pin is XTALI. NOTE6) VOX is the analog output rating. The applicable pin is XTALO. 15 CXD2854ER 5. Recommended Operating Conditions Table.4. Recommended Operating Conditions (VSS = AVSS = XVSS = 0 V) Parameter Symbol Min. Typ. Max. Unit VCVDD 0.99 1.10 1.21 V VDVDD 3.00 3.30 3.60 V VAVDD 3.00 3.30 3.60 V VXVDD 3.00 3.30 3.60 V VI5 (*1) 0 - 5.5 V VIA (*3) 0 - VAVDD V VIX (*4) 0 - VXVDD V VO5 (*1) 0 - VDVDD V VOX (*5) 0 - VXVDD V Junction Temperature Tj -20 - 125 °C Ambient Temperature Ta (*2) -20 - 85 °C Supply Voltage Input Voltage Output Voltage NOTE1) VI5 and VO5 are the 5 V tolerant I/O ratings. NOTE2) Ambient Temperature is for such test board condition given in JESD51-7 “High Effective Thermal Conductivity Test Board for Leaded Surface Mount Package”. Exposed-Pad is thoroughly attached to the test board. NOTE3) VIA is the analog input rating. The applicable pins are TAINP, TAINM, SIAIN, SQAIN and RFAIN. NOTE4) VIX is the analog input rating. The applicable pin is XTALI. NOTE5) VOX is the analog output rating. The applicable pin is XTALO. 16 CXD2854ER 6. DC Electrical Characteristics Table.5. DC Electrical Characteristics (VSS = AVSS = XVSS = 0 V, across voltage and temperature ranges in the recommended operating conditions) Parameter Symbol Condition Min. Typ. Max. Unit Pins Digital I/Os Corresponding I/Os are: GPIO[2:0], TSCLK, TSSYNC, TSVALID, TSDATA[7:0], RST_X, SLVADR0, SLVADR3, TTUSCL, TTUSDA, TIFAGC, SAGC, DSQIN, DSQOUT, TESTMODE GPIO[2:0] Input High Voltage VIH5 - 2.0 - 5.5 V RST_X SLVADR0 SLVADR3 TTUSDA Input Low Voltage VIL - -0.3 - 0.8 V DSQIN TESTMODE TIFAGC VOH2 IOH = -2 mA 2.4 - - V SAGC DSQOUT GPIO[2:0] TSCLK Output High Voltage VOH8 IOH = -8 mA 2.4 - - V TSSYNC TSVALID (*1) TSDATA[7:0] GPIO2 TSCLK VOH10 IOH = -10 mA 2.4 - - V TSSYNC TSVALID TSDATA[7:0] TIFAGC VOL2 IOL = +2 mA - - 0.4 V SAGC DSQOUT VOL4 IOL = +4 mA - - 0.4 V TTUSCL TTUSDA GPIO[2:0] TSCLK Output Low Voltage (*1) VOL8 IOL = +8 mA - - 0.4 V TSSYNC TSVALID TSDATA[7:0] GPIO2 TSCLK VOL10 IOL = +10 mA - - 0.4 V TSSYNC TSVALID TSDATA[7:0] RST_X SLVADR0 VI = 5.5 V or 0 Input Current IILH5 V - ±10 μA SLVADR3 DSQIN TESTMODE 17 CXD2854ER Parameter Symbol Condition Min. Typ. Max. Unit Pins GPIO[2:0] TSCLK TSSYNC TSVALID Output Leakage VO = 5.5 V or 0 IOZLH5 Current - - ±10 μA V TSDATA[7:0] TTUSCL TTUSDA TIFAGC SAGC DSQOUT Pull-up Resistance RPU - 25K - 80K Ω Pull-down Resistance RPD - 25K - 80K Ω - - ±10 μA All pins 3.0 3.3 5.5 V - Power-off Leakage VDVDD=0V IOFF Current SLVADR3 SLVADR0 TESTMODE VI=3.6V or 0V 2 HOST I C Interface Corresponding I/Os are: SCL, SDA I2C Bus Voltage VBUS;I2C - I2C Input High Voltage VIH;I2C - VBUS;I2C VBUS;I2C +0.5 - *0.7 V (5.5V max) SCL VBUS;I2C *0.3 2 I C Input Low Voltage VIL;I2C - -0.5 - (1.08V max) SDA V (*3) SDA Output Low VOL;SDA IOL=3mA - - 0.4 V SDA IILH;SCL VI=5.5V or 0V - - ±10 μA SCL IOZLH;SDA VO=5.5V or 0V - - ±10 μA SDA - - ±10 μA - - 1.4 Vp-p - - 1.0 Vp-p Voltage SCL Input Current SDA Output Leakage Current I2C Power-off Leakage VDVDD=0V IOFF;I2C Current VI=3.6V or 0V SCL SDA IF Input for Terrestrial Corresponding I/Os are: TAINP, TAINM Differential IF Input Full Scale VFS;IF input Range TAINP TAINM TAINP - TAINM IQ Input for Satellite Corresponding I/Os are: SIAIN, SQAIN IQ Input Full Scale Single-end VFS;IQ Range input 18 SIAIN SQAIN CXD2854ER Parameter Symbol Condition Min. Typ. Max. Unit Pins 0.35 - 1.4 Vp-p XTALI 9.6 16.8 29.3 mS XTALO - - VAVDD Vpp RFAIN V RFAIN Clock Input Corresponding I/Os are: XTALI, XTALO XTALI Input Dynamic AC coupled VIN;XI Range sine wave (*2) Δof Io = -2 mA XTALO gm;XO Transconductance and Io=0 mA RF Level Monitor Corresponding I/Os are: RFAIN RFAIN Input Full Scale Single-end VFS;RF Range input RFAIN Full-scale VAVDD VFST;RF - Transition Voltage VAVDD + - 0.015 0.015 RFAIN Zero-scale VZST;RF - -0.015 - 0.015 V RFAIN DNLRF 8-bit resolution -0.5 - 0.5 LSB RFAIN INLRF 8-bit resolution -1.0 - 1.0 LSB RFAIN Transition Voltage RFAIN Differential Non Linearity RFAIN Integral Non Linearity NOTE1) Output current of GPIO2, TSCLK, TSSYNC, TSVALID, TSDATA[7:0] can be selected by the register settings. NOTE2) This range is specified to ensure correct propagation of an external clock through the internal logic. It does not apply when a crystal is connected between XTALO and XTALI. NOTE3) I2C input low voltage level conforms to the I2C bus specification, which is VBUS;I2C * 0.3, when VBUS;I2C is less than or equal to 3.6 V. 19 CXD2854ER Table.6. Operating Current and Standby Current (VSS = AVSS = XVSS = 0 V, across voltage and temperature ranges in the recommended operating conditions) Parameter Condition Symbol Min. Typ. Max. Unit 256QAM, GI = 1/128, CR = 3/5, ICVDD;DVB-T2 - 311 550 mA FFT32K, BW = 8 MHz, IDVDD;DVB-T2 (*2) - 8 9 mA CNR = 17.2 dB IAVDD;DVB-T2 43 48 mA RF level monitor is active IXVDD;DVB-T2 - 8 9 mA ICVDD;DVB-T - 116 323 mA IDVDD;DVB-T (*2) - 8 9 mA IAVDD;DVB-T - 43 48 mA IXVDD;DVB-T - 8 9 mA ICVDD;DVB-C2 - 240 462 mA IDVDD;DVB-C2 (*2) - 8 9 mA IAVDD;DVB-C2 - 43 48 mA IXVDD;DVB-C2 - 8 9 mA ICVDD;DVB-C - 50 248 mA 256QAM, SR = 7.2 Msym/s IDVDD;DVB-C (*2) - 8 9 mA RF level monitor is active IAVDD;DVB-C - 43 48 mA IXVDD;DVB-C - 8 9 mA ICVDD;DVB-S2 - 377 595 mA 8PSK, CR = 3/5, SR = 45 Msym/s, IDVDD;DVB-S2 (*2) - 9 13 mA CNR = 5.8 dB IAVDD;DVB-S2 - 63 70 mA IXVDD;DVB-S2 - 8 9 mA ICVDD;DVB-S - 106 269 mA IDVDD;DVB-S (*2) - 9 13 mA IAVDD;DVB-S - 63 70 mA IXVDD;DVB-S - 8 9 mA Normal Operating Current DVB-T2 64QAM, GI = 1/32, CR = 7/8, DVB-T FFT8K, BW = 8 MHz RF level monitor is active 4096QAM, GI = 1/128, CR = 9/10, DVB-C2 BW = 8 MHz, CNR = 38 dB RF level monitor is active DVB-C DVB-S2 DVB-S QPSK, CR = 7/8, SR = 45 Msym/s 20 CXD2854ER Parameter Condition Symbol Min. Typ. Max. Unit ICVDD;ISDB-T - 116 323 mA 64QAM, GI = 1/32, CR = 7/8, IDVDD;ISDB-T (*2) - 8 9 mA MODE3, 13seg, BW = 6 MHz IAVDD;ISDB-T - 43 48 mA IXVDD;ISDB-T - 8 9 mA ICVDD;EWS - 102 303 mA IDVDD;EWS (*2) - 0.2 2 mA IAVDD;EWS - 43 48 mA IXVDD;EWS - 8 9 mA ICVDD;ISDB-T - 76 239 mA 8PSK(46slot) IDVDD;ISDB-T (*2) - 9 13 mA QPSK, R1/2 (2slot) IAVDD;ISDB-T - 53 60 mA IXVDD;ISDB-T - 8 9 mA ICVDD;Sleep - 20 64 mA IDVDD;Sleep - 0.2 0.5 mA IAVDD;Sleep - 9 12 mA IXVDD;Sleep - 8 9 mA ICVDD;Shutdown - 5 45 mA IDVDD;Shutdown - 0.2 0.5 mA IAVDD;Shutdown - 6 9 mA IXVDD;Shutdown - 0.001 0.002 mA ISDB-T 64QAM, GI = 1/32, CR = 7/8, ISDB-T MODE3, 13seg, BW = 6 MHz (EWS) When in EWS mode ISDB-S Standby Current When in Sleep mode (*3) Sleep ADC bias is active (*1) When in Shutdown mode (*3) Shutdown ADC bias is active (*1) NOTE1) The maximum standby current is at Ta = 85 °C. NOTE2) DVDD current consumption (IDVDD) is calculated based on the following assumptions: Typical current: TS loading 15 pF, TIFAGC/SAGC loading 1 pF held at center voltage. Maximum current: TS loading 15 pF, TIFAGC/SAGC loading 15 pF held at center voltage, all internal pull-up/down resistors driven by the opposite polarity. NOTE3) “Sleep mode” is when the reference clock is input to the demodulator and the demodulator is ready to demodulate. “Shutdown mode” is when the reference clock to the demodulator is disabled by oscillator enable. 21 CXD2854ER 7. AC Electrical Characteristics Table.7. AC Electrical Characteristics (VSS = AVSS = XVSS = 0 V, across voltage and temperature ranges in the recommended operating conditions) Parameter Symbol Condition Min. Typ. Max. Unit fSCL - - - 400 kHz tLOW;SCL - 1.3 - - μs tHIGH;SCL - 0.6 - - μs tHD;STA - 0.6 - - μs tSU;STA - 0.6 - - μs I2C Data Hold Time tHD;DAT - 0.0 - 0.9 μs I2C Data Setup Time tSU;DAT - 100 - - ns tSU;STO - 0.6 - - μs tSP;I2C - - - 50 ns tBUF;I2C - 1.3 - - μs Pins HOST I2C Interface Corresponding I/Os are: SCL, SDA SCL Clock Frequency Low Period of the SCL SCL Clock High Period of the SCL Clock Hold Time START Condition Setup Time for a Repeated START Condition Setup Time for SCL SDA STOP Condition Pulse Width of Spikes Allowed Bus Free Time between a STOP and START SDA Condition SDA Output Fall tof;I2C (*1) 21 - 250 ns CIN;I2C - - - 10 pF CLD;I2C - - - 400 pF Time I2C Input Capacitance SCL SDA 2 I C Output Load Capacitance 22 SDA CXD2854ER Parameter Symbol Condition Min. Typ. Max. Unit Pins TS Output Corresponding I/Os are: TSCLK, TSSYNC, TSVALID, TSDATA[7:0], GPIO2(TSERR) (*4) tCYC;P 61.6 - - ns 7.7 - - ns 27.7 - - ns 3.0 - - ns 27.7 - - ns 3.0 - - ns -2.4 - 2.4 ns -1.7 - 1.2 ns - - - 15 pF All pins (*2) - - 15 pF All pins CIN;GPIO - - - 5 pF All pins CLD;GPIO (*8) - - 20 pF All pins CIN;TTU - - - 5 pF TTUSCL CLD;TTU - - - 20 pF All pins CIN;DSQ - - - 5 pF DSQIN CLD;DSQ - - - 15 pF DSQOUT TSCLK Clock Cycle Parallel output Serial output tCYC;S (*5) (*9) tLOW;P Parallel output TSCLK Clock Low Serial output Period Time tLOW;S TSCLK (*5) (*9) tHIGH;P Parallel output TSCLK Clock High Serial output Period Time tHIGH;S (*5) (*9) tPD;P Parallel output TS Output Serial output Propagation Delay tPD;S Except TSCLK (*5) TS Output Load CLD;TS Capacitance AGC Output Interface Corresponding I/Os are: TIFAGC, SAGC AGC Output Load CLD;AGC Capacitance GPIO Interface Corresponding I/Os are: GPIO[2:0] GPIO Input Capacitance GPIO Output Load Capacitance 2 Tuner I C Interface Corresponding I/Os are: TTUSCL, TTUSDA Tuner I2C Input Capacitance Tuner I2C Output Load Capacitance DiSEqC Interface Corresponding I/Os are: DSQIN, DSQOUT DiSEqC Input Capacitance DiSEqC Output Load Capacitance 23 CXD2854ER Parameter Symbol Condition Min. Typ. Max. Unit Pins All pins Other I/Os Corresponding I/Os are: RST_X, SLVADR0, SLVADR3, TESTMODE Misc Input CIN;MISC - - - 5 pF FIN;IF - 0.1 - 60 MHz ZdiffNOR;IF Differential 3.4 - 7.0 kΩ Cpacitance IF Input for Terrestrial Corresponding I/Os are: TAINP, TAINM IF Input Bandwidth IF Input Impedance in Normal Operation Differential All pins IF Input Impedance ZdiffSTB;IF 8.0 - 12.0 kΩ - 24 - 36 pF FIN;IQ - 0.001 - 36 MHz ZINNOR;IQ - 2.5 - 4.5 kΩ ADC_VINCMEN in Standby =1 IF Input Capacitance CIN;IF IQ Input for Satellite Corresponding I/Os are: SIAIN, SQAIN IQ Input Bandwidth IQ Input Impedance in Normal Operation Single-end All pins IQ Input Impedance ZINSTB;IQ 3.2 - 100 kΩ - 20 - 31 pF FOSC;XI (*6) - 24 - MHz Ftol;XI (*3) - - ±100 ppm ADC_VINCMEN in Standby =1 IQ Input Capacitance CIN;IQ Clock Input Corresponding I/Os are: XTALI, XTALO XTALI Input Clock Frequency XTALI Frequency Tolerance XTALI XTALI Input ZIN;XI - 160 - 245 kΩ CIN;XI - 3 - 5 pF COUT;XO - 2 - 4 pF Impedance XTALI Input Capacitance XTALO Output Capacitance 24 XTALO CXD2854ER Parameter Symbol Condition Min. Typ. Max. Unit FIN;RF - 0 - 200 kHz ZIN;RF - 1.0 - - MΩ CIN;RF - 3 - 5 pF Pins RF Level Monitor Input Corresponding I/O is: RFAIN RFAIN Input Bandwidth RFAIN Input RFAIN Impedance RFAIN Input Capacitance NOTE1) Output fall time from VIH;I2C min to VIL;I2C max with a bus capacitance from 10 pF to 400 pF. NOTE2) This is the allowable capacitance value before the RC filter. NOTE3) Total of frequency tolerance includes aging and temperature stability. NOTE4) These pins must be set to the same output current mode. NOTE5) Choose output current mode so that TS outputs swing rail-to-rail to ensure AC timings. It is recommended to use 10 mA setting when TS clock frequency is above 100 MHz. NOTE6) Clock frequency must be carefully chosen depending on IF frequency of tuner to avoid clock interference to IF. Mandatory setting registers according to the XTALI input clock frequency. NOTE8) Refer to TS output load capacitance parameter for GPIO2 when GPIO2 is used as TSERR to align with TS interface AC timing including TSERR. NOTE9) These values are for the maximum TS serial clock frequency setting. TS serial clock frequency can be selected 2 by I C registers as shown in TS Output Interface section to reduce TS signal digital noise interference to IF. 25 CXD2854ER tof 70 % SDA 30 % tSU;DAT tHD;STA tBUF tSP tLOW SCL tHD;STA tSU;STA tHD;DAT S tSU;STO tHIGH Sr START Repeated START Fig.3. Default TSCLK polarity 2 Waveform of I C Interface tLOW tHIGH 50 % TSCLK tCYC TSDATA[7:0] TSVALID TSSYNC GPIO2(TSERR) 50 % tPD Inverted TSCLK polarity tHIGH TSCLK tLOW 50 % tCYC TSDATA[7:0] TSVALID TSSYNC GPIO2(TSERR) 50 % tPD NOTE: TSCLK polarity can be selected by a register setting. Fig.4. Waveform of TS Output Interface 26 P S STOP START CXD2854ER 8. Power Supply Sequence For all power supplies (i.e. CVDD, DVDD, AVDD and XVDD), there is no restriction on the order of applying or removing the power supplies. 27 CXD2854ER 9. I/O Interfaces 9-1. Clock Interface Corresponding I/Os are: XTALI and XTALO The CXD2854ER operates with the reference clock from a crystal or external clock source. XTALI and XTALO are the crystal oscillator input and output. 2 The oscillator is enabled by default and can be disabled by an I C register. XTALI, XTALO Internal voltage bias exists on XTALI and XTALO The crystal oscillator has internal bias voltage to pull XTALI to its operating DC level when the oscillator is active. There are two ways to input clock, one is to connect crystal between XTALI and XTALO, and other is to input AC coupled external sine wave clock from XTALI. 9-2. IF Input Interface for Terrestrial and Cable Corresponding I/Os are: TAINP and TAINM TAINP, TAINM Initial Condition: Hi-Z (Not biased) These are the differential IF input interface for terrestrial and cable. Standard-IF signal and Low-IF signal are supported. Supported IF center frequency for terrestrial(DVB) ◆ Standard-IF : 36.167 MHz ◆ Low-IF : 4 - 5 MHz typ. (*1) Supported IF center frequency for terrestrial(ISDB/SBTVD) ◆ Standard-IF : 44 MHz, 57 MHz ◆ Low-IF : 4 - 5 MHz typ. (*1) Supported IF center frequency for cable ◆ Standard-IF : 36.125 MHz ◆ Low-IF : 4 - 5 MHz typ. (*1) NOTE1) Low-IF signal frequencies are not standardized and restrictions may apply to certain combinations of center frequency and bandwidth. The ADC is internally biased at the center of the dynamic range in operating mode. When the CXD2854ER is powered-up, TAINP and TAINM are at high impedance without internally bias voltage. 28 Therefore, the AC signal input may be clamped CXD2854ER by the ESD device to ground in standby mode depending on the voltage level applied. 9-3. IQ Input Interface for Satellite Corresponding I/Os are: SIAIN and SQAIN SIAIN, SQAIN Initial Condition: Hi-Z (Not biased) These are the single-end zero-IF input interfaces for satellite. SIAIN is the I-ch input and SQAIN is the Q-ch input. The ADC is internally biased at the center of the dynamic range in operating mode. When the CXD2854ER is powered-up, SIAIN and SQAIN are at high impedance without internally bias voltage. Therefore, the AC signal input may be clamped by the ESD device to ground in standby mode depending on the voltage level applied. 9-4. RF Level Monitor Interface Corresponding I/O is: RFAIN RFAIN Initial Condition: Hi-Z This is tuner RF level monitor input pin. RFAIN monitors the input voltage level and converts to 8-bit digital data based on AVDD to AVSS full scale range. 9-5. Hardware Reset Corresponding I/O is: RST_X RST_X I/O type: Schmitt, 5 V tolerant This is the hardware reset pin to initialize CXD2854ER. RST_X needs to be held low before ramping up power supplies and until the oscillator and PLL becomes stable. SLVADR0, SLVADR3 and TESTMODE must be stable before asserting RST_X. Table.8. RST_X truth table RST_X 0 Description Assert hardware reset 29 CXD2854ER RST_X Description 1 Negate hardware reset 2 9-6. I C Interfaces Corresponding I/Os are: SCL, SDA, TTUSCL, TTUSDA, SLVADR0 and SLVADR3 2 I C bus is used to control CXD2854ER. CXD2854ER supports both Standard Mode and Fast Mode. CXD2854ER does not convert the mode between host and RF tuner, so whatever mode is selected by the host to communicate with the CXD2854ER is the mode used between CXD2854ER and RF tuner. For example, if the host communicates with the CXD2854ER in Standard Mode using SCL and SDA, the communications between CXD2854ER and RF tuner using TTUSCL and TTUSDA are also in Standard Mode. Table.9. Supported I2C modes I2C mode Description Standard Mode SCL operates at 100 kHz. When in Standard Mode, TTUSCL also operates at 100 kHz. Fast Mode SCL operates at 400 kHz. When in Fast Mode, TTUSCL also operates at 400 kHz. I2C-bus specification compatibility The host I2C interface (i.e. SCL and SDA) supports the mandatory protocol features for a Slave configuration as listed in the NXP specification reference document: UM10204 “I 2C - Bus specification and user manual Rev. 03 – 19 June 2007”. Refer to Table2 on page 8 of the reference document. The tuner I2C interface does not support multi-master function. Access to RF tuner 2 2 2 There are two ways to access RF tuner through tuner I C interface. One is “I C Repeater” function and the other is “I C Gateway” function. I2C Repeater function allows a host directly communicates to RF tuner through CXD2854ER. CXD2854ER just transparently propagates the I2C commands received from the host I2C interface to the tuner I 2C interface. CXD2854ER can enable or 2 2 disable I C Repeater function by setting I C register of the CXD2854ER. 2 I C gateway function requires a special protocol to communicate with RF tuner. When a host writes a gateway command 2 (0x09) to the CXD2854ER, CXD2854ER recognize the gateway command and propagates data between the host I C 2 interface and the tuner I C interface. 2 2 Unlike I2C Repeater function, I C gateway function does not require an I C register setting to enable or disable the function. Refer to the application note for I2C access sequences in detail. 30 CXD2854ER I2C slave address CXD2854ER operates under 7-bit slave address and requires two slave addresses, the address for system part and the address for demodulator part. The set of slave addresses can be chosen by setting the two slave address selection pins, 2 SLVADR0 and SLVADR3. The I C registers of all demodulator cores share the same slave address. 2 Table.10. I C Slave Addresses Including read/write bit When SLVADR0 = ’0’ and When SLVADR0 = ’1’ and SLVADR3 = ’0’ SLVADR3 = ’0’ Write Read Write Read System part 0xCC 0xCD 0xCE 0xCF Demodulator part 0xC8 0xC9 0xCA 0xCB When SLVADR0 = ’0’ and When SLVADR0 = ’1’ and SLVADR3 = ’1’ SLVADR3 = ’1’ Write Read Write Read System part 0xDC 0xDD 0xDE 0xDF Demodulator part 0xD8 0xD9 0xDA 0xDB SCL, SDA I/O type: Schmitt, 5 V tolerant, Open-drain Initial Condition: Hi-Z These are I2C slave interface to control the CXD2854ER. The bus can also communicate to RF tuner through the tuner I 2C interface (i.e. TTUSCL and TTUSDA) under the repeater function that transparently propagates the I 2C commands from a host to RF tuner. Mandatory protocol features for a slave configuration are supported as listed in the NXP specification 2 reference document: UM10204”I C - Bus specification and user manual Rev.03 – 19 June 2007”. Refer to Table 2 on page 8 of the reference document. TTUSCL, TTUSDA I/O type: Schmitt, 5 V tolerant, Open-drain Initial Condition: Hi-Z 2 2 These are for the tuner I C bus that connects CXD2854ER to RF tuner. The tuner I C Interface supports the mandatory protocol features for a single master configuration as listed in the NXP specification reference document: UM10204 “I 2C Bus specification and user manual Rev. 03 – 19 June 2007”. Refer to Table 2 on page 8 of the reference document. These pins are expected to be pulled up by external pull-up resistors. They must be pulled up even when they are not 31 CXD2854ER used in a system. SLVADR0 I/O type: Internal pull-down, 5 V tolerant 2 This is the bit 0 (LSB) of I C slave address. The pin is internally pulled-down. Therefore, when the pin is open, SLVADR0 2 becomes “0”. Fix SLAVDR0 before the hardware reset is negated to make sure the I C slave address of the CXD2854ER is fixed before it becomes active. Table.11. SLVADR0 truth table SLVADR0 Description 2 0 Set LSB of the I C slave address to 0. 1 Set LSB of the I2C slave address to 1. SLVADR3 I/O type: Internal pull-up, 5 V tolerant This is the bit 3 of I2C slave address. The pin is internally pulled-up. Therefore, when the pin is open, SLVADR3 becomes “1”. Fix SLAVDR3 before the hardware reset is negated to make sure the I2C slave address of the CXD2854ER is fixed before it becomes active. Table.12. SLVADR3 truth table SLVADR3 9-7. Description 2 0 Set Bit 3 of the I C slave address to 0. 1 Set Bit 3 of the I C slave address to 1. 2 AGC Output Interface Corresponding I/Os are: TIFAGC and SAGC The AGC output operates as a control signal from CXD2854ER to RF. It creates a feedback loop to automatically adjust input signal level received by the demodulator. At the AGC pin, the control signal is output in PWM form. PWM signal requires external RC components to integrate LPF to remove PWM harmonic content. The PWM signal with integrated LPF can create DC reference voltage. TIFAGC I/O type: n/a (CMOS output) Initial Condition: Hi-Z 32 CXD2854ER This is the PWM output to control IF AGC gain for terrestrial tuner. SAGC I/O type: n/a (CMOS output) Initial Condition: Hi-Z This is the PWM output to control AGC gain for satellite tuner. 9-8. TS Output Interface Corresponding I/Os are: TSCLK, TSVALID, TSSYNC and TSDATA[7:0] The TS output can be selected to be either parallel output or serial output. The serial data (TSDATA) can be output from either TSDATA7 or TSDATA0. 2 TS serial clock frequency can be selected from the following table by setting I C registers to reduce TS signal digital noise interference to IF. Table.13. TS serial clock frequencies for terrestrial and cable and satellite Standard DVB-T2/T/C2/C DVB-S2/S ISDB-T ISDB-S XTALI Input Clock 24M Hz 24 MHz 24M Hz 24 MHz TS Clock Frequency [MHz] 96.00 128.00 96.00 128.00 (Clock duty is 50 %) 76.80 96.00 76.80 96.00 64.00 76.80 64.00 76.80 48.00 64.00 48.00 64.00 38.40 48.00 38.40 48.00 38.40 38.40 CXD2854ER has a TS smoothing function to suppress PCR jitter of TS data. The following table shows the target PCR jitter values of CXD2854ER. Table.14. TS output PCR jitter values Parameter Target Value PCR jitter (*1) (*2) ±5μs NOTE1) In case of DVB-T2 standard, valid for modulation modes specified in DTG D-Book 7.0 Table 9-3a and Table 9-3b, and NorDig-Unified Test Specifications version 2.2.1 Table 2.17. M-PLP data with incorrect ISSY information. 33 This value will not be guaranteed if a transmitter sends CXD2854ER NOTE2) In case of DVB-C2 standard, valid for VV1XX modes. This value will not be guaranteed if a transmitter sends M-PLP data with incorrect ISSY information. TSCLK, TSVALID, TSSYNC, TSDATA[7:0] I/O type: 5V tolerant, Selectable Output Current Initial Condition: Hi-Z These are the transport stream output pins. Two output current modes are supported. These are selected by the control registers. 9-9. DiSEqC Interface Corresponding I/Os are: DSQIN and DSQOUT DiSEqC interface conforms to DiSEqC 1.x, DiSEqC 2.x and Single Cable Distribution (CENELEC/BS EN 50494) standards with external components. Supported DiSEqC versions are: DiSEqC 1.0, 1.1, 1.2, 2.0, 2.1 and 2.2. DSQIN I/O type: 5 V tolerant Initial Condition: Hi-Z Up to 16 words (max.) of the reply signal output by a slave device can be received. DSQOUT I/O type: 5 V tolerant Initial Condition: Hi-Z DiSEqC command, Tone Burst and Continuous Tone can be output. 9-10. General Purpose I/Os Corresponding I/Os are: GPIO0, GPIO1 and GPIO2 GPIO pins (i.e. GPIO0, GPIO1 and GPIO2) operate as a programmable control signal configured through I 2C register setting. GPIO pins have multiple functions which are shown in the following table. pin. TSERR signal can be output only from GPIO2 All other functions can be mapped to any of GPIO0, GPIO1 and GPIO2. PWM signal requires external RC components to integrate LPF to remove PWM harmonic content. reference voltage. 34 The PWM signal with integrated LPF can create DC CXD2854ER Table.15. GPIO Functions Pin Current Signal GPIO0/ 8 mA (*1) GPO I/O General purpose output O GPIO1/ (default) GPIO2 GPI Description 2 Output “High” or “Low” by writing I C registers General purpose input I PWM 2 Monitoring “High” or “Low” at terminal voltage by reading I C registers PWM signal output for general purpose. It can be used for RFAGC with O LPF. FEF_PART FEF part indicator (DVB-T2) O (L: FEF is Not active, H: FEF is active) GPIO0/ 8 mA (*1) T.B.D - T.B.D DSQTXEN O Control signals for Single Cable Distribution DSQRXEN O Control signals for DiSEqC 2.x GPIO1/ GPIO2/ TSDATA6 (*3) GPIO2 8 mA or TSERR Output TS error flag O 10 mA (*2) (L: No error, H: Error exists) NOTE1) Output current mode must be set to 8 mA (IOL = +8mA, IOH = -8mA) for these functions. NOTE2) Output current mode must be set to match with other TS outputs (i.e. TSCLK, TSVALID, TSSYNC, TSDATA[7:0]) NOTE3) DSQTXEN and DSQRXEN can be output from TSDATA6 pin when TS output is set to serial output mode. GPIO0, GPIO1 and GPIO2 I/O type: 5 V tolerant, Selectable output current (GPIO2 only) Initial Condition: Hi-Z These are the general purpose I/Os. GPIO2 has selectable output current function to match AC timing with TS interface when GPIO2 is used as TSERR. 9-11. Test Pins Corresponding I/O is: TESTMODE TESTMODE I/O type: Internal pull-down, 5 V tolerant This pin is to set LSI testing mode. For normal operation, connect TESTMODE directly to ground. 35 CXD2854ER Table.16. TESTMODE truth table TESTMODE Description 0 Set TESTMODE = 0 when in normal operation 1 TESTMODE = 1 is only for LSI testing purpose. 36 CXD2854ER 10. Package Outline 37 CXD2854ER 11. Marking 38 CXD2854ER IMPORTANT INFORMATION Application circuits shown, if any, are typical examples illustrating the operation of the devices, they are shown for general guidance purposes and may not be specifically relevant to individual requirements. Therefore, whilst Sony endeavour to ensure th at the information shown is as accurate as reasonably possible, Sony does not accept liability for any faults, damage or losses of any nature (i ncluding, but not limited, to consequential loss) arising from the use of the information contained in this document. Customers considering the use of any device shown in this document in special applications where extremely high levels of rel iability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, medical devices for life support, etc.) are recommended to consult with their Sony sales representatives before such use. All information contained in this document is proprietary to Sony. Title to all information remains in Sony, and the supply of the information contained in the document does not convey any license by implication or otherwise in respect of any Intellectual Property Rights. None of the information shown may be copied or any drawings or specifications reproduced without the prior consent of Sony. document is delivered to registered customers only for customers' use of corresponding products. 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