E07Z39B22

Digital CCD Camera Head Amplifier
CXA3796N
Description
The CXA3796N is a bipolar IC developed as a head amplifier for digital CCD cameras. This IC provides the
following functions: correlated double sampling, AGC for the CCD signal, A/D sample and hold, blanking, A/D
reference voltage, and an output driver.
(Applications: CCD cameras)
Features
 High sensitivity made possible by a high-gain AGC amplifier
 Blanking function provided for the purpose of calibrating the CCD output signal black level
 Regulator output pin provided for A/D converter reference voltage
 Built-in sample-and-hold circuits for camera signals required by external A/D converters
< Changes and improvements from CXA2096N >
 Selectable maximum gain of AGC amplifier (MAXGAIN mode)
 Minus gain setting of AGC amplifier (GAINSHIFT mode)
 CCDLEVEL output blanking function
 Input dynamic range expansion
 Noise characteristics improvement
Package
24-pin SSOP (Plastic)
Structure
Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license
by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating
the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E07Z39B22
CXA3796N
Absolute Maximum Ratings
 Supply voltage
VCC
5.5
V
 Operating temperature
Topr
–20 to +75
C
 Storage temperature
Tstg
–65 to +150
C
 Allowable power dissipation
PD
417
mW
3.0 to 3.6
V
Operating Conditions
 Supply voltage
VCC1, 2, 3
-2-
CXA3796N
ICONT
VCC2
DIN
PIN
CLPDM
GND1
SHD
SHP
VCC1
CCDLEVEL
AGCCONT
AGCCLP
Block Diagram and Pin Configuration
24
23
22
21
20
19
18
17
16
15
14
13
BUF
SH1
SH2
DC SHIFT
AGC
OB SW
SH3
AGC
CLP
DMSW2
CDS
CLP2
VREF
CAM SH
DMSW1
CDS
CLP1
VRT
DRV
OFFSET
VRT
VRB
DRV
BLK SW
VRB
DRVOUT
VCC3
8
9
10
11
12
CLPOB
GND3
7
XRS
GAINSHIFT
6
PBLK
5
OFFSET
4
VRT
3
VRB
2
MAXGAIN
1
GND2
DRV
-3-
CXA3796N
Pin Description
(VCC1, 2, 3 = 3.3V)
Pin
No.
Symbol
1 GND2
3 GND3
19 GND1
2 GAINSHIFT
I/O
Pin voltage
—
GND
Gain shifted
according to the
following setting.
I
VCC to 0.7VCC: 0dB
OPEN: –3dB
0.3VCC to GND: –6dB
Equivalent circuit
Description
Ground.
11µA
1k
120k
80k
40k
2k
2
2.2V
40k
120k
7p
1k
IOFFSET
Gain shift.
80k
27.5µA
220µA
11µA
40k
27.5µA
0 to
55µA
Driver output for A/D
converter capable of
direct DC coupling
capacitor.
2k
VRB =
1.485V
4 DRVOUT
55µA
55µA
O VRB to VRB + 110mV
ICONT
3.52 to 7.04mA
2k
Dynamic range = 1.07Vp-p.
4
CAM signal
6
5 VCC3
16 VCC1
23 VCC2
6 MAXGAIN
—
VCC
VCC to 0.7VCC: 34dB
OPEN: 26dB
I
0.3VCC to GND: 30dB
* AGCCONT = 3.0V
Power supply.
11µA
1k
120k
80k
40k
2k
6
2.2V
40k
120k
7p
1k
-4-
80k
11µA
40k
MAXGAIN.
CXA3796N
Pin
No.
Symbol
I/O
Pin voltage
Equivalent circuit
Description
1.485V regulator output.
100
1k
200
16.5k
7 VRB
O
1.485V (0.45VCC)
300
300
7
1.485V
1.3k
13.5k
110µA
4k
12
Be sure to decouple this
pin near the IC pins to
prevent the oscillation
and external noise when
this pin is not used.
(Recommended
capacitor value: 4.7F)
2.585V regulator output.
16k
1k
12
6.5k
8 VRT
O
2.585V (0.783VCC)
300
300
2.58V
8
23.5k
200
55µ
1k
50k
220µ
55µ
50k
200
1k
Controls the output offset.
2k
60k
1.65V
9 OFFSET
I
1.65 to 3.3V & 0V
1.5k
VRB
3k
24k
55µA
60k
55µA
2k
9
10 PBLK
60k
When 0V (preset mode):
VRB + 40mV
Camera signal
preblanking pulse input.
1k
60k
2k
I
When 3.3V: VRB + 0mV
When 1.65V: VRB + 110mV
1k
55µA
VTH = 1.65V
Be sure to decouple this
pin near the IC pins to
prevent the oscillation
and external noise when
this pin is not used.
(Recommended
capacitor value: 4.7F)
10
1.65V
Active: Low
60k
27.5µA
50µA
VTH = 0.74V
Active when Low.
Calibrates the black level
of the AGC output
waveform.
When PBLK is Low, the
DRVOUT potential is
forced to VRB.
440µA
1k
24k
145
11 XRS
11
I
Sampling
0.74V
7k
98µA
-5-
1k
Camera signal sampleand-hold pulse input.
CXA3796N
Pin
No.
Symbol
I/O
Pin voltage
Equivalent circuit
12 CLPOB
1k
16k
VTH = 1.65V
Description
60k
12
Clamp pulse input used to
clamp the optical black
portion of the camera
signal after it passes
through the AGC amplifier.
13
AGC clamp capacitor.
(Recommended value:
0.1F)
2k
I
1.65V
Active: Low
60k
55µA
1k
5k
5k
145
13 AGCCLP
O
Approximately1.4V
145
1k
50k
1.9V
1k
1k
1k
500
14
3.4k
3.4k 3.4k
3.18V
I
500k
2.475V
220µA
14 AGCCONT
3.4k
220µA
1.65 to 3.3V
(0.5VCC to 1.0VCC)
3k
ICONT
-6-
110µA
110µA 110µA
110µA
3k
AGC gain control input.
When 1.65V: –1 dB
(Minimum gain)
When 3.3V: 31.5 dB
(Maximum gain)
 MAXGAIN = OPEN
 GAINSHIFT = VCC
* Gain values can be
changed by setting two
pins shown above.
CXA3796N
Pin
No.
Symbol
I/O
Pin voltage
Equivalent circuit
Description
220µA
15 CCDLEVEL O
CCD signal black
level of DIN input
Approximately2.5V
15
500
500
250
17 SHP
I
VTH = 0.74V
Enables monitoring output
of the SH3 output camera
signal.
250
55µA
Preset level sample-andhold pulse input.
440µA
1k
36k
145
17
Sampling
18
0.745V
10.5k
18 SHD
I
VTH = 1.65V
Data level sample-andhold pulse input.
1k
1k
60k
1k
2k
20 CLPDM
1.65V
I
20
Active: Low
Clamp pulse input used
to clamp the dummy
pixel portion of the input
CCD signal.
60k
55µA
500
500
1k
145
21 PIN
22 DIN
Black level
Approximately2.5V
I
11µA
21
49k
22
1k
1.65 to 3.3V
22k
1k
11k
1k
27.5µA
DRVOUT output
waveform rise time
control input.
1k
15k
I
CCD signal input.
145
330µA
24 ICONT
500
11µA
2k
2.475V
24
6k
6k
45k
110µA
-7-
When 1.65V: Maximum
rise time
When 3.3V: Minimum
rise time
CXA3796N
Electrical Characteristics
(Ta = 25C, VCC1, 2, 3 = 3.3V)
Item
Symbol
Min. Typ. Max. Unit
IDC
VAGCCONT = 1.65V, open between VRT and VRB
33
MAXGAIN = OPEN, GAINSHIFT = VCC
ICONT = 3.3V, SHP, SHD = Duty75% (H:L = 3:1)
VCC = 3.0V
IDC30
VAGCCONT = 1.5V, open between VRT and VRB
29.5 41.3
MAXGAIN = OPEN, GAINSHIFT = VCC
ICONT = 3.0V, SHP, SHD = Duty75% (H:L = 3:1)
MAXGAIN1
DIN = 1s, 15 mVp-p pulse
A CONT max.1 VAGCCONT = 3.0V, ICONT = 3.3V
MAXGAIN = VCC, GAINSHIFT = VCC
31
34
37
MAXGAIN2
DIN = 1s, 20 mVp-p pulse
A CONT max.2 VAGCCONT = 3.0V, ICONT = 3.3V
MAXGAIN = GND, GAINSHIFT = VCC
27
30
33
MAXGAIN3
DIN = 1s, 30 mVp-p pulse
A CONT max.3 VAGCCONT = 3.0V, ICONT = 3.3V
MAXGAIN = OPEN, GAINSHIFT = VCC
23
26
29
DIN = 1s, 500 mVp-p pulse
GAINSHIFT1 A CONT min.1 VAGCCONT = 1.65V, ICONT = 3.3V
MAXGAIN = OPEN, GAINSHIFT = VCC
—
–0.8 1.4
DIN = 1s, 500 mVp-p pulse
GAINSHIFT2 A CONT min.2 VAGCCONT = 1.65V, ICONT = 3.3V
MAXGAIN = OPEN, GAINSHIFT = OPEN
—
–3.6
DIN = 1s, 500 mVp-p pulse
GAINSHIFT3 A CONT min.3 VAGCCONT = 1.65V, ICONT = 3.3V
MAXGAIN = OPEN, GAINSHIFT = GND
—
–6.5 –3.5
VCC = 3.3V
Current
consumption
AGC
Conditions
45.7 65.6
mA
59
–1
Gain variable
AGC G1
width 1
A CONT max.1 – A CONT min.1
29.6 34.8
—
Gain variable
AGC G2
width 2
A CONT max.2 – A CONT min.1
25.6 30.8
—
Gain variable
AGC G3
width 3
A CONT max.3 – A CONT min.1
21.6 26.8
—
Gain variable
AGC G4
width 4
A CONT max.1 – A CONT min.2
32
37.6
—
Gain variable
AGC G5
width 5
A CONT max.2 – A CONT min.2
28
33.6
—
Gain variable
AGC G6
width 6
A CONT max.3 – A CONT min.2
24
29.6
—
Gain variable
AGC G7
width 7
A CONT max.1 – A CONT min.3
34.5 40.5
—
Gain variable
AGC G8
width 8
A CONT max.2 – A CONT min.3
30.5 36.5
—
Gain variable
AGC G9
width 9
A CONT max.3 – A CONT min.3
26.5 32.5
—
-8-
dB
CXA3796N
Item
Symbol
REF
Min. Typ. Max. Unit
Dynamic
range Max.
AGCmax.D
VAGCCONT = 3.3V
MAXGAIN = OPEN, GAINSHIFT = VCC At the 0.88 1.07
level when DRVOUT output signal is saturated
—
V
Dynamic
range Typ.
AGCtyp.D
VAGCCONT = 2.2V
MAXGAIN = OPEN, GAINSHIFT = VCC At the 0.88 1.07
level when DRVOUT output signal is saturated
—
V
Offset High
CAOF high
OFFSET = 1.65V
88
115
—
Offset Low
CAOF low
OFFSET = 3.3V
—
3
10
Offset Preset CAOF pre
OFFSET = 0V
30
41
55
VRTDC level VRTO
400load
2535 2585 2635
VRBDC level VRBO
400load
1435 1485 1535 mV
AGC
DRV
Conditions
mV
VRT – VRB
VR
400load
1045 1087 1155
BLK
Offset
BLKOF1
BLKOF (PBLK = 3.3V) – BLKOF (PBLK = 0V)
ICONT = 3.3V
–15
2
30
mV
SH3
Dynamic
range
SH3 D
DIN = 1s, 1.1Vp-p pulse
0.9
1
—
V
-9-
CXA3796N
Electrical Characteristics Measurement Circuit
24
23
21
19
20
18
17
16
C3
0.1µF
15
14
AGCCLP
AGCCONT
VCC1
SHP
SHD
GND1
DIN
22
V3
1.65 to
3.3V
PL3
VCC1
3.3V
C2
1µF
CLPDM
C1
1µF
VCC2
ICONT
VCC2
3.3V
PL2
PL1
CCDLEVEL
AC
V2
PIN
V1
1.65 to
3.3V
13
BUF
SH1
SH2
DC SHIFT
AGC
OB SW
SH3
AGC
CLP
DMSW2
CDS
CLP2
VREF
CAM SH
DMSW1
CDS
CLP1
VRT
DRV
OFFSET
VRT
VRB
DRV
BLK SW
VRB
DRV
V6
3.3V
V5
2.03V
OPEN
OPEN
R3
10k
C5
4.7µ
C4
4.7µ
12
CLPOB
V4
0 to
3.3V
11
XRS
R1
400
10
PBLK
9
SW2
SW2
H
L
8
OFFSET
VCC3
3.3V
R2
22
7
VRT
6
VRB
5
VCC3
GND3
GND2
SW1
H
L
4
MAXGAIN
3
DRVOUT
2
GAINSHIFT
1
PL6
PL5
PL4
V7
3.3V
C6
40pF
GND
SW1
H
OPEN
L
GAINSHIFT
0dB mode
–3dB mode
–6dB mode
SW2
H
OPEN
L
MAXGAIN
34dB (VAGCCONT = 3.0V)
26dB (VAGCCONT = 3.0V)
30dB (VAGCCONT = 3.0V)
- 10 -
CXA3796N
Measurement Timing Chart
1H
2µs
2.5V
PL4 (CLPOB)
GND
1H
2µs
2.5V
PL1 (CLPDM)
GND
2.5V
PL6 (PBLK)
GND
1H
V2 (DIN)
Different for each test
Equivalent to CCD signal black level
2.5V
PL2 (SHD)
PL3 (SHP)
PL5 (XRS)
GND
- 11 -
CXA3796N
Application Circuit
CCD
24
23
22
21
19
20
18
17
16
0.1µF
15
14
AGCCLP
AGCCONT
CCDLEVEL
SHD
GND1
PIN
CLPDM
1µF
DIN
VCC2
ICONT
1µF
VAGCCONT
1.65㨪3.3V
SHP VCC
SHD
VCC1
CLPDM
SHP
VCC
VICONT
1.65㨪
3.3V
13
BUF
SH1
SH2
DC SHIFT
AGC
OB SW
SH3
AGC
CLP
DMSW2
CDS
CLP2
VREF
CAM SH
DMSW1
CDS
CLP1
VRT
DRV
OFFSET
VRT
VRB
DRV
BLK SW
VRB
DRV
CLPOB
12
PBLK
XRS
CLPOB
22
OPEN
VCC
OPEN
11
XRS
10
PBLK
9
OFFSET
8
VRT
7
VRB
6
MAXGAIN
5
DRVOUT
GND3
4
VCC3
3
GAINSHIFT
2
GND2
1
3.3V
A/D IN
3.3V
VRB
VRT
GAINSHIFT
0dB mode
–3dB mode
–6dB mode
GND
4.7µ
A/D
SW1
H
OPEN
L
VOFFSET
0㨪3.3V
4.7µ
SW2
H
OPEN
L
MAXGAIN
34dB (VAGCCONT = 3.0V)
26dB (VAGCCONT = 3.0V)
30dB (VAGCCONT = 3.0V)
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 12 -
CXA3796N
Description of Operation
Refer to the Block Diagram.
Timing Chart (when VCC = 3.3 V)
Signal interval
OPB interval
Idle transfer
interval
Signal interval
Precharge level
CCD output
Signal level
SHP
SHD
SH1 output
2.5V
SH2 output
[∗1]
SH3 output
[∗2]
2.5V
CLPDM
(2µ dummy bit portion
during the idle transfer interval)
2µs
AGC output
SH3 output
− SH2 output
Basic black level
Black level
0.715V
× (–N)
[∗3]
XRS
CLPOB
(2µ during the OPB interval)
2µs
CAMSH output
0.715V
PBLK
(10µ during the idle transfer interval)
10µs
BLK SW output
1.485V
[∗4]
DRVOUT output
[∗5]
Approx. VRB + 40mV when OFFSET = 0V
Approx. VRB + 110mV when OFFSET = 1.65V
Approx. VRB when OFFSET = 3.3V
- 13 -
CXA3796N
CDS (SH1, SH2, SH3):
The CCD signal from the CCD image sensor is input to PIN and DIN where correlated double sampling (CDS)
is performed by SH1, SH2 and SH3. The precharge level of the CCD output signal is sampled, held and output
by the SH2 output, and the signal level is sampled, held and output by the SH3 output. SH1 and SH2 are the
sample-and-hold circuits for the precharge level; SH3 is the sample-and-hold circuit for the signal level.
CDSCLP 1, 2:
CDSCLP1 and 2 stabilize the input signal DC level, clamp (CLPDM) the input signal during the idle transfer
interval for the purpose of eliminating the AGC input offset, and adjust the DC level ([*1], [*2]) of SH2 and SH3
in line with VREF. CDSCLP1 is the clamp circuit for the precharge level, and CDSCLP2 is the clamp circuit for
the signal level.
AGC:
AGC is the gain control amplifier for the camera signal.
The gain can be varied from –1 to +31dB (when MAXGAIN = OPEN, GAINSHIFT = VCC) by adjusting the
AGCCONT voltage control VAGCCONT from 1.65 to 3.3V.
* Gain width can be changed by MAXGAIN = VCC/OPEN/GND, GAINSHIFT = VCC/OPEN/GND setting.
CAM SH:
CAM SH is the sample-and-hold circuit for synchronizing the data read-in timing for the external A/D.
Sampling is possible according to the approximately 10ns sampling pulse width input to XRS.
AGCCLP:
The basic black level is set ([*3]) by clamping the AGC output waveform with the CLPOB clock during the OPB
interval. When PBLK is High and CLPOB is Low, the clamping circuit operates, adjusting the AGCCLP current
so that the DRVOUT potential equals the OFFSET potential (which is determined by the voltage applied to the
OFFSET pin), thus setting the AGCCLP potential. The AGCCLP capacitance is connected to the AGCCLP pin.
DC SHIFT:
This circuit functions when AGCCLP operates, following the AGCCLP potential and forcing a DC shift of the
AGC output waveform OPB interval to the basic black level. When AGCCLP is not operating, the basic black
level is maintained at its previous setting.
BLK SW:
The black level is calibrated by blanking the black level signal of the AGC output waveform so that it does not
fall below the basic black level and replacing the DC potential with VRB. ([*4])
The signal is blanked when PBLK is Low.
OFFSET:
OFFSET controls the DRV output waveform black level offset.
The offset of the DRVOUT camera signals can be adjusted when a voltage is applied to OFFSET. ([*5])
The voltage controlled by OFFSET is output as the DRV output DC offset via AGCCLP, DCSHIFT, CAMSH
and BLKSW.
When the OFFSET voltage is 1.65 to 3.3V, DRVOUT DC can vary in a linear fashion from VRB + 110mV to VRB.
In addition, when the OFFSET voltage is 0V, DRVOUT DC is preset to VRB + 40mV.
DRV:
DRV drives the external A/D. The current that flows to the last-stage amplifier in DRV is controlled by applying
voltage to the ICONT pin, making it possible to adjust the rise time of the output waveform, which affects the
external A/D load capacitance. The variable range is 1.65 to 3.3V, with 1.65V yielding the maximum and 3.3V
yielding the minimum. The optimum rise time for the external A/D input capacitance can be selected.
- 14 -
CXA3796N
VRT DRV, VRB DRV:
These are the external A/D reference voltage drivers. These circuits are connected to A/D VRT and VRB,
supplying 2.585V and 1.485V, respectively, when VCC is 3.3V. The IC's internal primary voltage is also
generated on the basis of the VRT and VRB voltage.
GAINSHIFT:
AGC gain curve can be shifted by setting GAINSHIFT as follows.
0dB shift
 When applying VCC
 When OPEN
–3dB shift
 When GND
–6dB shift
MAXGAIN:
AGC MAX gain can be changed by setting MAXGAIN as follows.
34dB * when VAGCCOUNT = 3.0V
 When applying VCC
 When OPEN
26dB * when VAGCCOUNT = 3.0V
 When GND
30dB * when VAGCCOUNT = 3.0V
CCDLEVEL BUF:
This is buffer to monitor SH3 output camera signal and output from CCDLEVEL. SH3 output is output to
CCDLEVEL when PBLK = High and internal generation voltage (Vref) is output when PBLK = Low.
- 15 -
CXA3796N
Example of Representative Characteristics
AGCCONT control supply voltage characteristics
VAGCCONT vs. Gain
40
40
35
GAINSHIFT = VCC (0dB)
MAXGAIN = VCC (34dB mode)
GAINSHIFT = OPEN (−3dB)
MAXGAIN = GND (30dB mode)
30
MAXGAIN = VCC (34dB mode)
30
MAXGAIN = GND (30dB mode)
MAXGAIN = OPEN (26dB mode)
MAXGAIN = OPEN (26dB mode)
25
Gain [dB]
25
Gain [dB]
35
20
15
20
15
10
10
5
5
0
0
−5
−5
0.5
0.6
0.7
0.8
VAGCCONT/VCC
0.9
1
0.9
1
40
35
30
GAINSHIFT = GND (−6dB)
MAXGAIN = VCC (34dB mode)
MAXGAIN = GND (30dB mode)
MAXGAIN = OPEN (26dB mode)
Gain [dB]
25
20
15
10
5
0
−5
−10
0.5
0.6
0.7
0.8
VAGCCONT/VCC
- 16 -
−10
0.5
0.6
0.7
0.8
VAGCCONT/VCC
0.9
1
CXA3796N
AGCCONT control supply voltage characteristics
VAGCCONT vs. Gain
OFFSET control supply voltage characteristics
VOFFSET vs. OFFSET
140
35
Tc = 27˚C
120
OFFSET [mV]
25
Gain [dB]
Tc = 27˚C
VCC = 3.0V
VCC = 3.3V
VCC = 3.6V
30
20
15
10
VCC = 3.0
VCC = 3.3
VCC = 3.6
100
80
60
40
5
20
0
−5
1.5
0
2
2.5
3
3.5
0
1
140
35
VCC = 3.3V
−20˚C
+27˚C
+75˚C
20
15
10
100
80
60
40
5
20
0
−5
1.65
VCC = 3.3V
Tc = −20˚C
Tc = +27˚C
Tc = +75˚C
120
OFFSET [mV]
Gain [dB]
25
3
OFFSET control temperature characteristics
VOFFSET vs. OFFSET
AGCCONT control temperature characteristics
AGCCONT vs. Gain
30
2
VOFFSET [V]
VAGCCONT [V]
0
2.15
2.65
0
3.15
VAGCCONT [V]
1
2
VOFFSET [V]
- 17 -
3
4
CXA3796N
Maximum signal amplitude temperature characteristics (Max. gain)
Tc vs. Vout
Maximum signal amplitude temperature characteristics (Min. gain)
Tc vs. Vout
1.4
1.4
VCC = 3.3V, AGCCONT = 3.3V
Input amplitude DIN = 28mVpp
Input amplitude DIN = 24mVpp
Input amplitude DIN = 21mVpp
1.3
1.3
1.2
1.2
1
0.9 31.29dB
DIN = 24mVpp
+0
31.29 –0.16 dB
31.29dB
DIN = 1250mVpp
1.1
VOUT [Vpp]
31.23dB
DIN = 28mVpp
+0
31.23 –0.18 dB
31.23dB
31.06dB
31.13dB
0.8
1
DIN = 1200mVpp
DIN = 1100mVpp
0.9
DIN = 1000mVpp
0.8
31.35dB
0.7
31.35dB DIN = 21mVpp
31.17dB
+0
31.235 –0.17 dB
DIN = 800mVpp
0.7
DIN = 700mVpp
0.6
–20
0
30
0.6
–20
130
80
30
0
Tc [˚C]
80
Tc [˚C]
VRT, VRB, VRT − VRB temperature characteristics
Tc vs. VRT, VRB, VRT − VRB
2.8
VCC = 3.3V
2.6
VRT, VRB, VRT − VRB [V]
VOUT [Vpp]
1.1
VCC = 3.3V, AGCCONT = 1.65V
Input amplitude DIN = 700mVpp
Input amplitude DIN = 800mVpp
Input amplitude DIN = 1Vpp
Input amplitude DIN = 1.1Vpp
Input amplitude DIN = 1.2Vpp
Input amplitude DIN = 1.25Vpp
VRT
2.4
2.2
2
1.8
1.6
VRB
1.4
1.2
VRT – VRB
1
–40
–20
0
20
40
Tc [˚C]
- 18 -
60
80
100
130
CXA3796N
Package Outline
(Unit: mm)
Ass’y: AOI
Marking
CXA3796N
- 19 -
CXA3796N
Package Outline
(Unit: mm)
Ass’y: SDT/PEC
24PIN SSOP (PLASTIC)
+ 0.2
1.25 – 0.1
∗7.8 ± 0.1
0.1
24
13
1
7.6 ± 0.2
∗5.6 ± 0.1
A
12
b
0.13 M
b = 0.22 ± 0.03
0.5 ± 0.2
0.1 ± 0.1
+ 0.03
0.15 – 0.01
0.65
B
DETAIL B : PALLADIUM
0˚ to 10˚
NOTE: Dimension "∗" does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SSOP-24P-L01
LEAD TREATMENT
PALLADIUM PLATING
EIAJ CODE
P-SSOP24-7.8x5.6-0.65
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.1g
JEDEC CODE
Marking
C
C: CXA3796N
B: Lot No. (Max. 7)
B
▤ℂ⸥ภ㧔Control No.㧕
⵾ㅧㅳ㧔Week manufactured㧕
⵾ㅧᐕ㧔⷏ᥲਅ 1 ᩴ㧕
㧔Year manufactured㧕
- 20 -
Sony Corporation
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