E13X12B4Y

SP14T Antenna Switch Module for 12TRx/2Tx with MIPI I/F for Qualcomm chipset
CXM3617ER
Description
The CXM3617ER is a SP14T antenna switch module for GSM / UMTS / CDMA / LTE multi-mode
handset.
The CXM3617ER has a +1.8 V CMOS compatible decoder with MIPI function for Qualcomm
chipset.
The Sony GaAs junction gate pHEMT (JPHEMT) MMIC process is used for low insertion loss and high
linearity. The device has low BOM with no DC blocking Capacitor.
(Applications: GSM/TD-SCDMA/WCDMA/LTE multi-mode handset)
Features

Low Insertion Loss:
0.50 dB (Typ.) TRx (Cellular Band)
0.70 dB (Typ.) TRx (IMT Tx Band)

Low Voltage Operation:
VDD = 2.5 V

Supports CMOS control for serial interface (MIPI I/F for Qualcomm chipset)

No DC Blocking Capacitors

Small Package Size:

Lead-Free and RoHS Compliant
VQFN-26P (2.8 mm × 3.2 mm × 0.775 mm Max.)
Structure
GaAs Junction Gate pHEMT (JPHEMT) MMIC Switch, CMOS Decoder
This IC is ESD sensitive device. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice.
This information does not convey any license by any implication or otherwise under any patents or other right.
Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume
responsibility for any problems arising out of the use of these circuits
1
CXM3617ER
Absolute Maximum Ratings
◆ Supply voltage
VDD
6
V
(Ta = 25 °C)
◆ Control voltage for MIPI
VIO
2.5
V
(Ta = 25 °C)
SDATA
2.5
V
(Ta = 25 °C)
SCLK
2.5
V
(Ta = 25 °C)
[Tx1]
36
dBm
(Duty cycle = 12.5  to 50 ) (Ta = 25 °C)
◆ Maximum input
[Tx2]
34
dBm
(Duty cycle = 12.5  to 50 ) (Ta = 25 °C)
[TRx]
32
dBm
(Ta = 25 °C)
◆ Operating temperature
Topr
–35 to +90
°C
◆ Storage temperature
Tstg
–65 to +150
°C
Block Diagram of SP14T Antenna Switch Module with MIPI
TRx1
TRx2
Ant
TRx3
TRx4
TRx5
TRx6
TRx7
TRx8
TRx9
TRx10
GaAs
JPHEMT
Ant-Switch
LPF1
LPF2
TRx11
TRx12
Tx1
Tx2
Level Shifter
Regulator
VDD
Decoder
DC/DC
MIPI
Converter
I/F
VIO
SDATA
SCLK
CMOS Switch Controller
2
CXM3617ER
Block Diagram
Ant
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F27
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F14
F28
F26
LPF1
TRx1
TRx2
TRx3
TRx4 TRx5
TRx6 TRx7
TRx8 TRx9 TRx10 TRx11 TRx12
3
Tx1
LPF2
Tx2
CXM3617ER
Truth Table
State
Path
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TRx1
TRx2
TRx3
TRx4
TRx5
TRx6
TRx7
TRx8
TRx9
TRx10
TRx11
TRx12
Tx1
Tx2
Isolation
D6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data Bits of Register 0
D5 D4 D3 D2 D1 D0
0
0
1
0
1
0
0
0
1
1
1
0
0
0
1
0
1
1
0
0
0
1
0
1
0
0
1
0
0
1
0
0
1
1
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
F1
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
F2
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
F3
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
F4
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
F5
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
F6
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
F7
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
SW State (*1)
F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
L
L
L
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
L
H
L
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
F8
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
*1) State “L” means a switch “OFF”, state “H” means a switch “ON”.
4
CXM3617ER
Pin Configuration
5
CXM3617ER
Electrical Characteristics
VDD = 2.5 V, Ta = 25 ˚C
Item
Symbol
Path
Condition
Min.
Typ.
Max.
*1, *2, *3, *10
-
0.51
0.61
*4, *11
-
0.57
0.67
*5
-
0.60
0.75
*6
-
0.66
0.86
*7
-
0.77
0.97
*1, *2, *3, *10
-
0.51
0.61
*4, *11
-
0.59
0.69
*5
-
0.62
0.77
*6
-
0.67
0.87
*7
-
0.78
0.98
*1, *2, *3, *10
-
0.52
0.62
*4, *11
-
0.58
0.68
*5
-
0.61
0.76
*6
-
0.67
0.87
*7
-
0.79
0.99
*1, *2, *3, *10
-
0.39
0.49
*4, *11
-
0.46
0.56
*5
-
0.48
0.63
*6
-
0.54
0.74
*7
-
0.64
0.84
*1, *2, *3, *10
-
0.41
0.51
*4, *11
-
0.63
0.73
*5
-
0.70
0.85
*6
-
0.83
1.03
*7
-
1.09
1.29
*1, *2, *3, *10
-
0.47
0.57
*4, *11
-
0.64
0.74
*5
-
0.69
0.84
*6
-
0.80
1.00
*7
-
1.02
1.22
*1, *2, *3, *10
-
0.52
0.62
*4, *11
-
0.60
0.70
*5
-
0.62
0.77
*6
-
0.68
0.88
*7
-
0.79
0.99
*1, *2, *3, *10
-
0.50
0.60
*4, *11
-
0.56
0.66
*5
-
0.58
0.73
*6
-
0.62
0.82
*7
-
0.73
0.93
*1, *2, *3, *10
-
0.51
0.61
*4, *11
-
0.55
0.65
*5
-
0.56
0.71
*6
-
0.60
0.80
*7
-
0.70
0.90
*1, *2, *3, *10
-
0.58
0.68
*4, *11
-
0.72
0.82
*5
-
0.78
0.93
*6
-
0.91
1.11
*7
-
1.12
1.32
*1, *2, *3, *10
-
0.55
0.65
*4, *11
-
0.69
0.79
*5
-
0.74
0.89
*6
-
0.86
1.06
*7
-
1.06
1.26
*1, *2, *3, *10
-
0.54
0.64
*4, *11
-
0.70
0.80
*5
-
0.76
0.91
*6
-
0.89
1.09
*7
-
1.15
1.35
Ant - Tx1
*8
-
1.09
1.24
Ant - Tx2
*9
-
1.03
1.23
Ant - TRx1
Ant - TRx2
Ant - TRx3
Ant - TRx4
Ant - TRx5
Ant - TRx6
Insertion Loss
IL
Ant - TRx7
Ant - TRx8
Ant - TRx9
Ant - TRx10
Ant - TRx11
Ant - TRx12
6
Unit
dB
CXM3617ER
VDD = 2.5 V, Ta = 25 ˚C
Item
Symbol
VSWR
VSWR
2fo
3fo
Harmonics
2fo
3fo
2fo
3fo
Path
All Ports in Active Paths
Ant - TRx1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
Unit
600 to 2170 MHz
-
-
1.50
-
-
-65
-55
-
-65
-55
-
-48
-36
-
-45
-40
-
-50
-45
-
-45
-36
1648 to 1805 MHz
25
-
-
1805 to 1830 MHz
30
-
-
2472 to 2745 MHz
25
-
-
3296 to 12750 MHz
15
-
-
3420 to 3820 MHz
25
-
-
Ant - Tx2
*9
Inter Modulation Product
Pow er in Rx Band
IMD2
Input IP3
IIP3
Ant - TRx1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
Sw itching Time
Ts
Ant - TRx1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, Tx1,
Tx2
Wakeup Time
Tw
Ant - TRx1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
960, 1990
915
dBm
1910
dB
5130 to 5730 MHz
20
-
6840 to 12750 MHz
20
-
-
*12, 13, 14, 17, 18, 21, 22
-
-
-105
*12, 15, 16, 19, 20, 23, 24
-
-
-105
*12, 25, 26
-
68
-
SCLK falling edge to 90% RF
in Active Mode
-
3
5
μs
dBm
-
4
6
μs
From Low Pow er Mode to
Active Mode
-
-
100
μs
Ivio
V IO = 1.80 V, Active Mode
-
0.20
0.40
mA
Ivio
V IO = 1.80 V, Low Pow er Mode
-
-
10
μA
Idd
V DD = 2.5 V, Active Mode
-
0.20
0.40
mA
Idd
V DD = 2.5 V, Low Pow er Mode
-
-
10
μA
Ant - TRx4
Supply Current
Max.
*8
Tx2 - Ant
VIO Current
Typ.
Ant - Tx1
ATT
IMD3
Min.
*3, *4
Tx1 - Ant
Attenuation
Condition
Isolation
Tx/TRx to Tx/TRx Isolation Matrix (Min.)
Active
Freq.
State
(MHz)
Tx1
Tx2
Tx1
824 to 915
25
Tx2
1710 to 1910
24
452 to 960
37
40
TRx1
1710 to 2170
34
35
2300 to 2690
30
37
452 to 960
39
40
TRx2
1710 to 2170
38
36
2300 to 2690
33
37
452 to 960
40
40
TRx3
1710 to 2170
40
36
2300 to 2690
35
37
452 to 960
40
40
TRx4
1710 to 2170
40
35
2300 to 2690
38
35
452 to 960
40
40
TRx5
1710 to 2170
40
40
2300 to 2690
38
40
452 to 960
40
40
TRx6
1710 to 2170
40
40
2300 to 2690
37
38
452 to 960
40
40
TRx7
1710 to 2170
40
36
2300 to 2690
36
33
452 to 960
40
40
TRx8
1710 to 2170
39
30
2300 to 2690
33
27
452 to 960
40
39
TRx9
1710 to 2170
35
27
2300 to 2690
31
23
452 to 960
32
36
TRx10
1710 to 2170
29
31
2300 to 2690
26
32
452 to 960
28
34
TRx11
1710 to 2170
25
31
2300 to 2690
23
33
452 to 960
24
33
TRx12
1710 to 2170
20
30
2300 to 2690
18
34
VDD = 2.5 V, Ta = 25 ˚C
TRx1
40
40
32
23
19
40
29
24
40
34
28
40
40
38
40
40
38
40
40
39
40
40
39
40
40
38
33
23
18
40
29
23
40
31
25
TRx2
40
40
34
24
20
29
20
17
40
29
24
40
40
38
40
40
39
40
40
40
40
40
40
40
40
40
40
30
25
40
33
28
40
35
29
TRx3
40
40
40
31
26
31
21
18
31
22
18
40
40
37
40
40
38
40
40
40
40
40
40
40
40
40
40
35
29
40
37
31
40
37
31
TRx4
40
40
40
32
27
40
28
23
32
21
17
40
35
30
40
36
30
40
40
34
40
40
35
40
40
35
40
34
29
40
35
29
40
35
29
7
Isolation (dB)
TRx5
TRx6
40
40
30
37
39
40
29
37
27
34
39
40
29
37
27
34
39
40
29
37
27
34
39
40
30
38
27
34
33
22
18
32
22
17
40
33
31
24
25
20
40
40
31
32
27
27
40
40
31
35
27
29
39
40
29
37
27
34
39
40
29
37
27
34
39
40
29
37
27
34
TRx7
40
40
40
40
38
40
40
38
40
40
38
40
40
37
40
31
26
34
24
19
33
24
20
40
29
24
40
40
37
40
40
37
40
40
36
TRx8
40
40
40
40
39
40
40
40
40
40
40
40
40
39
40
37
31
40
32
27
35
25
20
32
22
18
40
40
38
40
40
37
40
40
36
TRx9
40
40
40
40
38
40
40
39
40
40
39
40
40
38
40
40
33
40
35
29
40
31
25
33
23
19
40
40
35
40
40
34
40
40
33
TRx10
40
40
34
24
20
40
31
26
40
35
29
40
38
33
40
40
39
40
40
39
40
40
40
40
40
39
40
40
38
31
20
17
40
27
23
TRx11
40
38
40
30
24
40
35
28
40
37
30
40
40
33
40
40
35
40
40
35
40
40
36
40
40
35
40
40
34
31
21
17
34
22
17
TRx12
37
32
40
33
26
40
36
28
40
37
29
40
39
31
40
39
30
40
38
30
40
39
31
40
38
30
40
36
29
40
27
21
35
23
17
CXM3617ER
Corresponding Band of TRx (UMTS/CDMA/LTE)
*1 Pin = 26 dBm, 452 to 468 MHz (Band Class 5)
*2 Pin = 25 dBm, 704 to 787 MHz (Band 13, Band 17)
*3 Pin = 26 dBm, 824 to 960 MHz (Band 5, Band 8)
*4 Pin = 26 dBm, 1710 to 1990 MHz (Band 1 Tx, Band 2 Tx, Band 3 Tx, Band4 Tx)
*5 Pin = 10 dBm, 2110 to 2170 MHz (Band 1 Rx, Band 4 Rx)
*6 Pin = 26 dBm, 2300 to 2400 MHz (Band 40)
*7 Pin = 26 dBm, 2500 to 2690 MHz (Band 7)
*8 Pin = 35 dBm, 824 to 915 MHz (GSM850/900 Tx)
*9 Pin = 32 dBm, 1710 to 1910 MHz (GSM1800/1900 Tx)
*10 Pin = 10 dBm, 869 to 960 MHz (GSM850/900 Rx)
*11 Pin = 10 dBm, 1805 to 1990 MHz (GSM1800/1900 Rx)
*12 Measured with the recommended circuit
8
CXM3617ER
IMD Condition
Band
Band 1
Band 2
Band 5
fRx
fTx
fBlocker
on RF
[M Hz]
+20 dBm on RF
[M Hz]
-15 dBm on ANT
2140
IM D2 (fRx - fTx)
190
*13
IM D2 (fRx + fTx)
4090
*14
IM D3 (2fTx - fRx)
1760
*15
IM D3 (2fTx + fRx)
6040
*16
IM D2 (fRx - fTx)
80
*17
1950
1960
IM D2 (fRx + fTx)
3840
*18
IM D3 (2fTx - fRx)
1800
*19
IM D3 (2fTx + fRx)
5720
*20
1880
880
IM D Condition
[M Hz]
IM D2 (fRx - fTx)
45
*21
IM D2 (fRx + fTx)
1715
*22
IM D3 (2fTx - fRx)
790
*23
IM D3 (2fTx + fRx)
2550
*24
835
IIP3 Condition
f2
+27 dBm on RF
[M Hz]
1951
IIP3 Condition
IIP3 = (3 × Pout - IM D3)/2
Band 1
f1
+27 dBm on RF
[M Hz]
1950
Band 5
835
836
*26
Band
9
[dBm]
*25
CXM3617ER
Electrical Characteristics of Triple Beat Ratio
VDD = 2.5 V, Ta = 25 °C
Condition
Item
Triple
Beat
Ratio
Symbol
TBR
Path
ANT-TRx1, 2,
3, 4, 5, 6, 7,
8, 9, 10, 11,
12
Tx1 at
TRx
21.5 dBm
[MHz]
Tx2 at
TRx
21.5 dBm
[MHz]
Jammer at
ANT
–30 dBm
[MHz]
Triple
Beat
Product
at TRx
[MHz]
835.5
836.5
881.5
1880
1881
1960
Min.
Typ.
Max.
881.5  1
81
—
—
1960  1
81
—
—
Electrical characteristics are measured with all RF ports terminated in 50 .
Measured with the recommended circuit
Electrical Characteristics of Input IP2
VDD = 2.5 V, Ta = 25 °C
Condition
Item
Input
IP2
Symbol
IIP2
Path
ANT-TRx1,
2, 3, 4, 5, 6,
7, 8, 9, 10,
11, 12
Tx at TRx
24 dBm
[MHz]
Jammer at
ANT
–20 dBm
[MHz]
IM2
Product at
TRx
[MHz]
836.61
1718.22
836.61
Min.
Typ.
Max.
881.61
113.5
—
—
45
881.61
95.5
—
—
1885
3850
1965
95.5
—
—
1885
80
1965
95.5
—
—
1732.5
3865
2132.5
95.5
—
—
1732.5
400
2132.5
95.5
—
—
Electrical characteristics are measured with all RF ports terminated in 50 .
Measured with the recommended circuit
10
Unit
dBm
Unit
dBc
CXM3617ER
MIPI Specification
Features

PM_TRIG with three triggers

Software reset and debug using the RFFE_STATUS register

Register 0 write

Full speed write, Half speed read

GSID

Programmable USID
Control Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Unit
Supply Voltage
VDD
2.5
2.8
3.3
V
IDD
-
200
400
µA
IDD
-
-
10
µA
VIO
1.65
1.8
1.95
V
Ivio
-
200
400
µA
Ivio
-
-
10
µA
Signal level low
Vcl
0
-
0.2×VIO
V
Signal level high
Vch
0.8×VIO
-
VIO
V
SCLK write Frequency
fSCLKw
0.032
19.2
26
MHz
SCLK read Frequency
fSCLKr
0.032
9.6
13
MHz
SDATA/SCLK input capacitance
Cin
-
2
3
pF
Data setup time
Ts
2
-
-
ns
Data hold time
Th
5
-
-
ns
Turn on Time *
Ton
-
-
100
µs
Supply current
(ACTIVE) *VDD = 2.5 V
Supply current
Low Power(disable) *VDD = 2.5 V
Interface Supply Voltage
Supply current
(ACTIVE) *VIO = 1.8 V
Supply current
Low Power(disable) *VIO = 1.8 V
*Turn on time: Time to guarantee RF performance after switch activation.
11
CXM3617ER
Explanation of Register
Slave Address: 1011
Register Address
Register Name
Data Bits
Notes
Read
Write
0x0000
0x001A
0x001B
6:0
Antenna switch states (see Truth Table)
Register 0 Write command sequence use.
Trigger Supprt.
7:0
Antenna switch states (see Truth Table)
Read/Write command sequence use.
Trigger Supprt.
REGISTER_0
(Table A or B)
RFFE_STATUS
(Table C)
GROUP_ID
(Table D)
7
SOFTWARE RESET
6
COMMAND_FRAME_PARITY_ERR
5
COMMAND_LENGTH_ERR
4
ADDRESS_FRAME_PARITY_ERR
3
DATA_FRAME_PARITY_ERR
2
READ_UNUSED_REG
1
WRITE_UNUSED_REG
0
BID_GID_ERR
7:4
RESERVED
3:0
GROUP_SID
7:6
Power mode
5:3
Trigger_Mask_[2:0]
W
R/W
R/W
R/W
0x001C
PM_TRIG
(Table E)
2:0
Trigger_[2:0]
0x001D
PRODUCT_ID
(Table F)
7:0
PRODUCT_ID
R
0x001E
MANUFACTURER_ID
(Table G)
7:0
MANUFACTURER_ID[7:0]
R
7:6
SPARE
R
0x001F
SPARE
MANUFACTURER_ID
USID
(Table H)
5:4
MANUFACTURER_ID[9:8]
3:0
USID
MANUFACTURER_ID[9:0] is defined by SONY ID (0x01B0)
12
R/W
R
R/W
CXM3617ER
Write and Read command sequence
13
CXM3617ER
Register Map
･Register 0 Write command sequence use.
15
14
Sta te
Path
SSC
-
13
12
11
10
9
8
7
6
5
4
-
-
SA3
SA2
SA1
SA0
C0
D6
D5
D4
D3
D2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TRx1
TRx2
TRx3
TRx4
TRx5
TRx6
TRx7
TRx8
TRx9
TRx10
TRx11
TRx12
Tx1
Tx2
Isolation
1
0
1
0
1
1
1
0
0
0
1
0
1
0
1
0
1
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
0
1
0
1
0
1
1
1
0
0
1
0
1
0
1
1
1
0
1
0
1
0
1
1
1
1
0
1
0
1
1
1
0
1
0
1
1
0
1
0
1
0
1
1
0
1
3
2
1
0
D1
D0
Parity
Bit
P
Bu s
P ar k
-
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
0
0
1
0
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
1
1
1
0
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
1
0
1
1
1
0
0
0
0
1
1
0
1
0
0
1
0
1
1
1
0
0
0
0
1
0
0
0
0
1
0
1
0
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
0
1
0
0
0
0
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
1
0
17
16
15
14
13
12
11
10
Dat a
Slave Address
･Register Read/Write command sequence use.
24
23
Sta te
Path
SSC
-
22
21
20
19
-
-
SA3
SA2
SA1
SA0
A4
A3
A2
A1
A0
Parity
Bit
P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TRx1
TRx2
TRx3
TRx4
TRx5
TRx6
TRx7
TRx8
TRx9
TRx10
TRx11
TRx12
Tx1
Tx2
Isolation
1
0
1
0
1
0
0
1
1/0
0
0
0
0
0
1/0
1
0
1
0
1
0
0
1
1/0
0
0
0
0
0
1/0
1
0
1
0
1
0
0
1
1/0
0
0
0
0
0
1/0
1
0
1
0
1
0
0
1
1/0
0
0
0
0
0
1/0
1
0
1
0
1
0
0
1
1/0
0
0
0
0
0
1/0
1
0
1
0
1
0
0
1
1/0
0
0
0
0
0
1/0
1
0
1
0
1
0
0
1
1/0
0
0
0
0
0
1/0
1
0
1
0
1
0
0
1
1/0
0
0
0
0
0
1/0
1
0
1
0
1
0
0
1
1/0
0
0
0
0
0
1/0
1
0
1
0
1
0
0
1
1/0
0
0
0
0
0
1/0
1
0
1
0
1
0
0
1
1/0
0
0
0
0
0
1/0
1
0
1
0
1
0
0
1
1/0
0
0
0
0
0
1/0
1
0
1
0
1
0
0
1
1/0
0
0
0
0
0
1/0
1
0
1
0
1
0
0
1
1/0
0
0
0
0
0
1/0
1
0
1
0
1
0
0
1
1/0
0
0
0
0
0
1/0
9
8
7
6
Sta te
Path
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TRx1
TRx2
TRx3
TRx4
TRx5
TRx6
TRx7
TRx8
TRx9
TRx10
TRx11
TRx12
Tx1
Tx2
Isolation
Slave Address
5
4
18
Write/ Read Com m and
Write:010 Read:011
C2
C1
C0
3
Register Address
2
1
0
Bu s
P ar k
-
D7
D6
D5
D4
D3
D2
D1
D0
Parity
Bit
P
0
0
0
0
1
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Data
*Parity Bit
A Frame shall end with a single parity bit. The parity bit shall be driven such that the total number of bits
in the Frame that are driven to logic level one, including the parity bit, is odd.
14
CXM3617ER
15
CXM3617ER
Table E Register for Power Mode & Trigger Mode (0x001C)
Read
Write
Register
Address
Data Frame
Parity Bit
Data
Parity Bit
Items
Slave
Address
Command Frame
Command Frame
Slave
Address
Description
Bit
SA3 1
SA2 0
Address of Antenna Switch Module
SA1 1
SA0 1
C2
0
Write : 010
C1
1
Read: 011
C0 0/1
A4
1
A3
1
A2
1 Register Address: 0x001C
A1
0
A0
0
P
0/1 Parity bit for Command Frame
00: Normal operation (ACTIVE)
D7 0/1
01: Default settings (STARTUP)
10: Low power (LOW POWER)
D6 0/1
11: Reserved
D5 0/1 Trigger_Mask_[2:0]
D4 0/1 111: valid
D3 0/1 other: Invalid
D2 0/1 Trigger_[2:0]
D1 0/1 000: Invalid
D0 0/1 other: valid
P
0/1 Parity bit for Data Frame
Read
Write
Register
Address
Parity Bit
Initial value :
[D7:D6]
=10
Initial value :
[D5:D3]
=000
Initial value :
[D2:D0]
=000
Data Frame
Items
Table F Register for Product ID (0x001D)
Data
Parity Bit
16
SA3
SA2
SA1
SA0
C2
C1
C0
A4
A3
A2
A1
A0
P
Bit
1
0
1
1
0
1
1
1
1
1
0
1
0
D7
0
D6
0
D5
D4
D3
D2
D1
D0
P
0
0
0
1
1
0
1
Description
Address of Antenna Switch Module
Read Only
Register Address: 0x001D
Parity bit for Command Frame
Product ID : 06h
Parity bit for Data Frame
CXM3617ER
Table G Register for Manufacturer ID (0x001E)
Items
Read
Write
Register
Address
Parity Bit
Items
Address of Antenna Switch Module
Slave
Address
Description
Bit
SA3 1
SA2 0
Address of Antenna Switch Module
SA1 1
SA0 1
C2
0
Write : 010
C1
1
Read : 011
C0 0/1
A4
1
A3
1
A2
1 Register Address: 0x001F
A1
1
A0
1
P
0/1 Parity bit for Command Frame
SA3
SA2
SA1
SA0
C2
C1
C0
A4
A3
A2
A1
A0
P
D7
1
D7
0
D6
0
D6
0
D5
D4
D3
D2
D1
D0
P
1
Manufacturer ID [7:0]:B0h (SONY ID)
1
0
0
0
0
0 Parity bit for Data Frame
Command Frame
Command Frame
Slave
Address
Table H Register for Manufacturer ID and USID (0x001F)
Description
Bit
1
0
1
1
0
1
1
1
1
1
1
0
0
Read Only
Register Address: 0x001E
Parity bit for Command Frame
Read
Write
Register
Address
Parity Bit
Data
Parity Bit
Data Frame
Data Frame
SPARE
Data
Parity Bit
D5
D4
D3
D2
D1
D0
P
0
Manufacturer ID [9:8]:01h (SONY ID)
1
0/1
0/1
Programmable USID
0/1
0/1
0/1 Parity bit for Data Frame
Initial value :
[D3:D0]
=1011
For Programmable USID
The PRODUCT_ID and the MANUFACTURER_ID match, then a new USID is programmed.
17
CXM3617ER
TRx3
TRx4
GND
GND
Tx2
GND
10
9
8
15
7
6
17
VQFN-26P PKG
(2.8 mm×3.2 mm
×0.775 mm Max.)
18
Top View
4
19
Bottom pad: GND
3
16
5
20
21
C2
2
22
23
24
25
26
1
TRx9
TRx8
TRx7
TRx6
TRx5
GND
Ant
GND
GND
TRx2
11
SCLK
TRx1
12
SDATA
TRx10
13
VIO
TRx11
14
VDD
TRx12
Tx1
GND
Recommended Circuit
C3
*1: No DC blocking capacitors are required on all RF ports.
*2: DC levels of all RF ports are GND.
*3: L1 (22 nH) and C1 (22 pF) are recommended on Ant port for ESD protection.
*4: C2 (100 pF) and C3 (0.1 µF) are recommended.
18
C1
L1
CXM3617ER
Recommended Land Pattern
PCB GND Design for VQFN-26P (Image)
14
13
12
11
10
9
8
15
7
16
6
17
5
18
4
19
3
20
2
GND Via Hole
21
22
23
24
25
26
19
1
PKG Line
CXM3617ER
Package Outline
(Unit: mm)
20
CXM3617ER
Marking
21
CXM3617ER
Tape and Reel Size
22
CXM3617ER
Moisture Sensitivity
Moisture Sensitivity Level for this part is MSL = 2
23