Data Sheet

0804-5000-23 Industrial Powerline
Module
For Ethernet over Coax Applications
FEATURES
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Based on Qualcomm Atheros AR6400/AR1400 chipset
Based on HomePlug® AV standard optimised for Ethernet
over Coax (EoC) applications with raw data rates up to 200
MB/s
Temperature rated for industrial applications
MII (Host & PHY) interface
Supports1024/256/64/16/8-QAM, QPSK, BPSK, and
ROBO modulation schemes
128-bit AES Link Encryption with key management for
secure power line communications
Dynamic channel adaptation and channel estimation
maximizes throughput in harsh channel conditions
Advanced turbo code forward error correction
ToS, CoS and IP port number packet classifiers
Supports IGMP managed multicast sessions
Green standard (ROHS) compliant
GPIO second function as general data lines
Horizontal mounting configuration using standard 1.27mm
pin header
Integrates all components necessary to add Ethernet over
Coax functionality to any embedded system at low cost
APPLICATIONS
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Over-the-Top Video
Telco / IPTV
Ethernet-over-Coax (EoC)
and Multi-Dwelling Unit
(MDU) applications
DESCRIPTION
The Bel 0804-5000-23 single in line package (SIP) module is an industrial temperature rated
MAC/PHY/AFE Powerline communications (PLC) transceiver. The module complements the existing
range of Bel Powerline modules based on the Qualcomm Atheros AR6400/AR1400 and is optimised for
communications over coax networks.
The Bel 0804-5000-23 module enables the development of HD grade communications bridges to and
from the coax network. It also serves as a translator between the digital and analogue worlds. On the
digital side host interfaces include Ethernet MII Host or PHY. The data received and transmitted is
translated by the AR6400 to and from a complex analogue signal which is modulated on multiple carriers
and transmitted over the coax network.
In Partnership with
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
CORPORATE
ASIA
EUROPE
Bel Fuse Inc.
206 Van Vorst Street
Jersey City, NJ 07302
Tel 201-432-0463
Fax 201-432-9542
www.belfuse.com
Bel Fuse Ltd.
8F / 8 Luk Hop Street
San Po Kong
Kowloon, Hong Kong
Tel 852-2328-5515
Fax 852-2352-3706
www.belfuse.com
Bel Integrated Modules
28 Turkey Court, Turkey Mill
Ashford Road
Maidstone, Kent ME14 5PP
U.K.
Tel 44-1622-757395
Fax 44-1622-663252
www.belfuse.com
1
0804-5000-23 Industrial Powerline
Module
For Ethernet over Coax Applications
MODULE BLOCK DIAGRAM
Bel 0804-5000-23
GPIO
LEDs
AND
CONFIG
MII
(MDI)
TX
DAC
M
A
C
P
H
Y
BPF
PLC
COUPLER
ADC
BPF
AR1400
RX
AR6400
RESET
FLASH
SYS CLK
PLL
DC-DC
RAM
3.3V
DC
CXO
1V 11.2V
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
2
0804-5000-23 Industrial Powerline
Module
For Ethernet over Coax Applications
MODULE INTERFACE
Pin I/O table
Pin
Number
1
2
VDD
VSS
Pin
Number
26
27
3
VDD
28
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
VSS
VDD
TX+
TXVSS
RX+
RXRESET/
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
Reserved (required 10KΩ pull-up
resistor)
MDIO
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
MDC
Reserved
Reserved
Ground)
VSS
MRX_D0
MRX_D1
MRX_D2
MRX_D3
COL
MRX_CLK
VSS
MRX_ERR
MRX_DV
MTX_D0
MTX_D1
MTX_D2
MTX_D3
CRS
MTX_CLK
MTX_EN
VSS
PHY_RST/
VSS
49
PHY_CLK
50
VSS
24
25
Pin Name
Pin Name
(N.C.)
(required connection to
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
3
0804-5000-23 Industrial Powerline
Module
For Ethernet over Coax Applications
SYSTEM BLOCK DIAGRAM
Power
Reset
MII (MAC or PHY
mode)
PHY DEVICE
0804-5000-23
OR
Co-Axial
Network
Co-Axial
Coupler
Coupling
Interface
POWERLINE
MODULE
MDI
MAC
CONTROLLER
PHY utility
GPIO
The block diagram presents the 0804-5000-23 powerline module in a typical environment. Seven
different types of interfaces are shown. These interfaces are described in detail below.
Media Independent Interface (MII)
The MII interface is configured as either an Ethernet Medium Access Controller (MAC) or a Physical
Medium Dependent (PMD or PHY) controller. Medium Independent Interface (MII) is an industry
standard, multi-vendor interface between the MAC and PHY sub-layers. It provides a simple connection
between Ethernet PHY controllers and IEEE802.3 Ethernet MACs from a variety of sources.
MII consists of separate 4-bit data paths for transmit and receive data along with carrier sense and
collision detection. Further details of the MII are available from the IEEE 802.3u Standard.
Configuration straps described in Section 3 set the MII operation to a MAC or PHY controller. The MAC
and PHY configurations support 10 Mbps or 100 Mbps in half-duplex or full-duplex modes and flow
control for half-duplex and full-duplex connections. The Ethernet MAC module implements standard
Ethernet MAC functionality. The Ethernet MAC is connected to an external Ethernet PHY function. The
MAC configuration provides bridging between Ethernet and the powerline. The PHY configuration
emulates Ethernet PHY functionality and provides HomePlug AV connectivity to devices designed to
communicate over an Ethernet network.
The MII (Ethernet) interface has separate transmit and receive packet buffering. When operating as a
MAC the MII transmit FIFO is 2 KB and the receive FIFO is 8 KB. When operating as a PHY controller,
the MII transmit FIFO is 8 KB and the receive FIFO is 2 KB.
MII MAC
The MII MAC configuration operates as an IEEE 802.3 10/100-Mbps Ethernet MAC connected to an
external 10/100-Mbps Ethernet PHY.
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
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0804-5000-23 Industrial Powerline
Module
For Ethernet over Coax Applications
When the Power line module boots it attempts to configure the MII MAC interface, it will first scan all
external MII PHY’s starting from PHY #0 and will select the first PHY that responds with valid register
contents.
The PHY’s Link Status register will be read, and if the link is up, auto-negotiation will be performed. If the
PHY’s status indicates that auto-negotiation is not supported, auto-negotiation will not be performed.
Based upon the results of the PHY’s status registers, or auto-negotiation results, the PHY will be
configured in an operational mode (i.e. no loopback, no collision test, not in isolate, etc.). The MII MAC
within the Power line module will be configured for the same speed and duplex. External devices do not
have direct access to any MII MAC registers in the AR6400.
MII PHY
The MII PHY emulation hardware connects to an external 10/100-Mbps Ethernet MAC. The default PHY
functionality is configured through standard management data interface communications (MDI interface)
and may be overridden by the AR6400 MAC firmware access to the PHY emulation registers. The
interface supports the standard control and status register.

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Link speed at 10 Mbps or 100 Mbps
Full-duplex or half-duplex operation
Management data interface base address
Isolate to disconnect the PHY from the MII port
In MII PHY mode, auto-negotiation is not supported. GPIO Strapping on the Power line module will
determine the desired configuration, these straps will be reflected in the default settings in the MII PHY
Emulation registers.
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
5
0804-5000-23 Industrial Powerline
Module
For Ethernet over Coax Applications
MII signals
I/O
Pin
Number
Pin Name
30
MRX_D0
31
MRX_D1
32
MRX_D2
33
MRX_D3
34
35
37
COL
MRX_CLK
MRX_ERR
38
MRX_DV
39
MTX_D0
40
MTX_D1
41
MTX_D2
42
MTX_D3
43
CRS
MAC
Mode
I
I
I
I
I
O
I
PHY
Mode
Description
O
MII Receive Data. The PHY controller drives MRX_D[3:0] and
the MAC core receives MRX_D[3:0]. MRX_D[3:0] transitions
synchronously with respect to MRX_CLK. For each MRX_CLK
period in which MRX_DV is asserted, MRX_D[3:0] is valid.
MRX_D0 is the least-significant bit. The PHY controller tristates MRX_D[3:0] in isolate mode.
O
MII Collision Detected. The PHY controller asserts COL
when it detects a collision on the medium. COL remains
asserted while the collision condition persists. COL signal
transitions are not synchronous to either the MTX_CLK or the
MRX_CLK. The MAC core ignores the COL signal when
operating in the full-duplex mode. The PHY controller tri-states
COL in isolate mode.
O
MII Receive Clock. MRX_CLK is a continuous clock that
provides the timing reference for the transfer of the MRX_DV
and MRX_D[3:0] signals from the PHY controller to the MAC
core. The PHY controller sources MRX_CLK. MRX_CLK
frequency is equal to 25% of the data rate of the received
signal on the Ethernet cable. The PHY controller tri-states
MRX_CLK in isolate mode.
O
MII Receive Error. The PHY controller asserts MRX_ERR
high for one or more MRX_CLK periods to indicate to the MAC
core that an error (a coding error or any error that the PHY is
capable of detecting that is otherwise undetectable by the
MAC) was detected somewhere in the current frame.
MRX_ERR transitions synchronously with respect to
MRX_CLK. While MRX_DV is de-asserted, MRX_ERR has no
effect on the MAC core. The PHY controller tri-states
MRX_ERR in isolate mode.
O
MII Receive Data Valid. The PHY controller asserts MRX_DV
to indicate to the MAC core that it is presenting the recovered
and decoded data bits on MRX_D[3:0] and that the data on
MRX_D[3:0] is synchronous to MRX_CLK. MRX_DV
transitions synchronously with respect to MRX_CLK. MRX_DV
remains asserted continuously from the first recovered nibble
of the frame through the final recovered nibble, and is deasserted prior to the first MRX_CLK that follows the final
nibble. The PHY controller tri-states MRX_DV in isolate mode.
I
MII Transmit Data. The MAC core drives MTX_D[3:0] and the
PHY controller receives MTX_D[3:0]. MTX_D[3:0] transitions
synchronously with respect to MTX_CLK. For each MTX_CLK
period in which MTX_EN is asserted, MTX_D[3:0] is valid.
MTX_D0 is the least significant bit. The PHY controller ignores
MTX_D[3:0] in isolate mode.
O
MII Carrier Sense. The PHY controller asserts CRS when
either transmit or receive medium is non-idle. The PHY deasserts CRS when both transmit and receive medium are idle.
The PHY must ensure that CRS remains asserted throughout
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
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0804-5000-23 Industrial Powerline
Module
For Ethernet over Coax Applications
the duration of a collision condition. The transitions on the
CRS signal are not synchronous to either the MTX_CLK or the
MRX_CLK. The PHY controller tri-states CRS in isolate mode.
44
45
MTX_CLK
I
MTX_EN
O
O
MII Transmit Clock. MTX_CLK is a continuous clock that
provides a timing reference for the transfer of the MTX_EN
and MTX_D[3:0] signals from the MAC core to the PHY
controller. The PHY controller sources MTX_CLK. The
operating frequency of MTX_CLK is 25 MHz when operating at
100 Mbps and 2.5 MHz when operating at 10 Mbps. The PHY
controller tri-states MTX_CLK in isolate mode.
I
MII Transmit Enable. A high assertion on MTX_EN indicates
that the MAC core is presenting nibbles to the PHY controller
for transmission. The AR6400 MAC core asserts MTX_EN
with the first nibble of the preamble and keeps MTX_EN
asserted while all nibbles to be transmitted are presented to
the MII. MTX_EN is de-asserted prior to the first MTX_CLK
following the final nibble of the frame. MTX_EN transitions
synchronously with respect to MTX_CLK. The PHY controller
ignores MTX_EN in isolate mode.
Special care must be taken during PCB layout of the MII bus. Keep MII signal traces as short as possible
and preferably on inner PCB layers.
MII Management Data Interface (MDI)
The MII interface has a two-wire bi-directional serial Management Data Interface (MDI). This interface
provides access to the status and control registers in the Ethernet PHY logic. The MII and MDI pins are
shared between the MAC and PHY interfaces.
Pin
Number
25
26
Pin
Name
MDIO
MDC
I/O
MAC
Mode
I/O
O
Description
PHY
Mode
I/O
MII Management Data In/Out. This is the data input signal from
the PHY controller. The PHY drives the Read Data
synchronously with respect to the MDC clock during the read
cycles. This is also the data output signal from the MAC core that
drives the control information during the Read/Write cycles to the
PHY controller. The MAC core drives the MDO signal
synchronously with respect to the MDC. An external pull-up
resistor is needed on this pin.
I
MII Management Data Clock. The MAC core sources MDC as
the timing reference for transfer of information on the MDIO
signal. MDC signal has no maximum high or low times. MDC
minimum high and low times are 160 ns each, and the minimum
period for MDC is 400 ns.
General Purpose Input / Output (GPIO) pins Interface
General Purpose I/O pins are software programmable inputs or outputs, which can also be used as an
external interrupt source. As indicated in the table below, some of these GPIO signals also have
additional functionality as configuration straps. See section 3 for configuration options.
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
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0804-5000-23 Industrial Powerline
Module
For Ethernet over Coax Applications
Pin Number
Pin Name
12
GPIO0
13
GPIO1
14
GPIO2
15
GPIO3
16
GPIO4
17
GPIO5
18
GPIO6
19
GPIO7
20
GPIO8
21
GPIO9
22
GPIO10
23
GPIO11
* S. C. = software configurable.
Configuration
Strap Function
I/O
Internal Pull
Up/Down
N/A
N/A
N/A
ISODEF
SPEED
MD_A3
CFG_SEL
MD_A4
MP_SEL
N/A
BM_SEL
N/A
S.C
S.C
S.C
S.C
S.C
S.C
S.C
S.C
S.C
S.C
S.C
S.C
Up
Up
Up
Up
Up
Up
Down
Down
Up
Down
Down
Down
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
8
0804-5000-23 Industrial Powerline
Module
For Ethernet over Coax Applications
In addition to their configuration strap function, the GPIOs can perform some software configurable
functions after reset. The default configuration provided by Bel Fuse is as below:
GPIO
I/O
Default function after reset
GPIO0
O
GPIO1
I
GPIO2
I
GPIO[3..7]
O
GPIO8
O
GPIO9
O
GPIO10
O
GPIO11
O
Not Used (HiZ)
Typically connected to a push-button. This GPIO is used to add a new device
to, or remove an old device from, a HomePlug AC logical network. Contact
Bel Fuse for further information.
Typically connected to a push-button. The factory default PIB can be restored
by applying a low-level digital voltage on GPIO2 for greater than 0.5 seconds
and less than 3.0 seconds.
Not Used (HiZ)
To be connected to an LED. The LED gives indications about Power line Link
& activity:
On: Powerline link detected.
(0)
Flash: TX or RX powerline activity .
Off: Powerline link not detected.
To be connected to an LED. The LED gives indications about Ethernet Link &
activity:
On: Ethernet link detected.
Flash: Transmit or receive activity.
Off: No link detected.
To be connected to an LED. The LED gives indications about Power line
mode:
On: HomePlug 1.0 traffic detected
Flash: N/A
Off: Silence
To be connected to an LED. The LED gives indication about Power:
On: Power ready
(2)
Flash: Load firmware
Off: Power not ready
1. The Power line Link LED indicator turns On when powerline link is detected. If the AR6400 module is
serving as a STATION (STA), the LED indicator will flash to indicate transmit or receive powerline
activity. If the INT6400 module is serving as a CCO (central coordinator), the LED indicator will light
steadily ON, even in the presence of powerline activity.
2. If module flash memory is corrupted/blank or a host processor does not provide FW, the module ROM
based code will blink the POWER LED On and Off at a frequency of one cycle per second.
PHY utility interface
Pin
Number
Pin Name
I/O
47
PHY_RST/
O
PHY device Reset (active low). Connect to an external Ethernet PHY.
This reset output is a stretched version of the RESET/ input.
O
25MHz Clock Out. This output is a dedicated clock output that can be
used to drive the clock input on an external Ethernet PHY. This clock
output is only available when the AR6400 is configured in MAC mode,
and not in PHY mode of operation. Note that if this output is used, it is
strongly advised that the corresponding PHY_RST/ signal also be
connected to the external Ethernet PHY.
49
PHY_CLK
Description
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
9
0804-5000-23 Industrial Powerline
Module
For Ethernet over Coax Applications
Coupling Interface
Pin Number
Pin Name
I/O
6
TX+
O
7
TX-
O
9
RX+
I
10
RX-
I
Description
Differential TX Line Driver output, connects to coupling
transformer
Differential TX Line Driver output, connects to coupling
transformer
Differential RX Line Filter input, connects to coupling
transformer
Differential RX Line Filter input, connects to coupling
transformer
Special care must be taken during printed PCB layout of the coupling interface signals.
Route differential pairs close together and away from all other signals. Route each differential pair on the
same PCB layer. Keep both traces of each differential pair as identical to each other as possible.
Wide copper is needed here to support current density of up to 30MHz. These high frequencies result in
higher resistance due to skin effect. The wide traces also accommodate high transient currents caused
by voltage spikes. Trace widths between the Module and the coupling transformer must be no less than
0.020” (0.5 mm) and should be no greater than 0.030” (0.75 mm).
Reset Interface
Pin Number
Pin Name
I/O
Description
11
RESET/
I
Resets all IC logic when low.
Pin Number
Pin Name
I/O
Description
1, 3, 5
VDD
I
+3.3V with respect to VSS
2, 4, 8, 29,
36, 46, 48,
50
VSS
I
Ground
Power Interface
Reserved Pins
Internally connected and reserved for future use.
Pin Number
Type
Description
24
Reserved
Required 10KΩ pull-up resistor
27
Reserved
Do not connect externally
28
Reserved
Required connection to Ground
CONFIGURATION OPTIONS
The AR6400 MII and boot options are selected by the initial condition of GPIO pins. If a GPIO pin is not
used and its internal strapping resistor sets the booting option correctly, then the pin may be left
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
10
0804-5000-23 Industrial Powerline
Module
For Ethernet over Coax Applications
unconnected. If a GPIO pin is not used but the internal strapping resistor sets the booting option
incorrectly, then the pin must be pulled high or low to the correct booting option by an external resistor.
This resistor can be 10 k-Ohms down to a few hundred Ohms. 3.3 k-Ohms is typical. Many GPIO pins
are driven by firmware for LED output immediately after boot up so connecting these GPIO directly to
ground or VDD is unacceptable.
Pin Number
Pin Name
Strap Function
Internal Pull
Up/Down
15
GPIO3
ISODEF
Up
PHY MODE: Hi-Z MII interface
16
GPIO4
SPEED
Up
PHY MODE: 100Mbps
17
GPIO5
MD_A3
Up
PHY MODE: PHY Address
0x0100
18
GPIO6
CFG_SEL
Down
BOOT: SDRAM parameters from
Host
19
GPIO7
MD_A4
Down
PHY MODE: PHY address 0x0100
20
GPIO8
MP_SEL
Up
22
GPIO10
BM_SEL
Down
49
PHY_CLK
DUPLEX
Up
Default Function
HOST: MAC mode
BOOT: Firmware From Host
PHY MODE: Full Duplex
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
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0804-5000-23 Industrial Powerline
Module
For Ethernet over Coax Applications
MII Options
The MP_SEL strap is used to specify whether the AR6400 chip is configured for MII MAC mode, or in
MII PHY mode (i.e. reverse-MII mode). The encoding of this signal is shown in the following table:
MP_SEL
Mode
0
1
MII in PHY mode
MII in MAC mode
In MII PHY mode, there are 5 additional configuration straps that are unique to this mode of operation.
SPEED
MII Speed
DUPLEX
MII Duplex
0
1
10 Mbps
100 Mbps
0
1
Half Duplex
Full Duplex
ISODEF
Isolation
MD_A [3,4]
MII Management Address
0
1
Normal Operation
Isolated
00
01
10
11
0x00
0x08
0x10
0x18
Boot options
The BM_SEL strap is used to determine the source of the boot code for the embedded ARM processor.
Similarly, the CFG_SEL strap is used to determine the source of the SDRAM configuration applet. The
encodings for these two signals are shown in the following table.
BM_SEL
CFG_SEL
0
0
0
1
1
1
0
1
Meaning
Load SDRAM configuration and boot code from external host
Load SDRAM configuration applet from Flash, and then load boot code
from external host
Load SDRAM configuration
Load SDRAM configuration and boot code from Flash
DESIGN NOTES





Leave below lines unconnected if they are not unused:
 Pin 47: PHY_RST#
 Pin 49: PHY_CLK
 Pin 27: Reserved
Connect Pin 28 (Reserved) signal to the Ground.
Zero-cross Detection circuit is not required for DC line connection, but to work correctly the PLC
Module requires a pull-up resistor (10k) on ZC_IN line
Do not force other logic levels than default during the module boot on reserved GPIO Strapping’s,
GPIO: 0-2 and 3.
When the Power line module is in PHY mode, RX_ER signal should not be connected to the MII
Bus. This line is NOT tri-stated. Use a 10K Ohm pull down resistor only.
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
12
0804-5000-23 Industrial Powerline
Module
For Ethernet over Coax Applications
FIRMWARE
The 0804-5000-23 powerline modules are supplied programmed with the most recent firmware versions
and default Parameter Information Block (PIB) for EoC from Qualcomm Atheros. The PIB contains the
parameters used to configure the operation of the AR6400 chipset, including:




Network Management Key (NMK),
MAC address
Device Access Key (DAK),
GPIO function after reset.
This factory default PIB can be superseded by a customized User PIB using the Avitar PC-based
application. A non disclosure agreement is required with Qualcomm Atheros to access this tool.
ELECTRICAL CHARACTERISTICS
Symbol
VDD
Parameter
Supply voltage
Test Conditions
(1)
VIL
Low-level input voltage
VIH
High-level input voltage
VOL
Low-level output voltage
VOH
High-level output voltage
3.0
3.6
V
0.8
V
IOH = -4 mA, -12
(3)
mA
IIH
High-level input current
VI = 3.3 V
Gnd < VI < 3.3 V
V
0.4
(2)
VI = Gnd
Top
Units
IOL = 4 mA, 12 mA
Low-level input current
High-impedance output
current
Operating temperature
range
Max
2.0
IIL
IOZ
Min
V
2.4
V
-1
μA
1
μA
-1
+1
μA
-40
+85
°C
1. A typical supply current, assuming a nominal operation of 50% transmit and 50% receive duty cycle,
is 580 mA.
2. IOL=12 mA for all GPIOs. IOL = 4 mA for all other digital interfaces.
3. IOH = -12 mA for all GPIOs. IOH = -4 mA for all other digital interfaces
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
13
0804-5000-23 Industrial Powerline
Module
For Ethernet over Coax Applications
MECHANICAL
0804-5000-23
Horizontal Mount
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
CORPORATE
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Bel Fuse Inc.
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Tel 201-432-0463
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www.belfuse.com
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San Po Kong
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28 Turkey Court, Turkey Mill
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Tel 44-1622-757395
Fax 44-1622-663252
www.belfuse.com
14
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