® RT8125C/D High Efficiency Single Synchronous Buck PWM Controller General Description Features The RT8125C/D PWM controller provides high efficiency, excellent transient response, and high DC output accuracy needed for CPU core, I/O, and chipset RAM supplies in notebook computers. Richtek Mach ResponseTM technology is specifically designed for providing 100ns “instant-on” response to load transients while maintaining a relatively constant switching frequency. The RT8125C/D achieves high efficiency at a reduced cost by eliminating the current sense resistor found in traditional current mode PWMs. Efficiency is further enhanced by its ability to drive very large synchronous rectifier MOSFETs. The Buck conversion allows this device to directly step down high voltage batteries at the highest possible efficiency. The RT8125C/D provides an 1% high accuracy 0.8V reference voltage with minimum 1mA source/sink current for high accuracy output application. Richtek Mach ResponseTM Technology 1% High Accuracy 0.8V Reference VCC Input Range : 4.5V to 13.2V VOUT Operating Range : 0.3V to 3.3V Power Stage Input Range : 1.5V to 24V Fixed Operating Frequency : 300kHz VIN Detection LG_OCSET for Current Limit PGOOD Indicator Embedded Bootstrap Switch Ω) High Side Gate Driver Pull Low Resistor (10kΩ Current Limit with Low Side Current Sense Scheme Enable Function with Internal Pull High Current OVP/UVP/OTP/Pre-OVP/Current Limit Shutdown Current <100μ μA RoHS Compliant and Halogen Free Applications Pin Configurations Generic DC/DC Power Regulator Mother Boards and Desktop Servers (TOP VIEW) 1 2 3 GND BOOT UGATE PHASE LGATE/OCSET VCC 4 5 11 10 9 8 7 6 REFOUT REFIN PGOOD EN FB WDFN-10L 3x3 Simplified Application Circuit VCC Enable VIN VCC RT8125C/D UGATE EN BOOT PGOOD PGOOD PHASE REFOUT LGATE/ OCSET REFIN VOUT FB GND Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS8125C/D-02 June 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT8125C/D Ordering Information Marking Information RT8125C/D RT8125CGQW Package Type QW : WDFN-10L 3x3 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) OCP Scaling During Soft-Start C : No D : Yes 69= : Product code 69=YM DNN RT8125DGQW 6X= : Product code Note : Richtek products are : RoHS compliant and compatible with the current require- YMDNN : Date code 6X=YM DNN YMDNN : Date code ments of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Functional Pin Description Pin No. Pin Name Pin Function 1 BOOT Bootstrap Supply for High Side Gate Driver. Connect a capacitor between this pin and the PHASE pin. 2 UGATE Gate Drive Output for the External High Side MOSFET. 3 PHASE 4 LGATE/OCSET 5 VCC 6 FB VOUT Feedback Voltage Input. Connect the FB to a resistive voltage divider from VOUT to GND to set the output voltage from 0.3V to 3.3V 7 EN Enable Control Input. 8 PGOOD 9 REFIN 10 REFOUT 11 (Exposed Pad) GND Switch Node. It behaves as the current sense comparator input for low side MOSFET RDS(ON) sensing and reference voltage for on-time generation. Gate Drive Output for the Low Side External MOSFET. Connect a resistor (ROCSET) between this pin and GND to set the output current limit level. If ROCSET is not present , or the setting threshold greater than 400mV, the OC threshold is internally present to 315mV (typ.) Supply Voltage Input. It provides the power for the Buck controller, the low side driver and the bootstrap circuit for high side driver. Bypass to GND with a 4.7F ceramic capacitor. Open-drain Power Good Indicator. High impedance indicates that power is good. Reference Input. Connect a current console to REFIN pin, and connect a resistor between REFIN and REFOUT to tune up/down FB reference voltage. Reference Voltage Output. It provides an 1% high accuracy reference 0.8V with 2mA source/sink ability. Bypass to GND with a maximum 6.8nF ceramic capacitor. Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS8125C/D-02 June 2015 RT8125C/D Function Block Diagram On-time One Shot PHASE VREF REFIN + + - BOOT R S Comp Q UGATE PHASE VCC Minimum TOFF + 125% VREF - OVP Latch LGATE/OCSET GND - FB + 50% VREF Thermal Shutdown UVP Hiccup + 90% VREF VCC LDO & POR SS + REF VIN Detection + + Gm - Sample and Hold VDET - EN REFOUT PGOOD Operation The RT8125C/D is suitable for low external component count configuration with appropriate amount of Equivalent Series Resistance (ESR) capacitor(s) at the output. The output ripple valley voltage is monitored at a feedback point voltage. The synchronous high side MOSFET is turned on at the beginning of each cycle. After the internal one-shot timer expires, the MOSFET is turned off. The pulse width of this one-shot is determined by the converter's input and output voltages to keep the frequency Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS8125C/D-02 June 2015 fairly constant over the entire input voltage range. Another one-shot sets a minimum off-time (400ns typ.). The on-time comparator has two inputs, one is from the output voltage, the other is from the input voltage. The ontime of the high side switch is designed to be directly proportional to the output voltage and inversely proportional to the input voltage. The implementation results in a nearly constant switching frequency without the need of a clock generator. is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT8125C/D Absolute Maximum Ratings (Note 1) VCC to GND ---------------------------------------------------------------------------------------------------------------PGOOD, FB, EN, REFOUT, REFIN --------------------------------------------------------------------------------- BOOT to GND -------------------------------------------------------------------------------------------------------------<100ns ---------------------------------------------------------------------------------------------------------------------- BOOT to PHASE ---------------------------------------------------------------------------------------------------------<100ns ---------------------------------------------------------------------------------------------------------------------- PHASE to GND DC ----------------------------------------------------------------------------------------------------------------------------<100ns ---------------------------------------------------------------------------------------------------------------------- UGATE to GND ------------------------------------------------------------------------------------------------------------<100ns ---------------------------------------------------------------------------------------------------------------------- UGATE to PHASE DC ----------------------------------------------------------------------------------------------------------------------------<100ns ---------------------------------------------------------------------------------------------------------------------- LGATE to GND DC ----------------------------------------------------------------------------------------------------------------------------<100ns ---------------------------------------------------------------------------------------------------------------------- Power Dissipation, PD @ TA = 25°C WDFN-10L 3x3 ------------------------------------------------------------------------------------------------------------ Package Thermal Resistance (Note 2) WDFN-10L 3x3, θJA ------------------------------------------------------------------------------------------------------WDFN-10L 3x3, θJC ------------------------------------------------------------------------------------------------------ Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------ Junction Temperature ---------------------------------------------------------------------------------------------------- Storage Temperature Range ------------------------------------------------------------------------------------------- ESD Susceptibility (Note 3) HBM (Human Body Model) --------------------------------------------------------------------------------------------- Recommended Operating Conditions −0.3V to 15V −0.3V to 6.5V −0.3V to 40V −0.3V to 45V −0.3V to 15V −0.3V to 20V −5V to 25V −10V to 30V −0.3V to 40V −10V to 45V 0.3V to 15V −5V to 20V −0.3V to 15V −5V to 20V 3.28W 30.5°C/W 7.5°C/W 260°C 150°C −65°C to 150°C 2kV (Note 4) Input Voltage, VIN --------------------------------------------------------------------------------------------------------- 1.5V to 24V Supply Voltage, VCC ----------------------------------------------------------------------------------------------------- 4.5V to 13.2V Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS8125C/D-02 June 2015 RT8125C/D Electrical Characteristics (VCC = 5V, VIN = 15V, EN = 5V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 3.9 4.2 4.5 V -- 500 1250 A -- -- 100 A 786 794 802 mV -- -- 2 mA 1 0 1 A 0.3 -- 3.3 V PWM Controller VCC POR Threshold VCC Quiescent Supply Current IQ VCC Shutdown Current ISHDN REFOUT VREFOUT (Note 5) REFOUT Source / Sink Current FB Input Bias Current Rising Edge, Hysteresis = 120mV, PWM disabled below this level FB Forced above the Regulation Point, EN = 5V, REFOUT Current = 0 VCC Current, EN = 0V VCC = 4.5V to 13.2V, Sink/ Source Current = 2mA IREFOUT FB = 0.8V REFIN Input Voltage Range Switching Frequency (Note 6) 270 300 330 kHz 250 -- -- ns 9 10 11 A REFIN = 0.8V, No Load -- 0.7 -- ms LGATE 50 -- 400 mV ROCSET NC UVP Detect, FB Lower than REFIN Voltage OVP Detect, FB Higher than REFIN Voltage -- 315 -- mV 225 300 375 mV 225 300 375 mV 3.35 3.5 -- V -- 140 -- C 0.5 -- -- V -- 1.5 3 -- 2.25 4 Minimum Off-Time Current Sensing IOCSET Soft-Start Time TSS Protection Function Current Limit Setting Range Current Limit Threshold UV Threshold OVP Threshold REFIN Absolute OVP Threshold Thermal Shutdown VIN Detection Threshold Driver On-Resistance Latch VDET UGATE Driver Source RUGATEsr UGATE Driver Sink RUGATEsk VBOOT VPHASE = 12V, Source Current = 100mA BOOT PHASE = 12V, ISINK = 10mA LGATE Driver Source RLGATEsr VCC = 12V, Source Current = 100mA -- 1.5 3 LGATE Driver Sink RLGATEsk VCC = 12V, ISINK = 10mA -- 1 2 LGATE Rising (PHASE = 1.5V) -- 30 -- UGATE Rising -- 30 -- VCC to BOOT, 10mA -- -- 80 Dead Time Internal Boost Charging Switch On-Resistance Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS8125C/D-02 June 2015 ns is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT8125C/D Parameter Symbol Test Conditions Min Typ Max Unit 5 -- -- A EN Threshold EN Internal Pull High Current Enable Input Voltage EN = 0V Logic-High VIH 2.4 -- 5.5 Logic-Low VIL -- -- 0.4 V PGOOD (PGOOD High w/o OVP or UVP) PGOOD Blanking Time PGOOD Rising Edge After Soft-Start 1 3 5 ms Output Low Voltage ISINK = 4mA -- -- 0.3 V Leakage Current High State, Forced to 5V -- -- 1 A Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. The reference voltage shift -6mV from 0.8V for offset canceling under feedback valley control. Note 6. No production tested. Test condition VIN = 8V, VOUT = 1.1V, IOUT = 10A using application circuit. Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS8125C/D-02 June 2015 RT8125C/D Typical Application Circuit 5 VCC 4.7µF 7 Enable EN UGATE 2 BOOT 1 100k 5V PGOOD VIN VCC RT8125C/D 0.1µF 8 PGOOD PHASE 3 10 REFOUT LGATE/ 4 OCSET VOUT ROCSET 9 REFIN FB 6 GND 11 (Exposed Pad) Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS8125C/D-02 June 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT8125C/D Typical Operating Characteristics Output Voltage vs. Load Current 1.55 90 1.54 80 1.53 Output Voltage (V) Efficiency (%) Efficiency vs. Load Current 100 70 60 50 40 30 20 1.52 1.51 1.50 1.49 1.48 1.47 10 1.46 VIN = VCC = 12V, VOUT = 1.5V 0 0.01 VIN = VCC = 12V 1.45 0.1 1 10 100 0 2 4 6 Load Current (A) 10 12 14 16 18 20 Load Current (A) Frequency vs. Load Current TON vs. Temperature 450 500 400 480 350 460 300 TON (ns) Frequency (kHz)1 8 250 200 440 420 150 400 100 380 50 VIN = VCC = 12V, VOUT = 1.5V VIN = VCC = 12V, VOUT = 1.5V, No Load 0 360 0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 Load Current (A) Temperature (°C) Output Voltage vs. Temperature Load Transient Response 125 1.55 1.54 VOUT (100mV/Div) Output Voltage (V) 1.53 1.52 1.51 1.50 1.49 1.48 1.47 IOUT (10A/Div) 1.46 VIN = VCC = 12V, No Load VIN = VCC = 12V, VOUT = 1.5V 1.45 -50 -25 0 25 50 75 100 125 Time (200μs/Div) Temperature (°C) Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS8125C/D-02 June 2015 RT8125C/D Power Off from EN Power On from EN EN (5V/Div) EN (5V/Div) VOUT (1V/Div) VOUT (1V/Div) PGOOD (10V/Div) PGOOD (10V/Div) UGATE (20V/Div) VIN = VCC = 12V, IOUT = 50mA UGATE (20V/Div) VIN = VCC = 12V, IOUT = 10A Time (1ms/Div) Time (100μs/Div) Dynamic Output Voltage Control Dynamic Output Voltage Control VOUT (100mV/Div) VOUT (100mV/Div) VREFIN (200mV/Div) VREFIN (200mV/Div) VIN = VCC = 12V, IREFIN = 50μA x 1steps, IOUT = 10A VIN = VCC = 12V, IREFIN = -10μA x 5steps, IOUT = 10A Time (20μs/Div) Time (200μs/Div) OVP VFB (1V/Div) VOUT (1V/Div) PGOOD (5V/Div) LGATE (20V/Div) VIN = VCC = 12V Time (100μs/Div) Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS8125C/D-02 June 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT8125C/D Application Information The RT8125C/D PWM controller provides high efficiency, excellent transient response, and high DC output accuracy needed for CPU core, I/O, and chipset RAM supplies in notebook computers. Richtek Mach Response TM technology is specifically designed for providing 100ns “instant-on” response to load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The topology solves the poor load transient response timing problems of fixed frequency current mode PWMs and avoids the problems caused by widely varying switching frequencies in conventional constant on-time and constant off-time PWM schemes. Supply Voltage and Power On Reset (POR) The input voltage range for VCC is from 4.5 V to 13.2 V with respect to GND. An internal linear regulator regulates the supply voltage for internal control logic circuit. A minimum 0.1μF ceramic capacitor is recommended to bypass the supply voltage. Place the bypassing capacitor near the IC. VCC also supplies the integrated MOSFET drivers. A bootstrap diode is embedded to facilitate PCB design and reduce the total BOM cost. No external Schottky diode is required in real applications. The Power On Reset (POR) circuit monitors the supply voltage at the VCC pin. If VCC exceeds the POR rising threshold voltage (4.2V typ.), the controller resets and prepares the PWM for operation. If VCC falls below the POR falling threshold during normal operation, all MOSFETs stop switching. The POR rising and falling threshold has a hysteresis (0.12V typ.) to prevent unintentional noise based reset. Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 VIN Detection Once VCC exceeds its power on reset (POR) rising threshold voltage and the EN pin is set free, UGATE will output continuous pulses (~40kHz, 100ns), and LGATE will be forced low for converter input voltage VIN detection. If the voltage pulses at the PHASE pin are less than VIN detection threshold (VDET) when UGATE is turned off more than 3 cycles, VIN is recognized as ready. Then, the controller will initiate soft-start operation. For ensuring the VIN can be defected, the Phase to GND can't place schottky diode to avoid the phase voltage will be clamped to around -0.3V. Internal Soft-Start The RT8125C/D provides an internal soft-start function. The soft-start function is used to prevent large inrush current and output voltage overshoot while the converter is being powered-up. The soft-start function automatically begins once the chip is enabled. An internal current source charges the internal soft-start capacitor such that the internal soft-start voltage ramps up uniformly. The FB voltage will track the internal soft-start voltage during the soft-start interval. After the internal soft-start voltage exceeds the reference voltage, the FB voltage no longer tracks the soft-start voltage but rather follows the reference voltage. Therefore, the duty cycle of the UGATE signal as well as the input current at power up are limited. is a registered trademark of Richtek Technology Corporation. DS8125C/D-02 June 2015 RT8125C/D VCC POR threshold POR threshold EN LGATE UGATE 3.3V 0.8V Internal SS FB Soft-Start (TSS) PGOOD OCP VIN Programming Detection PGOOD Blanking Time Normal Operation LG turns on to discharge output voltage Figure 1. Soft-Start Timing Chart Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS8125C/D-02 June 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT8125C/D Soft Discharge Current Limit When VCC is less than POR falling threshold or EN goes low, the discharging mode will active. During discharging mode, LGATE will deliver discharging pulse and an internal switch from FB to GND will also create a path for discharging the output capacitor's residual charge to GND until the phase pin voltage below 0.7V. The RT8125C/D provides lossless over current protection by detecting the voltage drop across the low side MOSFET when it is turned on. The over current trip threshold is set by an external resistor, ROCSET, at LGATE. During LGATE is turned on, the RT8125C/D senses the PHASE voltage and compares to the OCP threshold. If the sensed PHASE voltage is lower than the OCP threshold, OCP will be triggered. When OCP is triggered, LGATE will turn on to prevent inductor current from increasing until the OCP condition is released. Output Voltage Setting The RT8125C/D supports external reference input to provide more flexible applications. The REFIN pin and REFOUT pin are implemented to be external reference input function. The RT8125C/D allows the output voltage of the DC/DC converter to be adjusted via an external resistor divider. It will try to maintain the feedback pin at REFIN pin input voltage. Current Limit Setting Over current threshold is externally programmed by adding a resistor (ROCSET) between LGATE and GND. Once VCC exceeds the POR threshold and the EN pin is enabled, an internal current source IOCSET flows through ROCSET. For maintain the OCP threshold accuracy while temperature variation, the current source (IOCSET) has an approximately 4500ppm/°C temperature slope to compensate the dependency of RDS(ON) of MOSFET. The voltage across ROCSET is stored as the over current protection threshold VOCSET. After that, the current source is switched off. ROCSET can be determined using the following equation : VOUT RFB1 FB RFB2 Figure 2. Output Voltage Setting V ROCSET = VOUT VOUT VVal t tON Figure 3. Output Voltage Waveform According to the resistor divider network above, the output voltage is set as : R V VOUT = VREFOUT 1 FB1 OUT 2 RFB2 IVALLEY RLGDS(ON) IOCSET where IVALLEY represents the desired inductor OCP trip current (valley inductor current). If ROCSET is not present, there is no current path for IOCSET to build the OCP threshold. In this situation, the OCP threshold is internally preset to 315mV (typical). For RT8125D, the OCP threshold in soft-start period will be reduced ot half of setting value. For example, if the desired OCP threshold is 30A,the OCP threshold will be 15A during soft-start period. For RT8125C, the OCP threshold is same as steady state during soft-stare period. For ensure current limit threshold accuracy, the Ciss of low-side MOSFET must less than 8nF. Note that the reference voltage at DEM is exceeds than CCM threshold 1%. Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 is a registered trademark of Richtek Technology Corporation. DS8125C/D-02 June 2015 RT8125C/D Over Voltage Protection (OVP) Comp FB The output voltage is scaled by the divider resistors and fed back to the FB pin. The voltage on the FB pin will be compared with the REFIN Voltage. For voltage related protection functions, including over voltage protection and under voltage protection. If the FB voltage is higher than the OVP threshold during operation, OVP will be triggered. When OVP is triggered, UGATE will go low and LGATE will go high to discharge the output capacitor. Once OVP is triggered, controller will be latched unless VCC POR is detected again or EN pin is reset. - 50% VREF + 125% VREF - UVP Hiccup UVP Threshold FB UGATE LGATE Comp FB + Delay Time (36µs typ.) OVP Latch OCP Programming VIN Detection Figure 5. UVP Operation MOSFET Drivers OVP Threshold FB UGATE Latch LGATE Delay Time (36µs typ.) Figure 4. OVP Operation Under Voltage Protection (UVP) The voltage on the FB pin is monitored for under voltage protection. Controller begins to detect UVP after soft-start finish. If the FB voltage is lower than the UVP threshold during normal operation, UVP will be triggered. When the UVP is triggered, both UGATE and LGATE will go low the RT8125C/D will enter hiccup mode and continuously try to restart until the UVP situation is removed. The RT8125C/D integrates high current gate drivers for the two N-MOSFETs to obtain high efficiency power conversion in synchronous Buck topology. A dead time is used to prevent crossover conduction for the high side and low side MOSFETs. Because both gate signals are off during dead time, the inductor current freewheels through the body diode of the low side MOSFET. The freewheeling current and the forward voltage of the body diode contribute to power loss. The RT8125C/D employs constant dead time control scheme to ensure safe operation without sacrificing efficiency. Furthermore, elaborate logic circuit is implemented to prevent cross conduction. For high output current applications, two or more power MOSFETs are usually paralleled to reduce RDS(ON). The gate driver needs to provide more current to switch on/off these paralleled MOSFETs. Gate driver with lower source/ sink current capability result in longer rising/falling time in gate signals, and therefore higher switching loss. The RT8125C/D embeds high current gate drivers to obtain high efficiency power conversion. The embedded drivers contribute to the majority of the power dissipation of the controller. Therefore, WDFN package is chosen for its power dissipation rating. If no gate resistor is used, the power dissipation of the controller can be approximately calculated using the following equation : PDRIVER = fSW QG VBOOT QG_Low Side VDRIVER_Low Side Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS8125C/D-02 June 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT8125C/D where VBOOT represents the voltage across the bootstrap capacitor and fSW is the switching frequency. It is important to ensure the package can dissipate the switching loss and have enough room for safe operation. Inductor Selection The inductor plays an important role in step-down converters because it stores the energy from the input power rail and then releases the energy to the load. From the viewpoint of efficiency, the DC Resistance (DCR) of the inductor should be as small as possible to minimize the conduction loss. In addition, the inductor covers a significant proportion of the board space, so its size is also important. Low profile inductors can save board space especially when the height has a limitation. However, low DCR and low profile inductors are usually not cost effective. Additionally, larger inductance results in lower ripple current, which translates into the lower power loss. The inductor current rising time increases with inductance value. This means the transient response will be slower. Therefore, the inductor design is a trade-off among performance, size and cost. In general, inductance is chosen such that the ripple current ranges between 20% to 40% of the full load current. The inductance can be calculated using the following equation : VIN VOUT V L(MIN) = OUT fSW k IOUT_Full Load VIN where k is the ratio between inductor ripple current and rated output current. Input Capacitor Selection Voltage rating and current rating are the key parameters when selecting an input capacitor. Conservatively speaking, an input capacitor should have a voltage rating 1.5 times greater than the maximum input voltage to be considered a safe design. The input capacitor is used to supply the input RMS current, which can be approximately calculated using the following equation : IRMS = IOUT VOUT VOUT 1 VIN VIN Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 The next step is to select a proper capacitor for the RMS current rating. Using more than one capacitor with low Equivalent Series Resistance (ESR) in parallel to form a capacitor bank is a good design. Placing a ceramic capacitor close to the drain of the high side MOSFET can also be helpful in reducing the input voltage ripple at heavy load. Output Capacitor Selection The output capacitor and the inductor form a low-pass filter in the Buck topology. In steady state condition, the ripple current flowing into/out of the capacitor results in voltage ripple. The output voltage ripples contains two components, ΔVOUT_ESR and ΔVOUT_C. VOUT_ESR = IL ESR VOUT_C = IL 1 8 COUT fSW When load transient occurs, the output capacitor supplies the load current before controller can respond. Therefore, the ESR will dominate the output voltage sag during load transient. The output voltage sag can be calculated using the following equation : VOUT_SAG = ESR IOUT For a given output voltage sag specification, the ESR value can be determined. Another parameter that has influence on the output voltage sag is the equivalent series inductance (ESL). The rapid change in load current results in di/dt during transient. Therefore ESL contributes to part of the voltage sag. Using a capacitor with low ESL will obtain better transient performance. Generally, using several capacitors connected in parallel will also have better transient performance than just one single capacitor with the same total ESR. Unlike electrolytic capacitors, the ceramic capacitor has relatively low ESR and can reduce the voltage deviation during load transient. However, the ceramic capacitor can only provide low capacitance value. Therefore, it is suggested to use a mixed combination of electrolytic capacitor and ceramic capacitor for achieving better transient performance. is a registered trademark of Richtek Technology Corporation. DS8125C/D-02 June 2015 RT8125C/D MOSFET Selection Maximum Power Dissipation (W)1 4.0 The majority of power loss in the step-down power conversion is due to the loss in the power MOSFETs. For low voltage high current applications, the duty cycle of the high side MOSFET is small. Therefore, the switching loss of the high side MOSFET is of concern. Power MOSFETs with lower total gate charge are preferred in such kind of application. However, the small duty cycle means the low side MOSFET is on for most of the switching cycle. Therefore, the conduction loss tends to dominate the total power loss of the converter. To improve the overall efficiency, MOSFETs with low RDS(ON) are preferred in the circuit design. In some cases, more than one MOSFET are connected in parallel to further decrease the on-state resistance. However, this depends on the low side MOSFET driver capability and the budget. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For WDFN-10L 3x3 package, the thermal resistance, θJA, is 30.5°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formulas : PD(MAX) = (125°C − 25°C) / (30.5°C/W) = 3.28W for WDFN-10L 3x3 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance. The derating curve in Figure 6 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS8125C/D-02 June 2015 3.2 2.4 1.6 0.8 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 6. Derating Curve of Maximum Power Dissipation Layout Considerations PCB layout is critical to high current high frequency switching converter designs. A good layout can help the controller to function properly and achieve expected performance. On the other hand, PCB without a carefully layout can radiate excessive noise, having more power loss and even malfunction in the controller. In order to avoid the above condition, the general guidelines can be followed in PCB layout. Power stage components should be placed first. Place the input bulk capacitors close to the high side power MOSFETs, and then locate the output inductor and finally the output capacitors. Placing the ceramic capacitor physically close to the drain of the high side MOSFET. This can reduce the input voltage drop when high side MOSFET is turned on. If more than one MOSFET is paralleled, each should have its own individual ceramic capacitor. Keep the high current loops as short as possible. During high speed switching, the current transition between MOSFETs usually causes di/dt voltage spike due to the parasitic components on PCB trace. Therefore, making the trace length between power MOSFETs and inductors wide and short can reduce the voltage spike and EMI. PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. Four-Layer PCB is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT8125C/D Make MOSFET gate driver path as short as possible. Since the gate driver uses narrow-width high current pulses to switch on/off power MOSFET, the driver path must be short to reduce the trace inductance. This is especially important for low side MOSFET, because this can reduce the possibility of shoot-through. Providing enough copper area around power MOSFETs to help heat dissipation. Using thick copper also reduces the trace resistance and inductance to have better performance. The output capacitors should be placed physically close to the load. This can minimize the trace parasitic components and improve transient response. All small signal components should be located close to the controller. The small signal components include the feedback voltage divider resistors, function setting components and high frequency bypass capacitors. The feedback voltage divider resistor must be placed close to FB pin, because the FB pin is inherently noisesensitive. Voltage feedback path must be away from switching nodes. The noisy switching node is, for example, the interconnection between high side MOSFET, low side MOSFET and inductor. Feedback path must be away from this kind of noisy node to avoid noise pick-up. A multi-layer PCB design is recommended. Make use of one single layer as the ground and have separate layers for power rail, or signal is suitable for PCB design. Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 is a registered trademark of Richtek Technology Corporation. DS8125C/D-02 June 2015 RT8125C/D Outline Dimension D2 D L E E2 1 e SEE DETAIL A b 2 1 2 1 A A1 A3 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 2.300 2.650 0.091 0.104 E 2.950 3.050 0.116 0.120 E2 1.500 1.750 0.059 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 10L DFN 3x3 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. DS8125C/D-02 June 2015 www.richtek.com 17